fb6ff3bf4d60fb17974467cfdc9a1c9614da7da3
[linux-2.6.git] / drivers / mfd / tps80031.c
1 /*
2  * driver/mfd/tps80031.c
3  *
4  * Core driver for TI TPS80031
5  *
6  * Copyright (C) 2011 NVIDIA Corporation
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, write to the Free Software Foundation, Inc.,
20  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
21  *
22  */
23
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/mutex.h>
29 #include <linux/slab.h>
30 #include <linux/gpio.h>
31 #include <linux/i2c.h>
32 #include <linux/pm.h>
33
34 #include <linux/mfd/core.h>
35 #include <linux/mfd/tps80031.h>
36
37 /* interrupt related registers */
38 #define TPS80031_INT_STS_A              0xD0
39 #define TPS80031_INT_STS_B              0xD1
40 #define TPS80031_INT_STS_C              0xD2
41 #define TPS80031_INT_MSK_LINE_A         0xD3
42 #define TPS80031_INT_MSK_LINE_B         0xD4
43 #define TPS80031_INT_MSK_LINE_C         0xD5
44 #define TPS80031_INT_MSK_STS_A          0xD6
45 #define TPS80031_INT_MSK_STS_B          0xD7
46 #define TPS80031_INT_MSK_STS_C          0xD8
47
48 #define TPS80031_CONTROLLER_STAT1               0xE3
49 #define CONTROLLER_STAT1_BAT_TEMP               0
50 #define CONTROLLER_STAT1_BAT_REMOVED            1
51 #define CONTROLLER_STAT1_VBUS_DET               2
52 #define CONTROLLER_STAT1_VAC_DET                3
53 #define CONTROLLER_STAT1_FAULT_WDG              4
54 #define CONTROLLER_STAT1_LINCH_GATED            6
55
56 #define TPS80031_CONTROLLER_INT_MASK            0xE0
57 #define CONTROLLER_INT_MASK_MVAC_DET            0
58 #define CONTROLLER_INT_MASK_MVBUS_DET           1
59 #define CONTROLLER_INT_MASK_MBAT_TEMP           2
60 #define CONTROLLER_INT_MASK_MFAULT_WDG          3
61 #define CONTROLLER_INT_MASK_MBAT_REMOVED        4
62 #define CONTROLLER_INT_MASK_MLINCH_GATED        5
63
64 #define CHARGE_CONTROL_SUB_INT_MASK             0x3F
65
66 /* Version number related register */
67 #define TPS80031_JTAGVERNUM             0x87
68 /* Epprom version */
69 #define TPS80031_EPROM_REV              0xDF
70
71 /* External control register */
72 #define REGEN1_BASE_ADD         0xAE
73 #define REGEN2_BASE_ADD         0xB1
74 #define SYSEN_BASE_ADD          0xB4
75
76 /* device control registers */
77 #define TPS80031_PHOENIX_DEV_ON 0x25
78 #define DEVOFF  1
79
80 #define CLK32KAO_BASE_ADD       0xBA
81 #define CLK32KG_BASE_ADD        0xBD
82 #define CLK32KAUDIO_BASE_ADD    0xC0
83
84 #define EXT_CONTROL_CFG_TRANS 0
85 #define EXT_CONTROL_CFG_STATE 1
86
87 #define STATE_OFF       0x00
88 #define STATE_ON        0x01
89 #define STATE_MASK      0x03
90
91 #define TRANS_SLEEP_OFF         0x00
92 #define TRANS_SLEEP_ON          0x04
93 #define TRANS_SLEEP_MASK        0x0C
94
95 #define TPS_NUM_SLAVES  4
96 #define EXT_PWR_REQ (PWR_REQ_INPUT_PREQ1 | PWR_REQ_INPUT_PREQ2 | \
97                 PWR_REQ_INPUT_PREQ3)
98 #define TPS80031_PREQ1_RES_ASS_A        0xD7
99 #define TPS80031_PREQ2_RES_ASS_A        0xDA
100 #define TPS80031_PREQ3_RES_ASS_A        0xDD
101 #define TPS80031_PHOENIX_MSK_TRANSITION 0x20
102
103
104 static u8 pmc_ext_control_base[] = {
105         REGEN1_BASE_ADD,
106         REGEN2_BASE_ADD,
107         SYSEN_BASE_ADD,
108 };
109
110 static u8 pmc_clk32k_control_base[] = {
111         CLK32KAO_BASE_ADD,
112         CLK32KG_BASE_ADD,
113         CLK32KAUDIO_BASE_ADD,
114 };
115 struct tps80031_irq_data {
116         u8      mask_reg;
117         u8      mask_mask;
118         u8      is_sec_int;
119         u8      parent_int;
120         u8      mask_sec_int_reg;
121         u8      int_mask_bit;
122         u8      int_sec_sts_reg;
123         u8      int_sts_bit;
124 };
125
126 #define TPS80031_IRQ(_reg, _mask)       \
127         {                                                       \
128                 .mask_reg = (TPS80031_INT_MSK_LINE_##_reg) -    \
129                                 TPS80031_INT_MSK_LINE_A,        \
130                 .mask_mask = (_mask),                           \
131         }
132
133 #define TPS80031_IRQ_SEC(_reg, _mask, _pint, _sint_mask_bit, _sint_sts_bit) \
134         {                                                               \
135                 .mask_reg = (TPS80031_INT_MSK_LINE_##_reg) -            \
136                                 TPS80031_INT_MSK_LINE_A,                \
137                 .mask_mask = (_mask),                                   \
138                 .is_sec_int = true,                                     \
139                 .parent_int = TPS80031_INT_##_pint,                     \
140                 .mask_sec_int_reg = TPS80031_CONTROLLER_INT_MASK,       \
141                 .int_mask_bit = CONTROLLER_INT_MASK_##_sint_mask_bit,   \
142                 .int_sec_sts_reg = TPS80031_CONTROLLER_STAT1,           \
143                 .int_sts_bit = CONTROLLER_STAT1_##_sint_sts_bit         \
144         }
145
146 static const struct tps80031_irq_data tps80031_irqs[] = {
147
148         [TPS80031_INT_PWRON]            = TPS80031_IRQ(A, 0),
149         [TPS80031_INT_RPWRON]           = TPS80031_IRQ(A, 1),
150         [TPS80031_INT_SYS_VLOW]         = TPS80031_IRQ(A, 2),
151         [TPS80031_INT_RTC_ALARM]        = TPS80031_IRQ(A, 3),
152         [TPS80031_INT_RTC_PERIOD]       = TPS80031_IRQ(A, 4),
153         [TPS80031_INT_HOT_DIE]          = TPS80031_IRQ(A, 5),
154         [TPS80031_INT_VXX_SHORT]        = TPS80031_IRQ(A, 6),
155         [TPS80031_INT_SPDURATION]       = TPS80031_IRQ(A, 7),
156         [TPS80031_INT_WATCHDOG]         = TPS80031_IRQ(B, 0),
157         [TPS80031_INT_BAT]              = TPS80031_IRQ(B, 1),
158         [TPS80031_INT_SIM]              = TPS80031_IRQ(B, 2),
159         [TPS80031_INT_MMC]              = TPS80031_IRQ(B, 3),
160         [TPS80031_INT_RES]              = TPS80031_IRQ(B, 4),
161         [TPS80031_INT_GPADC_RT]         = TPS80031_IRQ(B, 5),
162         [TPS80031_INT_GPADC_SW2_EOC]    = TPS80031_IRQ(B, 6),
163         [TPS80031_INT_CC_AUTOCAL]       = TPS80031_IRQ(B, 7),
164         [TPS80031_INT_ID_WKUP]          = TPS80031_IRQ(C, 0),
165         [TPS80031_INT_VBUSS_WKUP]       = TPS80031_IRQ(C, 1),
166         [TPS80031_INT_ID]               = TPS80031_IRQ(C, 2),
167         [TPS80031_INT_VBUS]             = TPS80031_IRQ(C, 3),
168         [TPS80031_INT_CHRG_CTRL]        = TPS80031_IRQ(C, 4),
169         [TPS80031_INT_EXT_CHRG]         = TPS80031_IRQ(C, 5),
170         [TPS80031_INT_INT_CHRG]         = TPS80031_IRQ(C, 6),
171         [TPS80031_INT_RES2]             = TPS80031_IRQ(C, 7),
172         [TPS80031_INT_BAT_TEMP_OVRANGE] = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
173                                                 MBAT_TEMP,      BAT_TEMP),
174         [TPS80031_INT_BAT_REMOVED]      = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
175                                                 MBAT_REMOVED,   BAT_REMOVED),
176         [TPS80031_INT_VBUS_DET]         = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
177                                                 MVBUS_DET,      VBUS_DET),
178         [TPS80031_INT_VAC_DET]          = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
179                                                 MVAC_DET,       VAC_DET),
180         [TPS80031_INT_FAULT_WDG]        = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
181                                                 MFAULT_WDG,     FAULT_WDG),
182         [TPS80031_INT_LINCH_GATED]      = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
183                                                 MLINCH_GATED,   LINCH_GATED),
184 };
185
186 static const int controller_stat1_irq_nr[] = {
187         TPS80031_INT_BAT_TEMP_OVRANGE,
188         TPS80031_INT_BAT_REMOVED,
189         TPS80031_INT_VBUS_DET,
190         TPS80031_INT_VAC_DET,
191         TPS80031_INT_FAULT_WDG,
192         0,
193         TPS80031_INT_LINCH_GATED,
194         0
195 };
196
197 /* Structure for TPS80031 Slaves */
198 struct tps80031_client {
199         struct i2c_client *client;
200         struct mutex lock;
201         u8 addr;
202 };
203
204 struct tps80031 {
205         struct device           *dev;
206         unsigned long           chip_info;
207         int                     es_version;
208
209         struct gpio_chip        gpio;
210         struct irq_chip         irq_chip;
211         struct mutex            irq_lock;
212         int                     irq_base;
213         u32                     irq_en;
214         u8                      mask_cache[3];
215         u8                      mask_reg[3];
216         u8                      cont_int_mask_reg;
217         u8                      cont_int_mask_cache;
218         u8                      cont_int_en;
219         u8                      prev_cont_stat1;
220         struct tps80031_client  tps_clients[TPS_NUM_SLAVES];
221 };
222
223 static inline int __tps80031_read(struct i2c_client *client,
224                                   int reg, uint8_t *val)
225 {
226         int ret;
227
228         ret = i2c_smbus_read_byte_data(client, reg);
229         if (ret < 0) {
230                 dev_err(&client->dev,
231                         "failed reading from addr 0x%02x, reg 0x%02x\n",
232                         client->addr, reg);
233                 return ret;
234         }
235
236         *val = (uint8_t)ret;
237
238         return 0;
239 }
240
241 static inline int __tps80031_reads(struct i2c_client *client, int reg,
242                                 int len, uint8_t *val)
243 {
244         int ret;
245
246         ret = i2c_smbus_read_i2c_block_data(client, reg, len, val);
247         if (ret < 0) {
248                 dev_err(&client->dev,
249                         "failed reading from addr 0x%02x, reg   0x%02x\n",
250                          client->addr, reg);
251                 return ret;
252         }
253
254         return 0;
255 }
256
257 static inline int __tps80031_write(struct i2c_client *client,
258                                  int reg, uint8_t val)
259 {
260         int ret;
261         ret = i2c_smbus_write_byte_data(client, reg, val);
262         if (ret < 0) {
263                 dev_err(&client->dev,
264                         "failed writing 0x%02x to 0x%02x\n", val, reg);
265                 return ret;
266         }
267
268         return 0;
269 }
270
271 static inline int __tps80031_writes(struct i2c_client *client, int reg,
272                                   int len, uint8_t *val)
273 {
274         int ret;
275
276         ret = i2c_smbus_write_i2c_block_data(client, reg, len, val);
277         if (ret < 0) {
278                 dev_err(&client->dev, "failed writings to 0x%02x\n", reg);
279                 return ret;
280         }
281
282         return 0;
283 }
284
285 int tps80031_write(struct device *dev, int sid, int reg, uint8_t val)
286 {
287         struct tps80031 *tps80031 = dev_get_drvdata(dev);
288         struct tps80031_client *tps = &tps80031->tps_clients[sid];
289         int ret;
290
291         mutex_lock(&tps->lock);
292         ret = __tps80031_write(tps->client, reg, val);
293         mutex_unlock(&tps->lock);
294
295         return ret;
296 }
297 EXPORT_SYMBOL_GPL(tps80031_write);
298
299 int tps80031_writes(struct device *dev, int sid, int reg, int len, uint8_t *val)
300 {
301         struct tps80031 *tps80031 = dev_get_drvdata(dev);
302         struct tps80031_client *tps = &tps80031->tps_clients[sid];
303         int ret;
304
305         mutex_lock(&tps->lock);
306         ret = __tps80031_writes(tps->client, reg, len, val);
307         mutex_unlock(&tps->lock);
308
309         return ret;
310 }
311 EXPORT_SYMBOL_GPL(tps80031_writes);
312
313 int tps80031_read(struct device *dev, int sid, int reg, uint8_t *val)
314 {
315         struct tps80031 *tps80031 = dev_get_drvdata(dev);
316         struct tps80031_client *tps = &tps80031->tps_clients[sid];
317
318         return __tps80031_read(tps->client, reg, val);
319 }
320 EXPORT_SYMBOL_GPL(tps80031_read);
321
322 int tps80031_reads(struct device *dev, int sid, int reg, int len, uint8_t *val)
323 {
324         struct tps80031 *tps80031 = dev_get_drvdata(dev);
325         struct tps80031_client *tps = &tps80031->tps_clients[sid];
326
327         return __tps80031_reads(tps->client, reg, len, val);
328 }
329 EXPORT_SYMBOL_GPL(tps80031_reads);
330
331 int tps80031_set_bits(struct device *dev, int sid, int reg, uint8_t bit_mask)
332 {
333         struct tps80031 *tps80031 = dev_get_drvdata(dev);
334         struct tps80031_client *tps = &tps80031->tps_clients[sid];
335         uint8_t reg_val;
336         int ret = 0;
337
338         mutex_lock(&tps->lock);
339
340         ret = __tps80031_read(tps->client, reg, &reg_val);
341         if (ret)
342                 goto out;
343
344         if ((reg_val & bit_mask) != bit_mask) {
345                 reg_val |= bit_mask;
346                 ret = __tps80031_write(tps->client, reg, reg_val);
347         }
348 out:
349         mutex_unlock(&tps->lock);
350         return ret;
351 }
352 EXPORT_SYMBOL_GPL(tps80031_set_bits);
353
354 int tps80031_clr_bits(struct device *dev, int sid, int reg, uint8_t bit_mask)
355 {
356         struct tps80031 *tps80031 = dev_get_drvdata(dev);
357         struct tps80031_client *tps = &tps80031->tps_clients[sid];
358         uint8_t reg_val;
359         int ret = 0;
360
361         mutex_lock(&tps->lock);
362
363         ret = __tps80031_read(tps->client, reg, &reg_val);
364         if (ret)
365                 goto out;
366
367         if (reg_val & bit_mask) {
368                 reg_val &= ~bit_mask;
369                 ret = __tps80031_write(tps->client, reg, reg_val);
370         }
371 out:
372         mutex_unlock(&tps->lock);
373         return ret;
374 }
375 EXPORT_SYMBOL_GPL(tps80031_clr_bits);
376
377 int tps80031_update(struct device *dev, int sid, int reg, uint8_t val,
378                 uint8_t mask)
379 {
380         struct tps80031 *tps80031 = dev_get_drvdata(dev);
381         struct tps80031_client *tps = &tps80031->tps_clients[sid];
382         uint8_t reg_val;
383         int ret = 0;
384
385         mutex_lock(&tps->lock);
386
387         ret = __tps80031_read(tps->client, reg, &reg_val);
388         if (ret)
389                 goto out;
390
391         if ((reg_val & mask) != val) {
392                 reg_val = (reg_val & ~mask) | (val & mask);
393                 ret = __tps80031_write(tps->client, reg, reg_val);
394         }
395 out:
396         mutex_unlock(&tps->lock);
397         return ret;
398 }
399 EXPORT_SYMBOL_GPL(tps80031_update);
400
401 int tps80031_force_update(struct device *dev, int sid, int reg, uint8_t val,
402                           uint8_t mask)
403 {
404         struct tps80031 *tps80031 = dev_get_drvdata(dev);
405         struct tps80031_client *tps = &tps80031->tps_clients[sid];
406         uint8_t reg_val;
407         int ret = 0;
408
409         mutex_lock(&tps->lock);
410
411         ret = __tps80031_read(tps->client, reg, &reg_val);
412         if (ret)
413                 goto out;
414
415         reg_val = (reg_val & ~mask) | (val & mask);
416         ret = __tps80031_write(tps->client, reg, reg_val);
417
418 out:
419         mutex_unlock(&tps->lock);
420         return ret;
421 }
422 EXPORT_SYMBOL_GPL(tps80031_force_update);
423
424 int tps80031_ext_power_req_config(struct device *dev,
425                 unsigned long ext_ctrl_flag, int preq_bit,
426                 int state_reg_add, int trans_reg_add)
427 {
428         u8 res_ass_reg = 0;
429         int preq_mask_bit = 0;
430         int ret;
431
432         if (!(ext_ctrl_flag & EXT_PWR_REQ))
433                 return 0;
434
435         if (ext_ctrl_flag & PWR_REQ_INPUT_PREQ1) {
436                 res_ass_reg = TPS80031_PREQ1_RES_ASS_A + (preq_bit >> 3);
437                 preq_mask_bit = 5;
438         } else if (ext_ctrl_flag & PWR_REQ_INPUT_PREQ2) {
439                 res_ass_reg = TPS80031_PREQ2_RES_ASS_A + (preq_bit >> 3);
440                 preq_mask_bit = 6;
441         } else if (ext_ctrl_flag & PWR_REQ_INPUT_PREQ3) {
442                 res_ass_reg = TPS80031_PREQ3_RES_ASS_A + (preq_bit >> 3);
443                 preq_mask_bit = 7;
444         }
445
446         /* Configure REQ_ASS registers */
447         ret = tps80031_set_bits(dev, SLAVE_ID1, res_ass_reg,
448                                         BIT(preq_bit & 0x7));
449         if (ret < 0) {
450                 dev_err(dev, "%s() Not able to set bit %d of "
451                         "reg %d error %d\n",
452                         __func__, preq_bit, res_ass_reg, ret);
453                 return ret;
454         }
455
456         /* Unmask the PREQ */
457         ret = tps80031_clr_bits(dev, SLAVE_ID1,
458                         TPS80031_PHOENIX_MSK_TRANSITION, BIT(preq_mask_bit));
459         if (ret < 0) {
460                 dev_err(dev, "%s() Not able to clear bit %d of "
461                         "reg %d error %d\n",
462                          __func__, preq_mask_bit,
463                         TPS80031_PHOENIX_MSK_TRANSITION, ret);
464                 return ret;
465         }
466
467         /* Switch regulator control to resource now */
468         if (ext_ctrl_flag & (PWR_REQ_INPUT_PREQ2 | PWR_REQ_INPUT_PREQ3)) {
469                 ret = tps80031_update(dev, SLAVE_ID1, state_reg_add, 0x0,
470                                                 STATE_MASK);
471                 if (ret < 0)
472                         dev_err(dev, "%s() Error in writing the STATE "
473                                 "register %d error %d\n", __func__,
474                                 state_reg_add, ret);
475         } else {
476                 ret = tps80031_update(dev, SLAVE_ID1, trans_reg_add,
477                                 TRANS_SLEEP_OFF, TRANS_SLEEP_MASK);
478                 if (ret < 0)
479                         dev_err(dev, "%s() Error in writing the TRANS "
480                                 "register %d error %d\n", __func__,
481                                 trans_reg_add, ret);
482         }
483         return ret;
484 }
485 EXPORT_SYMBOL_GPL(tps80031_ext_power_req_config);
486
487 unsigned long tps80031_get_chip_info(struct device *dev)
488 {
489         struct tps80031 *tps80031 = dev_get_drvdata(dev);
490         return tps80031->chip_info;
491 }
492 EXPORT_SYMBOL_GPL(tps80031_get_chip_info);
493
494 int tps80031_get_pmu_version(struct device *dev)
495 {
496         struct tps80031 *tps80031 = dev_get_drvdata(dev);
497         return tps80031->es_version;
498 }
499 EXPORT_SYMBOL_GPL(tps80031_get_pmu_version);
500
501 static struct tps80031 *tps80031_dev;
502 static void tps80031_power_off(void)
503 {
504         struct tps80031_client *tps = &tps80031_dev->tps_clients[SLAVE_ID1];
505
506         if (!tps->client)
507                 return;
508         dev_info(&tps->client->dev, "switching off PMU\n");
509         __tps80031_write(tps->client, TPS80031_PHOENIX_DEV_ON, DEVOFF);
510 }
511
512 static void tps80031_init_ext_control(struct tps80031 *tps80031,
513                         struct tps80031_platform_data *pdata) {
514         int ret;
515         int i;
516
517         /* Clear all external control for this rail */
518         for (i = 0; i < 9; ++i) {
519                 tps80031_write(tps80031->dev, SLAVE_ID1,
520                                 TPS80031_PREQ1_RES_ASS_A + i, 0);
521                 if (ret < 0)
522                         dev_err(tps80031->dev, "%s() Error in clearing "
523                                 "register %02x\n", __func__,
524                                 TPS80031_PREQ1_RES_ASS_A + i);
525         }
526
527         /* Mask the PREQ */
528         ret = tps80031_set_bits(tps80031->dev, SLAVE_ID1,
529                         TPS80031_PHOENIX_MSK_TRANSITION, 0x7 << 5);
530         if (ret < 0)
531                 dev_err(tps80031->dev, "%s() Not able to mask register "
532                         "0x%02x\n", __func__, TPS80031_PHOENIX_MSK_TRANSITION);
533 }
534
535 static int tps80031_gpio_get(struct gpio_chip *gc, unsigned offset)
536 {
537         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
538         struct tps80031_client *tps = &tps80031->tps_clients[SLAVE_ID1];
539         uint8_t state;
540         uint8_t trans;
541         int ret;
542
543         ret = __tps80031_read(tps->client,
544                         pmc_ext_control_base[offset] +
545                                 EXT_CONTROL_CFG_STATE, &state);
546         if (ret)
547                 return ret;
548
549         if (state != 0) {
550                 ret = __tps80031_read(tps->client,
551                                 pmc_ext_control_base[offset] +
552                                         EXT_CONTROL_CFG_TRANS, &trans);
553                 if (ret)
554                         return ret;
555                 return trans & 0x1;
556         }
557         return 0;
558 }
559
560 static void tps80031_gpio_set(struct gpio_chip *gc, unsigned offset,
561                         int value)
562 {
563         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
564
565         tps80031_update(tps80031->dev, SLAVE_ID1,
566                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_TRANS,
567                         value, 0x1);
568 }
569
570 static int tps80031_gpio_input(struct gpio_chip *gc, unsigned offset)
571 {
572         return -EIO;
573 }
574
575 static int tps80031_gpio_output(struct gpio_chip *gc, unsigned offset,
576                                 int value)
577 {
578         tps80031_gpio_set(gc, offset, value);
579         return 0;
580 }
581
582 static int tps80031_gpio_enable(struct gpio_chip *gc, unsigned offset)
583 {
584         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
585         int ret;
586
587         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
588                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_STATE,
589                                                 STATE_ON, STATE_MASK);
590         if (ret)
591                 return ret;
592
593         return tps80031_write(tps80031->dev, SLAVE_ID1,
594                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_TRANS, 0x0);
595 }
596
597 static void tps80031_gpio_disable(struct gpio_chip *gc, unsigned offset)
598 {
599         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
600         tps80031_update(tps80031->dev, SLAVE_ID1,
601                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_STATE,
602                                                 STATE_OFF, STATE_MASK);
603 }
604
605 static void tps80031_gpio_init(struct tps80031 *tps80031,
606                         struct tps80031_platform_data *pdata)
607 {
608         int ret;
609         int gpio_base = pdata->gpio_base;
610         struct tps80031_client *tps = &tps80031->tps_clients[SLAVE_ID1];
611         struct tps80031_gpio_init_data *gpio_init_data = pdata->gpio_init_data;
612         int data_size = pdata->gpio_init_data_size;
613         static int preq_bit_pos[TPS80031_GPIO_NR] = {16, 17, 18};
614         int base_add;
615         int i;
616
617         if (gpio_base <= 0)
618                 return;
619
620         /* Configure the external request mode */
621         for (i = 0; i < data_size; ++i) {
622                 struct tps80031_gpio_init_data *gpio_pd = &gpio_init_data[i];
623                 base_add = pmc_ext_control_base[gpio_pd->gpio_nr];
624
625                 if (gpio_pd->ext_ctrl_flag & EXT_PWR_REQ) {
626                         ret = tps80031_ext_power_req_config(tps80031->dev,
627                                 gpio_pd->ext_ctrl_flag,
628                                 preq_bit_pos[gpio_pd->gpio_nr],
629                                 base_add + EXT_CONTROL_CFG_STATE,
630                                 base_add + EXT_CONTROL_CFG_TRANS);
631                         if (ret < 0)
632                                 dev_warn(tps80031->dev, "Ext pwrreq GPIO "
633                                         "sleep control fails\n");
634                 }
635
636                 if (gpio_pd->ext_ctrl_flag & PWR_OFF_ON_SLEEP) {
637                         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
638                                 base_add + EXT_CONTROL_CFG_TRANS, 0x0, 0xC);
639                         if (ret < 0)
640                                 dev_warn(tps80031->dev, "GPIO OFF on sleep "
641                                         "control fails\n");
642                 }
643
644                 if (gpio_pd->ext_ctrl_flag & PWR_ON_ON_SLEEP) {
645                         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
646                                 base_add + EXT_CONTROL_CFG_TRANS, 0x4, 0xC);
647                         if (ret < 0)
648                                 dev_warn(tps80031->dev, "GPIO ON on sleep "
649                                         "control fails\n");
650                 }
651         }
652
653         tps80031->gpio.owner            = THIS_MODULE;
654         tps80031->gpio.label            = tps->client->name;
655         tps80031->gpio.dev              = tps80031->dev;
656         tps80031->gpio.base             = gpio_base;
657         tps80031->gpio.ngpio            = TPS80031_GPIO_NR;
658         tps80031->gpio.can_sleep        = 1;
659
660         tps80031->gpio.request          = tps80031_gpio_enable;
661         tps80031->gpio.free             = tps80031_gpio_disable;
662         tps80031->gpio.direction_input  = tps80031_gpio_input;
663         tps80031->gpio.direction_output = tps80031_gpio_output;
664         tps80031->gpio.set              = tps80031_gpio_set;
665         tps80031->gpio.get              = tps80031_gpio_get;
666
667         ret = gpiochip_add(&tps80031->gpio);
668         if (ret)
669                 dev_warn(tps80031->dev, "GPIO registration failed: %d\n", ret);
670 }
671
672 static int __remove_subdev(struct device *dev, void *unused)
673 {
674         platform_device_unregister(to_platform_device(dev));
675         return 0;
676 }
677
678 static int tps80031_remove_subdevs(struct tps80031 *tps80031)
679 {
680         return device_for_each_child(tps80031->dev, NULL, __remove_subdev);
681 }
682
683 static void tps80031_irq_lock(struct irq_data *data)
684 {
685         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
686
687         mutex_lock(&tps80031->irq_lock);
688 }
689
690 static void tps80031_irq_enable(struct irq_data *data)
691 {
692         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
693         unsigned int __irq = data->irq - tps80031->irq_base;
694         const struct tps80031_irq_data *irq_data = &tps80031_irqs[__irq];
695
696         if (irq_data->is_sec_int) {
697                 tps80031->cont_int_mask_reg &= ~(1 << irq_data->int_mask_bit);
698                 tps80031->cont_int_en |= (1 << irq_data->int_mask_bit);
699                 tps80031->mask_reg[irq_data->mask_reg] &= ~(1 << irq_data->mask_mask);
700                 tps80031->irq_en |= (1 << irq_data->parent_int);
701         } else
702                 tps80031->mask_reg[irq_data->mask_reg] &= ~(1 << irq_data->mask_mask);
703
704         tps80031->irq_en |= (1 << __irq);
705 }
706
707 static void tps80031_irq_disable(struct irq_data *data)
708 {
709         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
710
711         unsigned int __irq = data->irq - tps80031->irq_base;
712         const struct tps80031_irq_data *irq_data = &tps80031_irqs[__irq];
713
714         if (irq_data->is_sec_int) {
715                 tps80031->cont_int_mask_reg |= (1 << irq_data->int_mask_bit);
716                 tps80031->cont_int_en &= ~(1 << irq_data->int_mask_bit);
717                 if (!tps80031->cont_int_en) {
718                         tps80031->mask_reg[irq_data->mask_reg] |=
719                                                 (1 << irq_data->mask_mask);
720                         tps80031->irq_en &= ~(1 << irq_data->parent_int);
721                 }
722                 tps80031->irq_en &= ~(1 << __irq);
723         } else
724                 tps80031->mask_reg[irq_data->mask_reg] |= (1 << irq_data->mask_mask);
725
726         tps80031->irq_en &= ~(1 << __irq);
727 }
728
729 static void tps80031_irq_sync_unlock(struct irq_data *data)
730 {
731         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
732         int i;
733
734         for (i = 0; i < ARRAY_SIZE(tps80031->mask_reg); i++) {
735                 if (tps80031->mask_reg[i] != tps80031->mask_cache[i]) {
736                         if (!WARN_ON(tps80031_write(tps80031->dev, SLAVE_ID2,
737                                                 TPS80031_INT_MSK_LINE_A + i,
738                                                 tps80031->mask_reg[i])))
739                                 if (!WARN_ON(tps80031_write(tps80031->dev,
740                                                 SLAVE_ID2,
741                                                 TPS80031_INT_MSK_STS_A + i,
742                                                 tps80031->mask_reg[i])))
743                                         tps80031->mask_cache[i] =
744                                                         tps80031->mask_reg[i];
745                 }
746         }
747
748         if (tps80031->cont_int_mask_reg != tps80031->cont_int_mask_cache) {
749                 if (!WARN_ON(tps80031_write(tps80031->dev, SLAVE_ID2,
750                                 TPS80031_CONTROLLER_INT_MASK,
751                                 tps80031->cont_int_mask_reg)))
752                         tps80031->cont_int_mask_cache =
753                                                 tps80031->cont_int_mask_reg;
754         }
755
756         mutex_unlock(&tps80031->irq_lock);
757 }
758
759 static irqreturn_t tps80031_charge_control_irq(int irq, void *data)
760 {
761         struct tps80031 *tps80031 = data;
762         int ret = 0;
763         int i;
764         u8 cont_sts;
765         u8 org_sts;
766         if (irq != (tps80031->irq_base + TPS80031_INT_CHRG_CTRL)) {
767                 dev_err(tps80031->dev, "%s() Got the illegal interrupt %d\n",
768                                         __func__, irq);
769                 return IRQ_NONE;
770         }
771
772         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
773                         TPS80031_CONTROLLER_STAT1, &org_sts);
774         if (ret < 0) {
775                 dev_err(tps80031->dev, "%s(): failed to read controller state1 "
776                                 "status %d\n", __func__, ret);
777                 return IRQ_NONE;
778         }
779
780         /* Get change from last interrupt and mask for interested interrupt
781          * for charge control interrupt */
782         cont_sts = org_sts ^ tps80031->prev_cont_stat1;
783         tps80031->prev_cont_stat1 = org_sts;
784         /* Clear watchdog timer state */
785         tps80031->prev_cont_stat1 &= ~(1 << 4);
786         cont_sts &= 0x5F;
787
788         for (i = 0; i < 8; ++i) {
789                 if (!controller_stat1_irq_nr[i])
790                         continue;
791
792                 if ((cont_sts & BIT(i)) &&
793                         (tps80031->irq_en & BIT(controller_stat1_irq_nr[i])))
794                         handle_nested_irq(tps80031->irq_base +
795                                                 controller_stat1_irq_nr[i]);
796                 cont_sts &= ~BIT(i);
797         }
798         return IRQ_HANDLED;
799 }
800
801 static irqreturn_t tps80031_irq(int irq, void *data)
802 {
803         struct tps80031 *tps80031 = data;
804         int ret = 0;
805         u32 acks;
806         int i;
807         uint8_t tmp[3];
808
809         ret = tps80031_reads(tps80031->dev, SLAVE_ID2,
810                              TPS80031_INT_STS_A, 3, tmp);
811         if (ret < 0) {
812                 dev_err(tps80031->dev, "failed to read interrupt status\n");
813                 return IRQ_NONE;
814         }
815         acks = (tmp[2] << 16) | (tmp[1] << 8) | tmp[0];
816
817         if (acks) {
818                 ret = tps80031_writes(tps80031->dev, SLAVE_ID2,
819                                       TPS80031_INT_STS_A, 3, tmp);
820                 if (ret < 0) {
821                         dev_err(tps80031->dev, "failed to write "
822                                                 "interrupt status\n");
823                         return IRQ_NONE;
824                 }
825
826                 while (acks) {
827                         i = __ffs(acks);
828                         if (tps80031->irq_en & (1 << i))
829                                 handle_nested_irq(tps80031->irq_base + i);
830                         acks &= ~(1 << i);
831                 }
832         }
833
834         return IRQ_HANDLED;
835 }
836
837 static int __devinit tps80031_irq_init(struct tps80031 *tps80031, int irq,
838                                 int irq_base)
839 {
840         int i, ret;
841
842         if (!irq_base) {
843                 dev_warn(tps80031->dev, "No interrupt support on IRQ base\n");
844                 return -EINVAL;
845         }
846
847         mutex_init(&tps80031->irq_lock);
848
849         for (i = 0; i < 3; i++) {
850                 tps80031->mask_reg[i] = 0xFF;
851                 tps80031->mask_cache[i] = tps80031->mask_reg[i];
852                 tps80031_write(tps80031->dev, SLAVE_ID2,
853                                         TPS80031_INT_MSK_LINE_A + i,
854                                         tps80031->mask_cache[i]);
855                 tps80031_write(tps80031->dev, SLAVE_ID2,
856                                         TPS80031_INT_MSK_STS_A + i, 0xFF);
857                 tps80031_write(tps80031->dev, SLAVE_ID2,
858                                         TPS80031_INT_STS_A + i, 0xFF);
859         }
860
861         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
862                                 TPS80031_CONTROLLER_INT_MASK,
863                                 &tps80031->cont_int_mask_reg);
864         if (ret < 0) {
865                 dev_err(tps80031->dev, "Error in reading the controller_mask "
866                                         "register %d\n", ret);
867                 return ret;
868         }
869
870         tps80031->cont_int_mask_reg |= CHARGE_CONTROL_SUB_INT_MASK;
871         tps80031->cont_int_mask_cache = tps80031->cont_int_mask_reg;
872         tps80031->cont_int_en = 0;
873         ret = tps80031_write(tps80031->dev, SLAVE_ID2,
874                                 TPS80031_CONTROLLER_INT_MASK,
875                                 tps80031->cont_int_mask_reg);
876         if (ret < 0) {
877                 dev_err(tps80031->dev, "Error in writing the controller_mask "
878                                         "register %d\n", ret);
879                 return ret;
880         }
881
882         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
883                         TPS80031_CONTROLLER_STAT1, &tps80031->prev_cont_stat1);
884         if (ret < 0) {
885                 dev_err(tps80031->dev, "%s(): failed to read controller state1 "
886                                 "status %d\n", __func__, ret);
887                 return ret;
888         }
889
890         /* Clear watch dog interrupt status in status */
891         tps80031->prev_cont_stat1 &= ~(1 << 4);
892
893         tps80031->irq_base = irq_base;
894
895         tps80031->irq_chip.name = "tps80031";
896         tps80031->irq_chip.irq_enable = tps80031_irq_enable;
897         tps80031->irq_chip.irq_disable = tps80031_irq_disable;
898         tps80031->irq_chip.irq_bus_lock = tps80031_irq_lock;
899         tps80031->irq_chip.irq_bus_sync_unlock = tps80031_irq_sync_unlock;
900
901         for (i = 0; i < TPS80031_INT_NR; i++) {
902                 int __irq = i + tps80031->irq_base;
903                 irq_set_chip_data(__irq, tps80031);
904                 irq_set_chip_and_handler(__irq, &tps80031->irq_chip,
905                                          handle_simple_irq);
906                 irq_set_nested_thread(__irq, 1);
907 #ifdef CONFIG_ARM
908                 set_irq_flags(__irq, IRQF_VALID);
909 #endif
910         }
911
912         ret = request_threaded_irq(irq, NULL, tps80031_irq, IRQF_ONESHOT,
913                                 "tps80031", tps80031);
914         /* register the isr for the secondary interrupt */
915         if (!ret)
916                 ret = request_threaded_irq(irq_base + TPS80031_INT_CHRG_CTRL,
917                                 NULL, tps80031_charge_control_irq,
918                                 IRQF_ONESHOT, "80031_chg_ctl", tps80031);
919         if (!ret) {
920
921                 device_init_wakeup(tps80031->dev, 1);
922                 enable_irq_wake(irq);
923         }
924
925         return ret;
926 }
927
928 static void tps80031_clk32k_enable(struct tps80031 *tps80031, int base_add)
929 {
930         int ret;
931         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
932                         base_add + EXT_CONTROL_CFG_STATE, STATE_ON, STATE_MASK);
933         if (!ret)
934                 ret = tps80031_update(tps80031->dev, SLAVE_ID1,
935                                 base_add + EXT_CONTROL_CFG_TRANS,
936                                 STATE_ON, STATE_MASK);
937         if (ret < 0)
938                 dev_err(tps80031->dev, "Error in updating clock register\n");
939 }
940
941 static void tps80031_clk32k_init(struct tps80031 *tps80031,
942                         struct tps80031_platform_data *pdata)
943 {
944         int ret;
945         struct tps80031_clk32k_init_data *clk32_idata = pdata->clk32k_init_data;
946         int data_size = pdata->clk32k_init_data_size;
947         static int clk32k_preq_bit_pos[TPS80031_CLOCK32K_NR] = {-1, 20, 19};
948         int base_add;
949         int i;
950
951         if (!clk32_idata || !data_size)
952                 return;
953
954         /* Configure the external request mode */
955         for (i = 0; i < data_size; ++i) {
956                 struct tps80031_clk32k_init_data *clk32_pd =  &clk32_idata[i];
957                 base_add = pmc_clk32k_control_base[clk32_pd->clk32k_nr];
958                 if (clk32_pd->enable)
959                         tps80031_clk32k_enable(tps80031, base_add);
960
961                 if ((clk32_pd->ext_ctrl_flag & EXT_PWR_REQ) &&
962                          (clk32k_preq_bit_pos[clk32_pd->clk32k_nr] != -1)) {
963                         ret = tps80031_ext_power_req_config(tps80031->dev,
964                                 clk32_pd->ext_ctrl_flag,
965                                 clk32k_preq_bit_pos[clk32_pd->clk32k_nr],
966                                 base_add + EXT_CONTROL_CFG_STATE,
967                                 base_add + EXT_CONTROL_CFG_TRANS);
968                         if (ret < 0)
969                                 dev_warn(tps80031->dev, "Clk32 ext control "
970                                         "fails\n");
971                 }
972
973                 if (clk32_pd->ext_ctrl_flag & PWR_OFF_ON_SLEEP) {
974                         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
975                                 base_add + EXT_CONTROL_CFG_TRANS, 0x0, 0xC);
976                         if (ret < 0)
977                                 dev_warn(tps80031->dev, "clk OFF on sleep "
978                                         "control fails\n");
979                 }
980
981                 if (clk32_pd->ext_ctrl_flag & PWR_ON_ON_SLEEP) {
982                         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
983                                 base_add + EXT_CONTROL_CFG_TRANS, 0x4, 0xC);
984                         if (ret < 0)
985                                 dev_warn(tps80031->dev, "clk ON sleep "
986                                         "control fails\n");
987                 }
988         }
989 }
990
991 static int __devinit tps80031_add_subdevs(struct tps80031 *tps80031,
992                                           struct tps80031_platform_data *pdata)
993 {
994         struct tps80031_subdev_info *subdev;
995         struct platform_device *pdev;
996         int i, ret = 0;
997
998         for (i = 0; i < pdata->num_subdevs; i++) {
999                 subdev = &pdata->subdevs[i];
1000
1001                 pdev = platform_device_alloc(subdev->name, subdev->id);
1002
1003                 pdev->dev.parent = tps80031->dev;
1004                 pdev->dev.platform_data = subdev->platform_data;
1005
1006                 ret = platform_device_add(pdev);
1007                 if (ret)
1008                         goto failed;
1009         }
1010         return 0;
1011
1012 failed:
1013         tps80031_remove_subdevs(tps80031);
1014         return ret;
1015 }
1016
1017 #ifdef CONFIG_DEBUG_FS
1018 #include <linux/debugfs.h>
1019 #include <linux/seq_file.h>
1020 static void print_regs(const char *header, struct seq_file *s,
1021                 int sid, int start_offset, int end_offset)
1022 {
1023         struct tps80031 *tps80031 = s->private;
1024         struct tps80031_client *tps = &tps80031->tps_clients[sid];
1025         uint8_t reg_val;
1026         int i;
1027         int ret;
1028
1029         seq_printf(s, "%s\n", header);
1030         for (i = start_offset; i <= end_offset; ++i) {
1031                 ret = __tps80031_read(tps->client, i, &reg_val);
1032                 if (ret >= 0)
1033                         seq_printf(s, "Addr = 0x%02x Reg 0x%02x Value 0x%02x\n",
1034                                                 tps->client->addr, i, reg_val);
1035         }
1036         seq_printf(s, "------------------\n");
1037 }
1038
1039 static int dbg_tps_show(struct seq_file *s, void *unused)
1040 {
1041         seq_printf(s, "TPS80031 Registers\n");
1042         seq_printf(s, "------------------\n");
1043         print_regs("VIO Regs",       s, SLAVE_ID1, 0x47, 0x49);
1044         print_regs("VIO Regs",       s, SLAVE_ID0, 0x49, 0x4A);
1045         print_regs("SMPS1 Regs",     s, SLAVE_ID1, 0x53, 0x54);
1046         print_regs("SMPS1 Regs",     s, SLAVE_ID0, 0x55, 0x56);
1047         print_regs("SMPS1 Regs",     s, SLAVE_ID1, 0x57, 0x57);
1048         print_regs("SMPS2 Regs",     s, SLAVE_ID1, 0x59, 0x5B);
1049         print_regs("SMPS2 Regs",     s, SLAVE_ID0, 0x5B, 0x5C);
1050         print_regs("SMPS2 Regs",     s, SLAVE_ID1, 0x5C, 0x5D);
1051         print_regs("SMPS3 Regs",     s, SLAVE_ID1, 0x65, 0x68);
1052         print_regs("SMPS4 Regs",     s, SLAVE_ID1, 0x41, 0x44);
1053         print_regs("VANA Regs",      s, SLAVE_ID1, 0x81, 0x83);
1054         print_regs("VRTC Regs",      s, SLAVE_ID1, 0xC3, 0xC4);
1055         print_regs("LDO1 Regs",      s, SLAVE_ID1, 0x9D, 0x9F);
1056         print_regs("LDO2 Regs",      s, SLAVE_ID1, 0x85, 0x87);
1057         print_regs("LDO3 Regs",      s, SLAVE_ID1, 0x8D, 0x8F);
1058         print_regs("LDO4 Regs",      s, SLAVE_ID1, 0x89, 0x8B);
1059         print_regs("LDO5 Regs",      s, SLAVE_ID1, 0x99, 0x9B);
1060         print_regs("LDO6 Regs",      s, SLAVE_ID1, 0x91, 0x93);
1061         print_regs("LDO7 Regs",      s, SLAVE_ID1, 0xA5, 0xA7);
1062         print_regs("LDOUSB Regs",    s, SLAVE_ID1, 0xA1, 0xA3);
1063         print_regs("LDOLN Regs",     s, SLAVE_ID1, 0x95, 0x97);
1064         print_regs("REGEN1 Regs",    s, SLAVE_ID1, 0xAE, 0xAF);
1065         print_regs("REGEN2 Regs",    s, SLAVE_ID1, 0xB1, 0xB2);
1066         print_regs("SYSEN Regs",     s, SLAVE_ID1, 0xB4, 0xB5);
1067         print_regs("CLK32KAO Regs",  s, SLAVE_ID1, 0xBA, 0xBB);
1068         print_regs("CLK32KG Regs",   s, SLAVE_ID1, 0xBD, 0xBE);
1069         print_regs("CLK32KAUD Regs", s, SLAVE_ID1, 0xC0, 0xC1);
1070         print_regs("INT Regs",       s, SLAVE_ID2, 0xD0, 0xD8);
1071         print_regs("PREQ Regs",      s, SLAVE_ID1, 0xD7, 0xDF);
1072         print_regs("MASK_PH Regs",   s, SLAVE_ID1, 0x20, 0x21);
1073         print_regs("PMC MISC Regs",  s, SLAVE_ID1, 0xE0, 0xEF);
1074         print_regs("CONT_STATE",     s, SLAVE_ID2, 0xE0, 0xE4);
1075         print_regs("VERNUM Regs",    s, SLAVE_ID3, 0x87, 0x87);
1076         print_regs("EEPROM Regs",    s, SLAVE_ID3, 0xDF, 0xDF);
1077         print_regs("CHARGE Regs",    s, SLAVE_ID2, 0xDA, 0xF5);
1078         return 0;
1079 }
1080
1081 static int dbg_tps_open(struct inode *inode, struct file *file)
1082 {
1083         return single_open(file, dbg_tps_show, inode->i_private);
1084 }
1085
1086 static const struct file_operations debug_fops = {
1087         .open           = dbg_tps_open,
1088         .read           = seq_read,
1089         .llseek         = seq_lseek,
1090         .release        = single_release,
1091 };
1092
1093 static void __init tps80031_debuginit(struct tps80031 *tps)
1094 {
1095         (void)debugfs_create_file("tps80031", S_IRUGO, NULL,
1096                         tps, &debug_fops);
1097 }
1098 #else
1099 static void __init tps80031_debuginit(struct tps80031 *tpsi)
1100 {
1101         return;
1102 }
1103 #endif
1104
1105 static int __devexit tps80031_i2c_remove(struct i2c_client *client)
1106 {
1107         struct tps80031 *tps80031 = i2c_get_clientdata(client);
1108         int i;
1109
1110         if (client->irq)
1111                 free_irq(client->irq, tps80031);
1112
1113         if (tps80031->gpio.owner != NULL)
1114                 if (gpiochip_remove(&tps80031->gpio) < 0)
1115                         dev_err(&client->dev, "Error in removing the gpio driver\n");
1116
1117         for (i = 0; i < TPS_NUM_SLAVES; i++) {
1118                 struct tps80031_client *tps = &tps80031->tps_clients[i];
1119                 if (tps->client && tps->client != client)
1120                         i2c_unregister_device(tps->client);
1121                 tps80031->tps_clients[i].client = NULL;
1122                 mutex_destroy(&tps->lock);
1123         }
1124
1125         kfree(tps80031);
1126         return 0;
1127 }
1128
1129 static int __devinit tps80031_i2c_probe(struct i2c_client *client,
1130                                         const struct i2c_device_id *id)
1131 {
1132         struct tps80031_platform_data *pdata = client->dev.platform_data;
1133         struct tps80031 *tps80031;
1134         struct tps80031_client *tps;
1135         int ret;
1136         int jtag_ver;
1137         int ep_ver;
1138         int i;
1139
1140         if (!pdata) {
1141                 dev_err(&client->dev, "tps80031 requires platform data\n");
1142                 return -ENOTSUPP;
1143         }
1144
1145         jtag_ver = i2c_smbus_read_byte_data(client, TPS80031_JTAGVERNUM);
1146         if (jtag_ver < 0) {
1147                 dev_err(&client->dev, "Silicon version number read"
1148                                 " failed: %d\n", jtag_ver);
1149                 return -EIO;
1150         }
1151
1152         ep_ver = i2c_smbus_read_byte_data(client, TPS80031_EPROM_REV);
1153         if (ep_ver < 0) {
1154                 dev_err(&client->dev, "Silicon eeprom version read"
1155                                 " failed: %d\n", ep_ver);
1156                 return -EIO;
1157         }
1158
1159         dev_info(&client->dev, "Jtag version 0x%02x and Eeprom version 0x%02x\n",
1160                                                 jtag_ver, ep_ver);
1161
1162         tps80031 = kzalloc(sizeof(struct tps80031), GFP_KERNEL);
1163         if (tps80031 == NULL)
1164                 return -ENOMEM;
1165
1166         tps80031->es_version = jtag_ver;
1167         tps80031->dev = &client->dev;
1168         i2c_set_clientdata(client, tps80031);
1169         tps80031->chip_info = id->driver_data;
1170
1171         /* Set up slaves */
1172         tps80031->tps_clients[SLAVE_ID0].addr = I2C_ID0_ADDR;
1173         tps80031->tps_clients[SLAVE_ID1].addr = I2C_ID1_ADDR;
1174         tps80031->tps_clients[SLAVE_ID2].addr = I2C_ID2_ADDR;
1175         tps80031->tps_clients[SLAVE_ID3].addr = I2C_ID3_ADDR;
1176         for (i = 0; i < TPS_NUM_SLAVES; i++) {
1177                 tps = &tps80031->tps_clients[i];
1178                 if (tps->addr == client->addr)
1179                         tps->client = client;
1180                 else
1181                         tps->client = i2c_new_dummy(client->adapter,
1182                                                 tps->addr);
1183                 if (!tps->client) {
1184                         dev_err(&client->dev, "can't attach client %d\n", i);
1185                         ret = -ENOMEM;
1186                         goto fail;
1187                 }
1188                 i2c_set_clientdata(tps->client, tps80031);
1189                 mutex_init(&tps->lock);
1190         }
1191
1192         if (client->irq) {
1193                 ret = tps80031_irq_init(tps80031, client->irq,
1194                                         pdata->irq_base);
1195                 if (ret) {
1196                         dev_err(&client->dev, "IRQ init failed: %d\n", ret);
1197                         goto fail;
1198                 }
1199         }
1200         tps80031_init_ext_control(tps80031, pdata);
1201
1202         ret = tps80031_add_subdevs(tps80031, pdata);
1203         if (ret) {
1204                 dev_err(&client->dev, "add devices failed: %d\n", ret);
1205                 goto fail;
1206         }
1207
1208         tps80031_gpio_init(tps80031, pdata);
1209
1210         tps80031_clk32k_init(tps80031, pdata);
1211
1212         tps80031_debuginit(tps80031);
1213
1214         if (pdata->use_power_off && !pm_power_off)
1215                 pm_power_off = tps80031_power_off;
1216
1217         tps80031_dev = tps80031;
1218
1219         return 0;
1220
1221 fail:
1222         tps80031_i2c_remove(client);
1223         return ret;
1224 }
1225
1226 #ifdef CONFIG_PM
1227 static int tps80031_i2c_suspend(struct i2c_client *client, pm_message_t state)
1228 {
1229         if (client->irq)
1230                 disable_irq(client->irq);
1231         return 0;
1232 }
1233
1234 static int tps80031_i2c_resume(struct i2c_client *client)
1235 {
1236         if (client->irq)
1237                 enable_irq(client->irq);
1238         return 0;
1239 }
1240 #endif
1241
1242
1243 static const struct i2c_device_id tps80031_id_table[] = {
1244         { "tps80031", TPS80031 },
1245         { "tps80032", TPS80032 },
1246 };
1247 MODULE_DEVICE_TABLE(i2c, tps80031_id_table);
1248
1249 static struct i2c_driver tps80031_driver = {
1250         .driver = {
1251                 .name   = "tps80031",
1252                 .owner  = THIS_MODULE,
1253         },
1254         .probe          = tps80031_i2c_probe,
1255         .remove         = __devexit_p(tps80031_i2c_remove),
1256 #ifdef CONFIG_PM
1257         .suspend        = tps80031_i2c_suspend,
1258         .resume         = tps80031_i2c_resume,
1259 #endif
1260         .id_table       = tps80031_id_table,
1261 };
1262
1263 static int __init tps80031_init(void)
1264 {
1265         return i2c_add_driver(&tps80031_driver);
1266 }
1267 subsys_initcall(tps80031_init);
1268
1269 static void __exit tps80031_exit(void)
1270 {
1271         i2c_del_driver(&tps80031_driver);
1272 }
1273 module_exit(tps80031_exit);
1274
1275 MODULE_DESCRIPTION("TPS80031 core driver");
1276 MODULE_LICENSE("GPL");