power: tps80031: battery-gauge: register as mfd sub device
[linux-2.6.git] / drivers / mfd / tps80031.c
1 /*
2  * driver/mfd/tps80031.c
3  *
4  * Core driver for TI TPS80031
5  *
6  * Copyright (C) 2011 NVIDIA Corporation
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, write to the Free Software Foundation, Inc.,
20  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
21  *
22  */
23
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/mutex.h>
29 #include <linux/slab.h>
30 #include <linux/gpio.h>
31 #include <linux/i2c.h>
32 #include <linux/pm.h>
33 #include <linux/regmap.h>
34
35 #include <linux/mfd/core.h>
36 #include <linux/mfd/tps80031.h>
37
38 /* interrupt related registers */
39 #define TPS80031_INT_STS_A              0xD0
40 #define TPS80031_INT_STS_B              0xD1
41 #define TPS80031_INT_STS_C              0xD2
42 #define TPS80031_INT_MSK_LINE_A         0xD3
43 #define TPS80031_INT_MSK_LINE_B         0xD4
44 #define TPS80031_INT_MSK_LINE_C         0xD5
45 #define TPS80031_INT_MSK_STS_A          0xD6
46 #define TPS80031_INT_MSK_STS_B          0xD7
47 #define TPS80031_INT_MSK_STS_C          0xD8
48
49 #define TPS80031_CONTROLLER_STAT1               0xE3
50 #define CONTROLLER_STAT1_BAT_TEMP               0
51 #define CONTROLLER_STAT1_BAT_REMOVED            1
52 #define CONTROLLER_STAT1_VBUS_DET               2
53 #define CONTROLLER_STAT1_VAC_DET                3
54 #define CONTROLLER_STAT1_FAULT_WDG              4
55 #define CONTROLLER_STAT1_LINCH_GATED            6
56
57 #define TPS80031_CONTROLLER_INT_MASK            0xE0
58 #define CONTROLLER_INT_MASK_MVAC_DET            0
59 #define CONTROLLER_INT_MASK_MVBUS_DET           1
60 #define CONTROLLER_INT_MASK_MBAT_TEMP           2
61 #define CONTROLLER_INT_MASK_MFAULT_WDG          3
62 #define CONTROLLER_INT_MASK_MBAT_REMOVED        4
63 #define CONTROLLER_INT_MASK_MLINCH_GATED        5
64
65 #define CHARGE_CONTROL_SUB_INT_MASK             0x3F
66
67 /* Version number related register */
68 #define TPS80031_JTAGVERNUM             0x87
69 /* Epprom version */
70 #define TPS80031_EPROM_REV              0xDF
71
72 /* External control register */
73 #define REGEN1_BASE_ADD         0xAE
74 #define REGEN2_BASE_ADD         0xB1
75 #define SYSEN_BASE_ADD          0xB4
76
77 /* device control registers */
78 #define TPS80031_PHOENIX_DEV_ON 0x25
79 #define DEVOFF  1
80
81 #define CLK32KAO_BASE_ADD       0xBA
82 #define CLK32KG_BASE_ADD        0xBD
83 #define CLK32KAUDIO_BASE_ADD    0xC0
84
85 #define EXT_CONTROL_CFG_TRANS 0
86 #define EXT_CONTROL_CFG_STATE 1
87
88 #define STATE_OFF       0x00
89 #define STATE_ON        0x01
90 #define STATE_MASK      0x03
91
92 #define TRANS_SLEEP_OFF         0x00
93 #define TRANS_SLEEP_ON          0x04
94 #define TRANS_SLEEP_MASK        0x0C
95
96 #define TPS_NUM_SLAVES  4
97 #define EXT_PWR_REQ (PWR_REQ_INPUT_PREQ1 | PWR_REQ_INPUT_PREQ2 | \
98                 PWR_REQ_INPUT_PREQ3)
99 #define TPS80031_PREQ1_RES_ASS_A        0xD7
100 #define TPS80031_PREQ2_RES_ASS_A        0xDA
101 #define TPS80031_PREQ3_RES_ASS_A        0xDD
102 #define TPS80031_PHOENIX_MSK_TRANSITION 0x20
103
104 #define TPS80031_CFG_INPUT_PUPD1 0xF0
105 #define TPS80031_CFG_INPUT_PUPD2 0xF1
106 #define TPS80031_CFG_INPUT_PUPD3 0xF2
107 #define TPS80031_CFG_INPUT_PUPD4 0xF3
108
109 #define TPS80031_BBSPOR_CFG     0xE6
110 #define TPS80031_BBSPOR_CHG_EN  0x8
111
112 /* Valid Address ranges */
113 #define TPS80031_ID0_PMIC_SLAVE_SMPS_DVS        0x55 ... 0x5C
114
115 #define TPS80031_ID1_RTC                        0x00 ... 0x16
116 #define TPS80031_ID1_MEMORY                     0x17 ... 0x1E
117 #define TPS80031_ID1_PMC_MASTER                 0x1F ... 0x2D
118 #define TPS80031_ID1_PMC_SLAVE_MISC             0x31 ... 0x34
119 #define TPS80031_ID1_PMC_SLAVE_SMPS             0x40 ... 0x68
120 #define TPS80031_ID1_PMC_SLAVE_LDO              0x80 ... 0xA7
121 #define TPS80031_ID1_PMC_SLAVE_REOSURCES        0XAD ... 0xD0
122 #define TPS80031_ID1_PMC_PREQ_ASSIGN            0XD7 ... 0xDF
123 #define TPS80031_ID1_PMC_MISC                   0xE2 ... 0xEF
124 #define TPS80031_ID1_PMC_PU_PD_HZ               0xF0 ... 0xF6
125 #define TPS80031_ID1_PMC_BACKUP                 0xFA
126
127 #define TPS80031_ID2_USB                        0x00 ... 0x1A
128 #define TPS80031_ID2_GPADC_CONTROL              0x2E ... 0x36
129 #define TPS80031_ID2_GPADC_RESULTS              0x37 ... 0x3C
130 #define TPS80031_ID2_AUXILLIARIES               0x90 ... 0x9C
131 #define TPS80031_ID2_CUSTOM                     0xA0 ... 0xB9
132 #define TPS80031_ID2_PWM                        0xBA ... 0xBE
133 #define TPS80031_ID2_FUEL_GAUSE                 0xC0 ... 0xCB
134 #define TPS80031_ID2_INTERFACE_INTERRUPTS       0xD0 ... 0xD8
135 #define TPS80031_ID2_CHARGER                    0xDA ... 0xF5
136
137 #define TPS80031_ID3_TEST_LDO                   0x00 ... 0x09
138 #define TPS80031_ID3_TEST_SMPS                  0x10 ... 0x2B
139 #define TPS80031_ID3_TEST_POWER                 0x30 ... 0x36
140 #define TPS80031_ID3_TEST_CHARGER               0x40 ... 0x48
141 #define TPS80031_ID3_TEST_AUXILIIARIES          0x50 ... 0xB1
142
143 #define TPS80031_ID3_DIEID                      0xC0 ... 0xC8
144 #define TPS80031_ID3_TRIM_PHOENIX               0xCC ... 0xEA
145 #define TPS80031_ID3_TRIM_CUSTOM                0xEC ... 0xED
146
147 #define TPS80031_MAX_REGISTER   0x100
148
149 struct tps80031_pupd_data {
150         u8      reg;
151         u8      pullup_bit;
152         u8      pulldown_bit;
153 };
154
155 static u8 pmc_ext_control_base[] = {
156         REGEN1_BASE_ADD,
157         REGEN2_BASE_ADD,
158         SYSEN_BASE_ADD,
159 };
160
161 static u8 pmc_clk32k_control_base[] = {
162         CLK32KAO_BASE_ADD,
163         CLK32KG_BASE_ADD,
164         CLK32KAUDIO_BASE_ADD,
165 };
166 struct tps80031_irq_data {
167         u8      mask_reg;
168         u8      mask_mask;
169         u8      is_sec_int;
170         u8      parent_int;
171         u8      mask_sec_int_reg;
172         u8      int_mask_bit;
173         u8      int_sec_sts_reg;
174         u8      int_sts_bit;
175 };
176
177 #define TPS80031_IRQ(_reg, _mask)       \
178         {                                                       \
179                 .mask_reg = (TPS80031_INT_MSK_LINE_##_reg) -    \
180                                 TPS80031_INT_MSK_LINE_A,        \
181                 .mask_mask = (_mask),                           \
182         }
183
184 #define TPS80031_IRQ_SEC(_reg, _mask, _pint, _sint_mask_bit, _sint_sts_bit) \
185         {                                                               \
186                 .mask_reg = (TPS80031_INT_MSK_LINE_##_reg) -            \
187                                 TPS80031_INT_MSK_LINE_A,                \
188                 .mask_mask = (_mask),                                   \
189                 .is_sec_int = true,                                     \
190                 .parent_int = TPS80031_INT_##_pint,                     \
191                 .mask_sec_int_reg = TPS80031_CONTROLLER_INT_MASK,       \
192                 .int_mask_bit = CONTROLLER_INT_MASK_##_sint_mask_bit,   \
193                 .int_sec_sts_reg = TPS80031_CONTROLLER_STAT1,           \
194                 .int_sts_bit = CONTROLLER_STAT1_##_sint_sts_bit         \
195         }
196
197 static const struct tps80031_irq_data tps80031_irqs[] = {
198
199         [TPS80031_INT_PWRON]            = TPS80031_IRQ(A, 0),
200         [TPS80031_INT_RPWRON]           = TPS80031_IRQ(A, 1),
201         [TPS80031_INT_SYS_VLOW]         = TPS80031_IRQ(A, 2),
202         [TPS80031_INT_RTC_ALARM]        = TPS80031_IRQ(A, 3),
203         [TPS80031_INT_RTC_PERIOD]       = TPS80031_IRQ(A, 4),
204         [TPS80031_INT_HOT_DIE]          = TPS80031_IRQ(A, 5),
205         [TPS80031_INT_VXX_SHORT]        = TPS80031_IRQ(A, 6),
206         [TPS80031_INT_SPDURATION]       = TPS80031_IRQ(A, 7),
207         [TPS80031_INT_WATCHDOG]         = TPS80031_IRQ(B, 0),
208         [TPS80031_INT_BAT]              = TPS80031_IRQ(B, 1),
209         [TPS80031_INT_SIM]              = TPS80031_IRQ(B, 2),
210         [TPS80031_INT_MMC]              = TPS80031_IRQ(B, 3),
211         [TPS80031_INT_RES]              = TPS80031_IRQ(B, 4),
212         [TPS80031_INT_GPADC_RT]         = TPS80031_IRQ(B, 5),
213         [TPS80031_INT_GPADC_SW2_EOC]    = TPS80031_IRQ(B, 6),
214         [TPS80031_INT_CC_AUTOCAL]       = TPS80031_IRQ(B, 7),
215         [TPS80031_INT_ID_WKUP]          = TPS80031_IRQ(C, 0),
216         [TPS80031_INT_VBUSS_WKUP]       = TPS80031_IRQ(C, 1),
217         [TPS80031_INT_ID]               = TPS80031_IRQ(C, 2),
218         [TPS80031_INT_VBUS]             = TPS80031_IRQ(C, 3),
219         [TPS80031_INT_CHRG_CTRL]        = TPS80031_IRQ(C, 4),
220         [TPS80031_INT_EXT_CHRG]         = TPS80031_IRQ(C, 5),
221         [TPS80031_INT_INT_CHRG]         = TPS80031_IRQ(C, 6),
222         [TPS80031_INT_RES2]             = TPS80031_IRQ(C, 7),
223         [TPS80031_INT_BAT_TEMP_OVRANGE] = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
224                                                 MBAT_TEMP,      BAT_TEMP),
225         [TPS80031_INT_BAT_REMOVED]      = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
226                                                 MBAT_REMOVED,   BAT_REMOVED),
227         [TPS80031_INT_VBUS_DET]         = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
228                                                 MVBUS_DET,      VBUS_DET),
229         [TPS80031_INT_VAC_DET]          = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
230                                                 MVAC_DET,       VAC_DET),
231         [TPS80031_INT_FAULT_WDG]        = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
232                                                 MFAULT_WDG,     FAULT_WDG),
233         [TPS80031_INT_LINCH_GATED]      = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
234                                                 MLINCH_GATED,   LINCH_GATED),
235 };
236
237 #define PUPD_DATA(_reg, _pulldown_bit, _pullup_bit)     \
238         {                                               \
239                 .reg = TPS80031_CFG_INPUT_PUPD##_reg,   \
240                 .pulldown_bit = _pulldown_bit,          \
241                 .pullup_bit = _pullup_bit,              \
242         }
243
244 static const struct tps80031_pupd_data tps80031_pupds[] = {
245         [TPS80031_PREQ1]                = PUPD_DATA(1, 1 << 0,  1 << 1  ),
246         [TPS80031_PREQ2A]               = PUPD_DATA(1, 1 << 2,  1 << 3  ),
247         [TPS80031_PREQ2B]               = PUPD_DATA(1, 1 << 4,  1 << 5  ),
248         [TPS80031_PREQ2C]               = PUPD_DATA(1, 1 << 6,  1 << 7  ),
249         [TPS80031_PREQ3]                = PUPD_DATA(2, 1 << 0,  1 << 1  ),
250         [TPS80031_NRES_WARM]            = PUPD_DATA(2, 0,       1 << 2  ),
251         [TPS80031_PWM_FORCE]            = PUPD_DATA(2, 1 << 5,  0       ),
252         [TPS80031_CHRG_EXT_CHRG_STATZ]  = PUPD_DATA(2, 0,       1 << 6  ),
253         [TPS80031_SIM]                  = PUPD_DATA(3, 1 << 0,  1 << 1  ),
254         [TPS80031_MMC]                  = PUPD_DATA(3, 1 << 2,  1 << 3  ),
255         [TPS80031_GPADC_START]          = PUPD_DATA(3, 1 << 4,  0       ),
256         [TPS80031_DVSI2C_SCL]           = PUPD_DATA(4, 0,       1 << 0  ),
257         [TPS80031_DVSI2C_SDA]           = PUPD_DATA(4, 0,       1 << 1  ),
258         [TPS80031_CTLI2C_SCL]           = PUPD_DATA(4, 0,       1 << 2  ),
259         [TPS80031_CTLI2C_SDA]           = PUPD_DATA(4, 0,       1 << 3  ),
260 };
261
262 static const int controller_stat1_irq_nr[] = {
263         TPS80031_INT_BAT_TEMP_OVRANGE,
264         TPS80031_INT_BAT_REMOVED,
265         TPS80031_INT_VBUS_DET,
266         TPS80031_INT_VAC_DET,
267         TPS80031_INT_FAULT_WDG,
268         0,
269         TPS80031_INT_LINCH_GATED,
270         0
271 };
272
273 /* Structure for TPS80031 Slaves */
274 struct tps80031_client {
275         struct i2c_client *client;
276         struct mutex lock;
277         u8 addr;
278 };
279
280 struct tps80031 {
281         struct device           *dev;
282         unsigned long           chip_info;
283         int                     es_version;
284
285         struct gpio_chip        gpio;
286         struct irq_chip         irq_chip;
287         struct mutex            irq_lock;
288         int                     irq_base;
289         u32                     irq_en;
290         u8                      mask_cache[3];
291         u8                      mask_reg[3];
292         u8                      cont_int_mask_reg;
293         u8                      cont_int_mask_cache;
294         u8                      cont_int_en;
295         u8                      prev_cont_stat1;
296         struct tps80031_client  tps_clients[TPS_NUM_SLAVES];
297         struct regmap           *regmap[TPS_NUM_SLAVES];
298 };
299
300 /* TPS80031 sub mfd devices */
301 static struct mfd_cell tps80031_cell[] = {
302         {
303                 .name = "tps80031-regulators",
304         },
305         {
306                 .name = "tps80031-rtc",
307         },
308         {
309                 .name = "tps80031-battery-gauge",
310         },
311 };
312
313
314 int tps80031_write(struct device *dev, int sid, int reg, uint8_t val)
315 {
316         struct tps80031 *tps80031 = dev_get_drvdata(dev);
317
318         return regmap_write(tps80031->regmap[sid], reg, val);
319 }
320 EXPORT_SYMBOL_GPL(tps80031_write);
321
322 int tps80031_writes(struct device *dev, int sid, int reg, int len, uint8_t *val)
323 {
324         struct tps80031 *tps80031 = dev_get_drvdata(dev);
325
326         return regmap_bulk_write(tps80031->regmap[sid], reg, val, len);
327 }
328 EXPORT_SYMBOL_GPL(tps80031_writes);
329
330 int tps80031_read(struct device *dev, int sid, int reg, uint8_t *val)
331 {
332         struct tps80031 *tps80031 = dev_get_drvdata(dev);
333         unsigned int ival;
334         int ret;
335
336         ret = regmap_read(tps80031->regmap[sid], reg, &ival);
337         if (ret < 0) {
338                 dev_err(dev, "failed reading from reg 0x%02x\n", reg);
339                 return ret;
340         }
341
342         *val = ival;
343         return ret;
344 }
345 EXPORT_SYMBOL_GPL(tps80031_read);
346
347 int tps80031_reads(struct device *dev, int sid, int reg, int len, uint8_t *val)
348 {
349         struct tps80031 *tps80031 = dev_get_drvdata(dev);
350
351         return regmap_bulk_read(tps80031->regmap[sid], reg, val, len);
352 }
353 EXPORT_SYMBOL_GPL(tps80031_reads);
354
355 int tps80031_set_bits(struct device *dev, int sid, int reg, uint8_t bit_mask)
356 {
357         struct tps80031 *tps80031 = dev_get_drvdata(dev);
358
359         return regmap_update_bits(tps80031->regmap[sid], reg,
360                                 bit_mask, bit_mask);
361 }
362 EXPORT_SYMBOL_GPL(tps80031_set_bits);
363
364 int tps80031_clr_bits(struct device *dev, int sid, int reg, uint8_t bit_mask)
365 {
366         struct tps80031 *tps80031 = dev_get_drvdata(dev);
367
368         return regmap_update_bits(tps80031->regmap[sid], reg, bit_mask, 0);
369 }
370 EXPORT_SYMBOL_GPL(tps80031_clr_bits);
371
372 int tps80031_update(struct device *dev, int sid, int reg, uint8_t val,
373                 uint8_t mask)
374 {
375         struct tps80031 *tps80031 = dev_get_drvdata(dev);
376
377         return regmap_update_bits(tps80031->regmap[sid], reg, mask, val);
378 }
379 EXPORT_SYMBOL_GPL(tps80031_update);
380
381 int tps80031_force_update(struct device *dev, int sid, int reg, uint8_t val,
382                           uint8_t mask)
383 {
384         struct tps80031 *tps80031 = dev_get_drvdata(dev);
385         struct tps80031_client *tps = &tps80031->tps_clients[sid];
386         uint8_t reg_val;
387         int ret = 0;
388
389         mutex_lock(&tps->lock);
390
391         ret = tps80031_read(dev, sid, reg, &reg_val);
392         if (ret)
393                 goto out;
394
395         reg_val = (reg_val & ~mask) | (val & mask);
396         ret = tps80031_write(dev, sid, reg, reg_val);
397
398 out:
399         mutex_unlock(&tps->lock);
400         return ret;
401 }
402 EXPORT_SYMBOL_GPL(tps80031_force_update);
403
404 int tps80031_ext_power_req_config(struct device *dev,
405                 unsigned long ext_ctrl_flag, int preq_bit,
406                 int state_reg_add, int trans_reg_add)
407 {
408         u8 res_ass_reg = 0;
409         int preq_mask_bit = 0;
410         int ret;
411
412         if (!(ext_ctrl_flag & EXT_PWR_REQ))
413                 return 0;
414
415         if (ext_ctrl_flag & PWR_REQ_INPUT_PREQ1) {
416                 res_ass_reg = TPS80031_PREQ1_RES_ASS_A + (preq_bit >> 3);
417                 preq_mask_bit = 5;
418         } else if (ext_ctrl_flag & PWR_REQ_INPUT_PREQ2) {
419                 res_ass_reg = TPS80031_PREQ2_RES_ASS_A + (preq_bit >> 3);
420                 preq_mask_bit = 6;
421         } else if (ext_ctrl_flag & PWR_REQ_INPUT_PREQ3) {
422                 res_ass_reg = TPS80031_PREQ3_RES_ASS_A + (preq_bit >> 3);
423                 preq_mask_bit = 7;
424         }
425
426         /* Configure REQ_ASS registers */
427         ret = tps80031_set_bits(dev, SLAVE_ID1, res_ass_reg,
428                                         BIT(preq_bit & 0x7));
429         if (ret < 0) {
430                 dev_err(dev, "%s() Not able to set bit %d of "
431                         "reg %d error %d\n",
432                         __func__, preq_bit, res_ass_reg, ret);
433                 return ret;
434         }
435
436         /* Unmask the PREQ */
437         ret = tps80031_clr_bits(dev, SLAVE_ID1,
438                         TPS80031_PHOENIX_MSK_TRANSITION, BIT(preq_mask_bit));
439         if (ret < 0) {
440                 dev_err(dev, "%s() Not able to clear bit %d of "
441                         "reg %d error %d\n",
442                          __func__, preq_mask_bit,
443                         TPS80031_PHOENIX_MSK_TRANSITION, ret);
444                 return ret;
445         }
446
447         /* Switch regulator control to resource now */
448         if (ext_ctrl_flag & (PWR_REQ_INPUT_PREQ2 | PWR_REQ_INPUT_PREQ3)) {
449                 ret = tps80031_update(dev, SLAVE_ID1, state_reg_add, 0x0,
450                                                 STATE_MASK);
451                 if (ret < 0)
452                         dev_err(dev, "%s() Error in writing the STATE "
453                                 "register %d error %d\n", __func__,
454                                 state_reg_add, ret);
455         } else {
456                 ret = tps80031_update(dev, SLAVE_ID1, trans_reg_add,
457                                 TRANS_SLEEP_OFF, TRANS_SLEEP_MASK);
458                 if (ret < 0)
459                         dev_err(dev, "%s() Error in writing the TRANS "
460                                 "register %d error %d\n", __func__,
461                                 trans_reg_add, ret);
462         }
463         return ret;
464 }
465 EXPORT_SYMBOL_GPL(tps80031_ext_power_req_config);
466
467 unsigned long tps80031_get_chip_info(struct device *dev)
468 {
469         struct tps80031 *tps80031 = dev_get_drvdata(dev);
470         return tps80031->chip_info;
471 }
472 EXPORT_SYMBOL_GPL(tps80031_get_chip_info);
473
474 int tps80031_get_pmu_version(struct device *dev)
475 {
476         struct tps80031 *tps80031 = dev_get_drvdata(dev);
477         return tps80031->es_version;
478 }
479 EXPORT_SYMBOL_GPL(tps80031_get_pmu_version);
480
481 static struct tps80031 *tps80031_dev;
482 static void tps80031_power_off(void)
483 {
484         struct tps80031_client *tps = &tps80031_dev->tps_clients[SLAVE_ID1];
485
486         if (!tps->client)
487                 return;
488         dev_info(&tps->client->dev, "switching off PMU\n");
489         tps80031_write(&tps->client->dev, SLAVE_ID1,
490                                 TPS80031_PHOENIX_DEV_ON, DEVOFF);
491 }
492
493 static void tps80031_pupd_init(struct tps80031 *tps80031,
494                                struct tps80031_platform_data *pdata)
495 {
496         struct tps80031_pupd_init_data *pupd_init_data = pdata->pupd_init_data;
497         int data_size = pdata->pupd_init_data_size;
498         int i;
499
500         for (i = 0; i < data_size; ++i) {
501                 struct tps80031_pupd_init_data *pupd_init = &pupd_init_data[i];
502                 const struct tps80031_pupd_data *pupd =
503                         &tps80031_pupds[pupd_init->input_pin];
504                 u8 update_value = 0;
505                 u8 update_mask = pupd->pulldown_bit | pupd->pullup_bit;
506
507                 if (pupd_init->setting == TPS80031_PUPD_PULLDOWN)
508                         update_value = pupd->pulldown_bit;
509                 else if (pupd_init->setting == TPS80031_PUPD_PULLUP)
510                         update_value = pupd->pullup_bit;
511
512                 tps80031_update(tps80031->dev, SLAVE_ID1, pupd->reg,
513                                 update_value, update_mask);
514         }
515 }
516
517 static void tps80031_backup_battery_charger_control(struct tps80031 *tps80031,
518                                                     int enable)
519 {
520         if (enable)
521                 tps80031_update(tps80031->dev, SLAVE_ID1, TPS80031_BBSPOR_CFG,
522                                 TPS80031_BBSPOR_CHG_EN, TPS80031_BBSPOR_CHG_EN);
523         else
524                 tps80031_update(tps80031->dev, SLAVE_ID1, TPS80031_BBSPOR_CFG,
525                                 0, TPS80031_BBSPOR_CHG_EN);
526 }
527
528 static void tps80031_init_ext_control(struct tps80031 *tps80031,
529                         struct tps80031_platform_data *pdata) {
530         int ret;
531         int i;
532
533         /* Clear all external control for this rail */
534         for (i = 0; i < 9; ++i) {
535                 ret = tps80031_write(tps80031->dev, SLAVE_ID1,
536                                 TPS80031_PREQ1_RES_ASS_A + i, 0);
537                 if (ret < 0)
538                         dev_err(tps80031->dev, "%s() Error in clearing "
539                                 "register %02x\n", __func__,
540                                 TPS80031_PREQ1_RES_ASS_A + i);
541         }
542
543         /* Mask the PREQ */
544         ret = tps80031_set_bits(tps80031->dev, SLAVE_ID1,
545                         TPS80031_PHOENIX_MSK_TRANSITION, 0x7 << 5);
546         if (ret < 0)
547                 dev_err(tps80031->dev, "%s() Not able to mask register "
548                         "0x%02x\n", __func__, TPS80031_PHOENIX_MSK_TRANSITION);
549 }
550
551 static int tps80031_gpio_get(struct gpio_chip *gc, unsigned offset)
552 {
553         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
554         struct tps80031_client *tps = &tps80031->tps_clients[SLAVE_ID1];
555         uint8_t state;
556         uint8_t trans;
557         int ret;
558
559         ret = tps80031_read(&tps->client->dev, SLAVE_ID1,
560                         pmc_ext_control_base[offset] +
561                                 EXT_CONTROL_CFG_STATE, &state);
562         if (ret)
563                 return ret;
564
565         if (state != 0) {
566                 ret = tps80031_read(&tps->client->dev, SLAVE_ID1,
567                                 pmc_ext_control_base[offset] +
568                                         EXT_CONTROL_CFG_TRANS, &trans);
569                 if (ret)
570                         return ret;
571                 return trans & 0x1;
572         }
573         return 0;
574 }
575
576 static void tps80031_gpio_set(struct gpio_chip *gc, unsigned offset,
577                         int value)
578 {
579         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
580
581         tps80031_update(tps80031->dev, SLAVE_ID1,
582                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_TRANS,
583                         value, 0x1);
584 }
585
586 static int tps80031_gpio_input(struct gpio_chip *gc, unsigned offset)
587 {
588         return -EIO;
589 }
590
591 static int tps80031_gpio_output(struct gpio_chip *gc, unsigned offset,
592                                 int value)
593 {
594         tps80031_gpio_set(gc, offset, value);
595         return 0;
596 }
597
598 static int tps80031_gpio_enable(struct gpio_chip *gc, unsigned offset)
599 {
600         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
601         int ret;
602
603         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
604                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_STATE,
605                                                 STATE_ON, STATE_MASK);
606         if (ret)
607                 return ret;
608
609         return tps80031_write(tps80031->dev, SLAVE_ID1,
610                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_TRANS, 0x0);
611 }
612
613 static void tps80031_gpio_disable(struct gpio_chip *gc, unsigned offset)
614 {
615         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
616         tps80031_update(tps80031->dev, SLAVE_ID1,
617                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_STATE,
618                                                 STATE_OFF, STATE_MASK);
619 }
620
621 static void tps80031_gpio_init(struct tps80031 *tps80031,
622                         struct tps80031_platform_data *pdata)
623 {
624         int ret;
625         int gpio_base = pdata->gpio_base;
626         struct tps80031_client *tps = &tps80031->tps_clients[SLAVE_ID1];
627         struct tps80031_gpio_init_data *gpio_init_data = pdata->gpio_init_data;
628         int data_size = pdata->gpio_init_data_size;
629         static int preq_bit_pos[TPS80031_GPIO_NR] = {16, 17, 18};
630         int base_add;
631         int i;
632
633         if (gpio_base <= 0)
634                 return;
635
636         /* Configure the external request mode */
637         for (i = 0; i < data_size; ++i) {
638                 struct tps80031_gpio_init_data *gpio_pd = &gpio_init_data[i];
639                 base_add = pmc_ext_control_base[gpio_pd->gpio_nr];
640
641                 if (gpio_pd->ext_ctrl_flag & EXT_PWR_REQ) {
642                         ret = tps80031_ext_power_req_config(tps80031->dev,
643                                 gpio_pd->ext_ctrl_flag,
644                                 preq_bit_pos[gpio_pd->gpio_nr],
645                                 base_add + EXT_CONTROL_CFG_STATE,
646                                 base_add + EXT_CONTROL_CFG_TRANS);
647                         if (ret < 0)
648                                 dev_warn(tps80031->dev, "Ext pwrreq GPIO "
649                                         "sleep control fails\n");
650                 }
651
652                 if (gpio_pd->ext_ctrl_flag & PWR_OFF_ON_SLEEP) {
653                         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
654                                 base_add + EXT_CONTROL_CFG_TRANS, 0x0, 0xC);
655                         if (ret < 0)
656                                 dev_warn(tps80031->dev, "GPIO OFF on sleep "
657                                         "control fails\n");
658                 }
659
660                 if (gpio_pd->ext_ctrl_flag & PWR_ON_ON_SLEEP) {
661                         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
662                                 base_add + EXT_CONTROL_CFG_TRANS, 0x4, 0xC);
663                         if (ret < 0)
664                                 dev_warn(tps80031->dev, "GPIO ON on sleep "
665                                         "control fails\n");
666                 }
667         }
668
669         tps80031->gpio.owner            = THIS_MODULE;
670         tps80031->gpio.label            = tps->client->name;
671         tps80031->gpio.dev              = tps80031->dev;
672         tps80031->gpio.base             = gpio_base;
673         tps80031->gpio.ngpio            = TPS80031_GPIO_NR;
674         tps80031->gpio.can_sleep        = 1;
675
676         tps80031->gpio.request          = tps80031_gpio_enable;
677         tps80031->gpio.free             = tps80031_gpio_disable;
678         tps80031->gpio.direction_input  = tps80031_gpio_input;
679         tps80031->gpio.direction_output = tps80031_gpio_output;
680         tps80031->gpio.set              = tps80031_gpio_set;
681         tps80031->gpio.get              = tps80031_gpio_get;
682
683         ret = gpiochip_add(&tps80031->gpio);
684         if (ret)
685                 dev_warn(tps80031->dev, "GPIO registration failed: %d\n", ret);
686 }
687
688 static int __remove_subdev(struct device *dev, void *unused)
689 {
690         platform_device_unregister(to_platform_device(dev));
691         return 0;
692 }
693
694 static int tps80031_remove_subdevs(struct tps80031 *tps80031)
695 {
696         return device_for_each_child(tps80031->dev, NULL, __remove_subdev);
697 }
698
699 static void tps80031_irq_lock(struct irq_data *data)
700 {
701         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
702
703         mutex_lock(&tps80031->irq_lock);
704 }
705
706 static void tps80031_irq_enable(struct irq_data *data)
707 {
708         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
709         unsigned int __irq = data->irq - tps80031->irq_base;
710         const struct tps80031_irq_data *irq_data = &tps80031_irqs[__irq];
711
712         if (irq_data->is_sec_int) {
713                 tps80031->cont_int_mask_reg &= ~(1 << irq_data->int_mask_bit);
714                 tps80031->cont_int_en |= (1 << irq_data->int_mask_bit);
715                 tps80031->mask_reg[irq_data->mask_reg] &= ~(1 << irq_data->mask_mask);
716                 tps80031->irq_en |= (1 << irq_data->parent_int);
717         } else
718                 tps80031->mask_reg[irq_data->mask_reg] &= ~(1 << irq_data->mask_mask);
719
720         tps80031->irq_en |= (1 << __irq);
721 }
722
723 static void tps80031_irq_disable(struct irq_data *data)
724 {
725         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
726
727         unsigned int __irq = data->irq - tps80031->irq_base;
728         const struct tps80031_irq_data *irq_data = &tps80031_irqs[__irq];
729
730         if (irq_data->is_sec_int) {
731                 tps80031->cont_int_mask_reg |= (1 << irq_data->int_mask_bit);
732                 tps80031->cont_int_en &= ~(1 << irq_data->int_mask_bit);
733                 if (!tps80031->cont_int_en) {
734                         tps80031->mask_reg[irq_data->mask_reg] |=
735                                                 (1 << irq_data->mask_mask);
736                         tps80031->irq_en &= ~(1 << irq_data->parent_int);
737                 }
738                 tps80031->irq_en &= ~(1 << __irq);
739         } else
740                 tps80031->mask_reg[irq_data->mask_reg] |= (1 << irq_data->mask_mask);
741
742         tps80031->irq_en &= ~(1 << __irq);
743 }
744
745 static void tps80031_irq_sync_unlock(struct irq_data *data)
746 {
747         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
748         int i;
749
750         for (i = 0; i < ARRAY_SIZE(tps80031->mask_reg); i++) {
751                 if (tps80031->mask_reg[i] != tps80031->mask_cache[i]) {
752                         if (!WARN_ON(tps80031_write(tps80031->dev, SLAVE_ID2,
753                                                 TPS80031_INT_MSK_LINE_A + i,
754                                                 tps80031->mask_reg[i])))
755                                 if (!WARN_ON(tps80031_write(tps80031->dev,
756                                                 SLAVE_ID2,
757                                                 TPS80031_INT_MSK_STS_A + i,
758                                                 tps80031->mask_reg[i])))
759                                         tps80031->mask_cache[i] =
760                                                         tps80031->mask_reg[i];
761                 }
762         }
763
764         if (tps80031->cont_int_mask_reg != tps80031->cont_int_mask_cache) {
765                 if (!WARN_ON(tps80031_write(tps80031->dev, SLAVE_ID2,
766                                 TPS80031_CONTROLLER_INT_MASK,
767                                 tps80031->cont_int_mask_reg)))
768                         tps80031->cont_int_mask_cache =
769                                                 tps80031->cont_int_mask_reg;
770         }
771
772         mutex_unlock(&tps80031->irq_lock);
773 }
774
775 static irqreturn_t tps80031_charge_control_irq(int irq, void *data)
776 {
777         struct tps80031 *tps80031 = data;
778         int ret = 0;
779         int i;
780         u8 cont_sts;
781         u8 org_sts;
782         if (irq != (tps80031->irq_base + TPS80031_INT_CHRG_CTRL)) {
783                 dev_err(tps80031->dev, "%s() Got the illegal interrupt %d\n",
784                                         __func__, irq);
785                 return IRQ_NONE;
786         }
787
788         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
789                         TPS80031_CONTROLLER_STAT1, &org_sts);
790         if (ret < 0) {
791                 dev_err(tps80031->dev, "%s(): failed to read controller state1 "
792                                 "status %d\n", __func__, ret);
793                 return IRQ_NONE;
794         }
795
796         /* Get change from last interrupt and mask for interested interrupt
797          * for charge control interrupt */
798         cont_sts = org_sts ^ tps80031->prev_cont_stat1;
799         tps80031->prev_cont_stat1 = org_sts;
800         /* Clear watchdog timer state */
801         tps80031->prev_cont_stat1 &= ~(1 << 4);
802         cont_sts &= 0x5F;
803
804         for (i = 0; i < 8; ++i) {
805                 if (!controller_stat1_irq_nr[i])
806                         continue;
807
808                 if ((cont_sts & BIT(i)) &&
809                         (tps80031->irq_en & BIT(controller_stat1_irq_nr[i])))
810                         handle_nested_irq(tps80031->irq_base +
811                                                 controller_stat1_irq_nr[i]);
812                 cont_sts &= ~BIT(i);
813         }
814         return IRQ_HANDLED;
815 }
816
817 static irqreturn_t tps80031_irq(int irq, void *data)
818 {
819         struct tps80031 *tps80031 = data;
820         int ret = 0;
821         u32 acks;
822         int i;
823         uint8_t tmp[3];
824
825         ret = tps80031_reads(tps80031->dev, SLAVE_ID2,
826                              TPS80031_INT_STS_A, 3, tmp);
827         if (ret < 0) {
828                 dev_err(tps80031->dev, "failed to read interrupt status\n");
829                 return IRQ_NONE;
830         }
831         acks = (tmp[2] << 16) | (tmp[1] << 8) | tmp[0];
832
833         if (acks) {
834                 /*
835                  * Hardware behavior: hardware have the shadow register for
836                  * interrupt status register which is updated if interrupt
837                  * comes just after the interrupt status read. This shadow
838                  * register gets written to main status register and cleared
839                  * if any byte write happens in any of status register like
840                  * STS_A, STS_B or STS_C.
841                  * Hence here to clear the original interrupt status and
842                  * updating the STS register with the shadow register, it is
843                  * require to write only one byte in any of STS register.
844                  * Having multiple register write can cause the STS register
845                  * to clear without handling those interrupt and can cause
846                  * interrupt miss.
847                  */
848                 ret = tps80031_write(tps80031->dev, SLAVE_ID2,
849                                       TPS80031_INT_STS_A, 0);
850                 if (ret < 0) {
851                         dev_err(tps80031->dev, "failed to write "
852                                                 "interrupt status\n");
853                         return IRQ_NONE;
854                 }
855
856                 while (acks) {
857                         i = __ffs(acks);
858                         if (tps80031->irq_en & (1 << i))
859                                 handle_nested_irq(tps80031->irq_base + i);
860                         acks &= ~(1 << i);
861                 }
862         }
863
864         return IRQ_HANDLED;
865 }
866
867 static int __devinit tps80031_irq_init(struct tps80031 *tps80031, int irq,
868                                 int irq_base)
869 {
870         int i, ret;
871
872         if (!irq_base) {
873                 dev_warn(tps80031->dev, "No interrupt support on IRQ base\n");
874                 return -EINVAL;
875         }
876
877         mutex_init(&tps80031->irq_lock);
878
879         for (i = 0; i < 3; i++) {
880                 tps80031->mask_reg[i] = 0xFF;
881                 tps80031->mask_cache[i] = tps80031->mask_reg[i];
882                 tps80031_write(tps80031->dev, SLAVE_ID2,
883                                         TPS80031_INT_MSK_LINE_A + i,
884                                         tps80031->mask_cache[i]);
885                 tps80031_write(tps80031->dev, SLAVE_ID2,
886                                         TPS80031_INT_MSK_STS_A + i, 0xFF);
887                 tps80031_write(tps80031->dev, SLAVE_ID2,
888                                         TPS80031_INT_STS_A + i, 0xFF);
889         }
890
891         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
892                                 TPS80031_CONTROLLER_INT_MASK,
893                                 &tps80031->cont_int_mask_reg);
894         if (ret < 0) {
895                 dev_err(tps80031->dev, "Error in reading the controller_mask "
896                                         "register %d\n", ret);
897                 return ret;
898         }
899
900         tps80031->cont_int_mask_reg |= CHARGE_CONTROL_SUB_INT_MASK;
901         tps80031->cont_int_mask_cache = tps80031->cont_int_mask_reg;
902         tps80031->cont_int_en = 0;
903         ret = tps80031_write(tps80031->dev, SLAVE_ID2,
904                                 TPS80031_CONTROLLER_INT_MASK,
905                                 tps80031->cont_int_mask_reg);
906         if (ret < 0) {
907                 dev_err(tps80031->dev, "Error in writing the controller_mask "
908                                         "register %d\n", ret);
909                 return ret;
910         }
911
912         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
913                         TPS80031_CONTROLLER_STAT1, &tps80031->prev_cont_stat1);
914         if (ret < 0) {
915                 dev_err(tps80031->dev, "%s(): failed to read controller state1 "
916                                 "status %d\n", __func__, ret);
917                 return ret;
918         }
919
920         /* Clear watch dog interrupt status in status */
921         tps80031->prev_cont_stat1 &= ~(1 << 4);
922
923         tps80031->irq_base = irq_base;
924
925         tps80031->irq_chip.name = "tps80031";
926         tps80031->irq_chip.irq_enable = tps80031_irq_enable;
927         tps80031->irq_chip.irq_disable = tps80031_irq_disable;
928         tps80031->irq_chip.irq_bus_lock = tps80031_irq_lock;
929         tps80031->irq_chip.irq_bus_sync_unlock = tps80031_irq_sync_unlock;
930
931         for (i = 0; i < TPS80031_INT_NR; i++) {
932                 int __irq = i + tps80031->irq_base;
933                 irq_set_chip_data(__irq, tps80031);
934                 irq_set_chip_and_handler(__irq, &tps80031->irq_chip,
935                                          handle_simple_irq);
936                 irq_set_nested_thread(__irq, 1);
937 #ifdef CONFIG_ARM
938                 set_irq_flags(__irq, IRQF_VALID);
939 #endif
940         }
941
942         ret = request_threaded_irq(irq, NULL, tps80031_irq, IRQF_ONESHOT,
943                                 "tps80031", tps80031);
944         /* register the isr for the secondary interrupt */
945         if (!ret)
946                 ret = request_threaded_irq(irq_base + TPS80031_INT_CHRG_CTRL,
947                                 NULL, tps80031_charge_control_irq,
948                                 IRQF_ONESHOT, "80031_chg_ctl", tps80031);
949         if (!ret) {
950
951                 device_init_wakeup(tps80031->dev, 1);
952                 enable_irq_wake(irq);
953         }
954
955         return ret;
956 }
957
958 static void tps80031_clk32k_enable(struct tps80031 *tps80031, int base_add)
959 {
960         int ret;
961         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
962                         base_add + EXT_CONTROL_CFG_STATE, STATE_ON, STATE_MASK);
963         if (!ret)
964                 ret = tps80031_update(tps80031->dev, SLAVE_ID1,
965                                 base_add + EXT_CONTROL_CFG_TRANS,
966                                 STATE_ON, STATE_MASK);
967         if (ret < 0)
968                 dev_err(tps80031->dev, "Error in updating clock register\n");
969 }
970
971 static void tps80031_clk32k_init(struct tps80031 *tps80031,
972                         struct tps80031_platform_data *pdata)
973 {
974         int ret;
975         struct tps80031_clk32k_init_data *clk32_idata = pdata->clk32k_init_data;
976         int data_size = pdata->clk32k_init_data_size;
977         static int clk32k_preq_bit_pos[TPS80031_CLOCK32K_NR] = {-1, 20, 19};
978         int base_add;
979         int i;
980
981         if (!clk32_idata || !data_size)
982                 return;
983
984         /* Configure the external request mode */
985         for (i = 0; i < data_size; ++i) {
986                 struct tps80031_clk32k_init_data *clk32_pd =  &clk32_idata[i];
987                 base_add = pmc_clk32k_control_base[clk32_pd->clk32k_nr];
988                 if (clk32_pd->enable)
989                         tps80031_clk32k_enable(tps80031, base_add);
990
991                 if ((clk32_pd->ext_ctrl_flag & EXT_PWR_REQ) &&
992                          (clk32k_preq_bit_pos[clk32_pd->clk32k_nr] != -1)) {
993                         ret = tps80031_ext_power_req_config(tps80031->dev,
994                                 clk32_pd->ext_ctrl_flag,
995                                 clk32k_preq_bit_pos[clk32_pd->clk32k_nr],
996                                 base_add + EXT_CONTROL_CFG_STATE,
997                                 base_add + EXT_CONTROL_CFG_TRANS);
998                         if (ret < 0)
999                                 dev_warn(tps80031->dev, "Clk32 ext control "
1000                                         "fails\n");
1001                 }
1002
1003                 if (clk32_pd->ext_ctrl_flag & PWR_OFF_ON_SLEEP) {
1004                         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
1005                                 base_add + EXT_CONTROL_CFG_TRANS, 0x0, 0xC);
1006                         if (ret < 0)
1007                                 dev_warn(tps80031->dev, "clk OFF on sleep "
1008                                         "control fails\n");
1009                 }
1010
1011                 if (clk32_pd->ext_ctrl_flag & PWR_ON_ON_SLEEP) {
1012                         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
1013                                 base_add + EXT_CONTROL_CFG_TRANS, 0x4, 0xC);
1014                         if (ret < 0)
1015                                 dev_warn(tps80031->dev, "clk ON sleep "
1016                                         "control fails\n");
1017                 }
1018         }
1019 }
1020
1021 static int __devinit tps80031_add_subdevs(struct tps80031 *tps80031,
1022                                           struct tps80031_platform_data *pdata)
1023 {
1024         struct tps80031_subdev_info *subdev;
1025         struct platform_device *pdev;
1026         int i, ret = 0;
1027
1028         for (i = 0; i < pdata->num_subdevs; i++) {
1029                 subdev = &pdata->subdevs[i];
1030
1031                 pdev = platform_device_alloc(subdev->name, subdev->id);
1032
1033                 pdev->dev.parent = tps80031->dev;
1034                 pdev->dev.platform_data = subdev->platform_data;
1035
1036                 ret = platform_device_add(pdev);
1037                 if (ret)
1038                         goto failed;
1039         }
1040         return 0;
1041
1042 failed:
1043         tps80031_remove_subdevs(tps80031);
1044         return ret;
1045 }
1046
1047 #ifdef CONFIG_DEBUG_FS
1048 #include <linux/debugfs.h>
1049 #include <linux/seq_file.h>
1050 static void print_regs(const char *header, struct seq_file *s,
1051                 int sid, int start_offset, int end_offset)
1052 {
1053         struct tps80031 *tps80031 = s->private;
1054         struct tps80031_client *tps = &tps80031->tps_clients[sid];
1055         uint8_t reg_val;
1056         int i;
1057         int ret;
1058
1059         seq_printf(s, "%s\n", header);
1060         for (i = start_offset; i <= end_offset; ++i) {
1061                 ret = tps80031_read(&tps->client->dev, sid, i, &reg_val);
1062                 if (ret >= 0)
1063                         seq_printf(s, "Addr = 0x%02x Reg 0x%02x Value 0x%02x\n",
1064                                                 tps->client->addr, i, reg_val);
1065         }
1066         seq_printf(s, "------------------\n");
1067 }
1068
1069 static int dbg_tps_show(struct seq_file *s, void *unused)
1070 {
1071         seq_printf(s, "TPS80031 Registers\n");
1072         seq_printf(s, "------------------\n");
1073         print_regs("VIO Regs",       s, SLAVE_ID1, 0x47, 0x49);
1074         print_regs("VIO Regs",       s, SLAVE_ID0, 0x49, 0x4A);
1075         print_regs("SMPS1 Regs",     s, SLAVE_ID1, 0x53, 0x54);
1076         print_regs("SMPS1 Regs",     s, SLAVE_ID0, 0x55, 0x56);
1077         print_regs("SMPS1 Regs",     s, SLAVE_ID1, 0x57, 0x57);
1078         print_regs("SMPS2 Regs",     s, SLAVE_ID1, 0x59, 0x5B);
1079         print_regs("SMPS2 Regs",     s, SLAVE_ID0, 0x5B, 0x5C);
1080         print_regs("SMPS2 Regs",     s, SLAVE_ID1, 0x5C, 0x5D);
1081         print_regs("SMPS3 Regs",     s, SLAVE_ID1, 0x65, 0x68);
1082         print_regs("SMPS4 Regs",     s, SLAVE_ID1, 0x41, 0x44);
1083         print_regs("VANA Regs",      s, SLAVE_ID1, 0x81, 0x83);
1084         print_regs("VRTC Regs",      s, SLAVE_ID1, 0xC3, 0xC4);
1085         print_regs("LDO1 Regs",      s, SLAVE_ID1, 0x9D, 0x9F);
1086         print_regs("LDO2 Regs",      s, SLAVE_ID1, 0x85, 0x87);
1087         print_regs("LDO3 Regs",      s, SLAVE_ID1, 0x8D, 0x8F);
1088         print_regs("LDO4 Regs",      s, SLAVE_ID1, 0x89, 0x8B);
1089         print_regs("LDO5 Regs",      s, SLAVE_ID1, 0x99, 0x9B);
1090         print_regs("LDO6 Regs",      s, SLAVE_ID1, 0x91, 0x93);
1091         print_regs("LDO7 Regs",      s, SLAVE_ID1, 0xA5, 0xA7);
1092         print_regs("LDOUSB Regs",    s, SLAVE_ID1, 0xA1, 0xA3);
1093         print_regs("LDOLN Regs",     s, SLAVE_ID1, 0x95, 0x97);
1094         print_regs("REGEN1 Regs",    s, SLAVE_ID1, 0xAE, 0xAF);
1095         print_regs("REGEN2 Regs",    s, SLAVE_ID1, 0xB1, 0xB2);
1096         print_regs("SYSEN Regs",     s, SLAVE_ID1, 0xB4, 0xB5);
1097         print_regs("CLK32KAO Regs",  s, SLAVE_ID1, 0xBA, 0xBB);
1098         print_regs("CLK32KG Regs",   s, SLAVE_ID1, 0xBD, 0xBE);
1099         print_regs("CLK32KAUD Regs", s, SLAVE_ID1, 0xC0, 0xC1);
1100         print_regs("INT Regs",       s, SLAVE_ID2, 0xD0, 0xD8);
1101         print_regs("PREQ Regs",      s, SLAVE_ID1, 0xD7, 0xDF);
1102         print_regs("MASK_PH Regs",   s, SLAVE_ID1, 0x20, 0x21);
1103         print_regs("PMC MISC Regs",  s, SLAVE_ID1, 0xE0, 0xEF);
1104         print_regs("CONT_STATE",     s, SLAVE_ID2, 0xE0, 0xE4);
1105         print_regs("VERNUM Regs",    s, SLAVE_ID3, 0x87, 0x87);
1106         print_regs("EEPROM Regs",    s, SLAVE_ID3, 0xDF, 0xDF);
1107         print_regs("CHARGE Regs",    s, SLAVE_ID2, 0xDA, 0xF5);
1108         return 0;
1109 }
1110
1111 static int dbg_tps_open(struct inode *inode, struct file *file)
1112 {
1113         return single_open(file, dbg_tps_show, inode->i_private);
1114 }
1115
1116 static const struct file_operations debug_fops = {
1117         .open           = dbg_tps_open,
1118         .read           = seq_read,
1119         .llseek         = seq_lseek,
1120         .release        = single_release,
1121 };
1122
1123 static void __init tps80031_debuginit(struct tps80031 *tps)
1124 {
1125         (void)debugfs_create_file("tps80031", S_IRUGO, NULL,
1126                         tps, &debug_fops);
1127 }
1128 #else
1129 static void __init tps80031_debuginit(struct tps80031 *tpsi)
1130 {
1131         return;
1132 }
1133 #endif
1134
1135 static bool rd_wr_reg_id0(struct device *dev, unsigned int reg)
1136 {
1137         switch(reg) {
1138         case TPS80031_ID0_PMIC_SLAVE_SMPS_DVS:
1139                 return true;
1140         default:
1141                 pr_err("non-existing reg %s() %d reg %x\n", __func__, __LINE__, reg);
1142                 BUG();
1143                 return false;
1144         }
1145 }
1146
1147 static bool rd_wr_reg_id1(struct device *dev, unsigned int reg)
1148 {
1149         switch(reg) {
1150         case TPS80031_ID1_RTC:
1151         case TPS80031_ID1_MEMORY:
1152         case TPS80031_ID1_PMC_MASTER:
1153         case TPS80031_ID1_PMC_SLAVE_SMPS:
1154         case TPS80031_ID1_PMC_SLAVE_MISC:
1155         case TPS80031_ID1_PMC_SLAVE_LDO:
1156         case TPS80031_ID1_PMC_SLAVE_REOSURCES:
1157         case TPS80031_ID1_PMC_PREQ_ASSIGN:
1158         case TPS80031_ID1_PMC_MISC:
1159         case TPS80031_ID1_PMC_PU_PD_HZ:
1160         case TPS80031_ID1_PMC_BACKUP:
1161                 return true;
1162         default:
1163                 pr_err("non-existing reg %s() %d reg %x\n", __func__, __LINE__, reg);
1164                 BUG();
1165                 return false;
1166         }
1167 }
1168
1169 static bool rd_wr_reg_id2(struct device *dev, unsigned int reg)
1170 {
1171         switch(reg) {
1172         case TPS80031_ID2_USB:
1173         case TPS80031_ID2_GPADC_CONTROL:
1174         case TPS80031_ID2_GPADC_RESULTS:
1175         case TPS80031_ID2_AUXILLIARIES:
1176         case TPS80031_ID2_CUSTOM:
1177         case TPS80031_ID2_PWM:
1178         case TPS80031_ID2_FUEL_GAUSE:
1179         case TPS80031_ID2_INTERFACE_INTERRUPTS:
1180         case TPS80031_ID2_CHARGER:
1181                 return true;
1182         default:
1183                 pr_err("non-existing reg %s() %d reg %x\n", __func__, __LINE__, reg);
1184                 BUG();
1185                 return false;
1186         }
1187 }
1188 static bool rd_wr_reg_id3(struct device *dev, unsigned int reg)
1189 {
1190         switch(reg) {
1191         case TPS80031_ID3_TEST_LDO:
1192         case TPS80031_ID3_TEST_SMPS:
1193         case TPS80031_ID3_TEST_POWER:
1194         case TPS80031_ID3_TEST_CHARGER:
1195         case TPS80031_ID3_TEST_AUXILIIARIES:
1196         case TPS80031_ID3_DIEID:
1197         case TPS80031_ID3_TRIM_PHOENIX:
1198         case TPS80031_ID3_TRIM_CUSTOM:
1199                 return true;
1200         default:
1201                 pr_err("non-existing reg %s() %d reg %x\n", __func__, __LINE__, reg);
1202                 BUG();
1203                 return false;
1204         }
1205 }
1206
1207 static const struct regmap_config tps80031_regmap_configs[] = {
1208         {
1209                 .reg_bits = 8,
1210                 .val_bits = 8,
1211                 .writeable_reg = rd_wr_reg_id0,
1212                 .readable_reg = rd_wr_reg_id0,
1213                 .max_register = TPS80031_MAX_REGISTER - 1,
1214         },
1215         {
1216                 .reg_bits = 8,
1217                 .val_bits = 8,
1218                 .writeable_reg = rd_wr_reg_id1,
1219                 .readable_reg = rd_wr_reg_id1,
1220                 .max_register = TPS80031_MAX_REGISTER - 1,
1221         },
1222         {
1223                 .reg_bits = 8,
1224                 .val_bits = 8,
1225                 .writeable_reg = rd_wr_reg_id2,
1226                 .readable_reg = rd_wr_reg_id2,
1227                 .max_register = TPS80031_MAX_REGISTER - 1,
1228         },
1229         {
1230                 .reg_bits = 8,
1231                 .val_bits = 8,
1232                 .writeable_reg = rd_wr_reg_id3,
1233                 .readable_reg = rd_wr_reg_id3,
1234                 .max_register = TPS80031_MAX_REGISTER - 1,
1235         },
1236 };
1237
1238 static int __devexit tps80031_i2c_remove(struct i2c_client *client)
1239 {
1240         struct tps80031 *tps80031 = i2c_get_clientdata(client);
1241         int i;
1242
1243         mfd_remove_devices(tps80031->dev);
1244
1245         if (client->irq)
1246                 free_irq(client->irq, tps80031);
1247
1248         if (tps80031->gpio.owner != NULL)
1249                 if (gpiochip_remove(&tps80031->gpio) < 0)
1250                         dev_err(&client->dev, "Error in removing the gpio driver\n");
1251
1252         for (i = 0; i < TPS_NUM_SLAVES; i++) {
1253                 struct tps80031_client *tps = &tps80031->tps_clients[i];
1254                 if (tps->client && tps->client != client)
1255                         i2c_unregister_device(tps->client);
1256                 tps80031->tps_clients[i].client = NULL;
1257                 mutex_destroy(&tps->lock);
1258         }
1259
1260         return 0;
1261 }
1262
1263 static int __devinit tps80031_i2c_probe(struct i2c_client *client,
1264                                         const struct i2c_device_id *id)
1265 {
1266         struct tps80031_platform_data *pdata = client->dev.platform_data;
1267         struct tps80031 *tps80031;
1268         struct tps80031_client *tps;
1269         int ret;
1270         int jtag_ver;
1271         int ep_ver;
1272         int i;
1273
1274         if (!pdata) {
1275                 dev_err(&client->dev, "tps80031 requires platform data\n");
1276                 return -ENOTSUPP;
1277         }
1278
1279         jtag_ver = i2c_smbus_read_byte_data(client, TPS80031_JTAGVERNUM);
1280         if (jtag_ver < 0) {
1281                 dev_err(&client->dev, "Silicon version number read"
1282                                 " failed: %d\n", jtag_ver);
1283                 return -EIO;
1284         }
1285
1286         ep_ver = i2c_smbus_read_byte_data(client, TPS80031_EPROM_REV);
1287         if (ep_ver < 0) {
1288                 dev_err(&client->dev, "Silicon eeprom version read"
1289                                 " failed: %d\n", ep_ver);
1290                 return -EIO;
1291         }
1292
1293         dev_info(&client->dev, "Jtag version 0x%02x and Eeprom version 0x%02x\n",
1294                                                 jtag_ver, ep_ver);
1295
1296         tps80031 = devm_kzalloc(&client->dev, sizeof(*tps80031), GFP_KERNEL);
1297         if (!tps80031) {
1298                 dev_err(&client->dev, "Memory alloc for tps80031 failed\n");
1299                 return -ENOMEM;
1300         }
1301
1302         tps80031->es_version = jtag_ver;
1303         tps80031->dev = &client->dev;
1304         i2c_set_clientdata(client, tps80031);
1305         tps80031->chip_info = id->driver_data;
1306
1307         /* Set up slaves */
1308         tps80031->tps_clients[SLAVE_ID0].addr = I2C_ID0_ADDR;
1309         tps80031->tps_clients[SLAVE_ID1].addr = I2C_ID1_ADDR;
1310         tps80031->tps_clients[SLAVE_ID2].addr = I2C_ID2_ADDR;
1311         tps80031->tps_clients[SLAVE_ID3].addr = I2C_ID3_ADDR;
1312         for (i = 0; i < TPS_NUM_SLAVES; i++) {
1313                 tps = &tps80031->tps_clients[i];
1314                 if (tps->addr == client->addr)
1315                         tps->client = client;
1316                 else
1317                         tps->client = i2c_new_dummy(client->adapter,
1318                                                 tps->addr);
1319                 if (!tps->client) {
1320                         dev_err(&client->dev, "can't attach client %d\n", i);
1321                         ret = -ENOMEM;
1322                         goto fail_client_reg;
1323                 }
1324                 i2c_set_clientdata(tps->client, tps80031);
1325                 mutex_init(&tps->lock);
1326
1327                 tps80031->regmap[i] = devm_regmap_init_i2c(tps->client,
1328                                         &tps80031_regmap_configs[i]);
1329                 if (IS_ERR(tps80031->regmap[i])) {
1330                         ret = PTR_ERR(tps80031->regmap[i]);
1331                         dev_err(&client->dev,
1332                                 "regmap %d init failed, err %d\n", i, ret);
1333                         goto fail_client_reg;
1334                 }
1335         }
1336
1337         if (client->irq) {
1338                 ret = tps80031_irq_init(tps80031, client->irq,
1339                                         pdata->irq_base);
1340                 if (ret) {
1341                         dev_err(&client->dev, "IRQ init failed: %d\n", ret);
1342                         goto fail_client_reg;
1343                 }
1344         }
1345
1346         tps80031_pupd_init(tps80031, pdata);
1347
1348         tps80031_init_ext_control(tps80031, pdata);
1349
1350         ret = mfd_add_devices(tps80031->dev, -1,
1351                         tps80031_cell, ARRAY_SIZE(tps80031_cell), NULL, 0);
1352         if (ret < 0) {
1353                 dev_err(&client->dev, "mfd_add_devices failed: %d\n", ret);
1354                 goto fail_mfd_add;
1355         }
1356
1357         ret = tps80031_add_subdevs(tps80031, pdata);
1358         if (ret) {
1359                 dev_err(&client->dev, "add devices failed: %d\n", ret);
1360                 goto fail_add_subdev;
1361         }
1362
1363         tps80031_gpio_init(tps80031, pdata);
1364
1365         tps80031_clk32k_init(tps80031, pdata);
1366
1367         tps80031_debuginit(tps80031);
1368
1369         tps80031_backup_battery_charger_control(tps80031, 1);
1370
1371         if (pdata->use_power_off && !pm_power_off)
1372                 pm_power_off = tps80031_power_off;
1373
1374         tps80031_dev = tps80031;
1375
1376         return 0;
1377
1378 fail_add_subdev:
1379         mfd_remove_devices(tps80031->dev);
1380
1381 fail_mfd_add:
1382         if (client->irq)
1383                 free_irq(client->irq, tps80031);
1384 fail_client_reg:
1385         for (i = 0; i < TPS_NUM_SLAVES; i++) {
1386                 struct tps80031_client *tps = &tps80031->tps_clients[i];
1387                 if (tps->client && tps->client != client)
1388                         i2c_unregister_device(tps->client);
1389                 tps80031->tps_clients[i].client = NULL;
1390                 mutex_destroy(&tps->lock);
1391         }
1392         return ret;
1393 }
1394
1395 #ifdef CONFIG_PM
1396 static int tps80031_i2c_suspend(struct device *dev)
1397 {
1398         struct i2c_client *client = to_i2c_client(dev);
1399         struct tps80031 *tps80031 = i2c_get_clientdata(client);
1400         if (client->irq)
1401                 disable_irq(client->irq);
1402         tps80031_backup_battery_charger_control(tps80031, 0);
1403         return 0;
1404 }
1405
1406 static int tps80031_i2c_resume(struct device *dev)
1407 {
1408         struct i2c_client *client = to_i2c_client(dev);
1409         struct tps80031 *tps80031 = i2c_get_clientdata(client);
1410         tps80031_backup_battery_charger_control(tps80031, 1);
1411         if (client->irq)
1412                 enable_irq(client->irq);
1413         return 0;
1414 }
1415 static const struct dev_pm_ops tps80031_dev_pm_ops = {
1416         .suspend        = tps80031_i2c_suspend,
1417         .resume         = tps80031_i2c_resume,
1418 };
1419 #define TPS80031_DEV_PM (&tps80031_dev_pm_ops)
1420 #else
1421 #define TPS80031_DEV_PM NULL
1422 #endif
1423
1424
1425 static const struct i2c_device_id tps80031_id_table[] = {
1426         { "tps80031", TPS80031 },
1427         { "tps80032", TPS80032 },
1428 };
1429 MODULE_DEVICE_TABLE(i2c, tps80031_id_table);
1430
1431 static struct i2c_driver tps80031_driver = {
1432         .driver = {
1433                 .name   = "tps80031",
1434                 .owner  = THIS_MODULE,
1435                 .pm     = TPS80031_DEV_PM,
1436         },
1437         .probe          = tps80031_i2c_probe,
1438         .remove         = __devexit_p(tps80031_i2c_remove),
1439         .id_table       = tps80031_id_table,
1440 };
1441
1442 static int __init tps80031_init(void)
1443 {
1444         return i2c_add_driver(&tps80031_driver);
1445 }
1446 subsys_initcall(tps80031_init);
1447
1448 static void __exit tps80031_exit(void)
1449 {
1450         i2c_del_driver(&tps80031_driver);
1451 }
1452 module_exit(tps80031_exit);
1453
1454 MODULE_DESCRIPTION("TPS80031 core driver");
1455 MODULE_LICENSE("GPL");