Merge commit 'main-jb-2012.08.03-B4' into t114-0806
[linux-2.6.git] / drivers / mfd / tps80031.c
1 /*
2  * driver/mfd/tps80031.c
3  *
4  * Core driver for TI TPS80031
5  *
6  * Copyright (C) 2011 NVIDIA Corporation
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, write to the Free Software Foundation, Inc.,
20  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
21  *
22  */
23
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/mutex.h>
29 #include <linux/slab.h>
30 #include <linux/gpio.h>
31 #include <linux/i2c.h>
32 #include <linux/pm.h>
33 #include <linux/regmap.h>
34
35 #include <linux/mfd/core.h>
36 #include <linux/mfd/tps80031.h>
37
38 /* interrupt related registers */
39 #define TPS80031_INT_STS_A              0xD0
40 #define TPS80031_INT_STS_B              0xD1
41 #define TPS80031_INT_STS_C              0xD2
42 #define TPS80031_INT_MSK_LINE_A         0xD3
43 #define TPS80031_INT_MSK_LINE_B         0xD4
44 #define TPS80031_INT_MSK_LINE_C         0xD5
45 #define TPS80031_INT_MSK_STS_A          0xD6
46 #define TPS80031_INT_MSK_STS_B          0xD7
47 #define TPS80031_INT_MSK_STS_C          0xD8
48
49 #define TPS80031_CONTROLLER_STAT1               0xE3
50 #define CONTROLLER_STAT1_BAT_TEMP               0
51 #define CONTROLLER_STAT1_BAT_REMOVED            1
52 #define CONTROLLER_STAT1_VBUS_DET               2
53 #define CONTROLLER_STAT1_VAC_DET                3
54 #define CONTROLLER_STAT1_FAULT_WDG              4
55 #define CONTROLLER_STAT1_LINCH_GATED            6
56
57 #define TPS80031_CONTROLLER_INT_MASK            0xE0
58 #define CONTROLLER_INT_MASK_MVAC_DET            0
59 #define CONTROLLER_INT_MASK_MVBUS_DET           1
60 #define CONTROLLER_INT_MASK_MBAT_TEMP           2
61 #define CONTROLLER_INT_MASK_MFAULT_WDG          3
62 #define CONTROLLER_INT_MASK_MBAT_REMOVED        4
63 #define CONTROLLER_INT_MASK_MLINCH_GATED        5
64
65 #define CHARGE_CONTROL_SUB_INT_MASK             0x3F
66
67 /* Version number related register */
68 #define TPS80031_JTAGVERNUM             0x87
69 /* Epprom version */
70 #define TPS80031_EPROM_REV              0xDF
71
72 /* External control register */
73 #define REGEN1_BASE_ADD         0xAE
74 #define REGEN2_BASE_ADD         0xB1
75 #define SYSEN_BASE_ADD          0xB4
76
77 /* device control registers */
78 #define TPS80031_PHOENIX_DEV_ON 0x25
79 #define DEVOFF  1
80
81 #define CLK32KAO_BASE_ADD       0xBA
82 #define CLK32KG_BASE_ADD        0xBD
83 #define CLK32KAUDIO_BASE_ADD    0xC0
84
85 #define EXT_CONTROL_CFG_TRANS 0
86 #define EXT_CONTROL_CFG_STATE 1
87
88 #define STATE_OFF       0x00
89 #define STATE_ON        0x01
90 #define STATE_MASK      0x03
91
92 #define TRANS_SLEEP_OFF         0x00
93 #define TRANS_SLEEP_ON          0x04
94 #define TRANS_SLEEP_MASK        0x0C
95
96 #define TPS_NUM_SLAVES  4
97 #define EXT_PWR_REQ (PWR_REQ_INPUT_PREQ1 | PWR_REQ_INPUT_PREQ2 | \
98                 PWR_REQ_INPUT_PREQ3)
99 #define TPS80031_PREQ1_RES_ASS_A        0xD7
100 #define TPS80031_PREQ2_RES_ASS_A        0xDA
101 #define TPS80031_PREQ3_RES_ASS_A        0xDD
102 #define TPS80031_PHOENIX_MSK_TRANSITION 0x20
103
104 #define TPS80031_CFG_INPUT_PUPD1 0xF0
105 #define TPS80031_CFG_INPUT_PUPD2 0xF1
106 #define TPS80031_CFG_INPUT_PUPD3 0xF2
107 #define TPS80031_CFG_INPUT_PUPD4 0xF3
108
109 #define TPS80031_BBSPOR_CFG     0xE6
110 #define TPS80031_BBSPOR_CHG_EN  0x8
111
112 /* Valid Address ranges */
113 #define TPS80031_ID0_PMIC_SLAVE_SMPS_DVS        0x55 ... 0x5C
114
115 #define TPS80031_ID1_RTC                        0x00 ... 0x16
116 #define TPS80031_ID1_MEMORY                     0x17 ... 0x1E
117 #define TPS80031_ID1_PMC_MASTER                 0x1F ... 0x2D
118 #define TPS80031_ID1_PMC_SLAVE_MISC             0x31 ... 0x34
119 #define TPS80031_ID1_PMC_SLAVE_SMPS             0x40 ... 0x68
120 #define TPS80031_ID1_PMC_SLAVE_LDO              0x80 ... 0xA7
121 #define TPS80031_ID1_PMC_SLAVE_REOSURCES        0XAD ... 0xD0
122 #define TPS80031_ID1_PMC_PREQ_ASSIGN            0XD7 ... 0xDF
123 #define TPS80031_ID1_PMC_MISC                   0xE2 ... 0xEF
124 #define TPS80031_ID1_PMC_PU_PD_HZ               0xF0 ... 0xF6
125 #define TPS80031_ID1_PMC_BACKUP                 0xFA
126
127 #define TPS80031_ID2_USB                        0x00 ... 0x1A
128 #define TPS80031_ID2_GPADC_CONTROL              0x2E ... 0x36
129 #define TPS80031_ID2_GPADC_RESULTS              0x37 ... 0x3C
130 #define TPS80031_ID2_AUXILLIARIES               0x90 ... 0x9C
131 #define TPS80031_ID2_CUSTOM                     0xA0 ... 0xB9
132 #define TPS80031_ID2_PWM                        0xBA ... 0xBE
133 #define TPS80031_ID2_FUEL_GAUSE                 0xC0 ... 0xCB
134 #define TPS80031_ID2_INTERFACE_INTERRUPTS       0xD0 ... 0xD8
135 #define TPS80031_ID2_CHARGER                    0xDA ... 0xF5
136
137 #define TPS80031_ID3_TEST_LDO                   0x00 ... 0x09
138 #define TPS80031_ID3_TEST_SMPS                  0x10 ... 0x2B
139 #define TPS80031_ID3_TEST_POWER                 0x30 ... 0x36
140 #define TPS80031_ID3_TEST_CHARGER               0x40 ... 0x48
141 #define TPS80031_ID3_TEST_AUXILIIARIES          0x50 ... 0xB1
142
143 #define TPS80031_ID3_DIEID                      0xC0 ... 0xC8
144 #define TPS80031_ID3_TRIM_PHOENIX               0xCC ... 0xEA
145 #define TPS80031_ID3_TRIM_CUSTOM                0xEC ... 0xED
146
147 #define TPS80031_MAX_REGISTER   0x100
148
149 struct tps80031_pupd_data {
150         u8      reg;
151         u8      pullup_bit;
152         u8      pulldown_bit;
153 };
154
155 static u8 pmc_ext_control_base[] = {
156         REGEN1_BASE_ADD,
157         REGEN2_BASE_ADD,
158         SYSEN_BASE_ADD,
159 };
160
161 static u8 pmc_clk32k_control_base[] = {
162         CLK32KAO_BASE_ADD,
163         CLK32KG_BASE_ADD,
164         CLK32KAUDIO_BASE_ADD,
165 };
166 struct tps80031_irq_data {
167         u8      mask_reg;
168         u8      mask_mask;
169         u8      is_sec_int;
170         u8      parent_int;
171         u8      mask_sec_int_reg;
172         u8      int_mask_bit;
173         u8      int_sec_sts_reg;
174         u8      int_sts_bit;
175 };
176
177 #define TPS80031_IRQ(_reg, _mask)       \
178         {                                                       \
179                 .mask_reg = (TPS80031_INT_MSK_LINE_##_reg) -    \
180                                 TPS80031_INT_MSK_LINE_A,        \
181                 .mask_mask = (_mask),                           \
182         }
183
184 #define TPS80031_IRQ_SEC(_reg, _mask, _pint, _sint_mask_bit, _sint_sts_bit) \
185         {                                                               \
186                 .mask_reg = (TPS80031_INT_MSK_LINE_##_reg) -            \
187                                 TPS80031_INT_MSK_LINE_A,                \
188                 .mask_mask = (_mask),                                   \
189                 .is_sec_int = true,                                     \
190                 .parent_int = TPS80031_INT_##_pint,                     \
191                 .mask_sec_int_reg = TPS80031_CONTROLLER_INT_MASK,       \
192                 .int_mask_bit = CONTROLLER_INT_MASK_##_sint_mask_bit,   \
193                 .int_sec_sts_reg = TPS80031_CONTROLLER_STAT1,           \
194                 .int_sts_bit = CONTROLLER_STAT1_##_sint_sts_bit         \
195         }
196
197 static const struct tps80031_irq_data tps80031_irqs[] = {
198
199         [TPS80031_INT_PWRON]            = TPS80031_IRQ(A, 0),
200         [TPS80031_INT_RPWRON]           = TPS80031_IRQ(A, 1),
201         [TPS80031_INT_SYS_VLOW]         = TPS80031_IRQ(A, 2),
202         [TPS80031_INT_RTC_ALARM]        = TPS80031_IRQ(A, 3),
203         [TPS80031_INT_RTC_PERIOD]       = TPS80031_IRQ(A, 4),
204         [TPS80031_INT_HOT_DIE]          = TPS80031_IRQ(A, 5),
205         [TPS80031_INT_VXX_SHORT]        = TPS80031_IRQ(A, 6),
206         [TPS80031_INT_SPDURATION]       = TPS80031_IRQ(A, 7),
207         [TPS80031_INT_WATCHDOG]         = TPS80031_IRQ(B, 0),
208         [TPS80031_INT_BAT]              = TPS80031_IRQ(B, 1),
209         [TPS80031_INT_SIM]              = TPS80031_IRQ(B, 2),
210         [TPS80031_INT_MMC]              = TPS80031_IRQ(B, 3),
211         [TPS80031_INT_RES]              = TPS80031_IRQ(B, 4),
212         [TPS80031_INT_GPADC_RT]         = TPS80031_IRQ(B, 5),
213         [TPS80031_INT_GPADC_SW2_EOC]    = TPS80031_IRQ(B, 6),
214         [TPS80031_INT_CC_AUTOCAL]       = TPS80031_IRQ(B, 7),
215         [TPS80031_INT_ID_WKUP]          = TPS80031_IRQ(C, 0),
216         [TPS80031_INT_VBUSS_WKUP]       = TPS80031_IRQ(C, 1),
217         [TPS80031_INT_ID]               = TPS80031_IRQ(C, 2),
218         [TPS80031_INT_VBUS]             = TPS80031_IRQ(C, 3),
219         [TPS80031_INT_CHRG_CTRL]        = TPS80031_IRQ(C, 4),
220         [TPS80031_INT_EXT_CHRG]         = TPS80031_IRQ(C, 5),
221         [TPS80031_INT_INT_CHRG]         = TPS80031_IRQ(C, 6),
222         [TPS80031_INT_RES2]             = TPS80031_IRQ(C, 7),
223         [TPS80031_INT_BAT_TEMP_OVRANGE] = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
224                                                 MBAT_TEMP,      BAT_TEMP),
225         [TPS80031_INT_BAT_REMOVED]      = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
226                                                 MBAT_REMOVED,   BAT_REMOVED),
227         [TPS80031_INT_VBUS_DET]         = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
228                                                 MVBUS_DET,      VBUS_DET),
229         [TPS80031_INT_VAC_DET]          = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
230                                                 MVAC_DET,       VAC_DET),
231         [TPS80031_INT_FAULT_WDG]        = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
232                                                 MFAULT_WDG,     FAULT_WDG),
233         [TPS80031_INT_LINCH_GATED]      = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
234                                                 MLINCH_GATED,   LINCH_GATED),
235 };
236
237 #define PUPD_DATA(_reg, _pulldown_bit, _pullup_bit)     \
238         {                                               \
239                 .reg = TPS80031_CFG_INPUT_PUPD##_reg,   \
240                 .pulldown_bit = _pulldown_bit,          \
241                 .pullup_bit = _pullup_bit,              \
242         }
243
244 static const struct tps80031_pupd_data tps80031_pupds[] = {
245         [TPS80031_PREQ1]                = PUPD_DATA(1, 1 << 0,  1 << 1  ),
246         [TPS80031_PREQ2A]               = PUPD_DATA(1, 1 << 2,  1 << 3  ),
247         [TPS80031_PREQ2B]               = PUPD_DATA(1, 1 << 4,  1 << 5  ),
248         [TPS80031_PREQ2C]               = PUPD_DATA(1, 1 << 6,  1 << 7  ),
249         [TPS80031_PREQ3]                = PUPD_DATA(2, 1 << 0,  1 << 1  ),
250         [TPS80031_NRES_WARM]            = PUPD_DATA(2, 0,       1 << 2  ),
251         [TPS80031_PWM_FORCE]            = PUPD_DATA(2, 1 << 5,  0       ),
252         [TPS80031_CHRG_EXT_CHRG_STATZ]  = PUPD_DATA(2, 0,       1 << 6  ),
253         [TPS80031_SIM]                  = PUPD_DATA(3, 1 << 0,  1 << 1  ),
254         [TPS80031_MMC]                  = PUPD_DATA(3, 1 << 2,  1 << 3  ),
255         [TPS80031_GPADC_START]          = PUPD_DATA(3, 1 << 4,  0       ),
256         [TPS80031_DVSI2C_SCL]           = PUPD_DATA(4, 0,       1 << 0  ),
257         [TPS80031_DVSI2C_SDA]           = PUPD_DATA(4, 0,       1 << 1  ),
258         [TPS80031_CTLI2C_SCL]           = PUPD_DATA(4, 0,       1 << 2  ),
259         [TPS80031_CTLI2C_SDA]           = PUPD_DATA(4, 0,       1 << 3  ),
260 };
261
262 static const int controller_stat1_irq_nr[] = {
263         TPS80031_INT_BAT_TEMP_OVRANGE,
264         TPS80031_INT_BAT_REMOVED,
265         TPS80031_INT_VBUS_DET,
266         TPS80031_INT_VAC_DET,
267         TPS80031_INT_FAULT_WDG,
268         0,
269         TPS80031_INT_LINCH_GATED,
270         0
271 };
272
273 /* Structure for TPS80031 Slaves */
274 struct tps80031_client {
275         struct i2c_client *client;
276         struct mutex lock;
277         u8 addr;
278 };
279
280 struct tps80031 {
281         struct device           *dev;
282         unsigned long           chip_info;
283         int                     es_version;
284
285         struct gpio_chip        gpio;
286         struct irq_chip         irq_chip;
287         struct mutex            irq_lock;
288         int                     irq_base;
289         u32                     irq_en;
290         u8                      mask_cache[3];
291         u8                      mask_reg[3];
292         u8                      cont_int_mask_reg;
293         u8                      cont_int_mask_cache;
294         u8                      cont_int_en;
295         u8                      prev_cont_stat1;
296         struct tps80031_client  tps_clients[TPS_NUM_SLAVES];
297         struct regmap           *regmap[TPS_NUM_SLAVES];
298 };
299
300 /* TPS80031 sub mfd devices */
301 static struct mfd_cell tps80031_cell[] = {
302         {
303                 .name = "tps80031-regulators",
304         },
305 };
306
307
308 int tps80031_write(struct device *dev, int sid, int reg, uint8_t val)
309 {
310         struct tps80031 *tps80031 = dev_get_drvdata(dev);
311
312         return regmap_write(tps80031->regmap[sid], reg, val);
313 }
314 EXPORT_SYMBOL_GPL(tps80031_write);
315
316 int tps80031_writes(struct device *dev, int sid, int reg, int len, uint8_t *val)
317 {
318         struct tps80031 *tps80031 = dev_get_drvdata(dev);
319
320         return regmap_bulk_write(tps80031->regmap[sid], reg, val, len);
321 }
322 EXPORT_SYMBOL_GPL(tps80031_writes);
323
324 int tps80031_read(struct device *dev, int sid, int reg, uint8_t *val)
325 {
326         struct tps80031 *tps80031 = dev_get_drvdata(dev);
327         unsigned int ival;
328         int ret;
329
330         ret = regmap_read(tps80031->regmap[sid], reg, &ival);
331         if (ret < 0) {
332                 dev_err(dev, "failed reading from reg 0x%02x\n", reg);
333                 return ret;
334         }
335
336         *val = ival;
337         return ret;
338 }
339 EXPORT_SYMBOL_GPL(tps80031_read);
340
341 int tps80031_reads(struct device *dev, int sid, int reg, int len, uint8_t *val)
342 {
343         struct tps80031 *tps80031 = dev_get_drvdata(dev);
344
345         return regmap_bulk_read(tps80031->regmap[sid], reg, val, len);
346 }
347 EXPORT_SYMBOL_GPL(tps80031_reads);
348
349 int tps80031_set_bits(struct device *dev, int sid, int reg, uint8_t bit_mask)
350 {
351         struct tps80031 *tps80031 = dev_get_drvdata(dev);
352
353         return regmap_update_bits(tps80031->regmap[sid], reg,
354                                 bit_mask, bit_mask);
355 }
356 EXPORT_SYMBOL_GPL(tps80031_set_bits);
357
358 int tps80031_clr_bits(struct device *dev, int sid, int reg, uint8_t bit_mask)
359 {
360         struct tps80031 *tps80031 = dev_get_drvdata(dev);
361
362         return regmap_update_bits(tps80031->regmap[sid], reg, bit_mask, 0);
363 }
364 EXPORT_SYMBOL_GPL(tps80031_clr_bits);
365
366 int tps80031_update(struct device *dev, int sid, int reg, uint8_t val,
367                 uint8_t mask)
368 {
369         struct tps80031 *tps80031 = dev_get_drvdata(dev);
370
371         return regmap_update_bits(tps80031->regmap[sid], reg, mask, val);
372 }
373 EXPORT_SYMBOL_GPL(tps80031_update);
374
375 int tps80031_force_update(struct device *dev, int sid, int reg, uint8_t val,
376                           uint8_t mask)
377 {
378         struct tps80031 *tps80031 = dev_get_drvdata(dev);
379         struct tps80031_client *tps = &tps80031->tps_clients[sid];
380         uint8_t reg_val;
381         int ret = 0;
382
383         mutex_lock(&tps->lock);
384
385         ret = tps80031_read(dev, sid, reg, &reg_val);
386         if (ret)
387                 goto out;
388
389         reg_val = (reg_val & ~mask) | (val & mask);
390         ret = tps80031_write(dev, sid, reg, reg_val);
391
392 out:
393         mutex_unlock(&tps->lock);
394         return ret;
395 }
396 EXPORT_SYMBOL_GPL(tps80031_force_update);
397
398 int tps80031_ext_power_req_config(struct device *dev,
399                 unsigned long ext_ctrl_flag, int preq_bit,
400                 int state_reg_add, int trans_reg_add)
401 {
402         u8 res_ass_reg = 0;
403         int preq_mask_bit = 0;
404         int ret;
405
406         if (!(ext_ctrl_flag & EXT_PWR_REQ))
407                 return 0;
408
409         if (ext_ctrl_flag & PWR_REQ_INPUT_PREQ1) {
410                 res_ass_reg = TPS80031_PREQ1_RES_ASS_A + (preq_bit >> 3);
411                 preq_mask_bit = 5;
412         } else if (ext_ctrl_flag & PWR_REQ_INPUT_PREQ2) {
413                 res_ass_reg = TPS80031_PREQ2_RES_ASS_A + (preq_bit >> 3);
414                 preq_mask_bit = 6;
415         } else if (ext_ctrl_flag & PWR_REQ_INPUT_PREQ3) {
416                 res_ass_reg = TPS80031_PREQ3_RES_ASS_A + (preq_bit >> 3);
417                 preq_mask_bit = 7;
418         }
419
420         /* Configure REQ_ASS registers */
421         ret = tps80031_set_bits(dev, SLAVE_ID1, res_ass_reg,
422                                         BIT(preq_bit & 0x7));
423         if (ret < 0) {
424                 dev_err(dev, "%s() Not able to set bit %d of "
425                         "reg %d error %d\n",
426                         __func__, preq_bit, res_ass_reg, ret);
427                 return ret;
428         }
429
430         /* Unmask the PREQ */
431         ret = tps80031_clr_bits(dev, SLAVE_ID1,
432                         TPS80031_PHOENIX_MSK_TRANSITION, BIT(preq_mask_bit));
433         if (ret < 0) {
434                 dev_err(dev, "%s() Not able to clear bit %d of "
435                         "reg %d error %d\n",
436                          __func__, preq_mask_bit,
437                         TPS80031_PHOENIX_MSK_TRANSITION, ret);
438                 return ret;
439         }
440
441         /* Switch regulator control to resource now */
442         if (ext_ctrl_flag & (PWR_REQ_INPUT_PREQ2 | PWR_REQ_INPUT_PREQ3)) {
443                 ret = tps80031_update(dev, SLAVE_ID1, state_reg_add, 0x0,
444                                                 STATE_MASK);
445                 if (ret < 0)
446                         dev_err(dev, "%s() Error in writing the STATE "
447                                 "register %d error %d\n", __func__,
448                                 state_reg_add, ret);
449         } else {
450                 ret = tps80031_update(dev, SLAVE_ID1, trans_reg_add,
451                                 TRANS_SLEEP_OFF, TRANS_SLEEP_MASK);
452                 if (ret < 0)
453                         dev_err(dev, "%s() Error in writing the TRANS "
454                                 "register %d error %d\n", __func__,
455                                 trans_reg_add, ret);
456         }
457         return ret;
458 }
459 EXPORT_SYMBOL_GPL(tps80031_ext_power_req_config);
460
461 unsigned long tps80031_get_chip_info(struct device *dev)
462 {
463         struct tps80031 *tps80031 = dev_get_drvdata(dev);
464         return tps80031->chip_info;
465 }
466 EXPORT_SYMBOL_GPL(tps80031_get_chip_info);
467
468 int tps80031_get_pmu_version(struct device *dev)
469 {
470         struct tps80031 *tps80031 = dev_get_drvdata(dev);
471         return tps80031->es_version;
472 }
473 EXPORT_SYMBOL_GPL(tps80031_get_pmu_version);
474
475 static struct tps80031 *tps80031_dev;
476 static void tps80031_power_off(void)
477 {
478         struct tps80031_client *tps = &tps80031_dev->tps_clients[SLAVE_ID1];
479
480         if (!tps->client)
481                 return;
482         dev_info(&tps->client->dev, "switching off PMU\n");
483         tps80031_write(&tps->client->dev, SLAVE_ID1,
484                                 TPS80031_PHOENIX_DEV_ON, DEVOFF);
485 }
486
487 static void tps80031_pupd_init(struct tps80031 *tps80031,
488                                struct tps80031_platform_data *pdata)
489 {
490         struct tps80031_pupd_init_data *pupd_init_data = pdata->pupd_init_data;
491         int data_size = pdata->pupd_init_data_size;
492         int i;
493
494         for (i = 0; i < data_size; ++i) {
495                 struct tps80031_pupd_init_data *pupd_init = &pupd_init_data[i];
496                 const struct tps80031_pupd_data *pupd =
497                         &tps80031_pupds[pupd_init->input_pin];
498                 u8 update_value = 0;
499                 u8 update_mask = pupd->pulldown_bit | pupd->pullup_bit;
500
501                 if (pupd_init->setting == TPS80031_PUPD_PULLDOWN)
502                         update_value = pupd->pulldown_bit;
503                 else if (pupd_init->setting == TPS80031_PUPD_PULLUP)
504                         update_value = pupd->pullup_bit;
505
506                 tps80031_update(tps80031->dev, SLAVE_ID1, pupd->reg,
507                                 update_value, update_mask);
508         }
509 }
510
511 static void tps80031_backup_battery_charger_control(struct tps80031 *tps80031,
512                                                     int enable)
513 {
514         if (enable)
515                 tps80031_update(tps80031->dev, SLAVE_ID1, TPS80031_BBSPOR_CFG,
516                                 TPS80031_BBSPOR_CHG_EN, TPS80031_BBSPOR_CHG_EN);
517         else
518                 tps80031_update(tps80031->dev, SLAVE_ID1, TPS80031_BBSPOR_CFG,
519                                 0, TPS80031_BBSPOR_CHG_EN);
520 }
521
522 static void tps80031_init_ext_control(struct tps80031 *tps80031,
523                         struct tps80031_platform_data *pdata) {
524         int ret;
525         int i;
526
527         /* Clear all external control for this rail */
528         for (i = 0; i < 9; ++i) {
529                 ret = tps80031_write(tps80031->dev, SLAVE_ID1,
530                                 TPS80031_PREQ1_RES_ASS_A + i, 0);
531                 if (ret < 0)
532                         dev_err(tps80031->dev, "%s() Error in clearing "
533                                 "register %02x\n", __func__,
534                                 TPS80031_PREQ1_RES_ASS_A + i);
535         }
536
537         /* Mask the PREQ */
538         ret = tps80031_set_bits(tps80031->dev, SLAVE_ID1,
539                         TPS80031_PHOENIX_MSK_TRANSITION, 0x7 << 5);
540         if (ret < 0)
541                 dev_err(tps80031->dev, "%s() Not able to mask register "
542                         "0x%02x\n", __func__, TPS80031_PHOENIX_MSK_TRANSITION);
543 }
544
545 static int tps80031_gpio_get(struct gpio_chip *gc, unsigned offset)
546 {
547         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
548         struct tps80031_client *tps = &tps80031->tps_clients[SLAVE_ID1];
549         uint8_t state;
550         uint8_t trans;
551         int ret;
552
553         ret = tps80031_read(&tps->client->dev, SLAVE_ID1,
554                         pmc_ext_control_base[offset] +
555                                 EXT_CONTROL_CFG_STATE, &state);
556         if (ret)
557                 return ret;
558
559         if (state != 0) {
560                 ret = tps80031_read(&tps->client->dev, SLAVE_ID1,
561                                 pmc_ext_control_base[offset] +
562                                         EXT_CONTROL_CFG_TRANS, &trans);
563                 if (ret)
564                         return ret;
565                 return trans & 0x1;
566         }
567         return 0;
568 }
569
570 static void tps80031_gpio_set(struct gpio_chip *gc, unsigned offset,
571                         int value)
572 {
573         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
574
575         tps80031_update(tps80031->dev, SLAVE_ID1,
576                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_TRANS,
577                         value, 0x1);
578 }
579
580 static int tps80031_gpio_input(struct gpio_chip *gc, unsigned offset)
581 {
582         return -EIO;
583 }
584
585 static int tps80031_gpio_output(struct gpio_chip *gc, unsigned offset,
586                                 int value)
587 {
588         tps80031_gpio_set(gc, offset, value);
589         return 0;
590 }
591
592 static int tps80031_gpio_enable(struct gpio_chip *gc, unsigned offset)
593 {
594         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
595         int ret;
596
597         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
598                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_STATE,
599                                                 STATE_ON, STATE_MASK);
600         if (ret)
601                 return ret;
602
603         return tps80031_write(tps80031->dev, SLAVE_ID1,
604                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_TRANS, 0x0);
605 }
606
607 static void tps80031_gpio_disable(struct gpio_chip *gc, unsigned offset)
608 {
609         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
610         tps80031_update(tps80031->dev, SLAVE_ID1,
611                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_STATE,
612                                                 STATE_OFF, STATE_MASK);
613 }
614
615 static void tps80031_gpio_init(struct tps80031 *tps80031,
616                         struct tps80031_platform_data *pdata)
617 {
618         int ret;
619         int gpio_base = pdata->gpio_base;
620         struct tps80031_client *tps = &tps80031->tps_clients[SLAVE_ID1];
621         struct tps80031_gpio_init_data *gpio_init_data = pdata->gpio_init_data;
622         int data_size = pdata->gpio_init_data_size;
623         static int preq_bit_pos[TPS80031_GPIO_NR] = {16, 17, 18};
624         int base_add;
625         int i;
626
627         if (gpio_base <= 0)
628                 return;
629
630         /* Configure the external request mode */
631         for (i = 0; i < data_size; ++i) {
632                 struct tps80031_gpio_init_data *gpio_pd = &gpio_init_data[i];
633                 base_add = pmc_ext_control_base[gpio_pd->gpio_nr];
634
635                 if (gpio_pd->ext_ctrl_flag & EXT_PWR_REQ) {
636                         ret = tps80031_ext_power_req_config(tps80031->dev,
637                                 gpio_pd->ext_ctrl_flag,
638                                 preq_bit_pos[gpio_pd->gpio_nr],
639                                 base_add + EXT_CONTROL_CFG_STATE,
640                                 base_add + EXT_CONTROL_CFG_TRANS);
641                         if (ret < 0)
642                                 dev_warn(tps80031->dev, "Ext pwrreq GPIO "
643                                         "sleep control fails\n");
644                 }
645
646                 if (gpio_pd->ext_ctrl_flag & PWR_OFF_ON_SLEEP) {
647                         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
648                                 base_add + EXT_CONTROL_CFG_TRANS, 0x0, 0xC);
649                         if (ret < 0)
650                                 dev_warn(tps80031->dev, "GPIO OFF on sleep "
651                                         "control fails\n");
652                 }
653
654                 if (gpio_pd->ext_ctrl_flag & PWR_ON_ON_SLEEP) {
655                         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
656                                 base_add + EXT_CONTROL_CFG_TRANS, 0x4, 0xC);
657                         if (ret < 0)
658                                 dev_warn(tps80031->dev, "GPIO ON on sleep "
659                                         "control fails\n");
660                 }
661         }
662
663         tps80031->gpio.owner            = THIS_MODULE;
664         tps80031->gpio.label            = tps->client->name;
665         tps80031->gpio.dev              = tps80031->dev;
666         tps80031->gpio.base             = gpio_base;
667         tps80031->gpio.ngpio            = TPS80031_GPIO_NR;
668         tps80031->gpio.can_sleep        = 1;
669
670         tps80031->gpio.request          = tps80031_gpio_enable;
671         tps80031->gpio.free             = tps80031_gpio_disable;
672         tps80031->gpio.direction_input  = tps80031_gpio_input;
673         tps80031->gpio.direction_output = tps80031_gpio_output;
674         tps80031->gpio.set              = tps80031_gpio_set;
675         tps80031->gpio.get              = tps80031_gpio_get;
676
677         ret = gpiochip_add(&tps80031->gpio);
678         if (ret)
679                 dev_warn(tps80031->dev, "GPIO registration failed: %d\n", ret);
680 }
681
682 static int __remove_subdev(struct device *dev, void *unused)
683 {
684         platform_device_unregister(to_platform_device(dev));
685         return 0;
686 }
687
688 static int tps80031_remove_subdevs(struct tps80031 *tps80031)
689 {
690         return device_for_each_child(tps80031->dev, NULL, __remove_subdev);
691 }
692
693 static void tps80031_irq_lock(struct irq_data *data)
694 {
695         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
696
697         mutex_lock(&tps80031->irq_lock);
698 }
699
700 static void tps80031_irq_enable(struct irq_data *data)
701 {
702         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
703         unsigned int __irq = data->irq - tps80031->irq_base;
704         const struct tps80031_irq_data *irq_data = &tps80031_irqs[__irq];
705
706         if (irq_data->is_sec_int) {
707                 tps80031->cont_int_mask_reg &= ~(1 << irq_data->int_mask_bit);
708                 tps80031->cont_int_en |= (1 << irq_data->int_mask_bit);
709                 tps80031->mask_reg[irq_data->mask_reg] &= ~(1 << irq_data->mask_mask);
710                 tps80031->irq_en |= (1 << irq_data->parent_int);
711         } else
712                 tps80031->mask_reg[irq_data->mask_reg] &= ~(1 << irq_data->mask_mask);
713
714         tps80031->irq_en |= (1 << __irq);
715 }
716
717 static void tps80031_irq_disable(struct irq_data *data)
718 {
719         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
720
721         unsigned int __irq = data->irq - tps80031->irq_base;
722         const struct tps80031_irq_data *irq_data = &tps80031_irqs[__irq];
723
724         if (irq_data->is_sec_int) {
725                 tps80031->cont_int_mask_reg |= (1 << irq_data->int_mask_bit);
726                 tps80031->cont_int_en &= ~(1 << irq_data->int_mask_bit);
727                 if (!tps80031->cont_int_en) {
728                         tps80031->mask_reg[irq_data->mask_reg] |=
729                                                 (1 << irq_data->mask_mask);
730                         tps80031->irq_en &= ~(1 << irq_data->parent_int);
731                 }
732                 tps80031->irq_en &= ~(1 << __irq);
733         } else
734                 tps80031->mask_reg[irq_data->mask_reg] |= (1 << irq_data->mask_mask);
735
736         tps80031->irq_en &= ~(1 << __irq);
737 }
738
739 static void tps80031_irq_sync_unlock(struct irq_data *data)
740 {
741         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
742         int i;
743
744         for (i = 0; i < ARRAY_SIZE(tps80031->mask_reg); i++) {
745                 if (tps80031->mask_reg[i] != tps80031->mask_cache[i]) {
746                         if (!WARN_ON(tps80031_write(tps80031->dev, SLAVE_ID2,
747                                                 TPS80031_INT_MSK_LINE_A + i,
748                                                 tps80031->mask_reg[i])))
749                                 if (!WARN_ON(tps80031_write(tps80031->dev,
750                                                 SLAVE_ID2,
751                                                 TPS80031_INT_MSK_STS_A + i,
752                                                 tps80031->mask_reg[i])))
753                                         tps80031->mask_cache[i] =
754                                                         tps80031->mask_reg[i];
755                 }
756         }
757
758         if (tps80031->cont_int_mask_reg != tps80031->cont_int_mask_cache) {
759                 if (!WARN_ON(tps80031_write(tps80031->dev, SLAVE_ID2,
760                                 TPS80031_CONTROLLER_INT_MASK,
761                                 tps80031->cont_int_mask_reg)))
762                         tps80031->cont_int_mask_cache =
763                                                 tps80031->cont_int_mask_reg;
764         }
765
766         mutex_unlock(&tps80031->irq_lock);
767 }
768
769 static irqreturn_t tps80031_charge_control_irq(int irq, void *data)
770 {
771         struct tps80031 *tps80031 = data;
772         int ret = 0;
773         int i;
774         u8 cont_sts;
775         u8 org_sts;
776         if (irq != (tps80031->irq_base + TPS80031_INT_CHRG_CTRL)) {
777                 dev_err(tps80031->dev, "%s() Got the illegal interrupt %d\n",
778                                         __func__, irq);
779                 return IRQ_NONE;
780         }
781
782         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
783                         TPS80031_CONTROLLER_STAT1, &org_sts);
784         if (ret < 0) {
785                 dev_err(tps80031->dev, "%s(): failed to read controller state1 "
786                                 "status %d\n", __func__, ret);
787                 return IRQ_NONE;
788         }
789
790         /* Get change from last interrupt and mask for interested interrupt
791          * for charge control interrupt */
792         cont_sts = org_sts ^ tps80031->prev_cont_stat1;
793         tps80031->prev_cont_stat1 = org_sts;
794         /* Clear watchdog timer state */
795         tps80031->prev_cont_stat1 &= ~(1 << 4);
796         cont_sts &= 0x5F;
797
798         for (i = 0; i < 8; ++i) {
799                 if (!controller_stat1_irq_nr[i])
800                         continue;
801
802                 if ((cont_sts & BIT(i)) &&
803                         (tps80031->irq_en & BIT(controller_stat1_irq_nr[i])))
804                         handle_nested_irq(tps80031->irq_base +
805                                                 controller_stat1_irq_nr[i]);
806                 cont_sts &= ~BIT(i);
807         }
808         return IRQ_HANDLED;
809 }
810
811 static irqreturn_t tps80031_irq(int irq, void *data)
812 {
813         struct tps80031 *tps80031 = data;
814         int ret = 0;
815         u32 acks;
816         int i;
817         uint8_t tmp[3];
818
819         ret = tps80031_reads(tps80031->dev, SLAVE_ID2,
820                              TPS80031_INT_STS_A, 3, tmp);
821         if (ret < 0) {
822                 dev_err(tps80031->dev, "failed to read interrupt status\n");
823                 return IRQ_NONE;
824         }
825         acks = (tmp[2] << 16) | (tmp[1] << 8) | tmp[0];
826
827         if (acks) {
828                 /*
829                  * Hardware behavior: hardware have the shadow register for
830                  * interrupt status register which is updated if interrupt
831                  * comes just after the interrupt status read. This shadow
832                  * register gets written to main status register and cleared
833                  * if any byte write happens in any of status register like
834                  * STS_A, STS_B or STS_C.
835                  * Hence here to clear the original interrupt status and
836                  * updating the STS register with the shadow register, it is
837                  * require to write only one byte in any of STS register.
838                  * Having multiple register write can cause the STS register
839                  * to clear without handling those interrupt and can cause
840                  * interrupt miss.
841                  */
842                 ret = tps80031_write(tps80031->dev, SLAVE_ID2,
843                                       TPS80031_INT_STS_A, 0);
844                 if (ret < 0) {
845                         dev_err(tps80031->dev, "failed to write "
846                                                 "interrupt status\n");
847                         return IRQ_NONE;
848                 }
849
850                 while (acks) {
851                         i = __ffs(acks);
852                         if (tps80031->irq_en & (1 << i))
853                                 handle_nested_irq(tps80031->irq_base + i);
854                         acks &= ~(1 << i);
855                 }
856         }
857
858         return IRQ_HANDLED;
859 }
860
861 static int __devinit tps80031_irq_init(struct tps80031 *tps80031, int irq,
862                                 int irq_base)
863 {
864         int i, ret;
865
866         if (!irq_base) {
867                 dev_warn(tps80031->dev, "No interrupt support on IRQ base\n");
868                 return -EINVAL;
869         }
870
871         mutex_init(&tps80031->irq_lock);
872
873         for (i = 0; i < 3; i++) {
874                 tps80031->mask_reg[i] = 0xFF;
875                 tps80031->mask_cache[i] = tps80031->mask_reg[i];
876                 tps80031_write(tps80031->dev, SLAVE_ID2,
877                                         TPS80031_INT_MSK_LINE_A + i,
878                                         tps80031->mask_cache[i]);
879                 tps80031_write(tps80031->dev, SLAVE_ID2,
880                                         TPS80031_INT_MSK_STS_A + i, 0xFF);
881                 tps80031_write(tps80031->dev, SLAVE_ID2,
882                                         TPS80031_INT_STS_A + i, 0xFF);
883         }
884
885         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
886                                 TPS80031_CONTROLLER_INT_MASK,
887                                 &tps80031->cont_int_mask_reg);
888         if (ret < 0) {
889                 dev_err(tps80031->dev, "Error in reading the controller_mask "
890                                         "register %d\n", ret);
891                 return ret;
892         }
893
894         tps80031->cont_int_mask_reg |= CHARGE_CONTROL_SUB_INT_MASK;
895         tps80031->cont_int_mask_cache = tps80031->cont_int_mask_reg;
896         tps80031->cont_int_en = 0;
897         ret = tps80031_write(tps80031->dev, SLAVE_ID2,
898                                 TPS80031_CONTROLLER_INT_MASK,
899                                 tps80031->cont_int_mask_reg);
900         if (ret < 0) {
901                 dev_err(tps80031->dev, "Error in writing the controller_mask "
902                                         "register %d\n", ret);
903                 return ret;
904         }
905
906         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
907                         TPS80031_CONTROLLER_STAT1, &tps80031->prev_cont_stat1);
908         if (ret < 0) {
909                 dev_err(tps80031->dev, "%s(): failed to read controller state1 "
910                                 "status %d\n", __func__, ret);
911                 return ret;
912         }
913
914         /* Clear watch dog interrupt status in status */
915         tps80031->prev_cont_stat1 &= ~(1 << 4);
916
917         tps80031->irq_base = irq_base;
918
919         tps80031->irq_chip.name = "tps80031";
920         tps80031->irq_chip.irq_enable = tps80031_irq_enable;
921         tps80031->irq_chip.irq_disable = tps80031_irq_disable;
922         tps80031->irq_chip.irq_bus_lock = tps80031_irq_lock;
923         tps80031->irq_chip.irq_bus_sync_unlock = tps80031_irq_sync_unlock;
924
925         for (i = 0; i < TPS80031_INT_NR; i++) {
926                 int __irq = i + tps80031->irq_base;
927                 irq_set_chip_data(__irq, tps80031);
928                 irq_set_chip_and_handler(__irq, &tps80031->irq_chip,
929                                          handle_simple_irq);
930                 irq_set_nested_thread(__irq, 1);
931 #ifdef CONFIG_ARM
932                 set_irq_flags(__irq, IRQF_VALID);
933 #endif
934         }
935
936         ret = request_threaded_irq(irq, NULL, tps80031_irq, IRQF_ONESHOT,
937                                 "tps80031", tps80031);
938         /* register the isr for the secondary interrupt */
939         if (!ret)
940                 ret = request_threaded_irq(irq_base + TPS80031_INT_CHRG_CTRL,
941                                 NULL, tps80031_charge_control_irq,
942                                 IRQF_ONESHOT, "80031_chg_ctl", tps80031);
943         if (!ret) {
944
945                 device_init_wakeup(tps80031->dev, 1);
946                 enable_irq_wake(irq);
947         }
948
949         return ret;
950 }
951
952 static void tps80031_clk32k_enable(struct tps80031 *tps80031, int base_add)
953 {
954         int ret;
955         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
956                         base_add + EXT_CONTROL_CFG_STATE, STATE_ON, STATE_MASK);
957         if (!ret)
958                 ret = tps80031_update(tps80031->dev, SLAVE_ID1,
959                                 base_add + EXT_CONTROL_CFG_TRANS,
960                                 STATE_ON, STATE_MASK);
961         if (ret < 0)
962                 dev_err(tps80031->dev, "Error in updating clock register\n");
963 }
964
965 static void tps80031_clk32k_init(struct tps80031 *tps80031,
966                         struct tps80031_platform_data *pdata)
967 {
968         int ret;
969         struct tps80031_clk32k_init_data *clk32_idata = pdata->clk32k_init_data;
970         int data_size = pdata->clk32k_init_data_size;
971         static int clk32k_preq_bit_pos[TPS80031_CLOCK32K_NR] = {-1, 20, 19};
972         int base_add;
973         int i;
974
975         if (!clk32_idata || !data_size)
976                 return;
977
978         /* Configure the external request mode */
979         for (i = 0; i < data_size; ++i) {
980                 struct tps80031_clk32k_init_data *clk32_pd =  &clk32_idata[i];
981                 base_add = pmc_clk32k_control_base[clk32_pd->clk32k_nr];
982                 if (clk32_pd->enable)
983                         tps80031_clk32k_enable(tps80031, base_add);
984
985                 if ((clk32_pd->ext_ctrl_flag & EXT_PWR_REQ) &&
986                          (clk32k_preq_bit_pos[clk32_pd->clk32k_nr] != -1)) {
987                         ret = tps80031_ext_power_req_config(tps80031->dev,
988                                 clk32_pd->ext_ctrl_flag,
989                                 clk32k_preq_bit_pos[clk32_pd->clk32k_nr],
990                                 base_add + EXT_CONTROL_CFG_STATE,
991                                 base_add + EXT_CONTROL_CFG_TRANS);
992                         if (ret < 0)
993                                 dev_warn(tps80031->dev, "Clk32 ext control "
994                                         "fails\n");
995                 }
996
997                 if (clk32_pd->ext_ctrl_flag & PWR_OFF_ON_SLEEP) {
998                         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
999                                 base_add + EXT_CONTROL_CFG_TRANS, 0x0, 0xC);
1000                         if (ret < 0)
1001                                 dev_warn(tps80031->dev, "clk OFF on sleep "
1002                                         "control fails\n");
1003                 }
1004
1005                 if (clk32_pd->ext_ctrl_flag & PWR_ON_ON_SLEEP) {
1006                         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
1007                                 base_add + EXT_CONTROL_CFG_TRANS, 0x4, 0xC);
1008                         if (ret < 0)
1009                                 dev_warn(tps80031->dev, "clk ON sleep "
1010                                         "control fails\n");
1011                 }
1012         }
1013 }
1014
1015 static int __devinit tps80031_add_subdevs(struct tps80031 *tps80031,
1016                                           struct tps80031_platform_data *pdata)
1017 {
1018         struct tps80031_subdev_info *subdev;
1019         struct platform_device *pdev;
1020         int i, ret = 0;
1021
1022         for (i = 0; i < pdata->num_subdevs; i++) {
1023                 subdev = &pdata->subdevs[i];
1024
1025                 pdev = platform_device_alloc(subdev->name, subdev->id);
1026
1027                 pdev->dev.parent = tps80031->dev;
1028                 pdev->dev.platform_data = subdev->platform_data;
1029
1030                 ret = platform_device_add(pdev);
1031                 if (ret)
1032                         goto failed;
1033         }
1034         return 0;
1035
1036 failed:
1037         tps80031_remove_subdevs(tps80031);
1038         return ret;
1039 }
1040
1041 #ifdef CONFIG_DEBUG_FS
1042 #include <linux/debugfs.h>
1043 #include <linux/seq_file.h>
1044 static void print_regs(const char *header, struct seq_file *s,
1045                 int sid, int start_offset, int end_offset)
1046 {
1047         struct tps80031 *tps80031 = s->private;
1048         struct tps80031_client *tps = &tps80031->tps_clients[sid];
1049         uint8_t reg_val;
1050         int i;
1051         int ret;
1052
1053         seq_printf(s, "%s\n", header);
1054         for (i = start_offset; i <= end_offset; ++i) {
1055                 ret = tps80031_read(&tps->client->dev, sid, i, &reg_val);
1056                 if (ret >= 0)
1057                         seq_printf(s, "Addr = 0x%02x Reg 0x%02x Value 0x%02x\n",
1058                                                 tps->client->addr, i, reg_val);
1059         }
1060         seq_printf(s, "------------------\n");
1061 }
1062
1063 static int dbg_tps_show(struct seq_file *s, void *unused)
1064 {
1065         seq_printf(s, "TPS80031 Registers\n");
1066         seq_printf(s, "------------------\n");
1067         print_regs("VIO Regs",       s, SLAVE_ID1, 0x47, 0x49);
1068         print_regs("VIO Regs",       s, SLAVE_ID0, 0x49, 0x4A);
1069         print_regs("SMPS1 Regs",     s, SLAVE_ID1, 0x53, 0x54);
1070         print_regs("SMPS1 Regs",     s, SLAVE_ID0, 0x55, 0x56);
1071         print_regs("SMPS1 Regs",     s, SLAVE_ID1, 0x57, 0x57);
1072         print_regs("SMPS2 Regs",     s, SLAVE_ID1, 0x59, 0x5B);
1073         print_regs("SMPS2 Regs",     s, SLAVE_ID0, 0x5B, 0x5C);
1074         print_regs("SMPS2 Regs",     s, SLAVE_ID1, 0x5C, 0x5D);
1075         print_regs("SMPS3 Regs",     s, SLAVE_ID1, 0x65, 0x68);
1076         print_regs("SMPS4 Regs",     s, SLAVE_ID1, 0x41, 0x44);
1077         print_regs("VANA Regs",      s, SLAVE_ID1, 0x81, 0x83);
1078         print_regs("VRTC Regs",      s, SLAVE_ID1, 0xC3, 0xC4);
1079         print_regs("LDO1 Regs",      s, SLAVE_ID1, 0x9D, 0x9F);
1080         print_regs("LDO2 Regs",      s, SLAVE_ID1, 0x85, 0x87);
1081         print_regs("LDO3 Regs",      s, SLAVE_ID1, 0x8D, 0x8F);
1082         print_regs("LDO4 Regs",      s, SLAVE_ID1, 0x89, 0x8B);
1083         print_regs("LDO5 Regs",      s, SLAVE_ID1, 0x99, 0x9B);
1084         print_regs("LDO6 Regs",      s, SLAVE_ID1, 0x91, 0x93);
1085         print_regs("LDO7 Regs",      s, SLAVE_ID1, 0xA5, 0xA7);
1086         print_regs("LDOUSB Regs",    s, SLAVE_ID1, 0xA1, 0xA3);
1087         print_regs("LDOLN Regs",     s, SLAVE_ID1, 0x95, 0x97);
1088         print_regs("REGEN1 Regs",    s, SLAVE_ID1, 0xAE, 0xAF);
1089         print_regs("REGEN2 Regs",    s, SLAVE_ID1, 0xB1, 0xB2);
1090         print_regs("SYSEN Regs",     s, SLAVE_ID1, 0xB4, 0xB5);
1091         print_regs("CLK32KAO Regs",  s, SLAVE_ID1, 0xBA, 0xBB);
1092         print_regs("CLK32KG Regs",   s, SLAVE_ID1, 0xBD, 0xBE);
1093         print_regs("CLK32KAUD Regs", s, SLAVE_ID1, 0xC0, 0xC1);
1094         print_regs("INT Regs",       s, SLAVE_ID2, 0xD0, 0xD8);
1095         print_regs("PREQ Regs",      s, SLAVE_ID1, 0xD7, 0xDF);
1096         print_regs("MASK_PH Regs",   s, SLAVE_ID1, 0x20, 0x21);
1097         print_regs("PMC MISC Regs",  s, SLAVE_ID1, 0xE0, 0xEF);
1098         print_regs("CONT_STATE",     s, SLAVE_ID2, 0xE0, 0xE4);
1099         print_regs("VERNUM Regs",    s, SLAVE_ID3, 0x87, 0x87);
1100         print_regs("EEPROM Regs",    s, SLAVE_ID3, 0xDF, 0xDF);
1101         print_regs("CHARGE Regs",    s, SLAVE_ID2, 0xDA, 0xF5);
1102         return 0;
1103 }
1104
1105 static int dbg_tps_open(struct inode *inode, struct file *file)
1106 {
1107         return single_open(file, dbg_tps_show, inode->i_private);
1108 }
1109
1110 static const struct file_operations debug_fops = {
1111         .open           = dbg_tps_open,
1112         .read           = seq_read,
1113         .llseek         = seq_lseek,
1114         .release        = single_release,
1115 };
1116
1117 static void __init tps80031_debuginit(struct tps80031 *tps)
1118 {
1119         (void)debugfs_create_file("tps80031", S_IRUGO, NULL,
1120                         tps, &debug_fops);
1121 }
1122 #else
1123 static void __init tps80031_debuginit(struct tps80031 *tpsi)
1124 {
1125         return;
1126 }
1127 #endif
1128
1129 static bool rd_wr_reg_id0(struct device *dev, unsigned int reg)
1130 {
1131         switch(reg) {
1132         case TPS80031_ID0_PMIC_SLAVE_SMPS_DVS:
1133                 return true;
1134         default:
1135                 pr_err("non-existing reg %s() %d reg %x\n", __func__, __LINE__, reg);
1136                 BUG();
1137                 return false;
1138         }
1139 }
1140
1141 static bool rd_wr_reg_id1(struct device *dev, unsigned int reg)
1142 {
1143         switch(reg) {
1144         case TPS80031_ID1_RTC:
1145         case TPS80031_ID1_MEMORY:
1146         case TPS80031_ID1_PMC_MASTER:
1147         case TPS80031_ID1_PMC_SLAVE_SMPS:
1148         case TPS80031_ID1_PMC_SLAVE_MISC:
1149         case TPS80031_ID1_PMC_SLAVE_LDO:
1150         case TPS80031_ID1_PMC_SLAVE_REOSURCES:
1151         case TPS80031_ID1_PMC_PREQ_ASSIGN:
1152         case TPS80031_ID1_PMC_MISC:
1153         case TPS80031_ID1_PMC_PU_PD_HZ:
1154         case TPS80031_ID1_PMC_BACKUP:
1155                 return true;
1156         default:
1157                 pr_err("non-existing reg %s() %d reg %x\n", __func__, __LINE__, reg);
1158                 BUG();
1159                 return false;
1160         }
1161 }
1162
1163 static bool rd_wr_reg_id2(struct device *dev, unsigned int reg)
1164 {
1165         switch(reg) {
1166         case TPS80031_ID2_USB:
1167         case TPS80031_ID2_GPADC_CONTROL:
1168         case TPS80031_ID2_GPADC_RESULTS:
1169         case TPS80031_ID2_AUXILLIARIES:
1170         case TPS80031_ID2_CUSTOM:
1171         case TPS80031_ID2_PWM:
1172         case TPS80031_ID2_FUEL_GAUSE:
1173         case TPS80031_ID2_INTERFACE_INTERRUPTS:
1174         case TPS80031_ID2_CHARGER:
1175                 return true;
1176         default:
1177                 pr_err("non-existing reg %s() %d reg %x\n", __func__, __LINE__, reg);
1178                 BUG();
1179                 return false;
1180         }
1181 }
1182 static bool rd_wr_reg_id3(struct device *dev, unsigned int reg)
1183 {
1184         switch(reg) {
1185         case TPS80031_ID3_TEST_LDO:
1186         case TPS80031_ID3_TEST_SMPS:
1187         case TPS80031_ID3_TEST_POWER:
1188         case TPS80031_ID3_TEST_CHARGER:
1189         case TPS80031_ID3_TEST_AUXILIIARIES:
1190         case TPS80031_ID3_DIEID:
1191         case TPS80031_ID3_TRIM_PHOENIX:
1192         case TPS80031_ID3_TRIM_CUSTOM:
1193                 return true;
1194         default:
1195                 pr_err("non-existing reg %s() %d reg %x\n", __func__, __LINE__, reg);
1196                 BUG();
1197                 return false;
1198         }
1199 }
1200
1201 static const struct regmap_config tps80031_regmap_configs[] = {
1202         {
1203                 .reg_bits = 8,
1204                 .val_bits = 8,
1205                 .writeable_reg = rd_wr_reg_id0,
1206                 .readable_reg = rd_wr_reg_id0,
1207                 .max_register = TPS80031_MAX_REGISTER - 1,
1208         },
1209         {
1210                 .reg_bits = 8,
1211                 .val_bits = 8,
1212                 .writeable_reg = rd_wr_reg_id1,
1213                 .readable_reg = rd_wr_reg_id1,
1214                 .max_register = TPS80031_MAX_REGISTER - 1,
1215         },
1216         {
1217                 .reg_bits = 8,
1218                 .val_bits = 8,
1219                 .writeable_reg = rd_wr_reg_id2,
1220                 .readable_reg = rd_wr_reg_id2,
1221                 .max_register = TPS80031_MAX_REGISTER - 1,
1222         },
1223         {
1224                 .reg_bits = 8,
1225                 .val_bits = 8,
1226                 .writeable_reg = rd_wr_reg_id3,
1227                 .readable_reg = rd_wr_reg_id3,
1228                 .max_register = TPS80031_MAX_REGISTER - 1,
1229         },
1230 };
1231
1232 static int __devexit tps80031_i2c_remove(struct i2c_client *client)
1233 {
1234         struct tps80031 *tps80031 = i2c_get_clientdata(client);
1235         int i;
1236
1237         mfd_remove_devices(tps80031->dev);
1238
1239         if (client->irq)
1240                 free_irq(client->irq, tps80031);
1241
1242         if (tps80031->gpio.owner != NULL)
1243                 if (gpiochip_remove(&tps80031->gpio) < 0)
1244                         dev_err(&client->dev, "Error in removing the gpio driver\n");
1245
1246         for (i = 0; i < TPS_NUM_SLAVES; i++) {
1247                 struct tps80031_client *tps = &tps80031->tps_clients[i];
1248                 if (tps->client && tps->client != client)
1249                         i2c_unregister_device(tps->client);
1250                 tps80031->tps_clients[i].client = NULL;
1251                 mutex_destroy(&tps->lock);
1252         }
1253
1254         return 0;
1255 }
1256
1257 static int __devinit tps80031_i2c_probe(struct i2c_client *client,
1258                                         const struct i2c_device_id *id)
1259 {
1260         struct tps80031_platform_data *pdata = client->dev.platform_data;
1261         struct tps80031 *tps80031;
1262         struct tps80031_client *tps;
1263         int ret;
1264         int jtag_ver;
1265         int ep_ver;
1266         int i;
1267
1268         if (!pdata) {
1269                 dev_err(&client->dev, "tps80031 requires platform data\n");
1270                 return -ENOTSUPP;
1271         }
1272
1273         jtag_ver = i2c_smbus_read_byte_data(client, TPS80031_JTAGVERNUM);
1274         if (jtag_ver < 0) {
1275                 dev_err(&client->dev, "Silicon version number read"
1276                                 " failed: %d\n", jtag_ver);
1277                 return -EIO;
1278         }
1279
1280         ep_ver = i2c_smbus_read_byte_data(client, TPS80031_EPROM_REV);
1281         if (ep_ver < 0) {
1282                 dev_err(&client->dev, "Silicon eeprom version read"
1283                                 " failed: %d\n", ep_ver);
1284                 return -EIO;
1285         }
1286
1287         dev_info(&client->dev, "Jtag version 0x%02x and Eeprom version 0x%02x\n",
1288                                                 jtag_ver, ep_ver);
1289
1290         tps80031 = devm_kzalloc(&client->dev, sizeof(*tps80031), GFP_KERNEL);
1291         if (!tps80031) {
1292                 dev_err(&client->dev, "Memory alloc for tps80031 failed\n");
1293                 return -ENOMEM;
1294         }
1295
1296         tps80031->es_version = jtag_ver;
1297         tps80031->dev = &client->dev;
1298         i2c_set_clientdata(client, tps80031);
1299         tps80031->chip_info = id->driver_data;
1300
1301         /* Set up slaves */
1302         tps80031->tps_clients[SLAVE_ID0].addr = I2C_ID0_ADDR;
1303         tps80031->tps_clients[SLAVE_ID1].addr = I2C_ID1_ADDR;
1304         tps80031->tps_clients[SLAVE_ID2].addr = I2C_ID2_ADDR;
1305         tps80031->tps_clients[SLAVE_ID3].addr = I2C_ID3_ADDR;
1306         for (i = 0; i < TPS_NUM_SLAVES; i++) {
1307                 tps = &tps80031->tps_clients[i];
1308                 if (tps->addr == client->addr)
1309                         tps->client = client;
1310                 else
1311                         tps->client = i2c_new_dummy(client->adapter,
1312                                                 tps->addr);
1313                 if (!tps->client) {
1314                         dev_err(&client->dev, "can't attach client %d\n", i);
1315                         ret = -ENOMEM;
1316                         goto fail_client_reg;
1317                 }
1318                 i2c_set_clientdata(tps->client, tps80031);
1319                 mutex_init(&tps->lock);
1320
1321                 tps80031->regmap[i] = devm_regmap_init_i2c(tps->client,
1322                                         &tps80031_regmap_configs[i]);
1323                 if (IS_ERR(tps80031->regmap[i])) {
1324                         ret = PTR_ERR(tps80031->regmap[i]);
1325                         dev_err(&client->dev,
1326                                 "regmap %d init failed, err %d\n", i, ret);
1327                         goto fail_client_reg;
1328                 }
1329         }
1330
1331         if (client->irq) {
1332                 ret = tps80031_irq_init(tps80031, client->irq,
1333                                         pdata->irq_base);
1334                 if (ret) {
1335                         dev_err(&client->dev, "IRQ init failed: %d\n", ret);
1336                         goto fail_client_reg;
1337                 }
1338         }
1339
1340         tps80031_pupd_init(tps80031, pdata);
1341
1342         tps80031_init_ext_control(tps80031, pdata);
1343
1344         ret = mfd_add_devices(tps80031->dev, -1,
1345                         tps80031_cell, ARRAY_SIZE(tps80031_cell), NULL, 0);
1346         if (ret < 0) {
1347                 dev_err(&client->dev, "mfd_add_devices failed: %d\n", ret);
1348                 goto fail_mfd_add;
1349         }
1350
1351         ret = tps80031_add_subdevs(tps80031, pdata);
1352         if (ret) {
1353                 dev_err(&client->dev, "add devices failed: %d\n", ret);
1354                 goto fail_add_subdev;
1355         }
1356
1357         tps80031_gpio_init(tps80031, pdata);
1358
1359         tps80031_clk32k_init(tps80031, pdata);
1360
1361         tps80031_debuginit(tps80031);
1362
1363         tps80031_backup_battery_charger_control(tps80031, 1);
1364
1365         if (pdata->use_power_off && !pm_power_off)
1366                 pm_power_off = tps80031_power_off;
1367
1368         tps80031_dev = tps80031;
1369
1370         return 0;
1371
1372 fail_add_subdev:
1373         mfd_remove_devices(tps80031->dev);
1374
1375 fail_mfd_add:
1376         if (client->irq)
1377                 free_irq(client->irq, tps80031);
1378 fail_client_reg:
1379         for (i = 0; i < TPS_NUM_SLAVES; i++) {
1380                 struct tps80031_client *tps = &tps80031->tps_clients[i];
1381                 if (tps->client && tps->client != client)
1382                         i2c_unregister_device(tps->client);
1383                 tps80031->tps_clients[i].client = NULL;
1384                 mutex_destroy(&tps->lock);
1385         }
1386         return ret;
1387 }
1388
1389 #ifdef CONFIG_PM
1390 static int tps80031_i2c_suspend(struct device *dev)
1391 {
1392         struct i2c_client *client = to_i2c_client(dev);
1393         struct tps80031 *tps80031 = i2c_get_clientdata(client);
1394         if (client->irq)
1395                 disable_irq(client->irq);
1396         tps80031_backup_battery_charger_control(tps80031, 0);
1397         return 0;
1398 }
1399
1400 static int tps80031_i2c_resume(struct device *dev)
1401 {
1402         struct i2c_client *client = to_i2c_client(dev);
1403         struct tps80031 *tps80031 = i2c_get_clientdata(client);
1404         tps80031_backup_battery_charger_control(tps80031, 1);
1405         if (client->irq)
1406                 enable_irq(client->irq);
1407         return 0;
1408 }
1409 static const struct dev_pm_ops tps80031_dev_pm_ops = {
1410         .suspend        = tps80031_i2c_suspend,
1411         .resume         = tps80031_i2c_resume,
1412 };
1413 #define TPS80031_DEV_PM (&tps80031_dev_pm_ops)
1414 #else
1415 #define TPS80031_DEV_PM NULL
1416 #endif
1417
1418
1419 static const struct i2c_device_id tps80031_id_table[] = {
1420         { "tps80031", TPS80031 },
1421         { "tps80032", TPS80032 },
1422 };
1423 MODULE_DEVICE_TABLE(i2c, tps80031_id_table);
1424
1425 static struct i2c_driver tps80031_driver = {
1426         .driver = {
1427                 .name   = "tps80031",
1428                 .owner  = THIS_MODULE,
1429                 .pm     = TPS80031_DEV_PM,
1430         },
1431         .probe          = tps80031_i2c_probe,
1432         .remove         = __devexit_p(tps80031_i2c_remove),
1433         .id_table       = tps80031_id_table,
1434 };
1435
1436 static int __init tps80031_init(void)
1437 {
1438         return i2c_add_driver(&tps80031_driver);
1439 }
1440 subsys_initcall(tps80031_init);
1441
1442 static void __exit tps80031_exit(void)
1443 {
1444         i2c_del_driver(&tps80031_driver);
1445 }
1446 module_exit(tps80031_exit);
1447
1448 MODULE_DESCRIPTION("TPS80031 core driver");
1449 MODULE_LICENSE("GPL");