mfd: tps80031: add option to enable internal pullup or pulldown
[linux-2.6.git] / drivers / mfd / tps80031.c
1 /*
2  * driver/mfd/tps80031.c
3  *
4  * Core driver for TI TPS80031
5  *
6  * Copyright (C) 2011 NVIDIA Corporation
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, write to the Free Software Foundation, Inc.,
20  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
21  *
22  */
23
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/mutex.h>
29 #include <linux/slab.h>
30 #include <linux/gpio.h>
31 #include <linux/i2c.h>
32 #include <linux/pm.h>
33
34 #include <linux/mfd/core.h>
35 #include <linux/mfd/tps80031.h>
36
37 /* interrupt related registers */
38 #define TPS80031_INT_STS_A              0xD0
39 #define TPS80031_INT_STS_B              0xD1
40 #define TPS80031_INT_STS_C              0xD2
41 #define TPS80031_INT_MSK_LINE_A         0xD3
42 #define TPS80031_INT_MSK_LINE_B         0xD4
43 #define TPS80031_INT_MSK_LINE_C         0xD5
44 #define TPS80031_INT_MSK_STS_A          0xD6
45 #define TPS80031_INT_MSK_STS_B          0xD7
46 #define TPS80031_INT_MSK_STS_C          0xD8
47
48 #define TPS80031_CONTROLLER_STAT1               0xE3
49 #define CONTROLLER_STAT1_BAT_TEMP               0
50 #define CONTROLLER_STAT1_BAT_REMOVED            1
51 #define CONTROLLER_STAT1_VBUS_DET               2
52 #define CONTROLLER_STAT1_VAC_DET                3
53 #define CONTROLLER_STAT1_FAULT_WDG              4
54 #define CONTROLLER_STAT1_LINCH_GATED            6
55
56 #define TPS80031_CONTROLLER_INT_MASK            0xE0
57 #define CONTROLLER_INT_MASK_MVAC_DET            0
58 #define CONTROLLER_INT_MASK_MVBUS_DET           1
59 #define CONTROLLER_INT_MASK_MBAT_TEMP           2
60 #define CONTROLLER_INT_MASK_MFAULT_WDG          3
61 #define CONTROLLER_INT_MASK_MBAT_REMOVED        4
62 #define CONTROLLER_INT_MASK_MLINCH_GATED        5
63
64 #define CHARGE_CONTROL_SUB_INT_MASK             0x3F
65
66 /* Version number related register */
67 #define TPS80031_JTAGVERNUM             0x87
68 /* Epprom version */
69 #define TPS80031_EPROM_REV              0xDF
70
71 /* External control register */
72 #define REGEN1_BASE_ADD         0xAE
73 #define REGEN2_BASE_ADD         0xB1
74 #define SYSEN_BASE_ADD          0xB4
75
76 /* device control registers */
77 #define TPS80031_PHOENIX_DEV_ON 0x25
78 #define DEVOFF  1
79
80 #define CLK32KAO_BASE_ADD       0xBA
81 #define CLK32KG_BASE_ADD        0xBD
82 #define CLK32KAUDIO_BASE_ADD    0xC0
83
84 #define EXT_CONTROL_CFG_TRANS 0
85 #define EXT_CONTROL_CFG_STATE 1
86
87 #define STATE_OFF       0x00
88 #define STATE_ON        0x01
89 #define STATE_MASK      0x03
90
91 #define TRANS_SLEEP_OFF         0x00
92 #define TRANS_SLEEP_ON          0x04
93 #define TRANS_SLEEP_MASK        0x0C
94
95 #define TPS_NUM_SLAVES  4
96 #define EXT_PWR_REQ (PWR_REQ_INPUT_PREQ1 | PWR_REQ_INPUT_PREQ2 | \
97                 PWR_REQ_INPUT_PREQ3)
98 #define TPS80031_PREQ1_RES_ASS_A        0xD7
99 #define TPS80031_PREQ2_RES_ASS_A        0xDA
100 #define TPS80031_PREQ3_RES_ASS_A        0xDD
101 #define TPS80031_PHOENIX_MSK_TRANSITION 0x20
102
103 #define TPS80031_CFG_INPUT_PUPD1 0xF0
104 #define TPS80031_CFG_INPUT_PUPD2 0xF1
105 #define TPS80031_CFG_INPUT_PUPD3 0xF2
106 #define TPS80031_CFG_INPUT_PUPD4 0xF3
107
108 struct tps80031_pupd_data {
109         u8      reg;
110         u8      pullup_bit;
111         u8      pulldown_bit;
112 };
113
114 static u8 pmc_ext_control_base[] = {
115         REGEN1_BASE_ADD,
116         REGEN2_BASE_ADD,
117         SYSEN_BASE_ADD,
118 };
119
120 static u8 pmc_clk32k_control_base[] = {
121         CLK32KAO_BASE_ADD,
122         CLK32KG_BASE_ADD,
123         CLK32KAUDIO_BASE_ADD,
124 };
125 struct tps80031_irq_data {
126         u8      mask_reg;
127         u8      mask_mask;
128         u8      is_sec_int;
129         u8      parent_int;
130         u8      mask_sec_int_reg;
131         u8      int_mask_bit;
132         u8      int_sec_sts_reg;
133         u8      int_sts_bit;
134 };
135
136 #define TPS80031_IRQ(_reg, _mask)       \
137         {                                                       \
138                 .mask_reg = (TPS80031_INT_MSK_LINE_##_reg) -    \
139                                 TPS80031_INT_MSK_LINE_A,        \
140                 .mask_mask = (_mask),                           \
141         }
142
143 #define TPS80031_IRQ_SEC(_reg, _mask, _pint, _sint_mask_bit, _sint_sts_bit) \
144         {                                                               \
145                 .mask_reg = (TPS80031_INT_MSK_LINE_##_reg) -            \
146                                 TPS80031_INT_MSK_LINE_A,                \
147                 .mask_mask = (_mask),                                   \
148                 .is_sec_int = true,                                     \
149                 .parent_int = TPS80031_INT_##_pint,                     \
150                 .mask_sec_int_reg = TPS80031_CONTROLLER_INT_MASK,       \
151                 .int_mask_bit = CONTROLLER_INT_MASK_##_sint_mask_bit,   \
152                 .int_sec_sts_reg = TPS80031_CONTROLLER_STAT1,           \
153                 .int_sts_bit = CONTROLLER_STAT1_##_sint_sts_bit         \
154         }
155
156 static const struct tps80031_irq_data tps80031_irqs[] = {
157
158         [TPS80031_INT_PWRON]            = TPS80031_IRQ(A, 0),
159         [TPS80031_INT_RPWRON]           = TPS80031_IRQ(A, 1),
160         [TPS80031_INT_SYS_VLOW]         = TPS80031_IRQ(A, 2),
161         [TPS80031_INT_RTC_ALARM]        = TPS80031_IRQ(A, 3),
162         [TPS80031_INT_RTC_PERIOD]       = TPS80031_IRQ(A, 4),
163         [TPS80031_INT_HOT_DIE]          = TPS80031_IRQ(A, 5),
164         [TPS80031_INT_VXX_SHORT]        = TPS80031_IRQ(A, 6),
165         [TPS80031_INT_SPDURATION]       = TPS80031_IRQ(A, 7),
166         [TPS80031_INT_WATCHDOG]         = TPS80031_IRQ(B, 0),
167         [TPS80031_INT_BAT]              = TPS80031_IRQ(B, 1),
168         [TPS80031_INT_SIM]              = TPS80031_IRQ(B, 2),
169         [TPS80031_INT_MMC]              = TPS80031_IRQ(B, 3),
170         [TPS80031_INT_RES]              = TPS80031_IRQ(B, 4),
171         [TPS80031_INT_GPADC_RT]         = TPS80031_IRQ(B, 5),
172         [TPS80031_INT_GPADC_SW2_EOC]    = TPS80031_IRQ(B, 6),
173         [TPS80031_INT_CC_AUTOCAL]       = TPS80031_IRQ(B, 7),
174         [TPS80031_INT_ID_WKUP]          = TPS80031_IRQ(C, 0),
175         [TPS80031_INT_VBUSS_WKUP]       = TPS80031_IRQ(C, 1),
176         [TPS80031_INT_ID]               = TPS80031_IRQ(C, 2),
177         [TPS80031_INT_VBUS]             = TPS80031_IRQ(C, 3),
178         [TPS80031_INT_CHRG_CTRL]        = TPS80031_IRQ(C, 4),
179         [TPS80031_INT_EXT_CHRG]         = TPS80031_IRQ(C, 5),
180         [TPS80031_INT_INT_CHRG]         = TPS80031_IRQ(C, 6),
181         [TPS80031_INT_RES2]             = TPS80031_IRQ(C, 7),
182         [TPS80031_INT_BAT_TEMP_OVRANGE] = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
183                                                 MBAT_TEMP,      BAT_TEMP),
184         [TPS80031_INT_BAT_REMOVED]      = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
185                                                 MBAT_REMOVED,   BAT_REMOVED),
186         [TPS80031_INT_VBUS_DET]         = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
187                                                 MVBUS_DET,      VBUS_DET),
188         [TPS80031_INT_VAC_DET]          = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
189                                                 MVAC_DET,       VAC_DET),
190         [TPS80031_INT_FAULT_WDG]        = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
191                                                 MFAULT_WDG,     FAULT_WDG),
192         [TPS80031_INT_LINCH_GATED]      = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
193                                                 MLINCH_GATED,   LINCH_GATED),
194 };
195
196 #define PUPD_DATA(_reg, _pulldown_bit, _pullup_bit)     \
197         {                                               \
198                 .reg = TPS80031_CFG_INPUT_PUPD##_reg,   \
199                 .pulldown_bit = _pulldown_bit,          \
200                 .pullup_bit = _pullup_bit,              \
201         }
202
203 static const struct tps80031_pupd_data tps80031_pupds[] = {
204         [TPS80031_PREQ1]                = PUPD_DATA(1, 1 << 0,  1 << 1  ),
205         [TPS80031_PREQ2A]               = PUPD_DATA(1, 1 << 2,  1 << 3  ),
206         [TPS80031_PREQ2B]               = PUPD_DATA(1, 1 << 4,  1 << 5  ),
207         [TPS80031_PREQ2C]               = PUPD_DATA(1, 1 << 6,  1 << 7  ),
208         [TPS80031_PREQ3]                = PUPD_DATA(2, 1 << 0,  1 << 1  ),
209         [TPS80031_NRES_WARM]            = PUPD_DATA(2, 0,       1 << 2  ),
210         [TPS80031_PWM_FORCE]            = PUPD_DATA(2, 1 << 5,  0       ),
211         [TPS80031_CHRG_EXT_CHRG_STATZ]  = PUPD_DATA(2, 0,       1 << 6  ),
212         [TPS80031_SIM]                  = PUPD_DATA(3, 1 << 0,  1 << 1  ),
213         [TPS80031_MMC]                  = PUPD_DATA(3, 1 << 2,  1 << 3  ),
214         [TPS80031_GPADC_START]          = PUPD_DATA(3, 1 << 4,  0       ),
215         [TPS80031_DVSI2C_SCL]           = PUPD_DATA(4, 0,       1 << 0  ),
216         [TPS80031_DVSI2C_SDA]           = PUPD_DATA(4, 0,       1 << 1  ),
217         [TPS80031_CTLI2C_SCL]           = PUPD_DATA(4, 0,       1 << 2  ),
218         [TPS80031_CTLI2C_SDA]           = PUPD_DATA(4, 0,       1 << 3  ),
219 };
220
221 static const int controller_stat1_irq_nr[] = {
222         TPS80031_INT_BAT_TEMP_OVRANGE,
223         TPS80031_INT_BAT_REMOVED,
224         TPS80031_INT_VBUS_DET,
225         TPS80031_INT_VAC_DET,
226         TPS80031_INT_FAULT_WDG,
227         0,
228         TPS80031_INT_LINCH_GATED,
229         0
230 };
231
232 /* Structure for TPS80031 Slaves */
233 struct tps80031_client {
234         struct i2c_client *client;
235         struct mutex lock;
236         u8 addr;
237 };
238
239 struct tps80031 {
240         struct device           *dev;
241         unsigned long           chip_info;
242         int                     es_version;
243
244         struct gpio_chip        gpio;
245         struct irq_chip         irq_chip;
246         struct mutex            irq_lock;
247         int                     irq_base;
248         u32                     irq_en;
249         u8                      mask_cache[3];
250         u8                      mask_reg[3];
251         u8                      cont_int_mask_reg;
252         u8                      cont_int_mask_cache;
253         u8                      cont_int_en;
254         u8                      prev_cont_stat1;
255         struct tps80031_client  tps_clients[TPS_NUM_SLAVES];
256 };
257
258 static inline int __tps80031_read(struct i2c_client *client,
259                                   int reg, uint8_t *val)
260 {
261         int ret;
262
263         ret = i2c_smbus_read_byte_data(client, reg);
264         if (ret < 0) {
265                 dev_err(&client->dev,
266                         "failed reading from addr 0x%02x, reg 0x%02x\n",
267                         client->addr, reg);
268                 return ret;
269         }
270
271         *val = (uint8_t)ret;
272
273         return 0;
274 }
275
276 static inline int __tps80031_reads(struct i2c_client *client, int reg,
277                                 int len, uint8_t *val)
278 {
279         int ret;
280
281         ret = i2c_smbus_read_i2c_block_data(client, reg, len, val);
282         if (ret < 0) {
283                 dev_err(&client->dev,
284                         "failed reading from addr 0x%02x, reg   0x%02x\n",
285                          client->addr, reg);
286                 return ret;
287         }
288
289         return 0;
290 }
291
292 static inline int __tps80031_write(struct i2c_client *client,
293                                  int reg, uint8_t val)
294 {
295         int ret;
296         ret = i2c_smbus_write_byte_data(client, reg, val);
297         if (ret < 0) {
298                 dev_err(&client->dev,
299                         "failed writing 0x%02x to 0x%02x\n", val, reg);
300                 return ret;
301         }
302
303         return 0;
304 }
305
306 static inline int __tps80031_writes(struct i2c_client *client, int reg,
307                                   int len, uint8_t *val)
308 {
309         int ret;
310
311         ret = i2c_smbus_write_i2c_block_data(client, reg, len, val);
312         if (ret < 0) {
313                 dev_err(&client->dev, "failed writings to 0x%02x\n", reg);
314                 return ret;
315         }
316
317         return 0;
318 }
319
320 int tps80031_write(struct device *dev, int sid, int reg, uint8_t val)
321 {
322         struct tps80031 *tps80031 = dev_get_drvdata(dev);
323         struct tps80031_client *tps = &tps80031->tps_clients[sid];
324         int ret;
325
326         mutex_lock(&tps->lock);
327         ret = __tps80031_write(tps->client, reg, val);
328         mutex_unlock(&tps->lock);
329
330         return ret;
331 }
332 EXPORT_SYMBOL_GPL(tps80031_write);
333
334 int tps80031_writes(struct device *dev, int sid, int reg, int len, uint8_t *val)
335 {
336         struct tps80031 *tps80031 = dev_get_drvdata(dev);
337         struct tps80031_client *tps = &tps80031->tps_clients[sid];
338         int ret;
339
340         mutex_lock(&tps->lock);
341         ret = __tps80031_writes(tps->client, reg, len, val);
342         mutex_unlock(&tps->lock);
343
344         return ret;
345 }
346 EXPORT_SYMBOL_GPL(tps80031_writes);
347
348 int tps80031_read(struct device *dev, int sid, int reg, uint8_t *val)
349 {
350         struct tps80031 *tps80031 = dev_get_drvdata(dev);
351         struct tps80031_client *tps = &tps80031->tps_clients[sid];
352
353         return __tps80031_read(tps->client, reg, val);
354 }
355 EXPORT_SYMBOL_GPL(tps80031_read);
356
357 int tps80031_reads(struct device *dev, int sid, int reg, int len, uint8_t *val)
358 {
359         struct tps80031 *tps80031 = dev_get_drvdata(dev);
360         struct tps80031_client *tps = &tps80031->tps_clients[sid];
361
362         return __tps80031_reads(tps->client, reg, len, val);
363 }
364 EXPORT_SYMBOL_GPL(tps80031_reads);
365
366 int tps80031_set_bits(struct device *dev, int sid, int reg, uint8_t bit_mask)
367 {
368         struct tps80031 *tps80031 = dev_get_drvdata(dev);
369         struct tps80031_client *tps = &tps80031->tps_clients[sid];
370         uint8_t reg_val;
371         int ret = 0;
372
373         mutex_lock(&tps->lock);
374
375         ret = __tps80031_read(tps->client, reg, &reg_val);
376         if (ret)
377                 goto out;
378
379         if ((reg_val & bit_mask) != bit_mask) {
380                 reg_val |= bit_mask;
381                 ret = __tps80031_write(tps->client, reg, reg_val);
382         }
383 out:
384         mutex_unlock(&tps->lock);
385         return ret;
386 }
387 EXPORT_SYMBOL_GPL(tps80031_set_bits);
388
389 int tps80031_clr_bits(struct device *dev, int sid, int reg, uint8_t bit_mask)
390 {
391         struct tps80031 *tps80031 = dev_get_drvdata(dev);
392         struct tps80031_client *tps = &tps80031->tps_clients[sid];
393         uint8_t reg_val;
394         int ret = 0;
395
396         mutex_lock(&tps->lock);
397
398         ret = __tps80031_read(tps->client, reg, &reg_val);
399         if (ret)
400                 goto out;
401
402         if (reg_val & bit_mask) {
403                 reg_val &= ~bit_mask;
404                 ret = __tps80031_write(tps->client, reg, reg_val);
405         }
406 out:
407         mutex_unlock(&tps->lock);
408         return ret;
409 }
410 EXPORT_SYMBOL_GPL(tps80031_clr_bits);
411
412 int tps80031_update(struct device *dev, int sid, int reg, uint8_t val,
413                 uint8_t mask)
414 {
415         struct tps80031 *tps80031 = dev_get_drvdata(dev);
416         struct tps80031_client *tps = &tps80031->tps_clients[sid];
417         uint8_t reg_val;
418         int ret = 0;
419
420         mutex_lock(&tps->lock);
421
422         ret = __tps80031_read(tps->client, reg, &reg_val);
423         if (ret)
424                 goto out;
425
426         if ((reg_val & mask) != val) {
427                 reg_val = (reg_val & ~mask) | (val & mask);
428                 ret = __tps80031_write(tps->client, reg, reg_val);
429         }
430 out:
431         mutex_unlock(&tps->lock);
432         return ret;
433 }
434 EXPORT_SYMBOL_GPL(tps80031_update);
435
436 int tps80031_force_update(struct device *dev, int sid, int reg, uint8_t val,
437                           uint8_t mask)
438 {
439         struct tps80031 *tps80031 = dev_get_drvdata(dev);
440         struct tps80031_client *tps = &tps80031->tps_clients[sid];
441         uint8_t reg_val;
442         int ret = 0;
443
444         mutex_lock(&tps->lock);
445
446         ret = __tps80031_read(tps->client, reg, &reg_val);
447         if (ret)
448                 goto out;
449
450         reg_val = (reg_val & ~mask) | (val & mask);
451         ret = __tps80031_write(tps->client, reg, reg_val);
452
453 out:
454         mutex_unlock(&tps->lock);
455         return ret;
456 }
457 EXPORT_SYMBOL_GPL(tps80031_force_update);
458
459 int tps80031_ext_power_req_config(struct device *dev,
460                 unsigned long ext_ctrl_flag, int preq_bit,
461                 int state_reg_add, int trans_reg_add)
462 {
463         u8 res_ass_reg = 0;
464         int preq_mask_bit = 0;
465         int ret;
466
467         if (!(ext_ctrl_flag & EXT_PWR_REQ))
468                 return 0;
469
470         if (ext_ctrl_flag & PWR_REQ_INPUT_PREQ1) {
471                 res_ass_reg = TPS80031_PREQ1_RES_ASS_A + (preq_bit >> 3);
472                 preq_mask_bit = 5;
473         } else if (ext_ctrl_flag & PWR_REQ_INPUT_PREQ2) {
474                 res_ass_reg = TPS80031_PREQ2_RES_ASS_A + (preq_bit >> 3);
475                 preq_mask_bit = 6;
476         } else if (ext_ctrl_flag & PWR_REQ_INPUT_PREQ3) {
477                 res_ass_reg = TPS80031_PREQ3_RES_ASS_A + (preq_bit >> 3);
478                 preq_mask_bit = 7;
479         }
480
481         /* Configure REQ_ASS registers */
482         ret = tps80031_set_bits(dev, SLAVE_ID1, res_ass_reg,
483                                         BIT(preq_bit & 0x7));
484         if (ret < 0) {
485                 dev_err(dev, "%s() Not able to set bit %d of "
486                         "reg %d error %d\n",
487                         __func__, preq_bit, res_ass_reg, ret);
488                 return ret;
489         }
490
491         /* Unmask the PREQ */
492         ret = tps80031_clr_bits(dev, SLAVE_ID1,
493                         TPS80031_PHOENIX_MSK_TRANSITION, BIT(preq_mask_bit));
494         if (ret < 0) {
495                 dev_err(dev, "%s() Not able to clear bit %d of "
496                         "reg %d error %d\n",
497                          __func__, preq_mask_bit,
498                         TPS80031_PHOENIX_MSK_TRANSITION, ret);
499                 return ret;
500         }
501
502         /* Switch regulator control to resource now */
503         if (ext_ctrl_flag & (PWR_REQ_INPUT_PREQ2 | PWR_REQ_INPUT_PREQ3)) {
504                 ret = tps80031_update(dev, SLAVE_ID1, state_reg_add, 0x0,
505                                                 STATE_MASK);
506                 if (ret < 0)
507                         dev_err(dev, "%s() Error in writing the STATE "
508                                 "register %d error %d\n", __func__,
509                                 state_reg_add, ret);
510         } else {
511                 ret = tps80031_update(dev, SLAVE_ID1, trans_reg_add,
512                                 TRANS_SLEEP_OFF, TRANS_SLEEP_MASK);
513                 if (ret < 0)
514                         dev_err(dev, "%s() Error in writing the TRANS "
515                                 "register %d error %d\n", __func__,
516                                 trans_reg_add, ret);
517         }
518         return ret;
519 }
520 EXPORT_SYMBOL_GPL(tps80031_ext_power_req_config);
521
522 unsigned long tps80031_get_chip_info(struct device *dev)
523 {
524         struct tps80031 *tps80031 = dev_get_drvdata(dev);
525         return tps80031->chip_info;
526 }
527 EXPORT_SYMBOL_GPL(tps80031_get_chip_info);
528
529 int tps80031_get_pmu_version(struct device *dev)
530 {
531         struct tps80031 *tps80031 = dev_get_drvdata(dev);
532         return tps80031->es_version;
533 }
534 EXPORT_SYMBOL_GPL(tps80031_get_pmu_version);
535
536 static struct tps80031 *tps80031_dev;
537 static void tps80031_power_off(void)
538 {
539         struct tps80031_client *tps = &tps80031_dev->tps_clients[SLAVE_ID1];
540
541         if (!tps->client)
542                 return;
543         dev_info(&tps->client->dev, "switching off PMU\n");
544         __tps80031_write(tps->client, TPS80031_PHOENIX_DEV_ON, DEVOFF);
545 }
546
547 static void tps80031_pupd_init(struct tps80031 *tps80031,
548                                struct tps80031_platform_data *pdata)
549 {
550         struct tps80031_pupd_init_data *pupd_init_data = pdata->pupd_init_data;
551         int data_size = pdata->pupd_init_data_size;
552         int i;
553
554         for (i = 0; i < data_size; ++i) {
555                 struct tps80031_pupd_init_data *pupd_init = &pupd_init_data[i];
556                 const struct tps80031_pupd_data *pupd =
557                         &tps80031_pupds[pupd_init->input_pin];
558                 u8 update_value = 0;
559                 u8 update_mask = pupd->pulldown_bit | pupd->pullup_bit;
560
561                 if (pupd_init->setting == TPS80031_PUPD_PULLDOWN)
562                         update_value = pupd->pulldown_bit;
563                 else if (pupd_init->setting == TPS80031_PUPD_PULLUP)
564                         update_value = pupd->pullup_bit;
565
566                 tps80031_update(tps80031->dev, SLAVE_ID1, pupd->reg,
567                                 update_value, update_mask);
568         }
569 }
570
571 static void tps80031_init_ext_control(struct tps80031 *tps80031,
572                         struct tps80031_platform_data *pdata) {
573         int ret;
574         int i;
575
576         /* Clear all external control for this rail */
577         for (i = 0; i < 9; ++i) {
578                 tps80031_write(tps80031->dev, SLAVE_ID1,
579                                 TPS80031_PREQ1_RES_ASS_A + i, 0);
580                 if (ret < 0)
581                         dev_err(tps80031->dev, "%s() Error in clearing "
582                                 "register %02x\n", __func__,
583                                 TPS80031_PREQ1_RES_ASS_A + i);
584         }
585
586         /* Mask the PREQ */
587         ret = tps80031_set_bits(tps80031->dev, SLAVE_ID1,
588                         TPS80031_PHOENIX_MSK_TRANSITION, 0x7 << 5);
589         if (ret < 0)
590                 dev_err(tps80031->dev, "%s() Not able to mask register "
591                         "0x%02x\n", __func__, TPS80031_PHOENIX_MSK_TRANSITION);
592 }
593
594 static int tps80031_gpio_get(struct gpio_chip *gc, unsigned offset)
595 {
596         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
597         struct tps80031_client *tps = &tps80031->tps_clients[SLAVE_ID1];
598         uint8_t state;
599         uint8_t trans;
600         int ret;
601
602         ret = __tps80031_read(tps->client,
603                         pmc_ext_control_base[offset] +
604                                 EXT_CONTROL_CFG_STATE, &state);
605         if (ret)
606                 return ret;
607
608         if (state != 0) {
609                 ret = __tps80031_read(tps->client,
610                                 pmc_ext_control_base[offset] +
611                                         EXT_CONTROL_CFG_TRANS, &trans);
612                 if (ret)
613                         return ret;
614                 return trans & 0x1;
615         }
616         return 0;
617 }
618
619 static void tps80031_gpio_set(struct gpio_chip *gc, unsigned offset,
620                         int value)
621 {
622         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
623
624         tps80031_update(tps80031->dev, SLAVE_ID1,
625                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_TRANS,
626                         value, 0x1);
627 }
628
629 static int tps80031_gpio_input(struct gpio_chip *gc, unsigned offset)
630 {
631         return -EIO;
632 }
633
634 static int tps80031_gpio_output(struct gpio_chip *gc, unsigned offset,
635                                 int value)
636 {
637         tps80031_gpio_set(gc, offset, value);
638         return 0;
639 }
640
641 static int tps80031_gpio_enable(struct gpio_chip *gc, unsigned offset)
642 {
643         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
644         int ret;
645
646         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
647                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_STATE,
648                                                 STATE_ON, STATE_MASK);
649         if (ret)
650                 return ret;
651
652         return tps80031_write(tps80031->dev, SLAVE_ID1,
653                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_TRANS, 0x0);
654 }
655
656 static void tps80031_gpio_disable(struct gpio_chip *gc, unsigned offset)
657 {
658         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
659         tps80031_update(tps80031->dev, SLAVE_ID1,
660                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_STATE,
661                                                 STATE_OFF, STATE_MASK);
662 }
663
664 static void tps80031_gpio_init(struct tps80031 *tps80031,
665                         struct tps80031_platform_data *pdata)
666 {
667         int ret;
668         int gpio_base = pdata->gpio_base;
669         struct tps80031_client *tps = &tps80031->tps_clients[SLAVE_ID1];
670         struct tps80031_gpio_init_data *gpio_init_data = pdata->gpio_init_data;
671         int data_size = pdata->gpio_init_data_size;
672         static int preq_bit_pos[TPS80031_GPIO_NR] = {16, 17, 18};
673         int base_add;
674         int i;
675
676         if (gpio_base <= 0)
677                 return;
678
679         /* Configure the external request mode */
680         for (i = 0; i < data_size; ++i) {
681                 struct tps80031_gpio_init_data *gpio_pd = &gpio_init_data[i];
682                 base_add = pmc_ext_control_base[gpio_pd->gpio_nr];
683
684                 if (gpio_pd->ext_ctrl_flag & EXT_PWR_REQ) {
685                         ret = tps80031_ext_power_req_config(tps80031->dev,
686                                 gpio_pd->ext_ctrl_flag,
687                                 preq_bit_pos[gpio_pd->gpio_nr],
688                                 base_add + EXT_CONTROL_CFG_STATE,
689                                 base_add + EXT_CONTROL_CFG_TRANS);
690                         if (ret < 0)
691                                 dev_warn(tps80031->dev, "Ext pwrreq GPIO "
692                                         "sleep control fails\n");
693                 }
694
695                 if (gpio_pd->ext_ctrl_flag & PWR_OFF_ON_SLEEP) {
696                         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
697                                 base_add + EXT_CONTROL_CFG_TRANS, 0x0, 0xC);
698                         if (ret < 0)
699                                 dev_warn(tps80031->dev, "GPIO OFF on sleep "
700                                         "control fails\n");
701                 }
702
703                 if (gpio_pd->ext_ctrl_flag & PWR_ON_ON_SLEEP) {
704                         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
705                                 base_add + EXT_CONTROL_CFG_TRANS, 0x4, 0xC);
706                         if (ret < 0)
707                                 dev_warn(tps80031->dev, "GPIO ON on sleep "
708                                         "control fails\n");
709                 }
710         }
711
712         tps80031->gpio.owner            = THIS_MODULE;
713         tps80031->gpio.label            = tps->client->name;
714         tps80031->gpio.dev              = tps80031->dev;
715         tps80031->gpio.base             = gpio_base;
716         tps80031->gpio.ngpio            = TPS80031_GPIO_NR;
717         tps80031->gpio.can_sleep        = 1;
718
719         tps80031->gpio.request          = tps80031_gpio_enable;
720         tps80031->gpio.free             = tps80031_gpio_disable;
721         tps80031->gpio.direction_input  = tps80031_gpio_input;
722         tps80031->gpio.direction_output = tps80031_gpio_output;
723         tps80031->gpio.set              = tps80031_gpio_set;
724         tps80031->gpio.get              = tps80031_gpio_get;
725
726         ret = gpiochip_add(&tps80031->gpio);
727         if (ret)
728                 dev_warn(tps80031->dev, "GPIO registration failed: %d\n", ret);
729 }
730
731 static int __remove_subdev(struct device *dev, void *unused)
732 {
733         platform_device_unregister(to_platform_device(dev));
734         return 0;
735 }
736
737 static int tps80031_remove_subdevs(struct tps80031 *tps80031)
738 {
739         return device_for_each_child(tps80031->dev, NULL, __remove_subdev);
740 }
741
742 static void tps80031_irq_lock(struct irq_data *data)
743 {
744         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
745
746         mutex_lock(&tps80031->irq_lock);
747 }
748
749 static void tps80031_irq_enable(struct irq_data *data)
750 {
751         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
752         unsigned int __irq = data->irq - tps80031->irq_base;
753         const struct tps80031_irq_data *irq_data = &tps80031_irqs[__irq];
754
755         if (irq_data->is_sec_int) {
756                 tps80031->cont_int_mask_reg &= ~(1 << irq_data->int_mask_bit);
757                 tps80031->cont_int_en |= (1 << irq_data->int_mask_bit);
758                 tps80031->mask_reg[irq_data->mask_reg] &= ~(1 << irq_data->mask_mask);
759                 tps80031->irq_en |= (1 << irq_data->parent_int);
760         } else
761                 tps80031->mask_reg[irq_data->mask_reg] &= ~(1 << irq_data->mask_mask);
762
763         tps80031->irq_en |= (1 << __irq);
764 }
765
766 static void tps80031_irq_disable(struct irq_data *data)
767 {
768         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
769
770         unsigned int __irq = data->irq - tps80031->irq_base;
771         const struct tps80031_irq_data *irq_data = &tps80031_irqs[__irq];
772
773         if (irq_data->is_sec_int) {
774                 tps80031->cont_int_mask_reg |= (1 << irq_data->int_mask_bit);
775                 tps80031->cont_int_en &= ~(1 << irq_data->int_mask_bit);
776                 if (!tps80031->cont_int_en) {
777                         tps80031->mask_reg[irq_data->mask_reg] |=
778                                                 (1 << irq_data->mask_mask);
779                         tps80031->irq_en &= ~(1 << irq_data->parent_int);
780                 }
781                 tps80031->irq_en &= ~(1 << __irq);
782         } else
783                 tps80031->mask_reg[irq_data->mask_reg] |= (1 << irq_data->mask_mask);
784
785         tps80031->irq_en &= ~(1 << __irq);
786 }
787
788 static void tps80031_irq_sync_unlock(struct irq_data *data)
789 {
790         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
791         int i;
792
793         for (i = 0; i < ARRAY_SIZE(tps80031->mask_reg); i++) {
794                 if (tps80031->mask_reg[i] != tps80031->mask_cache[i]) {
795                         if (!WARN_ON(tps80031_write(tps80031->dev, SLAVE_ID2,
796                                                 TPS80031_INT_MSK_LINE_A + i,
797                                                 tps80031->mask_reg[i])))
798                                 if (!WARN_ON(tps80031_write(tps80031->dev,
799                                                 SLAVE_ID2,
800                                                 TPS80031_INT_MSK_STS_A + i,
801                                                 tps80031->mask_reg[i])))
802                                         tps80031->mask_cache[i] =
803                                                         tps80031->mask_reg[i];
804                 }
805         }
806
807         if (tps80031->cont_int_mask_reg != tps80031->cont_int_mask_cache) {
808                 if (!WARN_ON(tps80031_write(tps80031->dev, SLAVE_ID2,
809                                 TPS80031_CONTROLLER_INT_MASK,
810                                 tps80031->cont_int_mask_reg)))
811                         tps80031->cont_int_mask_cache =
812                                                 tps80031->cont_int_mask_reg;
813         }
814
815         mutex_unlock(&tps80031->irq_lock);
816 }
817
818 static irqreturn_t tps80031_charge_control_irq(int irq, void *data)
819 {
820         struct tps80031 *tps80031 = data;
821         int ret = 0;
822         int i;
823         u8 cont_sts;
824         u8 org_sts;
825         if (irq != (tps80031->irq_base + TPS80031_INT_CHRG_CTRL)) {
826                 dev_err(tps80031->dev, "%s() Got the illegal interrupt %d\n",
827                                         __func__, irq);
828                 return IRQ_NONE;
829         }
830
831         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
832                         TPS80031_CONTROLLER_STAT1, &org_sts);
833         if (ret < 0) {
834                 dev_err(tps80031->dev, "%s(): failed to read controller state1 "
835                                 "status %d\n", __func__, ret);
836                 return IRQ_NONE;
837         }
838
839         /* Get change from last interrupt and mask for interested interrupt
840          * for charge control interrupt */
841         cont_sts = org_sts ^ tps80031->prev_cont_stat1;
842         tps80031->prev_cont_stat1 = org_sts;
843         /* Clear watchdog timer state */
844         tps80031->prev_cont_stat1 &= ~(1 << 4);
845         cont_sts &= 0x5F;
846
847         for (i = 0; i < 8; ++i) {
848                 if (!controller_stat1_irq_nr[i])
849                         continue;
850
851                 if ((cont_sts & BIT(i)) &&
852                         (tps80031->irq_en & BIT(controller_stat1_irq_nr[i])))
853                         handle_nested_irq(tps80031->irq_base +
854                                                 controller_stat1_irq_nr[i]);
855                 cont_sts &= ~BIT(i);
856         }
857         return IRQ_HANDLED;
858 }
859
860 static irqreturn_t tps80031_irq(int irq, void *data)
861 {
862         struct tps80031 *tps80031 = data;
863         int ret = 0;
864         u32 acks;
865         int i;
866         uint8_t tmp[3];
867
868         ret = tps80031_reads(tps80031->dev, SLAVE_ID2,
869                              TPS80031_INT_STS_A, 3, tmp);
870         if (ret < 0) {
871                 dev_err(tps80031->dev, "failed to read interrupt status\n");
872                 return IRQ_NONE;
873         }
874         acks = (tmp[2] << 16) | (tmp[1] << 8) | tmp[0];
875
876         if (acks) {
877                 ret = tps80031_writes(tps80031->dev, SLAVE_ID2,
878                                       TPS80031_INT_STS_A, 3, tmp);
879                 if (ret < 0) {
880                         dev_err(tps80031->dev, "failed to write "
881                                                 "interrupt status\n");
882                         return IRQ_NONE;
883                 }
884
885                 while (acks) {
886                         i = __ffs(acks);
887                         if (tps80031->irq_en & (1 << i))
888                                 handle_nested_irq(tps80031->irq_base + i);
889                         acks &= ~(1 << i);
890                 }
891         }
892
893         return IRQ_HANDLED;
894 }
895
896 static int __devinit tps80031_irq_init(struct tps80031 *tps80031, int irq,
897                                 int irq_base)
898 {
899         int i, ret;
900
901         if (!irq_base) {
902                 dev_warn(tps80031->dev, "No interrupt support on IRQ base\n");
903                 return -EINVAL;
904         }
905
906         mutex_init(&tps80031->irq_lock);
907
908         for (i = 0; i < 3; i++) {
909                 tps80031->mask_reg[i] = 0xFF;
910                 tps80031->mask_cache[i] = tps80031->mask_reg[i];
911                 tps80031_write(tps80031->dev, SLAVE_ID2,
912                                         TPS80031_INT_MSK_LINE_A + i,
913                                         tps80031->mask_cache[i]);
914                 tps80031_write(tps80031->dev, SLAVE_ID2,
915                                         TPS80031_INT_MSK_STS_A + i, 0xFF);
916                 tps80031_write(tps80031->dev, SLAVE_ID2,
917                                         TPS80031_INT_STS_A + i, 0xFF);
918         }
919
920         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
921                                 TPS80031_CONTROLLER_INT_MASK,
922                                 &tps80031->cont_int_mask_reg);
923         if (ret < 0) {
924                 dev_err(tps80031->dev, "Error in reading the controller_mask "
925                                         "register %d\n", ret);
926                 return ret;
927         }
928
929         tps80031->cont_int_mask_reg |= CHARGE_CONTROL_SUB_INT_MASK;
930         tps80031->cont_int_mask_cache = tps80031->cont_int_mask_reg;
931         tps80031->cont_int_en = 0;
932         ret = tps80031_write(tps80031->dev, SLAVE_ID2,
933                                 TPS80031_CONTROLLER_INT_MASK,
934                                 tps80031->cont_int_mask_reg);
935         if (ret < 0) {
936                 dev_err(tps80031->dev, "Error in writing the controller_mask "
937                                         "register %d\n", ret);
938                 return ret;
939         }
940
941         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
942                         TPS80031_CONTROLLER_STAT1, &tps80031->prev_cont_stat1);
943         if (ret < 0) {
944                 dev_err(tps80031->dev, "%s(): failed to read controller state1 "
945                                 "status %d\n", __func__, ret);
946                 return ret;
947         }
948
949         /* Clear watch dog interrupt status in status */
950         tps80031->prev_cont_stat1 &= ~(1 << 4);
951
952         tps80031->irq_base = irq_base;
953
954         tps80031->irq_chip.name = "tps80031";
955         tps80031->irq_chip.irq_enable = tps80031_irq_enable;
956         tps80031->irq_chip.irq_disable = tps80031_irq_disable;
957         tps80031->irq_chip.irq_bus_lock = tps80031_irq_lock;
958         tps80031->irq_chip.irq_bus_sync_unlock = tps80031_irq_sync_unlock;
959
960         for (i = 0; i < TPS80031_INT_NR; i++) {
961                 int __irq = i + tps80031->irq_base;
962                 irq_set_chip_data(__irq, tps80031);
963                 irq_set_chip_and_handler(__irq, &tps80031->irq_chip,
964                                          handle_simple_irq);
965                 irq_set_nested_thread(__irq, 1);
966 #ifdef CONFIG_ARM
967                 set_irq_flags(__irq, IRQF_VALID);
968 #endif
969         }
970
971         ret = request_threaded_irq(irq, NULL, tps80031_irq, IRQF_ONESHOT,
972                                 "tps80031", tps80031);
973         /* register the isr for the secondary interrupt */
974         if (!ret)
975                 ret = request_threaded_irq(irq_base + TPS80031_INT_CHRG_CTRL,
976                                 NULL, tps80031_charge_control_irq,
977                                 IRQF_ONESHOT, "80031_chg_ctl", tps80031);
978         if (!ret) {
979
980                 device_init_wakeup(tps80031->dev, 1);
981                 enable_irq_wake(irq);
982         }
983
984         return ret;
985 }
986
987 static void tps80031_clk32k_enable(struct tps80031 *tps80031, int base_add)
988 {
989         int ret;
990         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
991                         base_add + EXT_CONTROL_CFG_STATE, STATE_ON, STATE_MASK);
992         if (!ret)
993                 ret = tps80031_update(tps80031->dev, SLAVE_ID1,
994                                 base_add + EXT_CONTROL_CFG_TRANS,
995                                 STATE_ON, STATE_MASK);
996         if (ret < 0)
997                 dev_err(tps80031->dev, "Error in updating clock register\n");
998 }
999
1000 static void tps80031_clk32k_init(struct tps80031 *tps80031,
1001                         struct tps80031_platform_data *pdata)
1002 {
1003         int ret;
1004         struct tps80031_clk32k_init_data *clk32_idata = pdata->clk32k_init_data;
1005         int data_size = pdata->clk32k_init_data_size;
1006         static int clk32k_preq_bit_pos[TPS80031_CLOCK32K_NR] = {-1, 20, 19};
1007         int base_add;
1008         int i;
1009
1010         if (!clk32_idata || !data_size)
1011                 return;
1012
1013         /* Configure the external request mode */
1014         for (i = 0; i < data_size; ++i) {
1015                 struct tps80031_clk32k_init_data *clk32_pd =  &clk32_idata[i];
1016                 base_add = pmc_clk32k_control_base[clk32_pd->clk32k_nr];
1017                 if (clk32_pd->enable)
1018                         tps80031_clk32k_enable(tps80031, base_add);
1019
1020                 if ((clk32_pd->ext_ctrl_flag & EXT_PWR_REQ) &&
1021                          (clk32k_preq_bit_pos[clk32_pd->clk32k_nr] != -1)) {
1022                         ret = tps80031_ext_power_req_config(tps80031->dev,
1023                                 clk32_pd->ext_ctrl_flag,
1024                                 clk32k_preq_bit_pos[clk32_pd->clk32k_nr],
1025                                 base_add + EXT_CONTROL_CFG_STATE,
1026                                 base_add + EXT_CONTROL_CFG_TRANS);
1027                         if (ret < 0)
1028                                 dev_warn(tps80031->dev, "Clk32 ext control "
1029                                         "fails\n");
1030                 }
1031
1032                 if (clk32_pd->ext_ctrl_flag & PWR_OFF_ON_SLEEP) {
1033                         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
1034                                 base_add + EXT_CONTROL_CFG_TRANS, 0x0, 0xC);
1035                         if (ret < 0)
1036                                 dev_warn(tps80031->dev, "clk OFF on sleep "
1037                                         "control fails\n");
1038                 }
1039
1040                 if (clk32_pd->ext_ctrl_flag & PWR_ON_ON_SLEEP) {
1041                         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
1042                                 base_add + EXT_CONTROL_CFG_TRANS, 0x4, 0xC);
1043                         if (ret < 0)
1044                                 dev_warn(tps80031->dev, "clk ON sleep "
1045                                         "control fails\n");
1046                 }
1047         }
1048 }
1049
1050 static int __devinit tps80031_add_subdevs(struct tps80031 *tps80031,
1051                                           struct tps80031_platform_data *pdata)
1052 {
1053         struct tps80031_subdev_info *subdev;
1054         struct platform_device *pdev;
1055         int i, ret = 0;
1056
1057         for (i = 0; i < pdata->num_subdevs; i++) {
1058                 subdev = &pdata->subdevs[i];
1059
1060                 pdev = platform_device_alloc(subdev->name, subdev->id);
1061
1062                 pdev->dev.parent = tps80031->dev;
1063                 pdev->dev.platform_data = subdev->platform_data;
1064
1065                 ret = platform_device_add(pdev);
1066                 if (ret)
1067                         goto failed;
1068         }
1069         return 0;
1070
1071 failed:
1072         tps80031_remove_subdevs(tps80031);
1073         return ret;
1074 }
1075
1076 #ifdef CONFIG_DEBUG_FS
1077 #include <linux/debugfs.h>
1078 #include <linux/seq_file.h>
1079 static void print_regs(const char *header, struct seq_file *s,
1080                 int sid, int start_offset, int end_offset)
1081 {
1082         struct tps80031 *tps80031 = s->private;
1083         struct tps80031_client *tps = &tps80031->tps_clients[sid];
1084         uint8_t reg_val;
1085         int i;
1086         int ret;
1087
1088         seq_printf(s, "%s\n", header);
1089         for (i = start_offset; i <= end_offset; ++i) {
1090                 ret = __tps80031_read(tps->client, i, &reg_val);
1091                 if (ret >= 0)
1092                         seq_printf(s, "Addr = 0x%02x Reg 0x%02x Value 0x%02x\n",
1093                                                 tps->client->addr, i, reg_val);
1094         }
1095         seq_printf(s, "------------------\n");
1096 }
1097
1098 static int dbg_tps_show(struct seq_file *s, void *unused)
1099 {
1100         seq_printf(s, "TPS80031 Registers\n");
1101         seq_printf(s, "------------------\n");
1102         print_regs("VIO Regs",       s, SLAVE_ID1, 0x47, 0x49);
1103         print_regs("VIO Regs",       s, SLAVE_ID0, 0x49, 0x4A);
1104         print_regs("SMPS1 Regs",     s, SLAVE_ID1, 0x53, 0x54);
1105         print_regs("SMPS1 Regs",     s, SLAVE_ID0, 0x55, 0x56);
1106         print_regs("SMPS1 Regs",     s, SLAVE_ID1, 0x57, 0x57);
1107         print_regs("SMPS2 Regs",     s, SLAVE_ID1, 0x59, 0x5B);
1108         print_regs("SMPS2 Regs",     s, SLAVE_ID0, 0x5B, 0x5C);
1109         print_regs("SMPS2 Regs",     s, SLAVE_ID1, 0x5C, 0x5D);
1110         print_regs("SMPS3 Regs",     s, SLAVE_ID1, 0x65, 0x68);
1111         print_regs("SMPS4 Regs",     s, SLAVE_ID1, 0x41, 0x44);
1112         print_regs("VANA Regs",      s, SLAVE_ID1, 0x81, 0x83);
1113         print_regs("VRTC Regs",      s, SLAVE_ID1, 0xC3, 0xC4);
1114         print_regs("LDO1 Regs",      s, SLAVE_ID1, 0x9D, 0x9F);
1115         print_regs("LDO2 Regs",      s, SLAVE_ID1, 0x85, 0x87);
1116         print_regs("LDO3 Regs",      s, SLAVE_ID1, 0x8D, 0x8F);
1117         print_regs("LDO4 Regs",      s, SLAVE_ID1, 0x89, 0x8B);
1118         print_regs("LDO5 Regs",      s, SLAVE_ID1, 0x99, 0x9B);
1119         print_regs("LDO6 Regs",      s, SLAVE_ID1, 0x91, 0x93);
1120         print_regs("LDO7 Regs",      s, SLAVE_ID1, 0xA5, 0xA7);
1121         print_regs("LDOUSB Regs",    s, SLAVE_ID1, 0xA1, 0xA3);
1122         print_regs("LDOLN Regs",     s, SLAVE_ID1, 0x95, 0x97);
1123         print_regs("REGEN1 Regs",    s, SLAVE_ID1, 0xAE, 0xAF);
1124         print_regs("REGEN2 Regs",    s, SLAVE_ID1, 0xB1, 0xB2);
1125         print_regs("SYSEN Regs",     s, SLAVE_ID1, 0xB4, 0xB5);
1126         print_regs("CLK32KAO Regs",  s, SLAVE_ID1, 0xBA, 0xBB);
1127         print_regs("CLK32KG Regs",   s, SLAVE_ID1, 0xBD, 0xBE);
1128         print_regs("CLK32KAUD Regs", s, SLAVE_ID1, 0xC0, 0xC1);
1129         print_regs("INT Regs",       s, SLAVE_ID2, 0xD0, 0xD8);
1130         print_regs("PREQ Regs",      s, SLAVE_ID1, 0xD7, 0xDF);
1131         print_regs("MASK_PH Regs",   s, SLAVE_ID1, 0x20, 0x21);
1132         print_regs("PMC MISC Regs",  s, SLAVE_ID1, 0xE0, 0xEF);
1133         print_regs("CONT_STATE",     s, SLAVE_ID2, 0xE0, 0xE4);
1134         print_regs("VERNUM Regs",    s, SLAVE_ID3, 0x87, 0x87);
1135         print_regs("EEPROM Regs",    s, SLAVE_ID3, 0xDF, 0xDF);
1136         print_regs("CHARGE Regs",    s, SLAVE_ID2, 0xDA, 0xF5);
1137         return 0;
1138 }
1139
1140 static int dbg_tps_open(struct inode *inode, struct file *file)
1141 {
1142         return single_open(file, dbg_tps_show, inode->i_private);
1143 }
1144
1145 static const struct file_operations debug_fops = {
1146         .open           = dbg_tps_open,
1147         .read           = seq_read,
1148         .llseek         = seq_lseek,
1149         .release        = single_release,
1150 };
1151
1152 static void __init tps80031_debuginit(struct tps80031 *tps)
1153 {
1154         (void)debugfs_create_file("tps80031", S_IRUGO, NULL,
1155                         tps, &debug_fops);
1156 }
1157 #else
1158 static void __init tps80031_debuginit(struct tps80031 *tpsi)
1159 {
1160         return;
1161 }
1162 #endif
1163
1164 static int __devexit tps80031_i2c_remove(struct i2c_client *client)
1165 {
1166         struct tps80031 *tps80031 = i2c_get_clientdata(client);
1167         int i;
1168
1169         if (client->irq)
1170                 free_irq(client->irq, tps80031);
1171
1172         if (tps80031->gpio.owner != NULL)
1173                 if (gpiochip_remove(&tps80031->gpio) < 0)
1174                         dev_err(&client->dev, "Error in removing the gpio driver\n");
1175
1176         for (i = 0; i < TPS_NUM_SLAVES; i++) {
1177                 struct tps80031_client *tps = &tps80031->tps_clients[i];
1178                 if (tps->client && tps->client != client)
1179                         i2c_unregister_device(tps->client);
1180                 tps80031->tps_clients[i].client = NULL;
1181                 mutex_destroy(&tps->lock);
1182         }
1183
1184         kfree(tps80031);
1185         return 0;
1186 }
1187
1188 static int __devinit tps80031_i2c_probe(struct i2c_client *client,
1189                                         const struct i2c_device_id *id)
1190 {
1191         struct tps80031_platform_data *pdata = client->dev.platform_data;
1192         struct tps80031 *tps80031;
1193         struct tps80031_client *tps;
1194         int ret;
1195         int jtag_ver;
1196         int ep_ver;
1197         int i;
1198
1199         if (!pdata) {
1200                 dev_err(&client->dev, "tps80031 requires platform data\n");
1201                 return -ENOTSUPP;
1202         }
1203
1204         jtag_ver = i2c_smbus_read_byte_data(client, TPS80031_JTAGVERNUM);
1205         if (jtag_ver < 0) {
1206                 dev_err(&client->dev, "Silicon version number read"
1207                                 " failed: %d\n", jtag_ver);
1208                 return -EIO;
1209         }
1210
1211         ep_ver = i2c_smbus_read_byte_data(client, TPS80031_EPROM_REV);
1212         if (ep_ver < 0) {
1213                 dev_err(&client->dev, "Silicon eeprom version read"
1214                                 " failed: %d\n", ep_ver);
1215                 return -EIO;
1216         }
1217
1218         dev_info(&client->dev, "Jtag version 0x%02x and Eeprom version 0x%02x\n",
1219                                                 jtag_ver, ep_ver);
1220
1221         tps80031 = kzalloc(sizeof(struct tps80031), GFP_KERNEL);
1222         if (tps80031 == NULL)
1223                 return -ENOMEM;
1224
1225         tps80031->es_version = jtag_ver;
1226         tps80031->dev = &client->dev;
1227         i2c_set_clientdata(client, tps80031);
1228         tps80031->chip_info = id->driver_data;
1229
1230         /* Set up slaves */
1231         tps80031->tps_clients[SLAVE_ID0].addr = I2C_ID0_ADDR;
1232         tps80031->tps_clients[SLAVE_ID1].addr = I2C_ID1_ADDR;
1233         tps80031->tps_clients[SLAVE_ID2].addr = I2C_ID2_ADDR;
1234         tps80031->tps_clients[SLAVE_ID3].addr = I2C_ID3_ADDR;
1235         for (i = 0; i < TPS_NUM_SLAVES; i++) {
1236                 tps = &tps80031->tps_clients[i];
1237                 if (tps->addr == client->addr)
1238                         tps->client = client;
1239                 else
1240                         tps->client = i2c_new_dummy(client->adapter,
1241                                                 tps->addr);
1242                 if (!tps->client) {
1243                         dev_err(&client->dev, "can't attach client %d\n", i);
1244                         ret = -ENOMEM;
1245                         goto fail;
1246                 }
1247                 i2c_set_clientdata(tps->client, tps80031);
1248                 mutex_init(&tps->lock);
1249         }
1250
1251         if (client->irq) {
1252                 ret = tps80031_irq_init(tps80031, client->irq,
1253                                         pdata->irq_base);
1254                 if (ret) {
1255                         dev_err(&client->dev, "IRQ init failed: %d\n", ret);
1256                         goto fail;
1257                 }
1258         }
1259
1260         tps80031_pupd_init(tps80031, pdata);
1261
1262         tps80031_init_ext_control(tps80031, pdata);
1263
1264         ret = tps80031_add_subdevs(tps80031, pdata);
1265         if (ret) {
1266                 dev_err(&client->dev, "add devices failed: %d\n", ret);
1267                 goto fail;
1268         }
1269
1270         tps80031_gpio_init(tps80031, pdata);
1271
1272         tps80031_clk32k_init(tps80031, pdata);
1273
1274         tps80031_debuginit(tps80031);
1275
1276         if (pdata->use_power_off && !pm_power_off)
1277                 pm_power_off = tps80031_power_off;
1278
1279         tps80031_dev = tps80031;
1280
1281         return 0;
1282
1283 fail:
1284         tps80031_i2c_remove(client);
1285         return ret;
1286 }
1287
1288 #ifdef CONFIG_PM
1289 static int tps80031_i2c_suspend(struct i2c_client *client, pm_message_t state)
1290 {
1291         if (client->irq)
1292                 disable_irq(client->irq);
1293         return 0;
1294 }
1295
1296 static int tps80031_i2c_resume(struct i2c_client *client)
1297 {
1298         if (client->irq)
1299                 enable_irq(client->irq);
1300         return 0;
1301 }
1302 #endif
1303
1304
1305 static const struct i2c_device_id tps80031_id_table[] = {
1306         { "tps80031", TPS80031 },
1307         { "tps80032", TPS80032 },
1308 };
1309 MODULE_DEVICE_TABLE(i2c, tps80031_id_table);
1310
1311 static struct i2c_driver tps80031_driver = {
1312         .driver = {
1313                 .name   = "tps80031",
1314                 .owner  = THIS_MODULE,
1315         },
1316         .probe          = tps80031_i2c_probe,
1317         .remove         = __devexit_p(tps80031_i2c_remove),
1318 #ifdef CONFIG_PM
1319         .suspend        = tps80031_i2c_suspend,
1320         .resume         = tps80031_i2c_resume,
1321 #endif
1322         .id_table       = tps80031_id_table,
1323 };
1324
1325 static int __init tps80031_init(void)
1326 {
1327         return i2c_add_driver(&tps80031_driver);
1328 }
1329 subsys_initcall(tps80031_init);
1330
1331 static void __exit tps80031_exit(void)
1332 {
1333         i2c_del_driver(&tps80031_driver);
1334 }
1335 module_exit(tps80031_exit);
1336
1337 MODULE_DESCRIPTION("TPS80031 core driver");
1338 MODULE_LICENSE("GPL");