regulator: tps8003x: Add Charging bus ID
[linux-2.6.git] / drivers / mfd / tps80031.c
1 /*
2  * driver/mfd/tps80031.c
3  *
4  * Core driver for TI TPS80031
5  *
6  * Copyright (C) 2011 NVIDIA Corporation
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, write to the Free Software Foundation, Inc.,
20  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
21  *
22  */
23
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/mutex.h>
29 #include <linux/slab.h>
30 #include <linux/gpio.h>
31 #include <linux/i2c.h>
32
33 #include <linux/mfd/core.h>
34 #include <linux/mfd/tps80031.h>
35
36 /* interrupt related registers */
37 #define TPS80031_INT_STS_A              0xD0
38 #define TPS80031_INT_STS_B              0xD1
39 #define TPS80031_INT_STS_C              0xD2
40 #define TPS80031_INT_MSK_LINE_A         0xD3
41 #define TPS80031_INT_MSK_LINE_B         0xD4
42 #define TPS80031_INT_MSK_LINE_C         0xD5
43 #define TPS80031_INT_MSK_STS_A          0xD6
44 #define TPS80031_INT_MSK_STS_B          0xD7
45 #define TPS80031_INT_MSK_STS_C          0xD8
46
47 #define TPS80031_CONTROLLER_STAT1               0xE3
48 #define CONTROLLER_STAT1_BAT_TEMP               0
49 #define CONTROLLER_STAT1_BAT_REMOVED            1
50 #define CONTROLLER_STAT1_VBUS_DET               2
51 #define CONTROLLER_STAT1_VAC_DET                3
52 #define CONTROLLER_STAT1_FAULT_WDG              4
53 #define CONTROLLER_STAT1_LINCH_GATED            6
54
55 #define TPS80031_CONTROLLER_INT_MASK            0xE0
56 #define CONTROLLER_INT_MASK_MVAC_DET            0
57 #define CONTROLLER_INT_MASK_MVBUS_DET           1
58 #define CONTROLLER_INT_MASK_MBAT_TEMP           2
59 #define CONTROLLER_INT_MASK_MFAULT_WDG          3
60 #define CONTROLLER_INT_MASK_MBAT_REMOVED        4
61 #define CONTROLLER_INT_MASK_MLINCH_GATED        5
62
63 #define CHARGE_CONTROL_SUB_INT_MASK             0x3F
64
65 /* Version number related register */
66 #define TPS80031_JTAGVERNUM             0x87
67 /* Epprom version */
68 #define TPS80031_EPROM_REV              0xDF
69
70 /* External control register */
71 #define REGEN1_BASE_ADD         0xAE
72 #define REGEN2_BASE_ADD         0xB1
73 #define SYSEN_BASE_ADD          0xB4
74
75 /* device control registers */
76 #define TPS80031_PHOENIX_DEV_ON 0x25
77 #define DEVOFF  1
78
79 #define CLK32KAO_BASE_ADD       0xBA
80 #define CLK32KG_BASE_ADD        0xBD
81 #define CLK32KAUDIO_BASE_ADD    0xC0
82
83 #define EXT_CONTROL_CFG_TRANS 0
84 #define EXT_CONTROL_CFG_STATE 1
85
86 #define STATE_OFF       0x00
87 #define STATE_ON        0x01
88 #define STATE_MASK      0x03
89
90 #define TPS_NUM_SLAVES  4
91
92 static u8 pmc_ext_control_base[] = {
93         REGEN1_BASE_ADD,
94         REGEN2_BASE_ADD,
95         SYSEN_BASE_ADD,
96 };
97
98 struct tps80031_irq_data {
99         u8      mask_reg;
100         u8      mask_mask;
101         u8      is_sec_int;
102         u8      parent_int;
103         u8      mask_sec_int_reg;
104         u8      int_mask_bit;
105         u8      int_sec_sts_reg;
106         u8      int_sts_bit;
107 };
108
109 #define TPS80031_IRQ(_reg, _mask)       \
110         {                                                       \
111                 .mask_reg = (TPS80031_INT_MSK_LINE_##_reg) -    \
112                                 TPS80031_INT_MSK_LINE_A,        \
113                 .mask_mask = (_mask),                           \
114         }
115
116 #define TPS80031_IRQ_SEC(_reg, _mask, _pint, _sint_mask_bit, _sint_sts_bit) \
117         {                                                               \
118                 .mask_reg = (TPS80031_INT_MSK_LINE_##_reg) -            \
119                                 TPS80031_INT_MSK_LINE_A,                \
120                 .mask_mask = (_mask),                                   \
121                 .is_sec_int = true,                                     \
122                 .parent_int = TPS80031_INT_##_pint,                     \
123                 .mask_sec_int_reg = TPS80031_CONTROLLER_INT_MASK,       \
124                 .int_mask_bit = CONTROLLER_INT_MASK_##_sint_mask_bit,   \
125                 .int_sec_sts_reg = TPS80031_CONTROLLER_STAT1,           \
126                 .int_sts_bit = CONTROLLER_STAT1_##_sint_sts_bit         \
127         }
128
129 static const struct tps80031_irq_data tps80031_irqs[] = {
130
131         [TPS80031_INT_PWRON]            = TPS80031_IRQ(A, 0),
132         [TPS80031_INT_RPWRON]           = TPS80031_IRQ(A, 1),
133         [TPS80031_INT_SYS_VLOW]         = TPS80031_IRQ(A, 2),
134         [TPS80031_INT_RTC_ALARM]        = TPS80031_IRQ(A, 3),
135         [TPS80031_INT_RTC_PERIOD]       = TPS80031_IRQ(A, 4),
136         [TPS80031_INT_HOT_DIE]          = TPS80031_IRQ(A, 5),
137         [TPS80031_INT_VXX_SHORT]        = TPS80031_IRQ(A, 6),
138         [TPS80031_INT_SPDURATION]       = TPS80031_IRQ(A, 7),
139         [TPS80031_INT_WATCHDOG]         = TPS80031_IRQ(B, 0),
140         [TPS80031_INT_BAT]              = TPS80031_IRQ(B, 1),
141         [TPS80031_INT_SIM]              = TPS80031_IRQ(B, 2),
142         [TPS80031_INT_MMC]              = TPS80031_IRQ(B, 3),
143         [TPS80031_INT_RES]              = TPS80031_IRQ(B, 4),
144         [TPS80031_INT_GPADC_RT]         = TPS80031_IRQ(B, 5),
145         [TPS80031_INT_GPADC_SW2_EOC]    = TPS80031_IRQ(B, 6),
146         [TPS80031_INT_CC_AUTOCAL]       = TPS80031_IRQ(B, 7),
147         [TPS80031_INT_ID_WKUP]          = TPS80031_IRQ(C, 0),
148         [TPS80031_INT_VBUSS_WKUP]       = TPS80031_IRQ(C, 1),
149         [TPS80031_INT_ID]               = TPS80031_IRQ(C, 2),
150         [TPS80031_INT_VBUS]             = TPS80031_IRQ(C, 3),
151         [TPS80031_INT_CHRG_CTRL]        = TPS80031_IRQ(C, 4),
152         [TPS80031_INT_EXT_CHRG]         = TPS80031_IRQ(C, 5),
153         [TPS80031_INT_INT_CHRG]         = TPS80031_IRQ(C, 6),
154         [TPS80031_INT_RES2]             = TPS80031_IRQ(C, 7),
155         [TPS80031_INT_BAT_TEMP_OVRANGE] = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
156                                                 MBAT_TEMP,      BAT_TEMP),
157         [TPS80031_INT_BAT_REMOVED]      = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
158                                                 MBAT_REMOVED,   BAT_REMOVED),
159         [TPS80031_INT_VBUS_DET]         = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
160                                                 MVBUS_DET,      VBUS_DET),
161         [TPS80031_INT_VAC_DET]          = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
162                                                 MVAC_DET,       VAC_DET),
163         [TPS80031_INT_FAULT_WDG]        = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
164                                                 MFAULT_WDG,     FAULT_WDG),
165         [TPS80031_INT_LINCH_GATED]      = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
166                                                 MLINCH_GATED,   LINCH_GATED),
167 };
168
169 static const int controller_stat1_irq_nr[] = {
170         TPS80031_INT_BAT_TEMP_OVRANGE,
171         TPS80031_INT_BAT_REMOVED,
172         TPS80031_INT_VBUS_DET,
173         TPS80031_INT_VAC_DET,
174         TPS80031_INT_FAULT_WDG,
175         0,
176         TPS80031_INT_LINCH_GATED,
177         0
178 };
179
180 /* Structure for TPS80031 Slaves */
181 struct tps80031_client {
182         struct i2c_client *client;
183         struct mutex lock;
184         u8 addr;
185 };
186
187 struct tps80031 {
188         struct device           *dev;
189         unsigned long           chip_info;
190
191         struct gpio_chip        gpio;
192         struct irq_chip         irq_chip;
193         struct mutex            irq_lock;
194         int                     irq_base;
195         u32                     irq_en;
196         u8                      mask_cache[3];
197         u8                      mask_reg[3];
198         u8                      cont_int_mask_reg;
199         u8                      cont_int_mask_cache;
200         u8                      cont_int_en;
201         u8                      prev_cont_stat1;
202         struct tps80031_client  tps_clients[TPS_NUM_SLAVES];
203 };
204
205 static inline int __tps80031_read(struct i2c_client *client,
206                                   int reg, uint8_t *val)
207 {
208         int ret;
209
210         ret = i2c_smbus_read_byte_data(client, reg);
211         if (ret < 0) {
212                 dev_err(&client->dev,
213                         "failed reading from addr 0x%02x, reg 0x%02x\n",
214                         client->addr, reg);
215                 return ret;
216         }
217
218         *val = (uint8_t)ret;
219
220         return 0;
221 }
222
223 static inline int __tps80031_reads(struct i2c_client *client, int reg,
224                                 int len, uint8_t *val)
225 {
226         int ret;
227
228         ret = i2c_smbus_read_i2c_block_data(client, reg, len, val);
229         if (ret < 0) {
230                 dev_err(&client->dev,
231                         "failed reading from addr 0x%02x, reg   0x%02x\n",
232                          client->addr, reg);
233                 return ret;
234         }
235
236         return 0;
237 }
238
239 static inline int __tps80031_write(struct i2c_client *client,
240                                  int reg, uint8_t val)
241 {
242         int ret;
243         ret = i2c_smbus_write_byte_data(client, reg, val);
244         if (ret < 0) {
245                 dev_err(&client->dev,
246                         "failed writing 0x%02x to 0x%02x\n", val, reg);
247                 return ret;
248         }
249
250         return 0;
251 }
252
253 static inline int __tps80031_writes(struct i2c_client *client, int reg,
254                                   int len, uint8_t *val)
255 {
256         int ret;
257
258         ret = i2c_smbus_write_i2c_block_data(client, reg, len, val);
259         if (ret < 0) {
260                 dev_err(&client->dev, "failed writings to 0x%02x\n", reg);
261                 return ret;
262         }
263
264         return 0;
265 }
266
267 int tps80031_write(struct device *dev, int sid, int reg, uint8_t val)
268 {
269         struct tps80031 *tps80031 = dev_get_drvdata(dev);
270         struct tps80031_client *tps = &tps80031->tps_clients[sid];
271         int ret;
272
273         mutex_lock(&tps->lock);
274         ret = __tps80031_write(tps->client, reg, val);
275         mutex_unlock(&tps->lock);
276
277         return ret;
278 }
279 EXPORT_SYMBOL_GPL(tps80031_write);
280
281 int tps80031_writes(struct device *dev, int sid, int reg, int len, uint8_t *val)
282 {
283         struct tps80031 *tps80031 = dev_get_drvdata(dev);
284         struct tps80031_client *tps = &tps80031->tps_clients[sid];
285         int ret;
286
287         mutex_lock(&tps->lock);
288         ret = __tps80031_writes(tps->client, reg, len, val);
289         mutex_unlock(&tps->lock);
290
291         return ret;
292 }
293 EXPORT_SYMBOL_GPL(tps80031_writes);
294
295 int tps80031_read(struct device *dev, int sid, int reg, uint8_t *val)
296 {
297         struct tps80031 *tps80031 = dev_get_drvdata(dev);
298         struct tps80031_client *tps = &tps80031->tps_clients[sid];
299
300         return __tps80031_read(tps->client, reg, val);
301 }
302 EXPORT_SYMBOL_GPL(tps80031_read);
303
304 int tps80031_reads(struct device *dev, int sid, int reg, int len, uint8_t *val)
305 {
306         struct tps80031 *tps80031 = dev_get_drvdata(dev);
307         struct tps80031_client *tps = &tps80031->tps_clients[sid];
308
309         return __tps80031_reads(tps->client, reg, len, val);
310 }
311 EXPORT_SYMBOL_GPL(tps80031_reads);
312
313 int tps80031_set_bits(struct device *dev, int sid, int reg, uint8_t bit_mask)
314 {
315         struct tps80031 *tps80031 = dev_get_drvdata(dev);
316         struct tps80031_client *tps = &tps80031->tps_clients[sid];
317         uint8_t reg_val;
318         int ret = 0;
319
320         mutex_lock(&tps->lock);
321
322         ret = __tps80031_read(tps->client, reg, &reg_val);
323         if (ret)
324                 goto out;
325
326         if ((reg_val & bit_mask) != bit_mask) {
327                 reg_val |= bit_mask;
328                 ret = __tps80031_write(tps->client, reg, reg_val);
329         }
330 out:
331         mutex_unlock(&tps->lock);
332         return ret;
333 }
334 EXPORT_SYMBOL_GPL(tps80031_set_bits);
335
336 int tps80031_clr_bits(struct device *dev, int sid, int reg, uint8_t bit_mask)
337 {
338         struct tps80031 *tps80031 = dev_get_drvdata(dev);
339         struct tps80031_client *tps = &tps80031->tps_clients[sid];
340         uint8_t reg_val;
341         int ret = 0;
342
343         mutex_lock(&tps->lock);
344
345         ret = __tps80031_read(tps->client, reg, &reg_val);
346         if (ret)
347                 goto out;
348
349         if (reg_val & bit_mask) {
350                 reg_val &= ~bit_mask;
351                 ret = __tps80031_write(tps->client, reg, reg_val);
352         }
353 out:
354         mutex_unlock(&tps->lock);
355         return ret;
356 }
357 EXPORT_SYMBOL_GPL(tps80031_clr_bits);
358
359 int tps80031_update(struct device *dev, int sid, int reg, uint8_t val,
360                 uint8_t mask)
361 {
362         struct tps80031 *tps80031 = dev_get_drvdata(dev);
363         struct tps80031_client *tps = &tps80031->tps_clients[sid];
364         uint8_t reg_val;
365         int ret = 0;
366
367         mutex_lock(&tps->lock);
368
369         ret = __tps80031_read(tps->client, reg, &reg_val);
370         if (ret)
371                 goto out;
372
373         if ((reg_val & mask) != val) {
374                 reg_val = (reg_val & ~mask) | (val & mask);
375                 ret = __tps80031_write(tps->client, reg, reg_val);
376         }
377 out:
378         mutex_unlock(&tps->lock);
379         return ret;
380 }
381 EXPORT_SYMBOL_GPL(tps80031_update);
382
383 int tps80031_force_update(struct device *dev, int sid, int reg, uint8_t val,
384                           uint8_t mask)
385 {
386         struct tps80031 *tps80031 = dev_get_drvdata(dev);
387         struct tps80031_client *tps = &tps80031->tps_clients[sid];
388         uint8_t reg_val;
389         int ret = 0;
390
391         mutex_lock(&tps->lock);
392
393         ret = __tps80031_read(tps->client, reg, &reg_val);
394         if (ret)
395                 goto out;
396
397         reg_val = (reg_val & ~mask) | (val & mask);
398         ret = __tps80031_write(tps->client, reg, reg_val);
399
400 out:
401         mutex_unlock(&tps->lock);
402         return ret;
403 }
404 EXPORT_SYMBOL_GPL(tps80031_force_update);
405
406 unsigned long tps80031_get_chip_info(struct device *dev)
407 {
408         struct tps80031 *tps80031 = dev_get_drvdata(dev);
409         return tps80031->chip_info;
410 }
411 EXPORT_SYMBOL_GPL(tps80031_get_chip_info);
412
413 static struct tps80031 *tps80031_dev;
414 int tps80031_power_off(void)
415 {
416         struct tps80031_client *tps = &tps80031_dev->tps_clients[SLAVE_ID1];
417
418         if (!tps->client)
419                 return -EINVAL;
420         dev_info(&tps->client->dev, "switching off PMU\n");
421         return __tps80031_write(tps->client, TPS80031_PHOENIX_DEV_ON, DEVOFF);
422 }
423
424 static int tps80031_gpio_get(struct gpio_chip *gc, unsigned offset)
425 {
426         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
427         struct tps80031_client *tps = &tps80031->tps_clients[SLAVE_ID1];
428         uint8_t state;
429         uint8_t trans;
430         int ret;
431
432         ret = __tps80031_read(tps->client,
433                         pmc_ext_control_base[offset] +
434                                 EXT_CONTROL_CFG_STATE, &state);
435         if (ret)
436                 return ret;
437
438         if (state != 0) {
439                 ret = __tps80031_read(tps->client,
440                                 pmc_ext_control_base[offset] +
441                                         EXT_CONTROL_CFG_TRANS, &trans);
442                 if (ret)
443                         return ret;
444                 return trans & 0x1;
445         }
446         return 0;
447 }
448
449 static void tps80031_gpio_set(struct gpio_chip *gc, unsigned offset,
450                         int value)
451 {
452         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
453
454         tps80031_update(tps80031->dev, SLAVE_ID1,
455                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_TRANS,
456                         value, 0x1);
457 }
458
459 static int tps80031_gpio_input(struct gpio_chip *gc, unsigned offset)
460 {
461         return -EIO;
462 }
463
464 static int tps80031_gpio_output(struct gpio_chip *gc, unsigned offset,
465                                 int value)
466 {
467         tps80031_gpio_set(gc, offset, value);
468         return 0;
469 }
470
471 static int tps80031_gpio_enable(struct gpio_chip *gc, unsigned offset)
472 {
473         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
474         int ret;
475
476         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
477                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_STATE,
478                                                 STATE_ON, STATE_MASK);
479         if (ret)
480                 return ret;
481
482         return tps80031_write(tps80031->dev, SLAVE_ID1,
483                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_TRANS, 0x0);
484 }
485
486 static void tps80031_gpio_disable(struct gpio_chip *gc, unsigned offset)
487 {
488         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
489         tps80031_update(tps80031->dev, SLAVE_ID1,
490                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_STATE,
491                                                 STATE_OFF, STATE_MASK);
492 }
493
494 static void tps80031_gpio_init(struct tps80031 *tps80031,
495                         struct tps80031_platform_data *pdata)
496 {
497         int ret;
498         int gpio_base = pdata->gpio_base;
499         struct tps80031_client *tps = &tps80031->tps_clients[SLAVE_ID1];
500
501         if (gpio_base <= 0)
502                 return;
503
504         tps80031->gpio.owner            = THIS_MODULE;
505         tps80031->gpio.label            = tps->client->name;
506         tps80031->gpio.dev              = tps80031->dev;
507         tps80031->gpio.base             = gpio_base;
508         tps80031->gpio.ngpio            = TPS80031_GPIO_NR;
509         tps80031->gpio.can_sleep        = 1;
510
511         tps80031->gpio.request          = tps80031_gpio_enable;
512         tps80031->gpio.free             = tps80031_gpio_disable;
513         tps80031->gpio.direction_input  = tps80031_gpio_input;
514         tps80031->gpio.direction_output = tps80031_gpio_output;
515         tps80031->gpio.set              = tps80031_gpio_set;
516         tps80031->gpio.get              = tps80031_gpio_get;
517
518         ret = gpiochip_add(&tps80031->gpio);
519         if (ret)
520                 dev_warn(tps80031->dev, "GPIO registration failed: %d\n", ret);
521 }
522
523 static int __remove_subdev(struct device *dev, void *unused)
524 {
525         platform_device_unregister(to_platform_device(dev));
526         return 0;
527 }
528
529 static int tps80031_remove_subdevs(struct tps80031 *tps80031)
530 {
531         return device_for_each_child(tps80031->dev, NULL, __remove_subdev);
532 }
533
534 static void tps80031_irq_lock(struct irq_data *data)
535 {
536         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
537
538         mutex_lock(&tps80031->irq_lock);
539 }
540
541 static void tps80031_irq_enable(struct irq_data *data)
542 {
543         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
544         unsigned int __irq = data->irq - tps80031->irq_base;
545         const struct tps80031_irq_data *irq_data = &tps80031_irqs[__irq];
546
547         if (irq_data->is_sec_int) {
548                 tps80031->cont_int_mask_reg &= ~(1 << irq_data->int_mask_bit);
549                 tps80031->cont_int_en |= (1 << irq_data->int_mask_bit);
550                 tps80031->mask_reg[irq_data->mask_reg] &= ~(1 << irq_data->mask_mask);
551                 tps80031->irq_en |= (1 << irq_data->parent_int);
552         } else
553                 tps80031->mask_reg[irq_data->mask_reg] &= ~(1 << irq_data->mask_mask);
554
555         tps80031->irq_en |= (1 << __irq);
556 }
557
558 static void tps80031_irq_disable(struct irq_data *data)
559 {
560         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
561
562         unsigned int __irq = data->irq - tps80031->irq_base;
563         const struct tps80031_irq_data *irq_data = &tps80031_irqs[__irq];
564
565         if (irq_data->is_sec_int) {
566                 tps80031->cont_int_mask_reg |= (1 << irq_data->int_mask_bit);
567                 tps80031->cont_int_en &= ~(1 << irq_data->int_mask_bit);
568                 if (!tps80031->cont_int_en) {
569                         tps80031->mask_reg[irq_data->mask_reg] |=
570                                                 (1 << irq_data->mask_mask);
571                         tps80031->irq_en &= ~(1 << irq_data->parent_int);
572                 }
573                 tps80031->irq_en &= ~(1 << __irq);
574         } else
575                 tps80031->mask_reg[irq_data->mask_reg] |= (1 << irq_data->mask_mask);
576
577         tps80031->irq_en &= ~(1 << __irq);
578 }
579
580 static void tps80031_irq_sync_unlock(struct irq_data *data)
581 {
582         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
583         int i;
584
585         for (i = 0; i < ARRAY_SIZE(tps80031->mask_reg); i++) {
586                 if (tps80031->mask_reg[i] != tps80031->mask_cache[i]) {
587                         if (!WARN_ON(tps80031_write(tps80031->dev, SLAVE_ID2,
588                                                 TPS80031_INT_MSK_LINE_A + i,
589                                                 tps80031->mask_reg[i])))
590                                 if (!WARN_ON(tps80031_write(tps80031->dev,
591                                                 SLAVE_ID2,
592                                                 TPS80031_INT_MSK_STS_A + i,
593                                                 tps80031->mask_reg[i])))
594                                         tps80031->mask_cache[i] =
595                                                         tps80031->mask_reg[i];
596                 }
597         }
598
599         if (tps80031->cont_int_mask_reg != tps80031->cont_int_mask_cache) {
600                 if (!WARN_ON(tps80031_write(tps80031->dev, SLAVE_ID2,
601                                 TPS80031_CONTROLLER_INT_MASK,
602                                 tps80031->cont_int_mask_reg)))
603                         tps80031->cont_int_mask_cache =
604                                                 tps80031->cont_int_mask_reg;
605         }
606
607         mutex_unlock(&tps80031->irq_lock);
608 }
609
610 static irqreturn_t tps80031_charge_control_irq(int irq, void *data)
611 {
612         struct tps80031 *tps80031 = data;
613         int ret = 0;
614         int i;
615         u8 cont_sts;
616         u8 org_sts;
617
618         if (irq != (tps80031->irq_base + TPS80031_INT_CHRG_CTRL)) {
619                 dev_err(tps80031->dev, "%s() Got the illegal interrupt %d\n",
620                                         __func__, irq);
621                 return IRQ_NONE;
622         }
623
624         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
625                         TPS80031_CONTROLLER_STAT1, &org_sts);
626         if (ret < 0) {
627                 dev_err(tps80031->dev, "%s(): failed to read controller state1 "
628                                 "status %d\n", __func__, ret);
629                 return IRQ_NONE;
630         }
631
632         /* Get change from last interrupt and mask for interested interrupt
633          * for charge control interrupt */
634         cont_sts = org_sts ^ tps80031->prev_cont_stat1;
635         tps80031->prev_cont_stat1 = org_sts;
636         cont_sts &= 0x5F;
637
638         for (i = 0; i < 8; ++i) {
639                 if (!controller_stat1_irq_nr[i])
640                         continue;
641                 if ((cont_sts & BIT(i)) &&
642                         (tps80031->irq_en & BIT(controller_stat1_irq_nr[i])))
643                         handle_nested_irq(tps80031->irq_base +
644                                                 controller_stat1_irq_nr[i]);
645                 cont_sts &= ~BIT(i);
646         }
647         return IRQ_HANDLED;
648 }
649
650 static irqreturn_t tps80031_irq(int irq, void *data)
651 {
652         struct tps80031 *tps80031 = data;
653         int ret = 0;
654         u8 tmp[3];
655         u32 acks;
656         int i;
657
658         for (i = 0; i < 3; i++) {
659                 ret = tps80031_read(tps80031->dev, SLAVE_ID2,
660                         TPS80031_INT_STS_A + i, &tmp[i]);
661                 if (ret < 0) {
662                         dev_err(tps80031->dev, "failed to read interrupt "
663                                                         "status\n");
664                         return IRQ_NONE;
665                 }
666                 if (tmp[i]) {
667                         ret = tps80031_write(tps80031->dev, SLAVE_ID2,
668                                         TPS80031_INT_STS_A + i, tmp[i]);
669                         if (ret < 0) {
670                                 dev_err(tps80031->dev, "failed to write "
671                                                         "interrupt status\n");
672                                 return IRQ_NONE;
673                         }
674                 }
675         }
676         acks = (tmp[2] << 16) | (tmp[1] << 8) | tmp[0];
677         while (acks) {
678                 i = __ffs(acks);
679                 if (tps80031->irq_en & (1 << i))
680                         handle_nested_irq(tps80031->irq_base + i);
681                 acks &= ~(1 << i);
682         }
683         return IRQ_HANDLED;
684 }
685
686 static int __devinit tps80031_irq_init(struct tps80031 *tps80031, int irq,
687                                 int irq_base)
688 {
689         int i, ret;
690
691         if (!irq_base) {
692                 dev_warn(tps80031->dev, "No interrupt support on IRQ base\n");
693                 return -EINVAL;
694         }
695
696         mutex_init(&tps80031->irq_lock);
697
698         for (i = 0; i < 3; i++) {
699                 tps80031->mask_reg[i] = 0xFF;
700                 tps80031->mask_cache[i] = tps80031->mask_reg[i];
701                 tps80031_write(tps80031->dev, SLAVE_ID2,
702                                         TPS80031_INT_MSK_LINE_A + i,
703                                         tps80031->mask_cache[i]);
704                 tps80031_write(tps80031->dev, SLAVE_ID2,
705                                         TPS80031_INT_MSK_STS_A + i, 0xFF);
706                 tps80031_write(tps80031->dev, SLAVE_ID2,
707                                         TPS80031_INT_STS_A + i, 0xFF);
708         }
709
710         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
711                                 TPS80031_CONTROLLER_INT_MASK,
712                                 &tps80031->cont_int_mask_reg);
713         if (ret < 0) {
714                 dev_err(tps80031->dev, "Error in reading the controller_mask "
715                                         "register %d\n", ret);
716                 return ret;
717         }
718
719         tps80031->cont_int_mask_reg |= CHARGE_CONTROL_SUB_INT_MASK;
720         tps80031->cont_int_mask_cache = tps80031->cont_int_mask_reg;
721         tps80031->cont_int_en = 0;
722         ret = tps80031_write(tps80031->dev, SLAVE_ID2,
723                                 TPS80031_CONTROLLER_INT_MASK,
724                                 tps80031->cont_int_mask_reg);
725         if (ret < 0) {
726                 dev_err(tps80031->dev, "Error in writing the controller_mask "
727                                         "register %d\n", ret);
728                 return ret;
729         }
730
731         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
732                         TPS80031_CONTROLLER_STAT1, &tps80031->prev_cont_stat1);
733         if (ret < 0) {
734                 dev_err(tps80031->dev, "%s(): failed to read controller state1 "
735                                 "status %d\n", __func__, ret);
736                 return ret;
737         }
738
739         tps80031->irq_base = irq_base;
740
741         tps80031->irq_chip.name = "tps80031";
742         tps80031->irq_chip.irq_enable = tps80031_irq_enable;
743         tps80031->irq_chip.irq_disable = tps80031_irq_disable;
744         tps80031->irq_chip.irq_bus_lock = tps80031_irq_lock;
745         tps80031->irq_chip.irq_bus_sync_unlock = tps80031_irq_sync_unlock;
746
747         for (i = 0; i < TPS80031_INT_NR; i++) {
748                 int __irq = i + tps80031->irq_base;
749                 irq_set_chip_data(__irq, tps80031);
750                 irq_set_chip_and_handler(__irq, &tps80031->irq_chip,
751                                          handle_simple_irq);
752                 irq_set_nested_thread(__irq, 1);
753 #ifdef CONFIG_ARM
754                 irq_set_status_flags(__irq, IRQF_VALID);
755 #endif
756         }
757
758         ret = request_threaded_irq(irq, NULL, tps80031_irq, IRQF_ONESHOT,
759                                 "tps80031", tps80031);
760         /* register the isr for the secondary interrupt */
761         if (!ret)
762                 ret = request_threaded_irq(irq_base + TPS80031_INT_CHRG_CTRL,
763                                 NULL, tps80031_charge_control_irq,
764                                 IRQF_ONESHOT, "80031_chg_ctl", tps80031);
765         if (!ret) {
766
767                 device_init_wakeup(tps80031->dev, 1);
768                 enable_irq_wake(irq);
769         }
770
771         return ret;
772 }
773
774 static void tps80031_clk32k_enable(struct tps80031 *tps80031, int base_add)
775 {
776         int ret;
777         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
778                         base_add + EXT_CONTROL_CFG_STATE, STATE_ON, STATE_MASK);
779         if (!ret)
780                 ret = tps80031_update(tps80031->dev, SLAVE_ID1,
781                                 base_add + EXT_CONTROL_CFG_TRANS,
782                                 STATE_ON, STATE_MASK);
783         if (ret < 0)
784                 dev_err(tps80031->dev, "Error in updating clock register\n");
785 }
786
787 static void tps80031_clk32k_init(struct tps80031 *tps80031,
788                         struct tps80031_platform_data *pdata)
789 {
790         struct tps80031_32kclock_plat_data *clk32k_pdata;
791
792         if (!(pdata && pdata->clk32k_pdata))
793                 return;
794
795         clk32k_pdata = pdata->clk32k_pdata;
796         if (clk32k_pdata->en_clk32kao)
797                 tps80031_clk32k_enable(tps80031, CLK32KAO_BASE_ADD);
798
799         if (clk32k_pdata->en_clk32kg)
800                 tps80031_clk32k_enable(tps80031, CLK32KG_BASE_ADD);
801
802         if (clk32k_pdata->en_clk32kaudio)
803                 tps80031_clk32k_enable(tps80031, CLK32KAUDIO_BASE_ADD);
804 }
805
806 static int __devinit tps80031_add_subdevs(struct tps80031 *tps80031,
807                                           struct tps80031_platform_data *pdata)
808 {
809         struct tps80031_subdev_info *subdev;
810         struct platform_device *pdev;
811         int i, ret = 0;
812
813         for (i = 0; i < pdata->num_subdevs; i++) {
814                 subdev = &pdata->subdevs[i];
815
816                 pdev = platform_device_alloc(subdev->name, subdev->id);
817
818                 pdev->dev.parent = tps80031->dev;
819                 pdev->dev.platform_data = subdev->platform_data;
820
821                 ret = platform_device_add(pdev);
822                 if (ret)
823                         goto failed;
824         }
825         return 0;
826
827 failed:
828         tps80031_remove_subdevs(tps80031);
829         return ret;
830 }
831
832 #ifdef CONFIG_DEBUG_FS
833 #include <linux/debugfs.h>
834 #include <linux/seq_file.h>
835 static void print_regs(const char *header, struct seq_file *s,
836                 int sid, int start_offset, int end_offset)
837 {
838         struct tps80031 *tps80031 = s->private;
839         struct tps80031_client *tps = &tps80031->tps_clients[sid];
840         uint8_t reg_val;
841         int i;
842         int ret;
843
844         seq_printf(s, "%s\n", header);
845         for (i = start_offset; i <= end_offset; ++i) {
846                 ret = __tps80031_read(tps->client, i, &reg_val);
847                 if (ret >= 0)
848                         seq_printf(s, "Addr = 0x%02x Reg 0x%02x Value 0x%02x\n",
849                                                 tps->client->addr, i, reg_val);
850         }
851         seq_printf(s, "------------------\n");
852 }
853
854 static int dbg_tps_show(struct seq_file *s, void *unused)
855 {
856         seq_printf(s, "TPS80031 Registers\n");
857         seq_printf(s, "------------------\n");
858         print_regs("VIO Regs",       s, SLAVE_ID1, 0x47, 0x49);
859         print_regs("VIO Regs",       s, SLAVE_ID0, 0x49, 0x4A);
860         print_regs("SMPS1 Regs",     s, SLAVE_ID1, 0x53, 0x54);
861         print_regs("SMPS1 Regs",     s, SLAVE_ID0, 0x55, 0x56);
862         print_regs("SMPS1 Regs",     s, SLAVE_ID1, 0x57, 0x57);
863         print_regs("SMPS2 Regs",     s, SLAVE_ID1, 0x59, 0x5B);
864         print_regs("SMPS2 Regs",     s, SLAVE_ID0, 0x5B, 0x5C);
865         print_regs("SMPS2 Regs",     s, SLAVE_ID1, 0x5C, 0x5D);
866         print_regs("SMPS3 Regs",     s, SLAVE_ID1, 0x65, 0x68);
867         print_regs("SMPS4 Regs",     s, SLAVE_ID1, 0x41, 0x44);
868         print_regs("VANA Regs",      s, SLAVE_ID1, 0x81, 0x83);
869         print_regs("VRTC Regs",      s, SLAVE_ID1, 0xC3, 0xC4);
870         print_regs("LDO1 Regs",      s, SLAVE_ID1, 0x9D, 0x9F);
871         print_regs("LDO2 Regs",      s, SLAVE_ID1, 0x85, 0x87);
872         print_regs("LDO3 Regs",      s, SLAVE_ID1, 0x8D, 0x8F);
873         print_regs("LDO4 Regs",      s, SLAVE_ID1, 0x89, 0x8B);
874         print_regs("LDO5 Regs",      s, SLAVE_ID1, 0x99, 0x9B);
875         print_regs("LDO6 Regs",      s, SLAVE_ID1, 0x91, 0x93);
876         print_regs("LDO7 Regs",      s, SLAVE_ID1, 0xA5, 0xA7);
877         print_regs("LDOUSB Regs",    s, SLAVE_ID1, 0xA1, 0xA3);
878         print_regs("LDOLN Regs",     s, SLAVE_ID1, 0x95, 0x97);
879         print_regs("REGEN1 Regs",    s, SLAVE_ID1, 0xAE, 0xAF);
880         print_regs("REGEN2 Regs",    s, SLAVE_ID1, 0xB1, 0xB2);
881         print_regs("SYSEN Regs",     s, SLAVE_ID1, 0xB4, 0xB5);
882         print_regs("CLK32KAO Regs",  s, SLAVE_ID1, 0xBA, 0xBB);
883         print_regs("CLK32KG Regs",   s, SLAVE_ID1, 0xBD, 0xBE);
884         print_regs("CLK32KAUD Regs", s, SLAVE_ID1, 0xC0, 0xC1);
885         print_regs("INT Regs",       s, SLAVE_ID2, 0xD0, 0xD8);
886         print_regs("PREQ Regs",      s, SLAVE_ID1, 0xD7, 0xDF);
887         print_regs("MASK_PH Regs",   s, SLAVE_ID1, 0x20, 0x21);
888         print_regs("CONT_STATE",     s, SLAVE_ID2, 0xE0, 0xE4);
889         print_regs("VERNUM Regs",    s, SLAVE_ID1, 0x87, 0x87);
890         print_regs("CHARGE Regs",    s, SLAVE_ID2, 0xDA, 0xF5);
891         return 0;
892 }
893
894 static int dbg_tps_open(struct inode *inode, struct file *file)
895 {
896         return single_open(file, dbg_tps_show, inode->i_private);
897 }
898
899 static const struct file_operations debug_fops = {
900         .open           = dbg_tps_open,
901         .read           = seq_read,
902         .llseek         = seq_lseek,
903         .release        = single_release,
904 };
905
906 static void __init tps80031_debuginit(struct tps80031 *tps)
907 {
908         (void)debugfs_create_file("tps80031", S_IRUGO, NULL,
909                         tps, &debug_fops);
910 }
911 #else
912 static void __init tps80031_debuginit(struct tps80031 *tpsi)
913 {
914         return;
915 }
916 #endif
917
918 static int __devexit tps80031_i2c_remove(struct i2c_client *client)
919 {
920         struct tps80031 *tps80031 = i2c_get_clientdata(client);
921         int i;
922
923         if (client->irq)
924                 free_irq(client->irq, tps80031);
925
926         if (tps80031->gpio.owner != NULL)
927                 if (gpiochip_remove(&tps80031->gpio) < 0)
928                         dev_err(&client->dev, "Error in removing the gpio driver\n");
929
930         for (i = 0; i < TPS_NUM_SLAVES; i++) {
931                 struct tps80031_client *tps = &tps80031->tps_clients[i];
932                 if (tps->client && tps->client != client)
933                         i2c_unregister_device(tps->client);
934                 tps80031->tps_clients[i].client = NULL;
935                 mutex_destroy(&tps->lock);
936         }
937
938         kfree(tps80031);
939         return 0;
940 }
941
942 static int __devinit tps80031_i2c_probe(struct i2c_client *client,
943                                         const struct i2c_device_id *id)
944 {
945         struct tps80031_platform_data *pdata = client->dev.platform_data;
946         struct tps80031 *tps80031;
947         struct tps80031_client *tps;
948         int ret;
949         int jtag_ver;
950         int ep_ver;
951         int i;
952
953         if (!pdata) {
954                 dev_err(&client->dev, "tps80031 requires platform data\n");
955                 return -ENOTSUPP;
956         }
957
958         jtag_ver = i2c_smbus_read_byte_data(client, TPS80031_JTAGVERNUM);
959         if (jtag_ver < 0) {
960                 dev_err(&client->dev, "Silicon version number read"
961                                 " failed: %d\n", jtag_ver);
962                 return -EIO;
963         }
964
965         ep_ver = i2c_smbus_read_byte_data(client, TPS80031_EPROM_REV);
966         if (ep_ver < 0) {
967                 dev_err(&client->dev, "Silicon eeprom version read"
968                                 " failed: %d\n", ep_ver);
969                 return -EIO;
970         }
971
972         dev_info(&client->dev, "Jtag version 0x%02x and Eeprom version 0x%02x\n",
973                                                 jtag_ver, ep_ver);
974
975         tps80031 = kzalloc(sizeof(struct tps80031), GFP_KERNEL);
976         if (tps80031 == NULL)
977                 return -ENOMEM;
978
979         tps80031->dev = &client->dev;
980         i2c_set_clientdata(client, tps80031);
981         tps80031->chip_info = id->driver_data;
982
983         /* Set up slaves */
984         tps80031->tps_clients[SLAVE_ID0].addr = I2C_ID0_ADDR;
985         tps80031->tps_clients[SLAVE_ID1].addr = I2C_ID1_ADDR;
986         tps80031->tps_clients[SLAVE_ID2].addr = I2C_ID2_ADDR;
987         tps80031->tps_clients[SLAVE_ID3].addr = I2C_ID3_ADDR;
988         for (i = 0; i < TPS_NUM_SLAVES; i++) {
989                 tps = &tps80031->tps_clients[i];
990                 if (tps->addr == client->addr)
991                         tps->client = client;
992                 else
993                         tps->client = i2c_new_dummy(client->adapter,
994                                                 tps->addr);
995                 if (!tps->client) {
996                         dev_err(&client->dev, "can't attach client %d\n", i);
997                         ret = -ENOMEM;
998                         goto fail;
999                 }
1000                 i2c_set_clientdata(tps->client, tps80031);
1001                 mutex_init(&tps->lock);
1002         }
1003
1004         if (client->irq) {
1005                 ret = tps80031_irq_init(tps80031, client->irq,
1006                                         pdata->irq_base);
1007                 if (ret) {
1008                         dev_err(&client->dev, "IRQ init failed: %d\n", ret);
1009                         goto fail;
1010                 }
1011         }
1012
1013         ret = tps80031_add_subdevs(tps80031, pdata);
1014         if (ret) {
1015                 dev_err(&client->dev, "add devices failed: %d\n", ret);
1016                 goto fail;
1017         }
1018
1019         tps80031_gpio_init(tps80031, pdata);
1020
1021         tps80031_clk32k_init(tps80031, pdata);
1022
1023         tps80031_debuginit(tps80031);
1024
1025         tps80031_dev = tps80031;
1026
1027         return 0;
1028
1029 fail:
1030         tps80031_i2c_remove(client);
1031         return ret;
1032 }
1033
1034 #ifdef CONFIG_PM
1035 static int tps80031_i2c_suspend(struct i2c_client *client, pm_message_t state)
1036 {
1037         if (client->irq)
1038                 disable_irq(client->irq);
1039         return 0;
1040 }
1041
1042 static int tps80031_i2c_resume(struct i2c_client *client)
1043 {
1044         if (client->irq)
1045                 enable_irq(client->irq);
1046         return 0;
1047 }
1048 #endif
1049
1050
1051 static const struct i2c_device_id tps80031_id_table[] = {
1052         { "tps80031", TPS80031 },
1053         { "tps80032", TPS80032 },
1054 };
1055 MODULE_DEVICE_TABLE(i2c, tps80031_id_table);
1056
1057 static struct i2c_driver tps80031_driver = {
1058         .driver = {
1059                 .name   = "tps80031",
1060                 .owner  = THIS_MODULE,
1061         },
1062         .probe          = tps80031_i2c_probe,
1063         .remove         = __devexit_p(tps80031_i2c_remove),
1064 #ifdef CONFIG_PM
1065         .suspend        = tps80031_i2c_suspend,
1066         .resume         = tps80031_i2c_resume,
1067 #endif
1068         .id_table       = tps80031_id_table,
1069 };
1070
1071 static int __init tps80031_init(void)
1072 {
1073         return i2c_add_driver(&tps80031_driver);
1074 }
1075 subsys_initcall(tps80031_init);
1076
1077 static void __exit tps80031_exit(void)
1078 {
1079         i2c_del_driver(&tps80031_driver);
1080 }
1081 module_exit(tps80031_exit);
1082
1083 MODULE_DESCRIPTION("TPS80031 core driver");
1084 MODULE_LICENSE("GPL");