Revert "Merge commit 'main-jb-2012.08.03-B4' into t114-0806"
[linux-2.6.git] / drivers / mfd / tps80031.c
1 /*
2  * driver/mfd/tps80031.c
3  *
4  * Core driver for TI TPS80031
5  *
6  * Copyright (C) 2011 NVIDIA Corporation
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, write to the Free Software Foundation, Inc.,
20  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
21  *
22  */
23
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/mutex.h>
29 #include <linux/slab.h>
30 #include <linux/gpio.h>
31 #include <linux/i2c.h>
32 #include <linux/pm.h>
33 #include <linux/regmap.h>
34
35 #include <linux/mfd/core.h>
36 #include <linux/mfd/tps80031.h>
37
38 /* interrupt related registers */
39 #define TPS80031_INT_STS_A              0xD0
40 #define TPS80031_INT_STS_B              0xD1
41 #define TPS80031_INT_STS_C              0xD2
42 #define TPS80031_INT_MSK_LINE_A         0xD3
43 #define TPS80031_INT_MSK_LINE_B         0xD4
44 #define TPS80031_INT_MSK_LINE_C         0xD5
45 #define TPS80031_INT_MSK_STS_A          0xD6
46 #define TPS80031_INT_MSK_STS_B          0xD7
47 #define TPS80031_INT_MSK_STS_C          0xD8
48
49 #define TPS80031_CONTROLLER_STAT1               0xE3
50 #define CONTROLLER_STAT1_BAT_TEMP               0
51 #define CONTROLLER_STAT1_BAT_REMOVED            1
52 #define CONTROLLER_STAT1_VBUS_DET               2
53 #define CONTROLLER_STAT1_VAC_DET                3
54 #define CONTROLLER_STAT1_FAULT_WDG              4
55 #define CONTROLLER_STAT1_LINCH_GATED            6
56
57 #define TPS80031_CONTROLLER_INT_MASK            0xE0
58 #define CONTROLLER_INT_MASK_MVAC_DET            0
59 #define CONTROLLER_INT_MASK_MVBUS_DET           1
60 #define CONTROLLER_INT_MASK_MBAT_TEMP           2
61 #define CONTROLLER_INT_MASK_MFAULT_WDG          3
62 #define CONTROLLER_INT_MASK_MBAT_REMOVED        4
63 #define CONTROLLER_INT_MASK_MLINCH_GATED        5
64
65 #define CHARGE_CONTROL_SUB_INT_MASK             0x3F
66
67 /* Version number related register */
68 #define TPS80031_JTAGVERNUM             0x87
69 /* Epprom version */
70 #define TPS80031_EPROM_REV              0xDF
71
72 /* External control register */
73 #define REGEN1_BASE_ADD         0xAE
74 #define REGEN2_BASE_ADD         0xB1
75 #define SYSEN_BASE_ADD          0xB4
76
77 /* device control registers */
78 #define TPS80031_PHOENIX_DEV_ON 0x25
79 #define DEVOFF  1
80
81 #define CLK32KAO_BASE_ADD       0xBA
82 #define CLK32KG_BASE_ADD        0xBD
83 #define CLK32KAUDIO_BASE_ADD    0xC0
84
85 #define EXT_CONTROL_CFG_TRANS 0
86 #define EXT_CONTROL_CFG_STATE 1
87
88 #define STATE_OFF       0x00
89 #define STATE_ON        0x01
90 #define STATE_MASK      0x03
91
92 #define TRANS_SLEEP_OFF         0x00
93 #define TRANS_SLEEP_ON          0x04
94 #define TRANS_SLEEP_MASK        0x0C
95
96 #define TPS_NUM_SLAVES  4
97 #define EXT_PWR_REQ (PWR_REQ_INPUT_PREQ1 | PWR_REQ_INPUT_PREQ2 | \
98                 PWR_REQ_INPUT_PREQ3)
99 #define TPS80031_PREQ1_RES_ASS_A        0xD7
100 #define TPS80031_PREQ2_RES_ASS_A        0xDA
101 #define TPS80031_PREQ3_RES_ASS_A        0xDD
102 #define TPS80031_PHOENIX_MSK_TRANSITION 0x20
103
104 #define TPS80031_CFG_INPUT_PUPD1 0xF0
105 #define TPS80031_CFG_INPUT_PUPD2 0xF1
106 #define TPS80031_CFG_INPUT_PUPD3 0xF2
107 #define TPS80031_CFG_INPUT_PUPD4 0xF3
108
109 #define TPS80031_BBSPOR_CFG     0xE6
110 #define TPS80031_BBSPOR_CHG_EN  0x8
111
112 /* Valid Address ranges */
113 #define TPS80031_ID0_PMIC_SLAVE_SMPS_DVS        0x55 ... 0x5C
114
115 #define TPS80031_ID1_RTC                        0x00 ... 0x16
116 #define TPS80031_ID1_MEMORY                     0x17 ... 0x1E
117 #define TPS80031_ID1_PMC_MASTER                 0x1F ... 0x2D
118 #define TPS80031_ID1_PMC_SLAVE_MISC             0x31 ... 0x34
119 #define TPS80031_ID1_PMC_SLAVE_SMPS             0x40 ... 0x68
120 #define TPS80031_ID1_PMC_SLAVE_LDO              0x80 ... 0xA7
121 #define TPS80031_ID1_PMC_SLAVE_REOSURCES        0XAD ... 0xD0
122 #define TPS80031_ID1_PMC_PREQ_ASSIGN            0XD7 ... 0xDF
123 #define TPS80031_ID1_PMC_MISC                   0xE2 ... 0xEF
124 #define TPS80031_ID1_PMC_PU_PD_HZ               0xF0 ... 0xF6
125 #define TPS80031_ID1_PMC_BACKUP                 0xFA
126
127 #define TPS80031_ID2_USB                        0x00 ... 0x1A
128 #define TPS80031_ID2_GPADC_CONTROL              0x2E ... 0x36
129 #define TPS80031_ID2_GPADC_RESULTS              0x37 ... 0x3C
130 #define TPS80031_ID2_AUXILLIARIES               0x90 ... 0x9C
131 #define TPS80031_ID2_CUSTOM                     0xA0 ... 0xB9
132 #define TPS80031_ID2_PWM                        0xBA ... 0xBE
133 #define TPS80031_ID2_FUEL_GAUSE                 0xC0 ... 0xCB
134 #define TPS80031_ID2_INTERFACE_INTERRUPTS       0xD0 ... 0xD8
135 #define TPS80031_ID2_CHARGER                    0xE0 ... 0xF5
136
137 #define TPS80031_ID3_TEST_LDO                   0x00 ... 0x09
138 #define TPS80031_ID3_TEST_SMPS                  0x10 ... 0x2B
139 #define TPS80031_ID3_TEST_POWER                 0x30 ... 0x36
140 #define TPS80031_ID3_TEST_CHARGER               0x40 ... 0x48
141 #define TPS80031_ID3_TEST_AUXILIIARIES          0x50 ... 0xB1
142
143 #define TPS80031_ID3_DIEID                      0xC0 ... 0xC8
144 #define TPS80031_ID3_TRIM_PHOENIX               0xCC ... 0xEA
145 #define TPS80031_ID3_TRIM_CUSTOM                0xEC ... 0xED
146
147 #define TPS80031_MAX_REGISTER   0x100
148
149 struct tps80031_pupd_data {
150         u8      reg;
151         u8      pullup_bit;
152         u8      pulldown_bit;
153 };
154
155 static u8 pmc_ext_control_base[] = {
156         REGEN1_BASE_ADD,
157         REGEN2_BASE_ADD,
158         SYSEN_BASE_ADD,
159 };
160
161 static u8 pmc_clk32k_control_base[] = {
162         CLK32KAO_BASE_ADD,
163         CLK32KG_BASE_ADD,
164         CLK32KAUDIO_BASE_ADD,
165 };
166 struct tps80031_irq_data {
167         u8      mask_reg;
168         u8      mask_mask;
169         u8      is_sec_int;
170         u8      parent_int;
171         u8      mask_sec_int_reg;
172         u8      int_mask_bit;
173         u8      int_sec_sts_reg;
174         u8      int_sts_bit;
175 };
176
177 #define TPS80031_IRQ(_reg, _mask)       \
178         {                                                       \
179                 .mask_reg = (TPS80031_INT_MSK_LINE_##_reg) -    \
180                                 TPS80031_INT_MSK_LINE_A,        \
181                 .mask_mask = (_mask),                           \
182         }
183
184 #define TPS80031_IRQ_SEC(_reg, _mask, _pint, _sint_mask_bit, _sint_sts_bit) \
185         {                                                               \
186                 .mask_reg = (TPS80031_INT_MSK_LINE_##_reg) -            \
187                                 TPS80031_INT_MSK_LINE_A,                \
188                 .mask_mask = (_mask),                                   \
189                 .is_sec_int = true,                                     \
190                 .parent_int = TPS80031_INT_##_pint,                     \
191                 .mask_sec_int_reg = TPS80031_CONTROLLER_INT_MASK,       \
192                 .int_mask_bit = CONTROLLER_INT_MASK_##_sint_mask_bit,   \
193                 .int_sec_sts_reg = TPS80031_CONTROLLER_STAT1,           \
194                 .int_sts_bit = CONTROLLER_STAT1_##_sint_sts_bit         \
195         }
196
197 static const struct tps80031_irq_data tps80031_irqs[] = {
198
199         [TPS80031_INT_PWRON]            = TPS80031_IRQ(A, 0),
200         [TPS80031_INT_RPWRON]           = TPS80031_IRQ(A, 1),
201         [TPS80031_INT_SYS_VLOW]         = TPS80031_IRQ(A, 2),
202         [TPS80031_INT_RTC_ALARM]        = TPS80031_IRQ(A, 3),
203         [TPS80031_INT_RTC_PERIOD]       = TPS80031_IRQ(A, 4),
204         [TPS80031_INT_HOT_DIE]          = TPS80031_IRQ(A, 5),
205         [TPS80031_INT_VXX_SHORT]        = TPS80031_IRQ(A, 6),
206         [TPS80031_INT_SPDURATION]       = TPS80031_IRQ(A, 7),
207         [TPS80031_INT_WATCHDOG]         = TPS80031_IRQ(B, 0),
208         [TPS80031_INT_BAT]              = TPS80031_IRQ(B, 1),
209         [TPS80031_INT_SIM]              = TPS80031_IRQ(B, 2),
210         [TPS80031_INT_MMC]              = TPS80031_IRQ(B, 3),
211         [TPS80031_INT_RES]              = TPS80031_IRQ(B, 4),
212         [TPS80031_INT_GPADC_RT]         = TPS80031_IRQ(B, 5),
213         [TPS80031_INT_GPADC_SW2_EOC]    = TPS80031_IRQ(B, 6),
214         [TPS80031_INT_CC_AUTOCAL]       = TPS80031_IRQ(B, 7),
215         [TPS80031_INT_ID_WKUP]          = TPS80031_IRQ(C, 0),
216         [TPS80031_INT_VBUSS_WKUP]       = TPS80031_IRQ(C, 1),
217         [TPS80031_INT_ID]               = TPS80031_IRQ(C, 2),
218         [TPS80031_INT_VBUS]             = TPS80031_IRQ(C, 3),
219         [TPS80031_INT_CHRG_CTRL]        = TPS80031_IRQ(C, 4),
220         [TPS80031_INT_EXT_CHRG]         = TPS80031_IRQ(C, 5),
221         [TPS80031_INT_INT_CHRG]         = TPS80031_IRQ(C, 6),
222         [TPS80031_INT_RES2]             = TPS80031_IRQ(C, 7),
223         [TPS80031_INT_BAT_TEMP_OVRANGE] = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
224                                                 MBAT_TEMP,      BAT_TEMP),
225         [TPS80031_INT_BAT_REMOVED]      = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
226                                                 MBAT_REMOVED,   BAT_REMOVED),
227         [TPS80031_INT_VBUS_DET]         = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
228                                                 MVBUS_DET,      VBUS_DET),
229         [TPS80031_INT_VAC_DET]          = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
230                                                 MVAC_DET,       VAC_DET),
231         [TPS80031_INT_FAULT_WDG]        = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
232                                                 MFAULT_WDG,     FAULT_WDG),
233         [TPS80031_INT_LINCH_GATED]      = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
234                                                 MLINCH_GATED,   LINCH_GATED),
235 };
236
237 #define PUPD_DATA(_reg, _pulldown_bit, _pullup_bit)     \
238         {                                               \
239                 .reg = TPS80031_CFG_INPUT_PUPD##_reg,   \
240                 .pulldown_bit = _pulldown_bit,          \
241                 .pullup_bit = _pullup_bit,              \
242         }
243
244 static const struct tps80031_pupd_data tps80031_pupds[] = {
245         [TPS80031_PREQ1]                = PUPD_DATA(1, 1 << 0,  1 << 1  ),
246         [TPS80031_PREQ2A]               = PUPD_DATA(1, 1 << 2,  1 << 3  ),
247         [TPS80031_PREQ2B]               = PUPD_DATA(1, 1 << 4,  1 << 5  ),
248         [TPS80031_PREQ2C]               = PUPD_DATA(1, 1 << 6,  1 << 7  ),
249         [TPS80031_PREQ3]                = PUPD_DATA(2, 1 << 0,  1 << 1  ),
250         [TPS80031_NRES_WARM]            = PUPD_DATA(2, 0,       1 << 2  ),
251         [TPS80031_PWM_FORCE]            = PUPD_DATA(2, 1 << 5,  0       ),
252         [TPS80031_CHRG_EXT_CHRG_STATZ]  = PUPD_DATA(2, 0,       1 << 6  ),
253         [TPS80031_SIM]                  = PUPD_DATA(3, 1 << 0,  1 << 1  ),
254         [TPS80031_MMC]                  = PUPD_DATA(3, 1 << 2,  1 << 3  ),
255         [TPS80031_GPADC_START]          = PUPD_DATA(3, 1 << 4,  0       ),
256         [TPS80031_DVSI2C_SCL]           = PUPD_DATA(4, 0,       1 << 0  ),
257         [TPS80031_DVSI2C_SDA]           = PUPD_DATA(4, 0,       1 << 1  ),
258         [TPS80031_CTLI2C_SCL]           = PUPD_DATA(4, 0,       1 << 2  ),
259         [TPS80031_CTLI2C_SDA]           = PUPD_DATA(4, 0,       1 << 3  ),
260 };
261
262 static const int controller_stat1_irq_nr[] = {
263         TPS80031_INT_BAT_TEMP_OVRANGE,
264         TPS80031_INT_BAT_REMOVED,
265         TPS80031_INT_VBUS_DET,
266         TPS80031_INT_VAC_DET,
267         TPS80031_INT_FAULT_WDG,
268         0,
269         TPS80031_INT_LINCH_GATED,
270         0
271 };
272
273 /* Structure for TPS80031 Slaves */
274 struct tps80031_client {
275         struct i2c_client *client;
276         struct mutex lock;
277         u8 addr;
278 };
279
280 struct tps80031 {
281         struct device           *dev;
282         unsigned long           chip_info;
283         int                     es_version;
284
285         struct gpio_chip        gpio;
286         struct irq_chip         irq_chip;
287         struct mutex            irq_lock;
288         int                     irq_base;
289         u32                     irq_en;
290         u8                      mask_cache[3];
291         u8                      mask_reg[3];
292         u8                      cont_int_mask_reg;
293         u8                      cont_int_mask_cache;
294         u8                      cont_int_en;
295         u8                      prev_cont_stat1;
296         struct tps80031_client  tps_clients[TPS_NUM_SLAVES];
297         struct regmap           *regmap[TPS_NUM_SLAVES];
298 };
299
300 int tps80031_write(struct device *dev, int sid, int reg, uint8_t val)
301 {
302         struct tps80031 *tps80031 = dev_get_drvdata(dev);
303
304         return regmap_write(tps80031->regmap[sid], reg, val);
305 }
306 EXPORT_SYMBOL_GPL(tps80031_write);
307
308 int tps80031_writes(struct device *dev, int sid, int reg, int len, uint8_t *val)
309 {
310         struct tps80031 *tps80031 = dev_get_drvdata(dev);
311
312         return regmap_bulk_write(tps80031->regmap[sid], reg, val, len);
313 }
314 EXPORT_SYMBOL_GPL(tps80031_writes);
315
316 int tps80031_read(struct device *dev, int sid, int reg, uint8_t *val)
317 {
318         struct tps80031 *tps80031 = dev_get_drvdata(dev);
319         unsigned int ival;
320         int ret;
321
322         ret = regmap_read(tps80031->regmap[sid], reg, &ival);
323         if (ret < 0) {
324                 dev_err(dev, "failed reading from reg 0x%02x\n", reg);
325                 return ret;
326         }
327
328         *val = ival;
329         return ret;
330 }
331 EXPORT_SYMBOL_GPL(tps80031_read);
332
333 int tps80031_reads(struct device *dev, int sid, int reg, int len, uint8_t *val)
334 {
335         struct tps80031 *tps80031 = dev_get_drvdata(dev);
336
337         return regmap_bulk_read(tps80031->regmap[sid], reg, val, len);
338 }
339 EXPORT_SYMBOL_GPL(tps80031_reads);
340
341 int tps80031_set_bits(struct device *dev, int sid, int reg, uint8_t bit_mask)
342 {
343         struct tps80031 *tps80031 = dev_get_drvdata(dev);
344
345         return regmap_update_bits(tps80031->regmap[sid], reg,
346                                 bit_mask, bit_mask);
347 }
348 EXPORT_SYMBOL_GPL(tps80031_set_bits);
349
350 int tps80031_clr_bits(struct device *dev, int sid, int reg, uint8_t bit_mask)
351 {
352         struct tps80031 *tps80031 = dev_get_drvdata(dev);
353
354         return regmap_update_bits(tps80031->regmap[sid], reg, bit_mask, 0);
355 }
356 EXPORT_SYMBOL_GPL(tps80031_clr_bits);
357
358 int tps80031_update(struct device *dev, int sid, int reg, uint8_t val,
359                 uint8_t mask)
360 {
361         struct tps80031 *tps80031 = dev_get_drvdata(dev);
362
363         return regmap_update_bits(tps80031->regmap[sid], reg, mask, val);
364 }
365 EXPORT_SYMBOL_GPL(tps80031_update);
366
367 int tps80031_force_update(struct device *dev, int sid, int reg, uint8_t val,
368                           uint8_t mask)
369 {
370         struct tps80031 *tps80031 = dev_get_drvdata(dev);
371         struct tps80031_client *tps = &tps80031->tps_clients[sid];
372         uint8_t reg_val;
373         int ret = 0;
374
375         mutex_lock(&tps->lock);
376
377         ret = tps80031_read(dev, sid, reg, &reg_val);
378         if (ret)
379                 goto out;
380
381         reg_val = (reg_val & ~mask) | (val & mask);
382         ret = tps80031_write(dev, sid, reg, reg_val);
383
384 out:
385         mutex_unlock(&tps->lock);
386         return ret;
387 }
388 EXPORT_SYMBOL_GPL(tps80031_force_update);
389
390 int tps80031_ext_power_req_config(struct device *dev,
391                 unsigned long ext_ctrl_flag, int preq_bit,
392                 int state_reg_add, int trans_reg_add)
393 {
394         u8 res_ass_reg = 0;
395         int preq_mask_bit = 0;
396         int ret;
397
398         if (!(ext_ctrl_flag & EXT_PWR_REQ))
399                 return 0;
400
401         if (ext_ctrl_flag & PWR_REQ_INPUT_PREQ1) {
402                 res_ass_reg = TPS80031_PREQ1_RES_ASS_A + (preq_bit >> 3);
403                 preq_mask_bit = 5;
404         } else if (ext_ctrl_flag & PWR_REQ_INPUT_PREQ2) {
405                 res_ass_reg = TPS80031_PREQ2_RES_ASS_A + (preq_bit >> 3);
406                 preq_mask_bit = 6;
407         } else if (ext_ctrl_flag & PWR_REQ_INPUT_PREQ3) {
408                 res_ass_reg = TPS80031_PREQ3_RES_ASS_A + (preq_bit >> 3);
409                 preq_mask_bit = 7;
410         }
411
412         /* Configure REQ_ASS registers */
413         ret = tps80031_set_bits(dev, SLAVE_ID1, res_ass_reg,
414                                         BIT(preq_bit & 0x7));
415         if (ret < 0) {
416                 dev_err(dev, "%s() Not able to set bit %d of "
417                         "reg %d error %d\n",
418                         __func__, preq_bit, res_ass_reg, ret);
419                 return ret;
420         }
421
422         /* Unmask the PREQ */
423         ret = tps80031_clr_bits(dev, SLAVE_ID1,
424                         TPS80031_PHOENIX_MSK_TRANSITION, BIT(preq_mask_bit));
425         if (ret < 0) {
426                 dev_err(dev, "%s() Not able to clear bit %d of "
427                         "reg %d error %d\n",
428                          __func__, preq_mask_bit,
429                         TPS80031_PHOENIX_MSK_TRANSITION, ret);
430                 return ret;
431         }
432
433         /* Switch regulator control to resource now */
434         if (ext_ctrl_flag & (PWR_REQ_INPUT_PREQ2 | PWR_REQ_INPUT_PREQ3)) {
435                 ret = tps80031_update(dev, SLAVE_ID1, state_reg_add, 0x0,
436                                                 STATE_MASK);
437                 if (ret < 0)
438                         dev_err(dev, "%s() Error in writing the STATE "
439                                 "register %d error %d\n", __func__,
440                                 state_reg_add, ret);
441         } else {
442                 ret = tps80031_update(dev, SLAVE_ID1, trans_reg_add,
443                                 TRANS_SLEEP_OFF, TRANS_SLEEP_MASK);
444                 if (ret < 0)
445                         dev_err(dev, "%s() Error in writing the TRANS "
446                                 "register %d error %d\n", __func__,
447                                 trans_reg_add, ret);
448         }
449         return ret;
450 }
451 EXPORT_SYMBOL_GPL(tps80031_ext_power_req_config);
452
453 unsigned long tps80031_get_chip_info(struct device *dev)
454 {
455         struct tps80031 *tps80031 = dev_get_drvdata(dev);
456         return tps80031->chip_info;
457 }
458 EXPORT_SYMBOL_GPL(tps80031_get_chip_info);
459
460 int tps80031_get_pmu_version(struct device *dev)
461 {
462         struct tps80031 *tps80031 = dev_get_drvdata(dev);
463         return tps80031->es_version;
464 }
465 EXPORT_SYMBOL_GPL(tps80031_get_pmu_version);
466
467 static struct tps80031 *tps80031_dev;
468 static void tps80031_power_off(void)
469 {
470         struct tps80031_client *tps = &tps80031_dev->tps_clients[SLAVE_ID1];
471
472         if (!tps->client)
473                 return;
474         dev_info(&tps->client->dev, "switching off PMU\n");
475         tps80031_write(&tps->client->dev, SLAVE_ID1,
476                                 TPS80031_PHOENIX_DEV_ON, DEVOFF);
477 }
478
479 static void tps80031_pupd_init(struct tps80031 *tps80031,
480                                struct tps80031_platform_data *pdata)
481 {
482         struct tps80031_pupd_init_data *pupd_init_data = pdata->pupd_init_data;
483         int data_size = pdata->pupd_init_data_size;
484         int i;
485
486         for (i = 0; i < data_size; ++i) {
487                 struct tps80031_pupd_init_data *pupd_init = &pupd_init_data[i];
488                 const struct tps80031_pupd_data *pupd =
489                         &tps80031_pupds[pupd_init->input_pin];
490                 u8 update_value = 0;
491                 u8 update_mask = pupd->pulldown_bit | pupd->pullup_bit;
492
493                 if (pupd_init->setting == TPS80031_PUPD_PULLDOWN)
494                         update_value = pupd->pulldown_bit;
495                 else if (pupd_init->setting == TPS80031_PUPD_PULLUP)
496                         update_value = pupd->pullup_bit;
497
498                 tps80031_update(tps80031->dev, SLAVE_ID1, pupd->reg,
499                                 update_value, update_mask);
500         }
501 }
502
503 static void tps80031_backup_battery_charger_control(struct tps80031 *tps80031,
504                                                     int enable)
505 {
506         if (enable)
507                 tps80031_update(tps80031->dev, SLAVE_ID1, TPS80031_BBSPOR_CFG,
508                                 TPS80031_BBSPOR_CHG_EN, TPS80031_BBSPOR_CHG_EN);
509         else
510                 tps80031_update(tps80031->dev, SLAVE_ID1, TPS80031_BBSPOR_CFG,
511                                 0, TPS80031_BBSPOR_CHG_EN);
512 }
513
514 static void tps80031_init_ext_control(struct tps80031 *tps80031,
515                         struct tps80031_platform_data *pdata) {
516         int ret;
517         int i;
518
519         /* Clear all external control for this rail */
520         for (i = 0; i < 9; ++i) {
521                 ret = tps80031_write(tps80031->dev, SLAVE_ID1,
522                                 TPS80031_PREQ1_RES_ASS_A + i, 0);
523                 if (ret < 0)
524                         dev_err(tps80031->dev, "%s() Error in clearing "
525                                 "register %02x\n", __func__,
526                                 TPS80031_PREQ1_RES_ASS_A + i);
527         }
528
529         /* Mask the PREQ */
530         ret = tps80031_set_bits(tps80031->dev, SLAVE_ID1,
531                         TPS80031_PHOENIX_MSK_TRANSITION, 0x7 << 5);
532         if (ret < 0)
533                 dev_err(tps80031->dev, "%s() Not able to mask register "
534                         "0x%02x\n", __func__, TPS80031_PHOENIX_MSK_TRANSITION);
535 }
536
537 static int tps80031_gpio_get(struct gpio_chip *gc, unsigned offset)
538 {
539         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
540         struct tps80031_client *tps = &tps80031->tps_clients[SLAVE_ID1];
541         uint8_t state;
542         uint8_t trans;
543         int ret;
544
545         ret = tps80031_read(&tps->client->dev, SLAVE_ID1,
546                         pmc_ext_control_base[offset] +
547                                 EXT_CONTROL_CFG_STATE, &state);
548         if (ret)
549                 return ret;
550
551         if (state != 0) {
552                 ret = tps80031_read(&tps->client->dev, SLAVE_ID1,
553                                 pmc_ext_control_base[offset] +
554                                         EXT_CONTROL_CFG_TRANS, &trans);
555                 if (ret)
556                         return ret;
557                 return trans & 0x1;
558         }
559         return 0;
560 }
561
562 static void tps80031_gpio_set(struct gpio_chip *gc, unsigned offset,
563                         int value)
564 {
565         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
566
567         tps80031_update(tps80031->dev, SLAVE_ID1,
568                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_TRANS,
569                         value, 0x1);
570 }
571
572 static int tps80031_gpio_input(struct gpio_chip *gc, unsigned offset)
573 {
574         return -EIO;
575 }
576
577 static int tps80031_gpio_output(struct gpio_chip *gc, unsigned offset,
578                                 int value)
579 {
580         tps80031_gpio_set(gc, offset, value);
581         return 0;
582 }
583
584 static int tps80031_gpio_enable(struct gpio_chip *gc, unsigned offset)
585 {
586         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
587         int ret;
588
589         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
590                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_STATE,
591                                                 STATE_ON, STATE_MASK);
592         if (ret)
593                 return ret;
594
595         return tps80031_write(tps80031->dev, SLAVE_ID1,
596                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_TRANS, 0x0);
597 }
598
599 static void tps80031_gpio_disable(struct gpio_chip *gc, unsigned offset)
600 {
601         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
602         tps80031_update(tps80031->dev, SLAVE_ID1,
603                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_STATE,
604                                                 STATE_OFF, STATE_MASK);
605 }
606
607 static void tps80031_gpio_init(struct tps80031 *tps80031,
608                         struct tps80031_platform_data *pdata)
609 {
610         int ret;
611         int gpio_base = pdata->gpio_base;
612         struct tps80031_client *tps = &tps80031->tps_clients[SLAVE_ID1];
613         struct tps80031_gpio_init_data *gpio_init_data = pdata->gpio_init_data;
614         int data_size = pdata->gpio_init_data_size;
615         static int preq_bit_pos[TPS80031_GPIO_NR] = {16, 17, 18};
616         int base_add;
617         int i;
618
619         if (gpio_base <= 0)
620                 return;
621
622         /* Configure the external request mode */
623         for (i = 0; i < data_size; ++i) {
624                 struct tps80031_gpio_init_data *gpio_pd = &gpio_init_data[i];
625                 base_add = pmc_ext_control_base[gpio_pd->gpio_nr];
626
627                 if (gpio_pd->ext_ctrl_flag & EXT_PWR_REQ) {
628                         ret = tps80031_ext_power_req_config(tps80031->dev,
629                                 gpio_pd->ext_ctrl_flag,
630                                 preq_bit_pos[gpio_pd->gpio_nr],
631                                 base_add + EXT_CONTROL_CFG_STATE,
632                                 base_add + EXT_CONTROL_CFG_TRANS);
633                         if (ret < 0)
634                                 dev_warn(tps80031->dev, "Ext pwrreq GPIO "
635                                         "sleep control fails\n");
636                 }
637
638                 if (gpio_pd->ext_ctrl_flag & PWR_OFF_ON_SLEEP) {
639                         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
640                                 base_add + EXT_CONTROL_CFG_TRANS, 0x0, 0xC);
641                         if (ret < 0)
642                                 dev_warn(tps80031->dev, "GPIO OFF on sleep "
643                                         "control fails\n");
644                 }
645
646                 if (gpio_pd->ext_ctrl_flag & PWR_ON_ON_SLEEP) {
647                         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
648                                 base_add + EXT_CONTROL_CFG_TRANS, 0x4, 0xC);
649                         if (ret < 0)
650                                 dev_warn(tps80031->dev, "GPIO ON on sleep "
651                                         "control fails\n");
652                 }
653         }
654
655         tps80031->gpio.owner            = THIS_MODULE;
656         tps80031->gpio.label            = tps->client->name;
657         tps80031->gpio.dev              = tps80031->dev;
658         tps80031->gpio.base             = gpio_base;
659         tps80031->gpio.ngpio            = TPS80031_GPIO_NR;
660         tps80031->gpio.can_sleep        = 1;
661
662         tps80031->gpio.request          = tps80031_gpio_enable;
663         tps80031->gpio.free             = tps80031_gpio_disable;
664         tps80031->gpio.direction_input  = tps80031_gpio_input;
665         tps80031->gpio.direction_output = tps80031_gpio_output;
666         tps80031->gpio.set              = tps80031_gpio_set;
667         tps80031->gpio.get              = tps80031_gpio_get;
668
669         ret = gpiochip_add(&tps80031->gpio);
670         if (ret)
671                 dev_warn(tps80031->dev, "GPIO registration failed: %d\n", ret);
672 }
673
674 static int __remove_subdev(struct device *dev, void *unused)
675 {
676         platform_device_unregister(to_platform_device(dev));
677         return 0;
678 }
679
680 static int tps80031_remove_subdevs(struct tps80031 *tps80031)
681 {
682         return device_for_each_child(tps80031->dev, NULL, __remove_subdev);
683 }
684
685 static void tps80031_irq_lock(struct irq_data *data)
686 {
687         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
688
689         mutex_lock(&tps80031->irq_lock);
690 }
691
692 static void tps80031_irq_enable(struct irq_data *data)
693 {
694         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
695         unsigned int __irq = data->irq - tps80031->irq_base;
696         const struct tps80031_irq_data *irq_data = &tps80031_irqs[__irq];
697
698         if (irq_data->is_sec_int) {
699                 tps80031->cont_int_mask_reg &= ~(1 << irq_data->int_mask_bit);
700                 tps80031->cont_int_en |= (1 << irq_data->int_mask_bit);
701                 tps80031->mask_reg[irq_data->mask_reg] &= ~(1 << irq_data->mask_mask);
702                 tps80031->irq_en |= (1 << irq_data->parent_int);
703         } else
704                 tps80031->mask_reg[irq_data->mask_reg] &= ~(1 << irq_data->mask_mask);
705
706         tps80031->irq_en |= (1 << __irq);
707 }
708
709 static void tps80031_irq_disable(struct irq_data *data)
710 {
711         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
712
713         unsigned int __irq = data->irq - tps80031->irq_base;
714         const struct tps80031_irq_data *irq_data = &tps80031_irqs[__irq];
715
716         if (irq_data->is_sec_int) {
717                 tps80031->cont_int_mask_reg |= (1 << irq_data->int_mask_bit);
718                 tps80031->cont_int_en &= ~(1 << irq_data->int_mask_bit);
719                 if (!tps80031->cont_int_en) {
720                         tps80031->mask_reg[irq_data->mask_reg] |=
721                                                 (1 << irq_data->mask_mask);
722                         tps80031->irq_en &= ~(1 << irq_data->parent_int);
723                 }
724                 tps80031->irq_en &= ~(1 << __irq);
725         } else
726                 tps80031->mask_reg[irq_data->mask_reg] |= (1 << irq_data->mask_mask);
727
728         tps80031->irq_en &= ~(1 << __irq);
729 }
730
731 static void tps80031_irq_sync_unlock(struct irq_data *data)
732 {
733         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
734         int i;
735
736         for (i = 0; i < ARRAY_SIZE(tps80031->mask_reg); i++) {
737                 if (tps80031->mask_reg[i] != tps80031->mask_cache[i]) {
738                         if (!WARN_ON(tps80031_write(tps80031->dev, SLAVE_ID2,
739                                                 TPS80031_INT_MSK_LINE_A + i,
740                                                 tps80031->mask_reg[i])))
741                                 if (!WARN_ON(tps80031_write(tps80031->dev,
742                                                 SLAVE_ID2,
743                                                 TPS80031_INT_MSK_STS_A + i,
744                                                 tps80031->mask_reg[i])))
745                                         tps80031->mask_cache[i] =
746                                                         tps80031->mask_reg[i];
747                 }
748         }
749
750         if (tps80031->cont_int_mask_reg != tps80031->cont_int_mask_cache) {
751                 if (!WARN_ON(tps80031_write(tps80031->dev, SLAVE_ID2,
752                                 TPS80031_CONTROLLER_INT_MASK,
753                                 tps80031->cont_int_mask_reg)))
754                         tps80031->cont_int_mask_cache =
755                                                 tps80031->cont_int_mask_reg;
756         }
757
758         mutex_unlock(&tps80031->irq_lock);
759 }
760
761 static irqreturn_t tps80031_charge_control_irq(int irq, void *data)
762 {
763         struct tps80031 *tps80031 = data;
764         int ret = 0;
765         int i;
766         u8 cont_sts;
767         u8 org_sts;
768         if (irq != (tps80031->irq_base + TPS80031_INT_CHRG_CTRL)) {
769                 dev_err(tps80031->dev, "%s() Got the illegal interrupt %d\n",
770                                         __func__, irq);
771                 return IRQ_NONE;
772         }
773
774         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
775                         TPS80031_CONTROLLER_STAT1, &org_sts);
776         if (ret < 0) {
777                 dev_err(tps80031->dev, "%s(): failed to read controller state1 "
778                                 "status %d\n", __func__, ret);
779                 return IRQ_NONE;
780         }
781
782         /* Get change from last interrupt and mask for interested interrupt
783          * for charge control interrupt */
784         cont_sts = org_sts ^ tps80031->prev_cont_stat1;
785         tps80031->prev_cont_stat1 = org_sts;
786         /* Clear watchdog timer state */
787         tps80031->prev_cont_stat1 &= ~(1 << 4);
788         cont_sts &= 0x5F;
789
790         for (i = 0; i < 8; ++i) {
791                 if (!controller_stat1_irq_nr[i])
792                         continue;
793
794                 if ((cont_sts & BIT(i)) &&
795                         (tps80031->irq_en & BIT(controller_stat1_irq_nr[i])))
796                         handle_nested_irq(tps80031->irq_base +
797                                                 controller_stat1_irq_nr[i]);
798                 cont_sts &= ~BIT(i);
799         }
800         return IRQ_HANDLED;
801 }
802
803 static irqreturn_t tps80031_irq(int irq, void *data)
804 {
805         struct tps80031 *tps80031 = data;
806         int ret = 0;
807         u32 acks;
808         int i;
809         uint8_t tmp[3];
810
811         ret = tps80031_reads(tps80031->dev, SLAVE_ID2,
812                              TPS80031_INT_STS_A, 3, tmp);
813         if (ret < 0) {
814                 dev_err(tps80031->dev, "failed to read interrupt status\n");
815                 return IRQ_NONE;
816         }
817         acks = (tmp[2] << 16) | (tmp[1] << 8) | tmp[0];
818
819         if (acks) {
820                 /*
821                  * Hardware behavior: hardware have the shadow register for
822                  * interrupt status register which is updated if interrupt
823                  * comes just after the interrupt status read. This shadow
824                  * register gets written to main status register and cleared
825                  * if any byte write happens in any of status register like
826                  * STS_A, STS_B or STS_C.
827                  * Hence here to clear the original interrupt status and
828                  * updating the STS register with the shadow register, it is
829                  * require to write only one byte in any of STS register.
830                  * Having multiple register write can cause the STS register
831                  * to clear without handling those interrupt and can cause
832                  * interrupt miss.
833                  */
834                 ret = tps80031_write(tps80031->dev, SLAVE_ID2,
835                                       TPS80031_INT_STS_A, 0);
836                 if (ret < 0) {
837                         dev_err(tps80031->dev, "failed to write "
838                                                 "interrupt status\n");
839                         return IRQ_NONE;
840                 }
841
842                 while (acks) {
843                         i = __ffs(acks);
844                         if (tps80031->irq_en & (1 << i))
845                                 handle_nested_irq(tps80031->irq_base + i);
846                         acks &= ~(1 << i);
847                 }
848         }
849
850         return IRQ_HANDLED;
851 }
852
853 static int __devinit tps80031_irq_init(struct tps80031 *tps80031, int irq,
854                                 int irq_base)
855 {
856         int i, ret;
857
858         if (!irq_base) {
859                 dev_warn(tps80031->dev, "No interrupt support on IRQ base\n");
860                 return -EINVAL;
861         }
862
863         mutex_init(&tps80031->irq_lock);
864
865         for (i = 0; i < 3; i++) {
866                 tps80031->mask_reg[i] = 0xFF;
867                 tps80031->mask_cache[i] = tps80031->mask_reg[i];
868                 tps80031_write(tps80031->dev, SLAVE_ID2,
869                                         TPS80031_INT_MSK_LINE_A + i,
870                                         tps80031->mask_cache[i]);
871                 tps80031_write(tps80031->dev, SLAVE_ID2,
872                                         TPS80031_INT_MSK_STS_A + i, 0xFF);
873                 tps80031_write(tps80031->dev, SLAVE_ID2,
874                                         TPS80031_INT_STS_A + i, 0xFF);
875         }
876
877         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
878                                 TPS80031_CONTROLLER_INT_MASK,
879                                 &tps80031->cont_int_mask_reg);
880         if (ret < 0) {
881                 dev_err(tps80031->dev, "Error in reading the controller_mask "
882                                         "register %d\n", ret);
883                 return ret;
884         }
885
886         tps80031->cont_int_mask_reg |= CHARGE_CONTROL_SUB_INT_MASK;
887         tps80031->cont_int_mask_cache = tps80031->cont_int_mask_reg;
888         tps80031->cont_int_en = 0;
889         ret = tps80031_write(tps80031->dev, SLAVE_ID2,
890                                 TPS80031_CONTROLLER_INT_MASK,
891                                 tps80031->cont_int_mask_reg);
892         if (ret < 0) {
893                 dev_err(tps80031->dev, "Error in writing the controller_mask "
894                                         "register %d\n", ret);
895                 return ret;
896         }
897
898         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
899                         TPS80031_CONTROLLER_STAT1, &tps80031->prev_cont_stat1);
900         if (ret < 0) {
901                 dev_err(tps80031->dev, "%s(): failed to read controller state1 "
902                                 "status %d\n", __func__, ret);
903                 return ret;
904         }
905
906         /* Clear watch dog interrupt status in status */
907         tps80031->prev_cont_stat1 &= ~(1 << 4);
908
909         tps80031->irq_base = irq_base;
910
911         tps80031->irq_chip.name = "tps80031";
912         tps80031->irq_chip.irq_enable = tps80031_irq_enable;
913         tps80031->irq_chip.irq_disable = tps80031_irq_disable;
914         tps80031->irq_chip.irq_bus_lock = tps80031_irq_lock;
915         tps80031->irq_chip.irq_bus_sync_unlock = tps80031_irq_sync_unlock;
916
917         for (i = 0; i < TPS80031_INT_NR; i++) {
918                 int __irq = i + tps80031->irq_base;
919                 irq_set_chip_data(__irq, tps80031);
920                 irq_set_chip_and_handler(__irq, &tps80031->irq_chip,
921                                          handle_simple_irq);
922                 irq_set_nested_thread(__irq, 1);
923 #ifdef CONFIG_ARM
924                 set_irq_flags(__irq, IRQF_VALID);
925 #endif
926         }
927
928         ret = request_threaded_irq(irq, NULL, tps80031_irq, IRQF_ONESHOT,
929                                 "tps80031", tps80031);
930         /* register the isr for the secondary interrupt */
931         if (!ret)
932                 ret = request_threaded_irq(irq_base + TPS80031_INT_CHRG_CTRL,
933                                 NULL, tps80031_charge_control_irq,
934                                 IRQF_ONESHOT, "80031_chg_ctl", tps80031);
935         if (!ret) {
936
937                 device_init_wakeup(tps80031->dev, 1);
938                 enable_irq_wake(irq);
939         }
940
941         return ret;
942 }
943
944 static void tps80031_clk32k_enable(struct tps80031 *tps80031, int base_add)
945 {
946         int ret;
947         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
948                         base_add + EXT_CONTROL_CFG_STATE, STATE_ON, STATE_MASK);
949         if (!ret)
950                 ret = tps80031_update(tps80031->dev, SLAVE_ID1,
951                                 base_add + EXT_CONTROL_CFG_TRANS,
952                                 STATE_ON, STATE_MASK);
953         if (ret < 0)
954                 dev_err(tps80031->dev, "Error in updating clock register\n");
955 }
956
957 static void tps80031_clk32k_init(struct tps80031 *tps80031,
958                         struct tps80031_platform_data *pdata)
959 {
960         int ret;
961         struct tps80031_clk32k_init_data *clk32_idata = pdata->clk32k_init_data;
962         int data_size = pdata->clk32k_init_data_size;
963         static int clk32k_preq_bit_pos[TPS80031_CLOCK32K_NR] = {-1, 20, 19};
964         int base_add;
965         int i;
966
967         if (!clk32_idata || !data_size)
968                 return;
969
970         /* Configure the external request mode */
971         for (i = 0; i < data_size; ++i) {
972                 struct tps80031_clk32k_init_data *clk32_pd =  &clk32_idata[i];
973                 base_add = pmc_clk32k_control_base[clk32_pd->clk32k_nr];
974                 if (clk32_pd->enable)
975                         tps80031_clk32k_enable(tps80031, base_add);
976
977                 if ((clk32_pd->ext_ctrl_flag & EXT_PWR_REQ) &&
978                          (clk32k_preq_bit_pos[clk32_pd->clk32k_nr] != -1)) {
979                         ret = tps80031_ext_power_req_config(tps80031->dev,
980                                 clk32_pd->ext_ctrl_flag,
981                                 clk32k_preq_bit_pos[clk32_pd->clk32k_nr],
982                                 base_add + EXT_CONTROL_CFG_STATE,
983                                 base_add + EXT_CONTROL_CFG_TRANS);
984                         if (ret < 0)
985                                 dev_warn(tps80031->dev, "Clk32 ext control "
986                                         "fails\n");
987                 }
988
989                 if (clk32_pd->ext_ctrl_flag & PWR_OFF_ON_SLEEP) {
990                         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
991                                 base_add + EXT_CONTROL_CFG_TRANS, 0x0, 0xC);
992                         if (ret < 0)
993                                 dev_warn(tps80031->dev, "clk OFF on sleep "
994                                         "control fails\n");
995                 }
996
997                 if (clk32_pd->ext_ctrl_flag & PWR_ON_ON_SLEEP) {
998                         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
999                                 base_add + EXT_CONTROL_CFG_TRANS, 0x4, 0xC);
1000                         if (ret < 0)
1001                                 dev_warn(tps80031->dev, "clk ON sleep "
1002                                         "control fails\n");
1003                 }
1004         }
1005 }
1006
1007 static int __devinit tps80031_add_subdevs(struct tps80031 *tps80031,
1008                                           struct tps80031_platform_data *pdata)
1009 {
1010         struct tps80031_subdev_info *subdev;
1011         struct platform_device *pdev;
1012         int i, ret = 0;
1013
1014         for (i = 0; i < pdata->num_subdevs; i++) {
1015                 subdev = &pdata->subdevs[i];
1016
1017                 pdev = platform_device_alloc(subdev->name, subdev->id);
1018
1019                 pdev->dev.parent = tps80031->dev;
1020                 pdev->dev.platform_data = subdev->platform_data;
1021
1022                 ret = platform_device_add(pdev);
1023                 if (ret)
1024                         goto failed;
1025         }
1026         return 0;
1027
1028 failed:
1029         tps80031_remove_subdevs(tps80031);
1030         return ret;
1031 }
1032
1033 #ifdef CONFIG_DEBUG_FS
1034 #include <linux/debugfs.h>
1035 #include <linux/seq_file.h>
1036 static void print_regs(const char *header, struct seq_file *s,
1037                 int sid, int start_offset, int end_offset)
1038 {
1039         struct tps80031 *tps80031 = s->private;
1040         struct tps80031_client *tps = &tps80031->tps_clients[sid];
1041         uint8_t reg_val;
1042         int i;
1043         int ret;
1044
1045         seq_printf(s, "%s\n", header);
1046         for (i = start_offset; i <= end_offset; ++i) {
1047                 ret = tps80031_read(&tps->client->dev, sid, i, &reg_val);
1048                 if (ret >= 0)
1049                         seq_printf(s, "Addr = 0x%02x Reg 0x%02x Value 0x%02x\n",
1050                                                 tps->client->addr, i, reg_val);
1051         }
1052         seq_printf(s, "------------------\n");
1053 }
1054
1055 static int dbg_tps_show(struct seq_file *s, void *unused)
1056 {
1057         seq_printf(s, "TPS80031 Registers\n");
1058         seq_printf(s, "------------------\n");
1059         print_regs("VIO Regs",       s, SLAVE_ID1, 0x47, 0x49);
1060         print_regs("VIO Regs",       s, SLAVE_ID0, 0x49, 0x4A);
1061         print_regs("SMPS1 Regs",     s, SLAVE_ID1, 0x53, 0x54);
1062         print_regs("SMPS1 Regs",     s, SLAVE_ID0, 0x55, 0x56);
1063         print_regs("SMPS1 Regs",     s, SLAVE_ID1, 0x57, 0x57);
1064         print_regs("SMPS2 Regs",     s, SLAVE_ID1, 0x59, 0x5B);
1065         print_regs("SMPS2 Regs",     s, SLAVE_ID0, 0x5B, 0x5C);
1066         print_regs("SMPS2 Regs",     s, SLAVE_ID1, 0x5C, 0x5D);
1067         print_regs("SMPS3 Regs",     s, SLAVE_ID1, 0x65, 0x68);
1068         print_regs("SMPS4 Regs",     s, SLAVE_ID1, 0x41, 0x44);
1069         print_regs("VANA Regs",      s, SLAVE_ID1, 0x81, 0x83);
1070         print_regs("VRTC Regs",      s, SLAVE_ID1, 0xC3, 0xC4);
1071         print_regs("LDO1 Regs",      s, SLAVE_ID1, 0x9D, 0x9F);
1072         print_regs("LDO2 Regs",      s, SLAVE_ID1, 0x85, 0x87);
1073         print_regs("LDO3 Regs",      s, SLAVE_ID1, 0x8D, 0x8F);
1074         print_regs("LDO4 Regs",      s, SLAVE_ID1, 0x89, 0x8B);
1075         print_regs("LDO5 Regs",      s, SLAVE_ID1, 0x99, 0x9B);
1076         print_regs("LDO6 Regs",      s, SLAVE_ID1, 0x91, 0x93);
1077         print_regs("LDO7 Regs",      s, SLAVE_ID1, 0xA5, 0xA7);
1078         print_regs("LDOUSB Regs",    s, SLAVE_ID1, 0xA1, 0xA3);
1079         print_regs("LDOLN Regs",     s, SLAVE_ID1, 0x95, 0x97);
1080         print_regs("REGEN1 Regs",    s, SLAVE_ID1, 0xAE, 0xAF);
1081         print_regs("REGEN2 Regs",    s, SLAVE_ID1, 0xB1, 0xB2);
1082         print_regs("SYSEN Regs",     s, SLAVE_ID1, 0xB4, 0xB5);
1083         print_regs("CLK32KAO Regs",  s, SLAVE_ID1, 0xBA, 0xBB);
1084         print_regs("CLK32KG Regs",   s, SLAVE_ID1, 0xBD, 0xBE);
1085         print_regs("CLK32KAUD Regs", s, SLAVE_ID1, 0xC0, 0xC1);
1086         print_regs("INT Regs",       s, SLAVE_ID2, 0xD0, 0xD8);
1087         print_regs("PREQ Regs",      s, SLAVE_ID1, 0xD7, 0xDF);
1088         print_regs("MASK_PH Regs",   s, SLAVE_ID1, 0x20, 0x21);
1089         print_regs("PMC MISC Regs",  s, SLAVE_ID1, 0xE0, 0xEF);
1090         print_regs("CONT_STATE",     s, SLAVE_ID2, 0xE0, 0xE4);
1091         print_regs("VERNUM Regs",    s, SLAVE_ID3, 0x87, 0x87);
1092         print_regs("EEPROM Regs",    s, SLAVE_ID3, 0xDF, 0xDF);
1093         print_regs("CHARGE Regs",    s, SLAVE_ID2, 0xDA, 0xF5);
1094         return 0;
1095 }
1096
1097 static int dbg_tps_open(struct inode *inode, struct file *file)
1098 {
1099         return single_open(file, dbg_tps_show, inode->i_private);
1100 }
1101
1102 static const struct file_operations debug_fops = {
1103         .open           = dbg_tps_open,
1104         .read           = seq_read,
1105         .llseek         = seq_lseek,
1106         .release        = single_release,
1107 };
1108
1109 static void __init tps80031_debuginit(struct tps80031 *tps)
1110 {
1111         (void)debugfs_create_file("tps80031", S_IRUGO, NULL,
1112                         tps, &debug_fops);
1113 }
1114 #else
1115 static void __init tps80031_debuginit(struct tps80031 *tpsi)
1116 {
1117         return;
1118 }
1119 #endif
1120
1121 static bool rd_wr_reg_id0(struct device *dev, unsigned int reg)
1122 {
1123         switch(reg) {
1124         case TPS80031_ID0_PMIC_SLAVE_SMPS_DVS:
1125                 return true;
1126         default:
1127                 pr_err("non-existing reg %s() %d reg %x\n", __func__, __LINE__, reg);
1128                 BUG();
1129                 return false;
1130         }
1131 }
1132
1133 static bool rd_wr_reg_id1(struct device *dev, unsigned int reg)
1134 {
1135         switch(reg) {
1136         case TPS80031_ID1_RTC:
1137         case TPS80031_ID1_MEMORY:
1138         case TPS80031_ID1_PMC_MASTER:
1139         case TPS80031_ID1_PMC_SLAVE_SMPS:
1140         case TPS80031_ID1_PMC_SLAVE_MISC:
1141         case TPS80031_ID1_PMC_SLAVE_LDO:
1142         case TPS80031_ID1_PMC_SLAVE_REOSURCES:
1143         case TPS80031_ID1_PMC_PREQ_ASSIGN:
1144         case TPS80031_ID1_PMC_MISC:
1145         case TPS80031_ID1_PMC_PU_PD_HZ:
1146         case TPS80031_ID1_PMC_BACKUP:
1147                 return true;
1148         default:
1149                 pr_err("non-existing reg %s() %d reg %x\n", __func__, __LINE__, reg);
1150                 BUG();
1151                 return false;
1152         }
1153 }
1154
1155 static bool rd_wr_reg_id2(struct device *dev, unsigned int reg)
1156 {
1157         switch(reg) {
1158         case TPS80031_ID2_USB:
1159         case TPS80031_ID2_GPADC_CONTROL:
1160         case TPS80031_ID2_GPADC_RESULTS:
1161         case TPS80031_ID2_AUXILLIARIES:
1162         case TPS80031_ID2_CUSTOM:
1163         case TPS80031_ID2_PWM:
1164         case TPS80031_ID2_FUEL_GAUSE:
1165         case TPS80031_ID2_INTERFACE_INTERRUPTS:
1166         case TPS80031_ID2_CHARGER:
1167                 return true;
1168         default:
1169                 pr_err("non-existing reg %s() %d reg %x\n", __func__, __LINE__, reg);
1170                 BUG();
1171                 return false;
1172         }
1173 }
1174 static bool rd_wr_reg_id3(struct device *dev, unsigned int reg)
1175 {
1176         switch(reg) {
1177         case TPS80031_ID3_TEST_LDO:
1178         case TPS80031_ID3_TEST_SMPS:
1179         case TPS80031_ID3_TEST_POWER:
1180         case TPS80031_ID3_TEST_CHARGER:
1181         case TPS80031_ID3_TEST_AUXILIIARIES:
1182         case TPS80031_ID3_DIEID:
1183         case TPS80031_ID3_TRIM_PHOENIX:
1184         case TPS80031_ID3_TRIM_CUSTOM:
1185                 return true;
1186         default:
1187                 pr_err("non-existing reg %s() %d reg %x\n", __func__, __LINE__, reg);
1188                 BUG();
1189                 return false;
1190         }
1191 }
1192
1193 static const struct regmap_config tps80031_regmap_configs[] = {
1194         {
1195                 .reg_bits = 8,
1196                 .val_bits = 8,
1197                 .writeable_reg = rd_wr_reg_id0,
1198                 .readable_reg = rd_wr_reg_id0,
1199                 .max_register = TPS80031_MAX_REGISTER - 1,
1200         },
1201         {
1202                 .reg_bits = 8,
1203                 .val_bits = 8,
1204                 .writeable_reg = rd_wr_reg_id1,
1205                 .readable_reg = rd_wr_reg_id1,
1206                 .max_register = TPS80031_MAX_REGISTER - 1,
1207         },
1208         {
1209                 .reg_bits = 8,
1210                 .val_bits = 8,
1211                 .writeable_reg = rd_wr_reg_id2,
1212                 .readable_reg = rd_wr_reg_id2,
1213                 .max_register = TPS80031_MAX_REGISTER - 1,
1214         },
1215         {
1216                 .reg_bits = 8,
1217                 .val_bits = 8,
1218                 .writeable_reg = rd_wr_reg_id3,
1219                 .readable_reg = rd_wr_reg_id3,
1220                 .max_register = TPS80031_MAX_REGISTER - 1,
1221         },
1222 };
1223
1224 static int __devexit tps80031_i2c_remove(struct i2c_client *client)
1225 {
1226         struct tps80031 *tps80031 = i2c_get_clientdata(client);
1227         int i;
1228
1229         if (client->irq)
1230                 free_irq(client->irq, tps80031);
1231
1232         if (tps80031->gpio.owner != NULL)
1233                 if (gpiochip_remove(&tps80031->gpio) < 0)
1234                         dev_err(&client->dev, "Error in removing the gpio driver\n");
1235
1236         for (i = 0; i < TPS_NUM_SLAVES; i++) {
1237                 struct tps80031_client *tps = &tps80031->tps_clients[i];
1238                 if (tps->client && tps->client != client)
1239                         i2c_unregister_device(tps->client);
1240                 tps80031->tps_clients[i].client = NULL;
1241                 mutex_destroy(&tps->lock);
1242         }
1243
1244         return 0;
1245 }
1246
1247 static int __devinit tps80031_i2c_probe(struct i2c_client *client,
1248                                         const struct i2c_device_id *id)
1249 {
1250         struct tps80031_platform_data *pdata = client->dev.platform_data;
1251         struct tps80031 *tps80031;
1252         struct tps80031_client *tps;
1253         int ret;
1254         int jtag_ver;
1255         int ep_ver;
1256         int i;
1257
1258         if (!pdata) {
1259                 dev_err(&client->dev, "tps80031 requires platform data\n");
1260                 return -ENOTSUPP;
1261         }
1262
1263         jtag_ver = i2c_smbus_read_byte_data(client, TPS80031_JTAGVERNUM);
1264         if (jtag_ver < 0) {
1265                 dev_err(&client->dev, "Silicon version number read"
1266                                 " failed: %d\n", jtag_ver);
1267                 return -EIO;
1268         }
1269
1270         ep_ver = i2c_smbus_read_byte_data(client, TPS80031_EPROM_REV);
1271         if (ep_ver < 0) {
1272                 dev_err(&client->dev, "Silicon eeprom version read"
1273                                 " failed: %d\n", ep_ver);
1274                 return -EIO;
1275         }
1276
1277         dev_info(&client->dev, "Jtag version 0x%02x and Eeprom version 0x%02x\n",
1278                                                 jtag_ver, ep_ver);
1279
1280         tps80031 = devm_kzalloc(&client->dev, sizeof(*tps80031), GFP_KERNEL);
1281         if (!tps80031) {
1282                 dev_err(&client->dev, "Memory alloc for tps80031 failed\n");
1283                 return -ENOMEM;
1284         }
1285
1286         tps80031->es_version = jtag_ver;
1287         tps80031->dev = &client->dev;
1288         i2c_set_clientdata(client, tps80031);
1289         tps80031->chip_info = id->driver_data;
1290
1291         /* Set up slaves */
1292         tps80031->tps_clients[SLAVE_ID0].addr = I2C_ID0_ADDR;
1293         tps80031->tps_clients[SLAVE_ID1].addr = I2C_ID1_ADDR;
1294         tps80031->tps_clients[SLAVE_ID2].addr = I2C_ID2_ADDR;
1295         tps80031->tps_clients[SLAVE_ID3].addr = I2C_ID3_ADDR;
1296         for (i = 0; i < TPS_NUM_SLAVES; i++) {
1297                 tps = &tps80031->tps_clients[i];
1298                 if (tps->addr == client->addr)
1299                         tps->client = client;
1300                 else
1301                         tps->client = i2c_new_dummy(client->adapter,
1302                                                 tps->addr);
1303                 if (!tps->client) {
1304                         dev_err(&client->dev, "can't attach client %d\n", i);
1305                         ret = -ENOMEM;
1306                         goto fail;
1307                 }
1308                 i2c_set_clientdata(tps->client, tps80031);
1309                 mutex_init(&tps->lock);
1310
1311                 tps80031->regmap[i] = devm_regmap_init_i2c(tps->client,
1312                                         &tps80031_regmap_configs[i]);
1313                 if (IS_ERR(tps80031->regmap[i])) {
1314                         ret = PTR_ERR(tps80031->regmap[i]);
1315                         dev_err(&client->dev,
1316                                 "regmap %d init failed, err %d\n", i, ret);
1317                         goto fail;
1318                 }
1319         }
1320
1321         if (client->irq) {
1322                 ret = tps80031_irq_init(tps80031, client->irq,
1323                                         pdata->irq_base);
1324                 if (ret) {
1325                         dev_err(&client->dev, "IRQ init failed: %d\n", ret);
1326                         goto fail;
1327                 }
1328         }
1329
1330         tps80031_pupd_init(tps80031, pdata);
1331
1332         tps80031_init_ext_control(tps80031, pdata);
1333
1334         ret = tps80031_add_subdevs(tps80031, pdata);
1335         if (ret) {
1336                 dev_err(&client->dev, "add devices failed: %d\n", ret);
1337                 goto fail;
1338         }
1339
1340         tps80031_gpio_init(tps80031, pdata);
1341
1342         tps80031_clk32k_init(tps80031, pdata);
1343
1344         tps80031_debuginit(tps80031);
1345
1346         tps80031_backup_battery_charger_control(tps80031, 1);
1347
1348         if (pdata->use_power_off && !pm_power_off)
1349                 pm_power_off = tps80031_power_off;
1350
1351         tps80031_dev = tps80031;
1352
1353         return 0;
1354
1355 fail:
1356         tps80031_i2c_remove(client);
1357         return ret;
1358 }
1359
1360 #ifdef CONFIG_PM
1361 static int tps80031_i2c_suspend(struct device *dev)
1362 {
1363         struct i2c_client *client = to_i2c_client(dev);
1364         struct tps80031 *tps80031 = i2c_get_clientdata(client);
1365         if (client->irq)
1366                 disable_irq(client->irq);
1367         tps80031_backup_battery_charger_control(tps80031, 0);
1368         return 0;
1369 }
1370
1371 static int tps80031_i2c_resume(struct device *dev)
1372 {
1373         struct i2c_client *client = to_i2c_client(dev);
1374         struct tps80031 *tps80031 = i2c_get_clientdata(client);
1375         tps80031_backup_battery_charger_control(tps80031, 1);
1376         if (client->irq)
1377                 enable_irq(client->irq);
1378         return 0;
1379 }
1380 static const struct dev_pm_ops tps80031_dev_pm_ops = {
1381         .suspend        = tps80031_i2c_suspend,
1382         .resume         = tps80031_i2c_resume,
1383 };
1384 #define TPS80031_DEV_PM (&tps80031_dev_pm_ops)
1385 #else
1386 #define TPS80031_DEV_PM NULL
1387 #endif
1388
1389
1390 static const struct i2c_device_id tps80031_id_table[] = {
1391         { "tps80031", TPS80031 },
1392         { "tps80032", TPS80032 },
1393 };
1394 MODULE_DEVICE_TABLE(i2c, tps80031_id_table);
1395
1396 static struct i2c_driver tps80031_driver = {
1397         .driver = {
1398                 .name   = "tps80031",
1399                 .owner  = THIS_MODULE,
1400                 .pm     = TPS80031_DEV_PM,
1401         },
1402         .probe          = tps80031_i2c_probe,
1403         .remove         = __devexit_p(tps80031_i2c_remove),
1404         .id_table       = tps80031_id_table,
1405 };
1406
1407 static int __init tps80031_init(void)
1408 {
1409         return i2c_add_driver(&tps80031_driver);
1410 }
1411 subsys_initcall(tps80031_init);
1412
1413 static void __exit tps80031_exit(void)
1414 {
1415         i2c_del_driver(&tps80031_driver);
1416 }
1417 module_exit(tps80031_exit);
1418
1419 MODULE_DESCRIPTION("TPS80031 core driver");
1420 MODULE_LICENSE("GPL");