config: tegra3: enable /dev mount with ACL
[linux-2.6.git] / drivers / mfd / tps80031.c
1 /*
2  * driver/mfd/tps80031.c
3  *
4  * Core driver for TI TPS80031
5  *
6  * Copyright (C) 2011 NVIDIA Corporation
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, write to the Free Software Foundation, Inc.,
20  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
21  *
22  */
23
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/mutex.h>
29 #include <linux/slab.h>
30 #include <linux/gpio.h>
31 #include <linux/i2c.h>
32 #include <linux/pm.h>
33 #include <linux/regmap.h>
34
35 #include <linux/mfd/core.h>
36 #include <linux/mfd/tps80031.h>
37
38 /* interrupt related registers */
39 #define TPS80031_INT_STS_A              0xD0
40 #define TPS80031_INT_STS_B              0xD1
41 #define TPS80031_INT_STS_C              0xD2
42 #define TPS80031_INT_MSK_LINE_A         0xD3
43 #define TPS80031_INT_MSK_LINE_B         0xD4
44 #define TPS80031_INT_MSK_LINE_C         0xD5
45 #define TPS80031_INT_MSK_STS_A          0xD6
46 #define TPS80031_INT_MSK_STS_B          0xD7
47 #define TPS80031_INT_MSK_STS_C          0xD8
48
49 #define TPS80031_CONTROLLER_STAT1               0xE3
50 #define CONTROLLER_STAT1_BAT_TEMP               0
51 #define CONTROLLER_STAT1_BAT_REMOVED            1
52 #define CONTROLLER_STAT1_VBUS_DET               2
53 #define CONTROLLER_STAT1_VAC_DET                3
54 #define CONTROLLER_STAT1_FAULT_WDG              4
55 #define CONTROLLER_STAT1_LINCH_GATED            6
56
57 #define TPS80031_CONTROLLER_INT_MASK            0xE0
58 #define CONTROLLER_INT_MASK_MVAC_DET            0
59 #define CONTROLLER_INT_MASK_MVBUS_DET           1
60 #define CONTROLLER_INT_MASK_MBAT_TEMP           2
61 #define CONTROLLER_INT_MASK_MFAULT_WDG          3
62 #define CONTROLLER_INT_MASK_MBAT_REMOVED        4
63 #define CONTROLLER_INT_MASK_MLINCH_GATED        5
64
65 #define CHARGE_CONTROL_SUB_INT_MASK             0x3F
66
67 /* Version number related register */
68 #define TPS80031_JTAGVERNUM             0x87
69 /* Epprom version */
70 #define TPS80031_EPROM_REV              0xDF
71
72 /* External control register */
73 #define REGEN1_BASE_ADD         0xAE
74 #define REGEN2_BASE_ADD         0xB1
75 #define SYSEN_BASE_ADD          0xB4
76
77 /* device control registers */
78 #define TPS80031_PHOENIX_DEV_ON 0x25
79 #define DEVOFF  1
80
81 #define CLK32KAO_BASE_ADD       0xBA
82 #define CLK32KG_BASE_ADD        0xBD
83 #define CLK32KAUDIO_BASE_ADD    0xC0
84
85 #define EXT_CONTROL_CFG_TRANS 0
86 #define EXT_CONTROL_CFG_STATE 1
87
88 #define STATE_OFF       0x00
89 #define STATE_ON        0x01
90 #define STATE_MASK      0x03
91
92 #define TRANS_SLEEP_OFF         0x00
93 #define TRANS_SLEEP_ON          0x04
94 #define TRANS_SLEEP_MASK        0x0C
95
96 #define TPS_NUM_SLAVES  4
97 #define EXT_PWR_REQ (PWR_REQ_INPUT_PREQ1 | PWR_REQ_INPUT_PREQ2 | \
98                 PWR_REQ_INPUT_PREQ3)
99 #define TPS80031_PREQ1_RES_ASS_A        0xD7
100 #define TPS80031_PREQ2_RES_ASS_A        0xDA
101 #define TPS80031_PREQ3_RES_ASS_A        0xDD
102 #define TPS80031_PHOENIX_MSK_TRANSITION 0x20
103
104 #define TPS80031_CFG_INPUT_PUPD1 0xF0
105 #define TPS80031_CFG_INPUT_PUPD2 0xF1
106 #define TPS80031_CFG_INPUT_PUPD3 0xF2
107 #define TPS80031_CFG_INPUT_PUPD4 0xF3
108
109 #define TPS80031_BBSPOR_CFG     0xE6
110 #define TPS80031_BBSPOR_CHG_EN  0x8
111
112 /* Valid Address ranges */
113 #define TPS80031_ID0_PMIC_SLAVE_SMPS_DVS        0x55 ... 0x5C
114
115 #define TPS80031_ID1_RTC                        0x00 ... 0x16
116 #define TPS80031_ID1_MEMORY                     0x17 ... 0x1E
117 #define TPS80031_ID1_PMC_MASTER                 0x1F ... 0x2D
118 #define TPS80031_ID1_PMC_SLAVE_MISC             0x31 ... 0x34
119 #define TPS80031_ID1_PMC_SLAVE_SMPS             0x40 ... 0x68
120 #define TPS80031_ID1_PMC_SLAVE_LDO              0x80 ... 0xA7
121 #define TPS80031_ID1_PMC_SLAVE_REOSURCES        0XAD ... 0xD0
122 #define TPS80031_ID1_PMC_PREQ_ASSIGN            0XD7 ... 0xDF
123 #define TPS80031_ID1_PMC_MISC                   0xE2 ... 0xEF
124 #define TPS80031_ID1_PMC_PU_PD_HZ               0xF0 ... 0xF6
125 #define TPS80031_ID1_PMC_BACKUP                 0xFA
126
127 #define TPS80031_ID2_USB                        0x00 ... 0x1A
128 #define TPS80031_ID2_GPADC_CONTROL              0x2E ... 0x36
129 #define TPS80031_ID2_GPADC_RESULTS              0x37 ... 0x3C
130 #define TPS80031_ID2_AUXILLIARIES               0x90 ... 0x9C
131 #define TPS80031_ID2_CUSTOM                     0xA0 ... 0xB9
132 #define TPS80031_ID2_PWM                        0xBA ... 0xBE
133 #define TPS80031_ID2_FUEL_GAUSE                 0xC0 ... 0xCB
134 #define TPS80031_ID2_INTERFACE_INTERRUPTS       0xD0 ... 0xD8
135 #define TPS80031_ID2_CHARGER                    0xDA ... 0xF5
136
137 #define TPS80031_ID3_TEST_LDO                   0x00 ... 0x09
138 #define TPS80031_ID3_TEST_SMPS                  0x10 ... 0x2B
139 #define TPS80031_ID3_TEST_POWER                 0x30 ... 0x36
140 #define TPS80031_ID3_TEST_CHARGER               0x40 ... 0x48
141 #define TPS80031_ID3_TEST_AUXILIIARIES          0x50 ... 0xB1
142
143 #define TPS80031_ID3_DIEID                      0xC0 ... 0xC8
144 #define TPS80031_ID3_TRIM_PHOENIX               0xCC ... 0xEA
145 #define TPS80031_ID3_TRIM_CUSTOM                0xEC ... 0xED
146
147 #define TPS80031_MAX_REGISTER   0x100
148
149 struct tps80031_pupd_data {
150         u8      reg;
151         u8      pullup_bit;
152         u8      pulldown_bit;
153 };
154
155 static u8 pmc_ext_control_base[] = {
156         REGEN1_BASE_ADD,
157         REGEN2_BASE_ADD,
158         SYSEN_BASE_ADD,
159 };
160
161 static u8 pmc_clk32k_control_base[] = {
162         CLK32KAO_BASE_ADD,
163         CLK32KG_BASE_ADD,
164         CLK32KAUDIO_BASE_ADD,
165 };
166 struct tps80031_irq_data {
167         u8      mask_reg;
168         u8      mask_mask;
169         u8      is_sec_int;
170         u8      parent_int;
171         u8      mask_sec_int_reg;
172         u8      int_mask_bit;
173         u8      int_sec_sts_reg;
174         u8      int_sts_bit;
175 };
176
177 #define TPS80031_IRQ(_reg, _mask)       \
178         {                                                       \
179                 .mask_reg = (TPS80031_INT_MSK_LINE_##_reg) -    \
180                                 TPS80031_INT_MSK_LINE_A,        \
181                 .mask_mask = (_mask),                           \
182         }
183
184 #define TPS80031_IRQ_SEC(_reg, _mask, _pint, _sint_mask_bit, _sint_sts_bit) \
185         {                                                               \
186                 .mask_reg = (TPS80031_INT_MSK_LINE_##_reg) -            \
187                                 TPS80031_INT_MSK_LINE_A,                \
188                 .mask_mask = (_mask),                                   \
189                 .is_sec_int = true,                                     \
190                 .parent_int = TPS80031_INT_##_pint,                     \
191                 .mask_sec_int_reg = TPS80031_CONTROLLER_INT_MASK,       \
192                 .int_mask_bit = CONTROLLER_INT_MASK_##_sint_mask_bit,   \
193                 .int_sec_sts_reg = TPS80031_CONTROLLER_STAT1,           \
194                 .int_sts_bit = CONTROLLER_STAT1_##_sint_sts_bit         \
195         }
196
197 static const struct tps80031_irq_data tps80031_irqs[] = {
198
199         [TPS80031_INT_PWRON]            = TPS80031_IRQ(A, 0),
200         [TPS80031_INT_RPWRON]           = TPS80031_IRQ(A, 1),
201         [TPS80031_INT_SYS_VLOW]         = TPS80031_IRQ(A, 2),
202         [TPS80031_INT_RTC_ALARM]        = TPS80031_IRQ(A, 3),
203         [TPS80031_INT_RTC_PERIOD]       = TPS80031_IRQ(A, 4),
204         [TPS80031_INT_HOT_DIE]          = TPS80031_IRQ(A, 5),
205         [TPS80031_INT_VXX_SHORT]        = TPS80031_IRQ(A, 6),
206         [TPS80031_INT_SPDURATION]       = TPS80031_IRQ(A, 7),
207         [TPS80031_INT_WATCHDOG]         = TPS80031_IRQ(B, 0),
208         [TPS80031_INT_BAT]              = TPS80031_IRQ(B, 1),
209         [TPS80031_INT_SIM]              = TPS80031_IRQ(B, 2),
210         [TPS80031_INT_MMC]              = TPS80031_IRQ(B, 3),
211         [TPS80031_INT_RES]              = TPS80031_IRQ(B, 4),
212         [TPS80031_INT_GPADC_RT]         = TPS80031_IRQ(B, 5),
213         [TPS80031_INT_GPADC_SW2_EOC]    = TPS80031_IRQ(B, 6),
214         [TPS80031_INT_CC_AUTOCAL]       = TPS80031_IRQ(B, 7),
215         [TPS80031_INT_ID_WKUP]          = TPS80031_IRQ(C, 0),
216         [TPS80031_INT_VBUSS_WKUP]       = TPS80031_IRQ(C, 1),
217         [TPS80031_INT_ID]               = TPS80031_IRQ(C, 2),
218         [TPS80031_INT_VBUS]             = TPS80031_IRQ(C, 3),
219         [TPS80031_INT_CHRG_CTRL]        = TPS80031_IRQ(C, 4),
220         [TPS80031_INT_EXT_CHRG]         = TPS80031_IRQ(C, 5),
221         [TPS80031_INT_INT_CHRG]         = TPS80031_IRQ(C, 6),
222         [TPS80031_INT_RES2]             = TPS80031_IRQ(C, 7),
223         [TPS80031_INT_BAT_TEMP_OVRANGE] = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
224                                                 MBAT_TEMP,      BAT_TEMP),
225         [TPS80031_INT_BAT_REMOVED]      = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
226                                                 MBAT_REMOVED,   BAT_REMOVED),
227         [TPS80031_INT_VBUS_DET]         = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
228                                                 MVBUS_DET,      VBUS_DET),
229         [TPS80031_INT_VAC_DET]          = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
230                                                 MVAC_DET,       VAC_DET),
231         [TPS80031_INT_FAULT_WDG]        = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
232                                                 MFAULT_WDG,     FAULT_WDG),
233         [TPS80031_INT_LINCH_GATED]      = TPS80031_IRQ_SEC(C, 4, CHRG_CTRL,
234                                                 MLINCH_GATED,   LINCH_GATED),
235 };
236
237 #define PUPD_DATA(_reg, _pulldown_bit, _pullup_bit)     \
238         {                                               \
239                 .reg = TPS80031_CFG_INPUT_PUPD##_reg,   \
240                 .pulldown_bit = _pulldown_bit,          \
241                 .pullup_bit = _pullup_bit,              \
242         }
243
244 static const struct tps80031_pupd_data tps80031_pupds[] = {
245         [TPS80031_PREQ1]                = PUPD_DATA(1, 1 << 0,  1 << 1  ),
246         [TPS80031_PREQ2A]               = PUPD_DATA(1, 1 << 2,  1 << 3  ),
247         [TPS80031_PREQ2B]               = PUPD_DATA(1, 1 << 4,  1 << 5  ),
248         [TPS80031_PREQ2C]               = PUPD_DATA(1, 1 << 6,  1 << 7  ),
249         [TPS80031_PREQ3]                = PUPD_DATA(2, 1 << 0,  1 << 1  ),
250         [TPS80031_NRES_WARM]            = PUPD_DATA(2, 0,       1 << 2  ),
251         [TPS80031_PWM_FORCE]            = PUPD_DATA(2, 1 << 5,  0       ),
252         [TPS80031_CHRG_EXT_CHRG_STATZ]  = PUPD_DATA(2, 0,       1 << 6  ),
253         [TPS80031_SIM]                  = PUPD_DATA(3, 1 << 0,  1 << 1  ),
254         [TPS80031_MMC]                  = PUPD_DATA(3, 1 << 2,  1 << 3  ),
255         [TPS80031_GPADC_START]          = PUPD_DATA(3, 1 << 4,  0       ),
256         [TPS80031_DVSI2C_SCL]           = PUPD_DATA(4, 0,       1 << 0  ),
257         [TPS80031_DVSI2C_SDA]           = PUPD_DATA(4, 0,       1 << 1  ),
258         [TPS80031_CTLI2C_SCL]           = PUPD_DATA(4, 0,       1 << 2  ),
259         [TPS80031_CTLI2C_SDA]           = PUPD_DATA(4, 0,       1 << 3  ),
260 };
261
262 static const int controller_stat1_irq_nr[] = {
263         TPS80031_INT_BAT_TEMP_OVRANGE,
264         TPS80031_INT_BAT_REMOVED,
265         TPS80031_INT_VBUS_DET,
266         TPS80031_INT_VAC_DET,
267         TPS80031_INT_FAULT_WDG,
268         0,
269         TPS80031_INT_LINCH_GATED,
270         0
271 };
272
273 /* Structure for TPS80031 Slaves */
274 struct tps80031_client {
275         struct i2c_client *client;
276         struct mutex lock;
277         u8 addr;
278 };
279
280 struct tps80031 {
281         struct device           *dev;
282         unsigned long           chip_info;
283         int                     es_version;
284
285         struct gpio_chip        gpio;
286         struct irq_chip         irq_chip;
287         struct mutex            irq_lock;
288         int                     irq_base;
289         u32                     irq_en;
290         u8                      mask_cache[3];
291         u8                      mask_reg[3];
292         u8                      cont_int_mask_reg;
293         u8                      cont_int_mask_cache;
294         u8                      cont_int_en;
295         u8                      prev_cont_stat1;
296         struct tps80031_client  tps_clients[TPS_NUM_SLAVES];
297         struct regmap           *regmap[TPS_NUM_SLAVES];
298 };
299
300 /* TPS80031 sub mfd devices */
301 static struct mfd_cell tps80031_cell[] = {
302         {
303                 .name = "tps80031-regulators",
304         },
305         {
306                 .name = "tps80031-rtc",
307         },
308         {
309                 .name = "tps80031-gpadc",
310         },
311         {
312                 .name = "tps80031-battery-gauge",
313         },
314         {
315                 .name = "tps80031-charger",
316         },
317 };
318
319
320 int tps80031_write(struct device *dev, int sid, int reg, uint8_t val)
321 {
322         struct tps80031 *tps80031 = dev_get_drvdata(dev);
323
324         return regmap_write(tps80031->regmap[sid], reg, val);
325 }
326 EXPORT_SYMBOL_GPL(tps80031_write);
327
328 int tps80031_writes(struct device *dev, int sid, int reg, int len, uint8_t *val)
329 {
330         struct tps80031 *tps80031 = dev_get_drvdata(dev);
331
332         return regmap_bulk_write(tps80031->regmap[sid], reg, val, len);
333 }
334 EXPORT_SYMBOL_GPL(tps80031_writes);
335
336 int tps80031_read(struct device *dev, int sid, int reg, uint8_t *val)
337 {
338         struct tps80031 *tps80031 = dev_get_drvdata(dev);
339         unsigned int ival;
340         int ret;
341
342         ret = regmap_read(tps80031->regmap[sid], reg, &ival);
343         if (ret < 0) {
344                 dev_err(dev, "failed reading from reg 0x%02x\n", reg);
345                 return ret;
346         }
347
348         *val = ival;
349         return ret;
350 }
351 EXPORT_SYMBOL_GPL(tps80031_read);
352
353 int tps80031_reads(struct device *dev, int sid, int reg, int len, uint8_t *val)
354 {
355         struct tps80031 *tps80031 = dev_get_drvdata(dev);
356
357         return regmap_bulk_read(tps80031->regmap[sid], reg, val, len);
358 }
359 EXPORT_SYMBOL_GPL(tps80031_reads);
360
361 int tps80031_set_bits(struct device *dev, int sid, int reg, uint8_t bit_mask)
362 {
363         struct tps80031 *tps80031 = dev_get_drvdata(dev);
364
365         return regmap_update_bits(tps80031->regmap[sid], reg,
366                                 bit_mask, bit_mask);
367 }
368 EXPORT_SYMBOL_GPL(tps80031_set_bits);
369
370 int tps80031_clr_bits(struct device *dev, int sid, int reg, uint8_t bit_mask)
371 {
372         struct tps80031 *tps80031 = dev_get_drvdata(dev);
373
374         return regmap_update_bits(tps80031->regmap[sid], reg, bit_mask, 0);
375 }
376 EXPORT_SYMBOL_GPL(tps80031_clr_bits);
377
378 int tps80031_update(struct device *dev, int sid, int reg, uint8_t val,
379                 uint8_t mask)
380 {
381         struct tps80031 *tps80031 = dev_get_drvdata(dev);
382
383         return regmap_update_bits(tps80031->regmap[sid], reg, mask, val);
384 }
385 EXPORT_SYMBOL_GPL(tps80031_update);
386
387 int tps80031_force_update(struct device *dev, int sid, int reg, uint8_t val,
388                           uint8_t mask)
389 {
390         struct tps80031 *tps80031 = dev_get_drvdata(dev);
391         struct tps80031_client *tps = &tps80031->tps_clients[sid];
392         uint8_t reg_val;
393         int ret = 0;
394
395         mutex_lock(&tps->lock);
396
397         ret = tps80031_read(dev, sid, reg, &reg_val);
398         if (ret)
399                 goto out;
400
401         reg_val = (reg_val & ~mask) | (val & mask);
402         ret = tps80031_write(dev, sid, reg, reg_val);
403
404 out:
405         mutex_unlock(&tps->lock);
406         return ret;
407 }
408 EXPORT_SYMBOL_GPL(tps80031_force_update);
409
410 int tps80031_ext_power_req_config(struct device *dev,
411                 unsigned long ext_ctrl_flag, int preq_bit,
412                 int state_reg_add, int trans_reg_add)
413 {
414         u8 res_ass_reg = 0;
415         int preq_mask_bit = 0;
416         int ret;
417
418         if (!(ext_ctrl_flag & EXT_PWR_REQ))
419                 return 0;
420
421         if (ext_ctrl_flag & PWR_REQ_INPUT_PREQ1) {
422                 res_ass_reg = TPS80031_PREQ1_RES_ASS_A + (preq_bit >> 3);
423                 preq_mask_bit = 5;
424         } else if (ext_ctrl_flag & PWR_REQ_INPUT_PREQ2) {
425                 res_ass_reg = TPS80031_PREQ2_RES_ASS_A + (preq_bit >> 3);
426                 preq_mask_bit = 6;
427         } else if (ext_ctrl_flag & PWR_REQ_INPUT_PREQ3) {
428                 res_ass_reg = TPS80031_PREQ3_RES_ASS_A + (preq_bit >> 3);
429                 preq_mask_bit = 7;
430         }
431
432         /* Configure REQ_ASS registers */
433         ret = tps80031_set_bits(dev, SLAVE_ID1, res_ass_reg,
434                                         BIT(preq_bit & 0x7));
435         if (ret < 0) {
436                 dev_err(dev, "%s() Not able to set bit %d of "
437                         "reg %d error %d\n",
438                         __func__, preq_bit, res_ass_reg, ret);
439                 return ret;
440         }
441
442         /* Unmask the PREQ */
443         ret = tps80031_clr_bits(dev, SLAVE_ID1,
444                         TPS80031_PHOENIX_MSK_TRANSITION, BIT(preq_mask_bit));
445         if (ret < 0) {
446                 dev_err(dev, "%s() Not able to clear bit %d of "
447                         "reg %d error %d\n",
448                          __func__, preq_mask_bit,
449                         TPS80031_PHOENIX_MSK_TRANSITION, ret);
450                 return ret;
451         }
452
453         /* Switch regulator control to resource now */
454         if (ext_ctrl_flag & (PWR_REQ_INPUT_PREQ2 | PWR_REQ_INPUT_PREQ3)) {
455                 ret = tps80031_update(dev, SLAVE_ID1, state_reg_add, 0x0,
456                                                 STATE_MASK);
457                 if (ret < 0)
458                         dev_err(dev, "%s() Error in writing the STATE "
459                                 "register %d error %d\n", __func__,
460                                 state_reg_add, ret);
461         } else {
462                 ret = tps80031_update(dev, SLAVE_ID1, trans_reg_add,
463                                 TRANS_SLEEP_OFF, TRANS_SLEEP_MASK);
464                 if (ret < 0)
465                         dev_err(dev, "%s() Error in writing the TRANS "
466                                 "register %d error %d\n", __func__,
467                                 trans_reg_add, ret);
468         }
469         return ret;
470 }
471 EXPORT_SYMBOL_GPL(tps80031_ext_power_req_config);
472
473 unsigned long tps80031_get_chip_info(struct device *dev)
474 {
475         struct tps80031 *tps80031 = dev_get_drvdata(dev);
476         return tps80031->chip_info;
477 }
478 EXPORT_SYMBOL_GPL(tps80031_get_chip_info);
479
480 int tps80031_get_pmu_version(struct device *dev)
481 {
482         struct tps80031 *tps80031 = dev_get_drvdata(dev);
483         return tps80031->es_version;
484 }
485 EXPORT_SYMBOL_GPL(tps80031_get_pmu_version);
486
487 static struct tps80031 *tps80031_dev;
488 static void tps80031_power_off(void)
489 {
490         struct tps80031_client *tps = &tps80031_dev->tps_clients[SLAVE_ID1];
491
492         if (!tps->client)
493                 return;
494         dev_info(&tps->client->dev, "switching off PMU\n");
495         tps80031_write(&tps->client->dev, SLAVE_ID1,
496                                 TPS80031_PHOENIX_DEV_ON, DEVOFF);
497 }
498
499 static void tps80031_pupd_init(struct tps80031 *tps80031,
500                                struct tps80031_platform_data *pdata)
501 {
502         struct tps80031_pupd_init_data *pupd_init_data = pdata->pupd_init_data;
503         int data_size = pdata->pupd_init_data_size;
504         int i;
505
506         for (i = 0; i < data_size; ++i) {
507                 struct tps80031_pupd_init_data *pupd_init = &pupd_init_data[i];
508                 const struct tps80031_pupd_data *pupd =
509                         &tps80031_pupds[pupd_init->input_pin];
510                 u8 update_value = 0;
511                 u8 update_mask = pupd->pulldown_bit | pupd->pullup_bit;
512
513                 if (pupd_init->setting == TPS80031_PUPD_PULLDOWN)
514                         update_value = pupd->pulldown_bit;
515                 else if (pupd_init->setting == TPS80031_PUPD_PULLUP)
516                         update_value = pupd->pullup_bit;
517
518                 tps80031_update(tps80031->dev, SLAVE_ID1, pupd->reg,
519                                 update_value, update_mask);
520         }
521 }
522
523 static void tps80031_backup_battery_charger_control(struct tps80031 *tps80031,
524                                                     int enable)
525 {
526         if (enable)
527                 tps80031_update(tps80031->dev, SLAVE_ID1, TPS80031_BBSPOR_CFG,
528                                 TPS80031_BBSPOR_CHG_EN, TPS80031_BBSPOR_CHG_EN);
529         else
530                 tps80031_update(tps80031->dev, SLAVE_ID1, TPS80031_BBSPOR_CFG,
531                                 0, TPS80031_BBSPOR_CHG_EN);
532 }
533
534 static void tps80031_init_ext_control(struct tps80031 *tps80031,
535                         struct tps80031_platform_data *pdata) {
536         int ret;
537         int i;
538
539         /* Clear all external control for this rail */
540         for (i = 0; i < 9; ++i) {
541                 ret = tps80031_write(tps80031->dev, SLAVE_ID1,
542                                 TPS80031_PREQ1_RES_ASS_A + i, 0);
543                 if (ret < 0)
544                         dev_err(tps80031->dev, "%s() Error in clearing "
545                                 "register %02x\n", __func__,
546                                 TPS80031_PREQ1_RES_ASS_A + i);
547         }
548
549         /* Mask the PREQ */
550         ret = tps80031_set_bits(tps80031->dev, SLAVE_ID1,
551                         TPS80031_PHOENIX_MSK_TRANSITION, 0x7 << 5);
552         if (ret < 0)
553                 dev_err(tps80031->dev, "%s() Not able to mask register "
554                         "0x%02x\n", __func__, TPS80031_PHOENIX_MSK_TRANSITION);
555 }
556
557 static int tps80031_gpio_get(struct gpio_chip *gc, unsigned offset)
558 {
559         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
560         struct tps80031_client *tps = &tps80031->tps_clients[SLAVE_ID1];
561         uint8_t state;
562         uint8_t trans;
563         int ret;
564
565         ret = tps80031_read(&tps->client->dev, SLAVE_ID1,
566                         pmc_ext_control_base[offset] +
567                                 EXT_CONTROL_CFG_STATE, &state);
568         if (ret)
569                 return ret;
570
571         if (state != 0) {
572                 ret = tps80031_read(&tps->client->dev, SLAVE_ID1,
573                                 pmc_ext_control_base[offset] +
574                                         EXT_CONTROL_CFG_TRANS, &trans);
575                 if (ret)
576                         return ret;
577                 return trans & 0x1;
578         }
579         return 0;
580 }
581
582 static void tps80031_gpio_set(struct gpio_chip *gc, unsigned offset,
583                         int value)
584 {
585         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
586
587         tps80031_update(tps80031->dev, SLAVE_ID1,
588                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_TRANS,
589                         value, 0x1);
590 }
591
592 static int tps80031_gpio_input(struct gpio_chip *gc, unsigned offset)
593 {
594         return -EIO;
595 }
596
597 static int tps80031_gpio_output(struct gpio_chip *gc, unsigned offset,
598                                 int value)
599 {
600         tps80031_gpio_set(gc, offset, value);
601         return 0;
602 }
603
604 static int tps80031_gpio_enable(struct gpio_chip *gc, unsigned offset)
605 {
606         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
607         int ret;
608
609         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
610                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_STATE,
611                                                 STATE_ON, STATE_MASK);
612         if (ret)
613                 return ret;
614
615         return tps80031_write(tps80031->dev, SLAVE_ID1,
616                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_TRANS, 0x0);
617 }
618
619 static void tps80031_gpio_disable(struct gpio_chip *gc, unsigned offset)
620 {
621         struct tps80031 *tps80031 = container_of(gc, struct tps80031, gpio);
622         tps80031_update(tps80031->dev, SLAVE_ID1,
623                 pmc_ext_control_base[offset] + EXT_CONTROL_CFG_STATE,
624                                                 STATE_OFF, STATE_MASK);
625 }
626
627 static void tps80031_gpio_init(struct tps80031 *tps80031,
628                         struct tps80031_platform_data *pdata)
629 {
630         int ret;
631         int gpio_base = pdata->gpio_base;
632         struct tps80031_client *tps = &tps80031->tps_clients[SLAVE_ID1];
633         struct tps80031_gpio_init_data *gpio_init_data = pdata->gpio_init_data;
634         int data_size = pdata->gpio_init_data_size;
635         static int preq_bit_pos[TPS80031_GPIO_NR] = {16, 17, 18};
636         int base_add;
637         int i;
638
639         if (gpio_base <= 0)
640                 return;
641
642         /* Configure the external request mode */
643         for (i = 0; i < data_size; ++i) {
644                 struct tps80031_gpio_init_data *gpio_pd = &gpio_init_data[i];
645                 base_add = pmc_ext_control_base[gpio_pd->gpio_nr];
646
647                 if (gpio_pd->ext_ctrl_flag & EXT_PWR_REQ) {
648                         ret = tps80031_ext_power_req_config(tps80031->dev,
649                                 gpio_pd->ext_ctrl_flag,
650                                 preq_bit_pos[gpio_pd->gpio_nr],
651                                 base_add + EXT_CONTROL_CFG_STATE,
652                                 base_add + EXT_CONTROL_CFG_TRANS);
653                         if (ret < 0)
654                                 dev_warn(tps80031->dev, "Ext pwrreq GPIO "
655                                         "sleep control fails\n");
656                 }
657
658                 if (gpio_pd->ext_ctrl_flag & PWR_OFF_ON_SLEEP) {
659                         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
660                                 base_add + EXT_CONTROL_CFG_TRANS, 0x0, 0xC);
661                         if (ret < 0)
662                                 dev_warn(tps80031->dev, "GPIO OFF on sleep "
663                                         "control fails\n");
664                 }
665
666                 if (gpio_pd->ext_ctrl_flag & PWR_ON_ON_SLEEP) {
667                         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
668                                 base_add + EXT_CONTROL_CFG_TRANS, 0x4, 0xC);
669                         if (ret < 0)
670                                 dev_warn(tps80031->dev, "GPIO ON on sleep "
671                                         "control fails\n");
672                 }
673         }
674
675         tps80031->gpio.owner            = THIS_MODULE;
676         tps80031->gpio.label            = tps->client->name;
677         tps80031->gpio.dev              = tps80031->dev;
678         tps80031->gpio.base             = gpio_base;
679         tps80031->gpio.ngpio            = TPS80031_GPIO_NR;
680         tps80031->gpio.can_sleep        = 1;
681
682         tps80031->gpio.request          = tps80031_gpio_enable;
683         tps80031->gpio.free             = tps80031_gpio_disable;
684         tps80031->gpio.direction_input  = tps80031_gpio_input;
685         tps80031->gpio.direction_output = tps80031_gpio_output;
686         tps80031->gpio.set              = tps80031_gpio_set;
687         tps80031->gpio.get              = tps80031_gpio_get;
688
689         ret = gpiochip_add(&tps80031->gpio);
690         if (ret)
691                 dev_warn(tps80031->dev, "GPIO registration failed: %d\n", ret);
692 }
693
694 static void tps80031_irq_lock(struct irq_data *data)
695 {
696         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
697
698         mutex_lock(&tps80031->irq_lock);
699 }
700
701 static void tps80031_irq_enable(struct irq_data *data)
702 {
703         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
704         unsigned int __irq = data->irq - tps80031->irq_base;
705         const struct tps80031_irq_data *irq_data = &tps80031_irqs[__irq];
706
707         if (irq_data->is_sec_int) {
708                 tps80031->cont_int_mask_reg &= ~(1 << irq_data->int_mask_bit);
709                 tps80031->cont_int_en |= (1 << irq_data->int_mask_bit);
710                 tps80031->mask_reg[irq_data->mask_reg] &= ~(1 << irq_data->mask_mask);
711                 tps80031->irq_en |= (1 << irq_data->parent_int);
712         } else
713                 tps80031->mask_reg[irq_data->mask_reg] &= ~(1 << irq_data->mask_mask);
714
715         tps80031->irq_en |= (1 << __irq);
716 }
717
718 static void tps80031_irq_disable(struct irq_data *data)
719 {
720         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
721
722         unsigned int __irq = data->irq - tps80031->irq_base;
723         const struct tps80031_irq_data *irq_data = &tps80031_irqs[__irq];
724
725         if (irq_data->is_sec_int) {
726                 tps80031->cont_int_mask_reg |= (1 << irq_data->int_mask_bit);
727                 tps80031->cont_int_en &= ~(1 << irq_data->int_mask_bit);
728                 if (!tps80031->cont_int_en) {
729                         tps80031->mask_reg[irq_data->mask_reg] |=
730                                                 (1 << irq_data->mask_mask);
731                         tps80031->irq_en &= ~(1 << irq_data->parent_int);
732                 }
733                 tps80031->irq_en &= ~(1 << __irq);
734         } else
735                 tps80031->mask_reg[irq_data->mask_reg] |= (1 << irq_data->mask_mask);
736
737         tps80031->irq_en &= ~(1 << __irq);
738 }
739
740 static void tps80031_irq_sync_unlock(struct irq_data *data)
741 {
742         struct tps80031 *tps80031 = irq_data_get_irq_chip_data(data);
743         int i;
744
745         for (i = 0; i < ARRAY_SIZE(tps80031->mask_reg); i++) {
746                 if (tps80031->mask_reg[i] != tps80031->mask_cache[i]) {
747                         if (!WARN_ON(tps80031_write(tps80031->dev, SLAVE_ID2,
748                                                 TPS80031_INT_MSK_LINE_A + i,
749                                                 tps80031->mask_reg[i])))
750                                 if (!WARN_ON(tps80031_write(tps80031->dev,
751                                                 SLAVE_ID2,
752                                                 TPS80031_INT_MSK_STS_A + i,
753                                                 tps80031->mask_reg[i])))
754                                         tps80031->mask_cache[i] =
755                                                         tps80031->mask_reg[i];
756                 }
757         }
758
759         if (tps80031->cont_int_mask_reg != tps80031->cont_int_mask_cache) {
760                 if (!WARN_ON(tps80031_write(tps80031->dev, SLAVE_ID2,
761                                 TPS80031_CONTROLLER_INT_MASK,
762                                 tps80031->cont_int_mask_reg)))
763                         tps80031->cont_int_mask_cache =
764                                                 tps80031->cont_int_mask_reg;
765         }
766
767         mutex_unlock(&tps80031->irq_lock);
768 }
769
770 static irqreturn_t tps80031_charge_control_irq(int irq, void *data)
771 {
772         struct tps80031 *tps80031 = data;
773         int ret = 0;
774         int i;
775         u8 cont_sts;
776         u8 org_sts;
777         if (irq != (tps80031->irq_base + TPS80031_INT_CHRG_CTRL)) {
778                 dev_err(tps80031->dev, "%s() Got the illegal interrupt %d\n",
779                                         __func__, irq);
780                 return IRQ_NONE;
781         }
782
783         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
784                         TPS80031_CONTROLLER_STAT1, &org_sts);
785         if (ret < 0) {
786                 dev_err(tps80031->dev, "%s(): failed to read controller state1 "
787                                 "status %d\n", __func__, ret);
788                 return IRQ_NONE;
789         }
790
791         /* Get change from last interrupt and mask for interested interrupt
792          * for charge control interrupt */
793         cont_sts = org_sts ^ tps80031->prev_cont_stat1;
794         tps80031->prev_cont_stat1 = org_sts;
795         /* Clear watchdog timer state */
796         tps80031->prev_cont_stat1 &= ~(1 << 4);
797         cont_sts &= 0x5F;
798
799         for (i = 0; i < 8; ++i) {
800                 if (!controller_stat1_irq_nr[i])
801                         continue;
802
803                 if ((cont_sts & BIT(i)) &&
804                         (tps80031->irq_en & BIT(controller_stat1_irq_nr[i])))
805                         handle_nested_irq(tps80031->irq_base +
806                                                 controller_stat1_irq_nr[i]);
807                 cont_sts &= ~BIT(i);
808         }
809         return IRQ_HANDLED;
810 }
811
812 static irqreturn_t tps80031_irq(int irq, void *data)
813 {
814         struct tps80031 *tps80031 = data;
815         int ret = 0;
816         u32 acks;
817         int i;
818         uint8_t tmp[3];
819
820         ret = tps80031_reads(tps80031->dev, SLAVE_ID2,
821                              TPS80031_INT_STS_A, 3, tmp);
822         if (ret < 0) {
823                 dev_err(tps80031->dev, "failed to read interrupt status\n");
824                 return IRQ_NONE;
825         }
826         acks = (tmp[2] << 16) | (tmp[1] << 8) | tmp[0];
827
828         if (acks) {
829                 /*
830                  * Hardware behavior: hardware have the shadow register for
831                  * interrupt status register which is updated if interrupt
832                  * comes just after the interrupt status read. This shadow
833                  * register gets written to main status register and cleared
834                  * if any byte write happens in any of status register like
835                  * STS_A, STS_B or STS_C.
836                  * Hence here to clear the original interrupt status and
837                  * updating the STS register with the shadow register, it is
838                  * require to write only one byte in any of STS register.
839                  * Having multiple register write can cause the STS register
840                  * to clear without handling those interrupt and can cause
841                  * interrupt miss.
842                  */
843                 ret = tps80031_write(tps80031->dev, SLAVE_ID2,
844                                       TPS80031_INT_STS_A, 0);
845                 if (ret < 0) {
846                         dev_err(tps80031->dev, "failed to write "
847                                                 "interrupt status\n");
848                         return IRQ_NONE;
849                 }
850
851                 while (acks) {
852                         i = __ffs(acks);
853                         if (tps80031->irq_en & (1 << i))
854                                 handle_nested_irq(tps80031->irq_base + i);
855                         acks &= ~(1 << i);
856                 }
857         }
858
859         return IRQ_HANDLED;
860 }
861
862 static int __devinit tps80031_irq_init(struct tps80031 *tps80031, int irq,
863                                 int irq_base)
864 {
865         int i, ret;
866
867         if (!irq_base) {
868                 dev_warn(tps80031->dev, "No interrupt support on IRQ base\n");
869                 return -EINVAL;
870         }
871
872         mutex_init(&tps80031->irq_lock);
873
874         for (i = 0; i < 3; i++) {
875                 tps80031->mask_reg[i] = 0xFF;
876                 tps80031->mask_cache[i] = tps80031->mask_reg[i];
877                 tps80031_write(tps80031->dev, SLAVE_ID2,
878                                         TPS80031_INT_MSK_LINE_A + i,
879                                         tps80031->mask_cache[i]);
880                 tps80031_write(tps80031->dev, SLAVE_ID2,
881                                         TPS80031_INT_MSK_STS_A + i, 0xFF);
882                 tps80031_write(tps80031->dev, SLAVE_ID2,
883                                         TPS80031_INT_STS_A + i, 0xFF);
884         }
885
886         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
887                                 TPS80031_CONTROLLER_INT_MASK,
888                                 &tps80031->cont_int_mask_reg);
889         if (ret < 0) {
890                 dev_err(tps80031->dev, "Error in reading the controller_mask "
891                                         "register %d\n", ret);
892                 return ret;
893         }
894
895         tps80031->cont_int_mask_reg |= CHARGE_CONTROL_SUB_INT_MASK;
896         tps80031->cont_int_mask_cache = tps80031->cont_int_mask_reg;
897         tps80031->cont_int_en = 0;
898         ret = tps80031_write(tps80031->dev, SLAVE_ID2,
899                                 TPS80031_CONTROLLER_INT_MASK,
900                                 tps80031->cont_int_mask_reg);
901         if (ret < 0) {
902                 dev_err(tps80031->dev, "Error in writing the controller_mask "
903                                         "register %d\n", ret);
904                 return ret;
905         }
906
907         ret = tps80031_read(tps80031->dev, SLAVE_ID2,
908                         TPS80031_CONTROLLER_STAT1, &tps80031->prev_cont_stat1);
909         if (ret < 0) {
910                 dev_err(tps80031->dev, "%s(): failed to read controller state1 "
911                                 "status %d\n", __func__, ret);
912                 return ret;
913         }
914
915         /* Clear watch dog interrupt status in status */
916         tps80031->prev_cont_stat1 &= ~(1 << 4);
917
918         tps80031->irq_base = irq_base;
919
920         tps80031->irq_chip.name = "tps80031";
921         tps80031->irq_chip.irq_enable = tps80031_irq_enable;
922         tps80031->irq_chip.irq_disable = tps80031_irq_disable;
923         tps80031->irq_chip.irq_bus_lock = tps80031_irq_lock;
924         tps80031->irq_chip.irq_bus_sync_unlock = tps80031_irq_sync_unlock;
925
926         for (i = 0; i < TPS80031_INT_NR; i++) {
927                 int __irq = i + tps80031->irq_base;
928                 irq_set_chip_data(__irq, tps80031);
929                 irq_set_chip_and_handler(__irq, &tps80031->irq_chip,
930                                          handle_simple_irq);
931                 irq_set_nested_thread(__irq, 1);
932 #ifdef CONFIG_ARM
933                 set_irq_flags(__irq, IRQF_VALID);
934 #endif
935         }
936
937         ret = request_threaded_irq(irq, NULL, tps80031_irq, IRQF_ONESHOT,
938                                 "tps80031", tps80031);
939         /* register the isr for the secondary interrupt */
940         if (!ret)
941                 ret = request_threaded_irq(irq_base + TPS80031_INT_CHRG_CTRL,
942                                 NULL, tps80031_charge_control_irq,
943                                 IRQF_ONESHOT, "80031_chg_ctl", tps80031);
944         if (!ret) {
945
946                 device_init_wakeup(tps80031->dev, 1);
947                 enable_irq_wake(irq);
948         }
949
950         return ret;
951 }
952
953 static void tps80031_clk32k_enable(struct tps80031 *tps80031, int base_add)
954 {
955         int ret;
956         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
957                         base_add + EXT_CONTROL_CFG_STATE, STATE_ON, STATE_MASK);
958         if (!ret)
959                 ret = tps80031_update(tps80031->dev, SLAVE_ID1,
960                                 base_add + EXT_CONTROL_CFG_TRANS,
961                                 STATE_ON, STATE_MASK);
962         if (ret < 0)
963                 dev_err(tps80031->dev, "Error in updating clock register\n");
964 }
965
966 static void tps80031_clk32k_init(struct tps80031 *tps80031,
967                         struct tps80031_platform_data *pdata)
968 {
969         int ret;
970         struct tps80031_clk32k_init_data *clk32_idata = pdata->clk32k_init_data;
971         int data_size = pdata->clk32k_init_data_size;
972         static int clk32k_preq_bit_pos[TPS80031_CLOCK32K_NR] = {-1, 20, 19};
973         int base_add;
974         int i;
975
976         if (!clk32_idata || !data_size)
977                 return;
978
979         /* Configure the external request mode */
980         for (i = 0; i < data_size; ++i) {
981                 struct tps80031_clk32k_init_data *clk32_pd =  &clk32_idata[i];
982                 base_add = pmc_clk32k_control_base[clk32_pd->clk32k_nr];
983                 if (clk32_pd->enable)
984                         tps80031_clk32k_enable(tps80031, base_add);
985
986                 if ((clk32_pd->ext_ctrl_flag & EXT_PWR_REQ) &&
987                          (clk32k_preq_bit_pos[clk32_pd->clk32k_nr] != -1)) {
988                         ret = tps80031_ext_power_req_config(tps80031->dev,
989                                 clk32_pd->ext_ctrl_flag,
990                                 clk32k_preq_bit_pos[clk32_pd->clk32k_nr],
991                                 base_add + EXT_CONTROL_CFG_STATE,
992                                 base_add + EXT_CONTROL_CFG_TRANS);
993                         if (ret < 0)
994                                 dev_warn(tps80031->dev, "Clk32 ext control "
995                                         "fails\n");
996                 }
997
998                 if (clk32_pd->ext_ctrl_flag & PWR_OFF_ON_SLEEP) {
999                         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
1000                                 base_add + EXT_CONTROL_CFG_TRANS, 0x0, 0xC);
1001                         if (ret < 0)
1002                                 dev_warn(tps80031->dev, "clk OFF on sleep "
1003                                         "control fails\n");
1004                 }
1005
1006                 if (clk32_pd->ext_ctrl_flag & PWR_ON_ON_SLEEP) {
1007                         ret = tps80031_update(tps80031->dev, SLAVE_ID1,
1008                                 base_add + EXT_CONTROL_CFG_TRANS, 0x4, 0xC);
1009                         if (ret < 0)
1010                                 dev_warn(tps80031->dev, "clk ON sleep "
1011                                         "control fails\n");
1012                 }
1013         }
1014 }
1015
1016 #ifdef CONFIG_DEBUG_FS
1017 #include <linux/debugfs.h>
1018 #include <linux/seq_file.h>
1019 static void print_regs(const char *header, struct seq_file *s,
1020                 int sid, int start_offset, int end_offset)
1021 {
1022         struct tps80031 *tps80031 = s->private;
1023         struct tps80031_client *tps = &tps80031->tps_clients[sid];
1024         uint8_t reg_val;
1025         int i;
1026         int ret;
1027
1028         seq_printf(s, "%s\n", header);
1029         for (i = start_offset; i <= end_offset; ++i) {
1030                 ret = tps80031_read(&tps->client->dev, sid, i, &reg_val);
1031                 if (ret >= 0)
1032                         seq_printf(s, "Addr = 0x%02x Reg 0x%02x Value 0x%02x\n",
1033                                                 tps->client->addr, i, reg_val);
1034         }
1035         seq_printf(s, "------------------\n");
1036 }
1037
1038 static int dbg_tps_show(struct seq_file *s, void *unused)
1039 {
1040         seq_printf(s, "TPS80031 Registers\n");
1041         seq_printf(s, "------------------\n");
1042         print_regs("VIO Regs",       s, SLAVE_ID1, 0x47, 0x49);
1043         print_regs("VIO Regs",       s, SLAVE_ID0, 0x49, 0x4A);
1044         print_regs("SMPS1 Regs",     s, SLAVE_ID1, 0x53, 0x54);
1045         print_regs("SMPS1 Regs",     s, SLAVE_ID0, 0x55, 0x56);
1046         print_regs("SMPS1 Regs",     s, SLAVE_ID1, 0x57, 0x57);
1047         print_regs("SMPS2 Regs",     s, SLAVE_ID1, 0x59, 0x5B);
1048         print_regs("SMPS2 Regs",     s, SLAVE_ID0, 0x5B, 0x5C);
1049         print_regs("SMPS2 Regs",     s, SLAVE_ID1, 0x5C, 0x5D);
1050         print_regs("SMPS3 Regs",     s, SLAVE_ID1, 0x65, 0x68);
1051         print_regs("SMPS4 Regs",     s, SLAVE_ID1, 0x41, 0x44);
1052         print_regs("VANA Regs",      s, SLAVE_ID1, 0x81, 0x83);
1053         print_regs("VRTC Regs",      s, SLAVE_ID1, 0xC3, 0xC4);
1054         print_regs("LDO1 Regs",      s, SLAVE_ID1, 0x9D, 0x9F);
1055         print_regs("LDO2 Regs",      s, SLAVE_ID1, 0x85, 0x87);
1056         print_regs("LDO3 Regs",      s, SLAVE_ID1, 0x8D, 0x8F);
1057         print_regs("LDO4 Regs",      s, SLAVE_ID1, 0x89, 0x8B);
1058         print_regs("LDO5 Regs",      s, SLAVE_ID1, 0x99, 0x9B);
1059         print_regs("LDO6 Regs",      s, SLAVE_ID1, 0x91, 0x93);
1060         print_regs("LDO7 Regs",      s, SLAVE_ID1, 0xA5, 0xA7);
1061         print_regs("LDOUSB Regs",    s, SLAVE_ID1, 0xA1, 0xA3);
1062         print_regs("LDOLN Regs",     s, SLAVE_ID1, 0x95, 0x97);
1063         print_regs("REGEN1 Regs",    s, SLAVE_ID1, 0xAE, 0xAF);
1064         print_regs("REGEN2 Regs",    s, SLAVE_ID1, 0xB1, 0xB2);
1065         print_regs("SYSEN Regs",     s, SLAVE_ID1, 0xB4, 0xB5);
1066         print_regs("CLK32KAO Regs",  s, SLAVE_ID1, 0xBA, 0xBB);
1067         print_regs("CLK32KG Regs",   s, SLAVE_ID1, 0xBD, 0xBE);
1068         print_regs("CLK32KAUD Regs", s, SLAVE_ID1, 0xC0, 0xC1);
1069         print_regs("INT Regs",       s, SLAVE_ID2, 0xD0, 0xD8);
1070         print_regs("PREQ Regs",      s, SLAVE_ID1, 0xD7, 0xDF);
1071         print_regs("MASK_PH Regs",   s, SLAVE_ID1, 0x20, 0x21);
1072         print_regs("PMC MISC Regs",  s, SLAVE_ID1, 0xE0, 0xEF);
1073         print_regs("CONT_STATE",     s, SLAVE_ID2, 0xE0, 0xE4);
1074         print_regs("VERNUM Regs",    s, SLAVE_ID3, 0x87, 0x87);
1075         print_regs("EEPROM Regs",    s, SLAVE_ID3, 0xDF, 0xDF);
1076         print_regs("CHARGE Regs",    s, SLAVE_ID2, 0xDA, 0xF5);
1077         return 0;
1078 }
1079
1080 static int dbg_tps_open(struct inode *inode, struct file *file)
1081 {
1082         return single_open(file, dbg_tps_show, inode->i_private);
1083 }
1084
1085 static const struct file_operations debug_fops = {
1086         .open           = dbg_tps_open,
1087         .read           = seq_read,
1088         .llseek         = seq_lseek,
1089         .release        = single_release,
1090 };
1091
1092 static void __init tps80031_debuginit(struct tps80031 *tps)
1093 {
1094         (void)debugfs_create_file("tps80031", S_IRUGO, NULL,
1095                         tps, &debug_fops);
1096 }
1097 #else
1098 static void __init tps80031_debuginit(struct tps80031 *tpsi)
1099 {
1100         return;
1101 }
1102 #endif
1103
1104 static bool rd_wr_reg_id0(struct device *dev, unsigned int reg)
1105 {
1106         switch(reg) {
1107         case TPS80031_ID0_PMIC_SLAVE_SMPS_DVS:
1108                 return true;
1109         default:
1110                 pr_err("non-existing reg %s() %d reg %x\n", __func__, __LINE__, reg);
1111                 BUG();
1112                 return false;
1113         }
1114 }
1115
1116 static bool rd_wr_reg_id1(struct device *dev, unsigned int reg)
1117 {
1118         switch(reg) {
1119         case TPS80031_ID1_RTC:
1120         case TPS80031_ID1_MEMORY:
1121         case TPS80031_ID1_PMC_MASTER:
1122         case TPS80031_ID1_PMC_SLAVE_SMPS:
1123         case TPS80031_ID1_PMC_SLAVE_MISC:
1124         case TPS80031_ID1_PMC_SLAVE_LDO:
1125         case TPS80031_ID1_PMC_SLAVE_REOSURCES:
1126         case TPS80031_ID1_PMC_PREQ_ASSIGN:
1127         case TPS80031_ID1_PMC_MISC:
1128         case TPS80031_ID1_PMC_PU_PD_HZ:
1129         case TPS80031_ID1_PMC_BACKUP:
1130                 return true;
1131         default:
1132                 pr_err("non-existing reg %s() %d reg %x\n", __func__, __LINE__, reg);
1133                 BUG();
1134                 return false;
1135         }
1136 }
1137
1138 static bool rd_wr_reg_id2(struct device *dev, unsigned int reg)
1139 {
1140         switch(reg) {
1141         case TPS80031_ID2_USB:
1142         case TPS80031_ID2_GPADC_CONTROL:
1143         case TPS80031_ID2_GPADC_RESULTS:
1144         case TPS80031_ID2_AUXILLIARIES:
1145         case TPS80031_ID2_CUSTOM:
1146         case TPS80031_ID2_PWM:
1147         case TPS80031_ID2_FUEL_GAUSE:
1148         case TPS80031_ID2_INTERFACE_INTERRUPTS:
1149         case TPS80031_ID2_CHARGER:
1150                 return true;
1151         default:
1152                 pr_err("non-existing reg %s() %d reg %x\n", __func__, __LINE__, reg);
1153                 BUG();
1154                 return false;
1155         }
1156 }
1157 static bool rd_wr_reg_id3(struct device *dev, unsigned int reg)
1158 {
1159         switch(reg) {
1160         case TPS80031_ID3_TEST_LDO:
1161         case TPS80031_ID3_TEST_SMPS:
1162         case TPS80031_ID3_TEST_POWER:
1163         case TPS80031_ID3_TEST_CHARGER:
1164         case TPS80031_ID3_TEST_AUXILIIARIES:
1165         case TPS80031_ID3_DIEID:
1166         case TPS80031_ID3_TRIM_PHOENIX:
1167         case TPS80031_ID3_TRIM_CUSTOM:
1168                 return true;
1169         default:
1170                 pr_err("non-existing reg %s() %d reg %x\n", __func__, __LINE__, reg);
1171                 BUG();
1172                 return false;
1173         }
1174 }
1175
1176 static const struct regmap_config tps80031_regmap_configs[] = {
1177         {
1178                 .reg_bits = 8,
1179                 .val_bits = 8,
1180                 .writeable_reg = rd_wr_reg_id0,
1181                 .readable_reg = rd_wr_reg_id0,
1182                 .max_register = TPS80031_MAX_REGISTER - 1,
1183         },
1184         {
1185                 .reg_bits = 8,
1186                 .val_bits = 8,
1187                 .writeable_reg = rd_wr_reg_id1,
1188                 .readable_reg = rd_wr_reg_id1,
1189                 .max_register = TPS80031_MAX_REGISTER - 1,
1190         },
1191         {
1192                 .reg_bits = 8,
1193                 .val_bits = 8,
1194                 .writeable_reg = rd_wr_reg_id2,
1195                 .readable_reg = rd_wr_reg_id2,
1196                 .max_register = TPS80031_MAX_REGISTER - 1,
1197         },
1198         {
1199                 .reg_bits = 8,
1200                 .val_bits = 8,
1201                 .writeable_reg = rd_wr_reg_id3,
1202                 .readable_reg = rd_wr_reg_id3,
1203                 .max_register = TPS80031_MAX_REGISTER - 1,
1204         },
1205 };
1206
1207 static int __devexit tps80031_i2c_remove(struct i2c_client *client)
1208 {
1209         struct tps80031 *tps80031 = i2c_get_clientdata(client);
1210         int i;
1211
1212         mfd_remove_devices(tps80031->dev);
1213
1214         if (client->irq)
1215                 free_irq(client->irq, tps80031);
1216
1217         if (tps80031->gpio.owner != NULL)
1218                 if (gpiochip_remove(&tps80031->gpio) < 0)
1219                         dev_err(&client->dev, "Error in removing the gpio driver\n");
1220
1221         for (i = 0; i < TPS_NUM_SLAVES; i++) {
1222                 struct tps80031_client *tps = &tps80031->tps_clients[i];
1223                 if (tps->client && tps->client != client)
1224                         i2c_unregister_device(tps->client);
1225                 tps80031->tps_clients[i].client = NULL;
1226                 mutex_destroy(&tps->lock);
1227         }
1228
1229         return 0;
1230 }
1231
1232 static int __devinit tps80031_i2c_probe(struct i2c_client *client,
1233                                         const struct i2c_device_id *id)
1234 {
1235         struct tps80031_platform_data *pdata = client->dev.platform_data;
1236         struct tps80031 *tps80031;
1237         struct tps80031_client *tps;
1238         int ret;
1239         int jtag_ver;
1240         int ep_ver;
1241         int i;
1242
1243         if (!pdata) {
1244                 dev_err(&client->dev, "tps80031 requires platform data\n");
1245                 return -ENOTSUPP;
1246         }
1247
1248         jtag_ver = i2c_smbus_read_byte_data(client, TPS80031_JTAGVERNUM);
1249         if (jtag_ver < 0) {
1250                 dev_err(&client->dev, "Silicon version number read"
1251                                 " failed: %d\n", jtag_ver);
1252                 return -EIO;
1253         }
1254
1255         ep_ver = i2c_smbus_read_byte_data(client, TPS80031_EPROM_REV);
1256         if (ep_ver < 0) {
1257                 dev_err(&client->dev, "Silicon eeprom version read"
1258                                 " failed: %d\n", ep_ver);
1259                 return -EIO;
1260         }
1261
1262         dev_info(&client->dev, "Jtag version 0x%02x and Eeprom version 0x%02x\n",
1263                                                 jtag_ver, ep_ver);
1264
1265         tps80031 = devm_kzalloc(&client->dev, sizeof(*tps80031), GFP_KERNEL);
1266         if (!tps80031) {
1267                 dev_err(&client->dev, "Memory alloc for tps80031 failed\n");
1268                 return -ENOMEM;
1269         }
1270
1271         tps80031->es_version = jtag_ver;
1272         tps80031->dev = &client->dev;
1273         i2c_set_clientdata(client, tps80031);
1274         tps80031->chip_info = id->driver_data;
1275
1276         /* Set up slaves */
1277         tps80031->tps_clients[SLAVE_ID0].addr = I2C_ID0_ADDR;
1278         tps80031->tps_clients[SLAVE_ID1].addr = I2C_ID1_ADDR;
1279         tps80031->tps_clients[SLAVE_ID2].addr = I2C_ID2_ADDR;
1280         tps80031->tps_clients[SLAVE_ID3].addr = I2C_ID3_ADDR;
1281         for (i = 0; i < TPS_NUM_SLAVES; i++) {
1282                 tps = &tps80031->tps_clients[i];
1283                 if (tps->addr == client->addr)
1284                         tps->client = client;
1285                 else
1286                         tps->client = i2c_new_dummy(client->adapter,
1287                                                 tps->addr);
1288                 if (!tps->client) {
1289                         dev_err(&client->dev, "can't attach client %d\n", i);
1290                         ret = -ENOMEM;
1291                         goto fail_client_reg;
1292                 }
1293                 i2c_set_clientdata(tps->client, tps80031);
1294                 mutex_init(&tps->lock);
1295
1296                 tps80031->regmap[i] = devm_regmap_init_i2c(tps->client,
1297                                         &tps80031_regmap_configs[i]);
1298                 if (IS_ERR(tps80031->regmap[i])) {
1299                         ret = PTR_ERR(tps80031->regmap[i]);
1300                         dev_err(&client->dev,
1301                                 "regmap %d init failed, err %d\n", i, ret);
1302                         goto fail_client_reg;
1303                 }
1304         }
1305
1306         if (client->irq) {
1307                 ret = tps80031_irq_init(tps80031, client->irq,
1308                                         pdata->irq_base);
1309                 if (ret) {
1310                         dev_err(&client->dev, "IRQ init failed: %d\n", ret);
1311                         goto fail_client_reg;
1312                 }
1313         }
1314
1315         tps80031_pupd_init(tps80031, pdata);
1316
1317         tps80031_init_ext_control(tps80031, pdata);
1318
1319         ret = mfd_add_devices(tps80031->dev, -1,
1320                         tps80031_cell, ARRAY_SIZE(tps80031_cell), NULL, 0);
1321         if (ret < 0) {
1322                 dev_err(&client->dev, "mfd_add_devices failed: %d\n", ret);
1323                 goto fail_mfd_add;
1324         }
1325
1326         tps80031_gpio_init(tps80031, pdata);
1327
1328         tps80031_clk32k_init(tps80031, pdata);
1329
1330         tps80031_debuginit(tps80031);
1331
1332         tps80031_backup_battery_charger_control(tps80031, 1);
1333
1334         if (pdata->use_power_off && !pm_power_off)
1335                 pm_power_off = tps80031_power_off;
1336
1337         tps80031_dev = tps80031;
1338
1339         return 0;
1340
1341 fail_mfd_add:
1342         if (client->irq)
1343                 free_irq(client->irq, tps80031);
1344 fail_client_reg:
1345         for (i = 0; i < TPS_NUM_SLAVES; i++) {
1346                 struct tps80031_client *tps = &tps80031->tps_clients[i];
1347                 if (tps->client && tps->client != client)
1348                         i2c_unregister_device(tps->client);
1349                 tps80031->tps_clients[i].client = NULL;
1350                 mutex_destroy(&tps->lock);
1351         }
1352         return ret;
1353 }
1354
1355 #ifdef CONFIG_PM
1356 static int tps80031_i2c_suspend(struct device *dev)
1357 {
1358         struct i2c_client *client = to_i2c_client(dev);
1359         struct tps80031 *tps80031 = i2c_get_clientdata(client);
1360         if (client->irq)
1361                 disable_irq(client->irq);
1362         tps80031_backup_battery_charger_control(tps80031, 0);
1363         return 0;
1364 }
1365
1366 static int tps80031_i2c_resume(struct device *dev)
1367 {
1368         struct i2c_client *client = to_i2c_client(dev);
1369         struct tps80031 *tps80031 = i2c_get_clientdata(client);
1370         tps80031_backup_battery_charger_control(tps80031, 1);
1371         if (client->irq)
1372                 enable_irq(client->irq);
1373         return 0;
1374 }
1375 static const struct dev_pm_ops tps80031_dev_pm_ops = {
1376         .suspend        = tps80031_i2c_suspend,
1377         .resume         = tps80031_i2c_resume,
1378 };
1379 #define TPS80031_DEV_PM (&tps80031_dev_pm_ops)
1380 #else
1381 #define TPS80031_DEV_PM NULL
1382 #endif
1383
1384
1385 static const struct i2c_device_id tps80031_id_table[] = {
1386         { "tps80031", TPS80031 },
1387         { "tps80032", TPS80032 },
1388 };
1389 MODULE_DEVICE_TABLE(i2c, tps80031_id_table);
1390
1391 static struct i2c_driver tps80031_driver = {
1392         .driver = {
1393                 .name   = "tps80031",
1394                 .owner  = THIS_MODULE,
1395                 .pm     = TPS80031_DEV_PM,
1396         },
1397         .probe          = tps80031_i2c_probe,
1398         .remove         = __devexit_p(tps80031_i2c_remove),
1399         .id_table       = tps80031_id_table,
1400 };
1401
1402 static int __init tps80031_init(void)
1403 {
1404         return i2c_add_driver(&tps80031_driver);
1405 }
1406 subsys_initcall(tps80031_init);
1407
1408 static void __exit tps80031_exit(void)
1409 {
1410         i2c_del_driver(&tps80031_driver);
1411 }
1412 module_exit(tps80031_exit);
1413
1414 MODULE_DESCRIPTION("TPS80031 core driver");
1415 MODULE_LICENSE("GPL");