mfd: palmas: add USB VBUS LP0 wakeup option
[linux-2.6.git] / drivers / mfd / palmas.c
1 /*
2  * TI Palmas MFD Driver
3  *
4  * Copyright 2011-2012 Texas Instruments Inc.
5  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
6  *
7  * Author: Graeme Gregory <gg@slimlogic.co.uk>
8  *
9  *  This program is free software; you can redistribute it and/or modify it
10  *  under  the terms of the GNU General  Public License as published by the
11  *  Free Software Foundation;  either version 2 of the License, or (at your
12  *  option) any later version.
13  *
14  */
15
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <linux/init.h>
19 #include <linux/slab.h>
20 #include <linux/i2c.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/irqdomain.h>
24 #include <linux/regmap.h>
25 #include <linux/err.h>
26 #include <linux/mfd/core.h>
27 #include <linux/mfd/palmas.h>
28
29 #define EXT_PWR_REQ (PALMAS_EXT_CONTROL_ENABLE1 |       \
30                         PALMAS_EXT_CONTROL_ENABLE2 |    \
31                         PALMAS_EXT_CONTROL_NSLEEP)
32
33 static const struct resource gpadc_resource[] = {
34         {
35                 .name = "EOC_SW",
36                 .start = PALMAS_GPADC_EOC_SW_IRQ,
37                 .end = PALMAS_GPADC_EOC_SW_IRQ,
38                 .flags = IORESOURCE_IRQ,
39         }
40 };
41
42 static const struct resource usb_resource[] = {
43         {
44                 .name = "ID",
45                 .start = PALMAS_ID_OTG_IRQ,
46                 .end = PALMAS_ID_OTG_IRQ,
47                 .flags = IORESOURCE_IRQ,
48         },
49         {
50                 .name = "ID_WAKEUP",
51                 .start = PALMAS_ID_IRQ,
52                 .end = PALMAS_ID_IRQ,
53                 .flags = IORESOURCE_IRQ,
54         },
55         {
56                 .name = "VBUS",
57                 .start = PALMAS_VBUS_OTG_IRQ,
58                 .end = PALMAS_VBUS_OTG_IRQ,
59                 .flags = IORESOURCE_IRQ,
60         },
61         {
62                 .name = "VBUS_WAKEUP",
63                 .start = PALMAS_VBUS_IRQ,
64                 .end = PALMAS_VBUS_IRQ,
65                 .flags = IORESOURCE_IRQ,
66         },
67 };
68
69 static const struct resource palma_extcon_resource[] = {
70         {
71                 .name = "VBUS-IRQ",
72                 .start = PALMAS_VBUS_IRQ,
73                 .end = PALMAS_VBUS_IRQ,
74                 .flags = IORESOURCE_IRQ,
75         },
76         {
77                 .name = "ID-IRQ",
78                 .start = PALMAS_ID_IRQ,
79                 .end = PALMAS_ID_IRQ,
80                 .flags = IORESOURCE_IRQ,
81         },
82 };
83
84 static const struct resource rtc_resource[] = {
85         {
86                 .name = "RTC_ALARM",
87                 .start = PALMAS_RTC_ALARM_IRQ,
88                 .end = PALMAS_RTC_ALARM_IRQ,
89                 .flags = IORESOURCE_IRQ,
90         },
91 };
92
93 static const struct resource pwron_resource[] = {
94         {
95                 .name = "PWRON_BUTTON",
96                 .start = PALMAS_PWRON_IRQ,
97                 .end = PALMAS_PWRON_IRQ,
98                 .flags = IORESOURCE_IRQ,
99         },
100 };
101
102 static const struct resource wdt_resource[] = {
103         {
104                 .name = "WDT",
105                 .start = PALMAS_WDT_IRQ,
106                 .end = PALMAS_WDT_IRQ,
107                 .flags = IORESOURCE_IRQ,
108         },
109 };
110
111 enum palmas_ids {
112         PALMAS_PIN_MUX_ID,
113         PALMAS_PMIC_ID,
114         PALMAS_GPIO_ID,
115         PALMAS_LEDS_ID,
116         PALMAS_WDT_ID,
117         PALMAS_RTC_ID,
118         PALMAS_PWRBUTTON_ID,
119         PALMAS_GPADC_ID,
120         PALMAS_RESOURCE_ID,
121         PALMAS_CLK_ID,
122         PALMAS_PWM_ID,
123         PALMAS_USB_ID,
124         PALMAS_EXTCON_ID,
125 };
126
127 static const struct mfd_cell palmas_children[] = {
128         {
129                 .name = "palmas-pinctrl",
130                 .id = PALMAS_PIN_MUX_ID,
131         },
132         {
133                 .name = "palmas-pmic",
134                 .id = PALMAS_PMIC_ID,
135         },
136         {
137                 .name = "palmas-gpio",
138                 .id = PALMAS_GPIO_ID,
139         },
140         {
141                 .name = "palmas-leds",
142                 .id = PALMAS_LEDS_ID,
143         },
144         {
145                 .name = "palmas-wdt",
146                 .num_resources = ARRAY_SIZE(wdt_resource),
147                 .resources = wdt_resource,
148                 .id = PALMAS_WDT_ID,
149         },
150         {
151                 .name = "palmas-rtc",
152                 .num_resources = ARRAY_SIZE(rtc_resource),
153                 .resources = rtc_resource,
154                 .id = PALMAS_RTC_ID,
155         },
156         {
157                 .name = "palmas-pwrbutton",
158                 .num_resources = ARRAY_SIZE(pwron_resource),
159                 .resources = pwron_resource,
160                 .id = PALMAS_PWRBUTTON_ID,
161         },
162         {
163                 .name = "palmas-gpadc",
164                 .num_resources = ARRAY_SIZE(gpadc_resource),
165                 .resources = gpadc_resource,
166                 .id = PALMAS_GPADC_ID,
167         },
168         {
169                 .name = "palmas-resource",
170                 .id = PALMAS_RESOURCE_ID,
171         },
172         {
173                 .name = "palmas-clk",
174                 .id = PALMAS_CLK_ID,
175         },
176         {
177                 .name = "palmas-pwm",
178                 .id = PALMAS_PWM_ID,
179         },
180         {
181                 .name = "palmas-usb",
182                 .num_resources = ARRAY_SIZE(usb_resource),
183                 .resources = usb_resource,
184                 .id = PALMAS_USB_ID,
185         },
186         {
187                 .name = "palmas-extcon",
188                 .num_resources = ARRAY_SIZE(palma_extcon_resource),
189                 .resources = palma_extcon_resource,
190                 .id = PALMAS_EXTCON_ID,
191         }
192 };
193
194 static bool is_volatile_palma_func_reg(struct device *dev, unsigned int reg)
195 {
196         if ((reg >= (PALMAS_SMPS12_CTRL + 0x20)) &&
197                         (reg <= (PALMAS_SMPS9_VOLTAGE + 0x20)))
198                 return false;
199         return true;
200 }
201
202 static const struct regmap_config palmas_regmap_config[PALMAS_NUM_CLIENTS] = {
203         {
204                 .reg_bits = 8,
205                 .val_bits = 8,
206                 .max_register = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
207                                         PALMAS_PRIMARY_SECONDARY_PAD3),
208                 .volatile_reg = is_volatile_palma_func_reg,
209                 .cache_type  = REGCACHE_RBTREE,
210         },
211         {
212                 .reg_bits = 8,
213                 .val_bits = 8,
214                 .max_register = PALMAS_BASE_TO_REG(PALMAS_GPADC_BASE,
215                                         PALMAS_GPADC_SMPS_VSEL_MONITORING),
216         },
217         {
218                 .reg_bits = 8,
219                 .val_bits = 8,
220                 .max_register = PALMAS_BASE_TO_REG(PALMAS_TRIM_GPADC_BASE,
221                                         PALMAS_GPADC_TRIM16),
222         },
223 };
224
225 #define PALMAS_MAX_INTERRUPT_MASK_REG   4
226 #define PALMAS_MAX_INTERRUPT_EDGE_REG   8
227
228 struct palmas_regs {
229         int reg_base;
230         int reg_add;
231 };
232
233 struct palmas_irq_regs {
234         struct palmas_regs mask_reg[PALMAS_MAX_INTERRUPT_MASK_REG];
235         struct palmas_regs status_reg[PALMAS_MAX_INTERRUPT_MASK_REG];
236         struct palmas_regs edge_reg[PALMAS_MAX_INTERRUPT_EDGE_REG];
237 };
238
239 #define PALMAS_REGS(base, add)  { .reg_base = base, .reg_add = add, }
240 static struct palmas_irq_regs palmas_irq_regs = {
241         .mask_reg = {
242                 PALMAS_REGS(PALMAS_INTERRUPT_BASE, PALMAS_INT1_MASK),
243                 PALMAS_REGS(PALMAS_INTERRUPT_BASE, PALMAS_INT2_MASK),
244                 PALMAS_REGS(PALMAS_INTERRUPT_BASE, PALMAS_INT3_MASK),
245                 PALMAS_REGS(PALMAS_INTERRUPT_BASE, PALMAS_INT4_MASK),
246         },
247         .status_reg = {
248                 PALMAS_REGS(PALMAS_INTERRUPT_BASE, PALMAS_INT1_STATUS),
249                 PALMAS_REGS(PALMAS_INTERRUPT_BASE, PALMAS_INT2_STATUS),
250                 PALMAS_REGS(PALMAS_INTERRUPT_BASE, PALMAS_INT3_STATUS),
251                 PALMAS_REGS(PALMAS_INTERRUPT_BASE, PALMAS_INT4_STATUS),
252         },
253         .edge_reg = {
254                 PALMAS_REGS(PALMAS_INTERRUPT_BASE,
255                                         PALMAS_INT1_EDGE_DETECT1_RESERVED),
256                 PALMAS_REGS(PALMAS_INTERRUPT_BASE,
257                                         PALMAS_INT1_EDGE_DETECT2_RESERVED),
258                 PALMAS_REGS(PALMAS_INTERRUPT_BASE,
259                                         PALMAS_INT2_EDGE_DETECT1_RESERVED),
260                 PALMAS_REGS(PALMAS_INTERRUPT_BASE,
261                                         PALMAS_INT2_EDGE_DETECT2_RESERVED),
262                 PALMAS_REGS(PALMAS_INTERRUPT_BASE,
263                                         PALMAS_INT3_EDGE_DETECT1_RESERVED),
264                 PALMAS_REGS(PALMAS_INTERRUPT_BASE,
265                                         PALMAS_INT3_EDGE_DETECT2_RESERVED),
266                 PALMAS_REGS(PALMAS_INTERRUPT_BASE, PALMAS_INT4_EDGE_DETECT1),
267                 PALMAS_REGS(PALMAS_INTERRUPT_BASE, PALMAS_INT4_EDGE_DETECT2),
268         },
269 };
270
271 struct palmas_irq {
272         unsigned int    interrupt_mask;
273         unsigned int    rising_mask;
274         unsigned int    falling_mask;
275         unsigned int    edge_mask;
276         unsigned int    mask_reg_index;
277         unsigned int    edge_reg_index;
278 };
279
280 #define PALMAS_IRQ(_nr, _imask, _mrindex, _rmask, _fmask, _erindex)     \
281 [PALMAS_##_nr] = {                                                      \
282                         .interrupt_mask = PALMAS_##_imask,              \
283                         .mask_reg_index = _mrindex,                     \
284                         .rising_mask = _rmask,                          \
285                         .falling_mask = _fmask,                         \
286                         .edge_mask = _rmask | _fmask,                   \
287                         .edge_reg_index = _erindex                      \
288                 }
289
290 static struct palmas_irq palmas_irqs[] = {
291         /* INT1 IRQs */
292         PALMAS_IRQ(CHARG_DET_N_VBUS_OVV_IRQ,
293                         INT1_STATUS_CHARG_DET_N_VBUS_OVV, 0, 0, 0, 0),
294         PALMAS_IRQ(PWRON_IRQ, INT1_STATUS_PWRON, 0, 0, 0, 0),
295         PALMAS_IRQ(LONG_PRESS_KEY_IRQ, INT1_STATUS_LONG_PRESS_KEY, 0, 0, 0, 0),
296         PALMAS_IRQ(RPWRON_IRQ, INT1_STATUS_RPWRON, 0, 0, 0, 0),
297         PALMAS_IRQ(PWRDOWN_IRQ, INT1_STATUS_PWRDOWN, 0, 0, 0, 0),
298         PALMAS_IRQ(HOTDIE_IRQ, INT1_STATUS_HOTDIE, 0, 0, 0, 0),
299         PALMAS_IRQ(VSYS_MON_IRQ, INT1_STATUS_VSYS_MON, 0, 0, 0, 0),
300         PALMAS_IRQ(VBAT_MON_IRQ, INT1_STATUS_VBAT_MON, 0, 0, 0, 0),
301         /* INT2 IRQs */
302         PALMAS_IRQ(RTC_ALARM_IRQ, INT2_STATUS_RTC_ALARM, 1, 0, 0, 0),
303         PALMAS_IRQ(RTC_TIMER_IRQ, INT2_STATUS_RTC_TIMER, 1, 0, 0, 0),
304         PALMAS_IRQ(WDT_IRQ, INT2_STATUS_WDT, 1, 0, 0, 0),
305         PALMAS_IRQ(BATREMOVAL_IRQ, INT2_STATUS_BATREMOVAL, 1, 0, 0, 0),
306         PALMAS_IRQ(RESET_IN_IRQ, INT2_STATUS_RESET_IN, 1, 0, 0, 0),
307         PALMAS_IRQ(FBI_BB_IRQ, INT2_STATUS_FBI_BB, 1, 0, 0, 0),
308         PALMAS_IRQ(SHORT_IRQ, INT2_STATUS_SHORT, 1, 0, 0, 0),
309         PALMAS_IRQ(VAC_ACOK_IRQ, INT2_STATUS_VAC_ACOK, 1, 0, 0, 0),
310         /* INT3 IRQs */
311         PALMAS_IRQ(GPADC_AUTO_0_IRQ, INT3_STATUS_GPADC_AUTO_0, 2, 0, 0, 0),
312         PALMAS_IRQ(GPADC_AUTO_1_IRQ, INT3_STATUS_GPADC_AUTO_1, 2, 0, 0, 0),
313         PALMAS_IRQ(GPADC_EOC_SW_IRQ, INT3_STATUS_GPADC_EOC_SW, 2, 0, 0, 0),
314         PALMAS_IRQ(GPADC_EOC_RT_IRQ, INT3_STATUS_GPADC_EOC_RT, 2, 0, 0, 0),
315         PALMAS_IRQ(ID_OTG_IRQ, INT3_STATUS_ID_OTG, 2, 0, 0, 0),
316         PALMAS_IRQ(ID_IRQ, INT3_STATUS_ID, 2, 0, 0, 0),
317         PALMAS_IRQ(VBUS_OTG_IRQ, INT3_STATUS_VBUS_OTG, 2, 0, 0, 0),
318         PALMAS_IRQ(VBUS_IRQ, INT3_STATUS_VBUS, 2, 0, 0, 0),
319         /* INT4 IRQs */
320         PALMAS_IRQ(GPIO_0_IRQ, INT4_STATUS_GPIO_0, 3,
321                         PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING,
322                         PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING, 6),
323         PALMAS_IRQ(GPIO_1_IRQ, INT4_STATUS_GPIO_1, 3,
324                         PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING,
325                         PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING, 6),
326         PALMAS_IRQ(GPIO_2_IRQ, INT4_STATUS_GPIO_2, 3,
327                         PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING,
328                         PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING, 6),
329         PALMAS_IRQ(GPIO_3_IRQ, INT4_STATUS_GPIO_3, 3,
330                         PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING,
331                         PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING, 6),
332         PALMAS_IRQ(GPIO_4_IRQ, INT4_STATUS_GPIO_4, 3,
333                         PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING,
334                         PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING, 7),
335         PALMAS_IRQ(GPIO_5_IRQ, INT4_STATUS_GPIO_5, 3,
336                         PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING,
337                         PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING, 7),
338         PALMAS_IRQ(GPIO_6_IRQ, INT4_STATUS_GPIO_6, 3,
339                         PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING,
340                         PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING, 7),
341         PALMAS_IRQ(GPIO_7_IRQ, INT4_STATUS_GPIO_7, 3,
342                         PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING,
343                         PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING, 7),
344 };
345
346 struct palmas_irq_chip_data {
347         struct palmas           *palmas;
348         int                     irq_base;
349         int                     irq;
350         struct mutex            irq_lock;
351         struct irq_chip         irq_chip;
352         struct irq_domain       *domain;
353
354         struct palmas_irq_regs  *irq_regs;
355         struct palmas_irq       *irqs;
356         int                     num_irqs;
357         unsigned int            mask_value[PALMAS_MAX_INTERRUPT_MASK_REG];
358         unsigned int            status_value[PALMAS_MAX_INTERRUPT_MASK_REG];
359         unsigned int            edge_value[PALMAS_MAX_INTERRUPT_EDGE_REG];
360         unsigned int            mask_def_value[PALMAS_MAX_INTERRUPT_MASK_REG];
361         unsigned int            edge_def_value[PALMAS_MAX_INTERRUPT_EDGE_REG];
362         int                     num_mask_regs;
363         int                     num_edge_regs;
364         int                     wake_count;
365 };
366
367 static inline const struct palmas_irq *irq_to_palmas_irq(
368         struct palmas_irq_chip_data *data, int irq)
369 {
370         return &data->irqs[irq];
371 }
372
373 static void palmas_irq_lock(struct irq_data *data)
374 {
375         struct palmas_irq_chip_data *d = irq_data_get_irq_chip_data(data);
376
377         mutex_lock(&d->irq_lock);
378 }
379
380 static void palmas_irq_sync_unlock(struct irq_data *data)
381 {
382         struct palmas_irq_chip_data *d = irq_data_get_irq_chip_data(data);
383         int i, ret;
384
385         for (i = 0; i < d->num_mask_regs; i++) {
386                 ret = palmas_update_bits(d->palmas,
387                                 d->irq_regs->mask_reg[i].reg_base,
388                                 d->irq_regs->mask_reg[i].reg_add,
389                                 d->mask_def_value[i], d->mask_value[i]);
390                 if (ret < 0)
391                         dev_err(d->palmas->dev, "Failed to sync masks in %x\n",
392                                         d->irq_regs->mask_reg[i].reg_add);
393         }
394
395         for (i = 0; i < d->num_edge_regs; i++) {
396                 if (!d->edge_def_value[i])
397                         continue;
398
399                 ret = palmas_update_bits(d->palmas,
400                                 d->irq_regs->edge_reg[i].reg_base,
401                                 d->irq_regs->edge_reg[i].reg_add,
402                                 d->edge_def_value[i], d->edge_value[i]);
403                 if (ret < 0)
404                         dev_err(d->palmas->dev, "Failed to sync edge in %x\n",
405                                         d->irq_regs->edge_reg[i].reg_add);
406         }
407
408         /* If we've changed our wakeup count propagate it to the parent */
409         if (d->wake_count < 0)
410                 for (i = d->wake_count; i < 0; i++)
411                         irq_set_irq_wake(d->irq, 0);
412         else if (d->wake_count > 0)
413                 for (i = 0; i < d->wake_count; i++)
414                         irq_set_irq_wake(d->irq, 1);
415
416         d->wake_count = 0;
417
418         mutex_unlock(&d->irq_lock);
419 }
420
421 static void palmas_irq_enable(struct irq_data *data)
422 {
423         struct palmas_irq_chip_data *d = irq_data_get_irq_chip_data(data);
424         const struct palmas_irq *irq_data = irq_to_palmas_irq(d, data->hwirq);
425
426         d->mask_value[irq_data->mask_reg_index] &= ~irq_data->interrupt_mask;
427 }
428
429 static void palmas_irq_disable(struct irq_data *data)
430 {
431         struct palmas_irq_chip_data *d = irq_data_get_irq_chip_data(data);
432         const struct palmas_irq *irq_data = irq_to_palmas_irq(d, data->hwirq);
433
434         d->mask_value[irq_data->mask_reg_index] |= irq_data->interrupt_mask;
435 }
436
437 static int palmas_irq_set_type(struct irq_data *data, unsigned int type)
438 {
439         struct palmas_irq_chip_data *d = irq_data_get_irq_chip_data(data);
440         const struct palmas_irq *irq_data = irq_to_palmas_irq(d, data->hwirq);
441         unsigned int reg = irq_data->edge_reg_index;
442
443         if (!irq_data->edge_mask)
444                 return 0;
445
446         d->edge_value[reg] &= ~irq_data->edge_mask;
447         switch (type) {
448         case IRQ_TYPE_EDGE_FALLING:
449                 d->edge_value[reg] |= irq_data->falling_mask;
450                 break;
451
452         case IRQ_TYPE_EDGE_RISING:
453                 d->edge_value[reg] |= irq_data->rising_mask;
454                 break;
455
456         case IRQ_TYPE_EDGE_BOTH:
457                 d->edge_value[reg] |= irq_data->edge_mask;
458                 break;
459
460         default:
461                 return -EINVAL;
462         }
463         return 0;
464 }
465
466 static int palmas_irq_set_wake(struct irq_data *data, unsigned int on)
467 {
468         struct palmas_irq_chip_data *d = irq_data_get_irq_chip_data(data);
469
470         if (on)
471                 d->wake_count++;
472         else
473                 d->wake_count--;
474
475         return 0;
476 }
477
478 static const struct irq_chip palmas_irq_chip = {
479         .irq_bus_lock           = palmas_irq_lock,
480         .irq_bus_sync_unlock    = palmas_irq_sync_unlock,
481         .irq_disable            = palmas_irq_disable,
482         .irq_enable             = palmas_irq_enable,
483         .irq_set_type           = palmas_irq_set_type,
484         .irq_set_wake           = palmas_irq_set_wake,
485 };
486
487 static irqreturn_t palmas_irq_thread(int irq, void *data)
488 {
489         struct palmas_irq_chip_data *d = data;
490         int ret, i;
491         bool handled = false;
492
493         for (i = 0; i < d->num_mask_regs; i++) {
494                 ret = palmas_read(d->palmas,
495                                 d->irq_regs->status_reg[i].reg_base,
496                                 d->irq_regs->status_reg[i].reg_add,
497                                 &d->status_value[i]);
498
499                 if (ret != 0) {
500                         dev_err(d->palmas->dev,
501                                 "Failed to read IRQ status: %d\n", ret);
502                         return IRQ_NONE;
503                 }
504                 d->status_value[i] &= ~d->mask_value[i];
505         }
506
507         for (i = 0; i < d->num_irqs; i++) {
508                 if (d->status_value[d->irqs[i].mask_reg_index] &
509                                 d->irqs[i].interrupt_mask) {
510                         handle_nested_irq(irq_find_mapping(d->domain, i));
511                         handled = true;
512                 }
513         }
514
515         if (handled)
516                 return IRQ_HANDLED;
517         else
518                 return IRQ_NONE;
519 }
520
521 static int palmas_irq_map(struct irq_domain *h, unsigned int virq,
522                           irq_hw_number_t hw)
523 {
524         struct palmas_irq_chip_data *data = h->host_data;
525
526         irq_set_chip_data(virq, data);
527         irq_set_chip(virq, &data->irq_chip);
528         irq_set_nested_thread(virq, 1);
529
530         /* ARM needs us to explicitly flag the IRQ as valid
531          * and will set them noprobe when we do so. */
532 #ifdef CONFIG_ARM
533         set_irq_flags(virq, IRQF_VALID);
534 #else
535         irq_set_noprobe(virq);
536 #endif
537
538         return 0;
539 }
540
541 static struct irq_domain_ops palmas_domain_ops = {
542         .map    = palmas_irq_map,
543         .xlate  = irq_domain_xlate_twocell,
544 };
545
546 static int palmas_add_irq_chip(struct palmas *palmas, int irq, int irq_flags,
547                         int irq_base, struct palmas_irq_chip_data **data)
548 {
549         struct palmas_irq_chip_data *d;
550         int i;
551         int ret;
552         unsigned int status_value;
553         int num_irqs = ARRAY_SIZE(palmas_irqs);
554
555         if (irq_base) {
556                 irq_base = irq_alloc_descs(irq_base, 0, num_irqs, 0);
557                 if (irq_base < 0) {
558                         dev_warn(palmas->dev, "Failed to allocate IRQs: %d\n",
559                                  irq_base);
560                         return irq_base;
561                 }
562         }
563
564         d = devm_kzalloc(palmas->dev, sizeof(*d), GFP_KERNEL);
565         if (!d) {
566                 dev_err(palmas->dev, "mem alloc for d failed\n");
567                 return -ENOMEM;
568         }
569
570         d->palmas = palmas;
571         d->irq = irq;
572         d->irq_base = irq_base;
573         mutex_init(&d->irq_lock);
574         d->irq_chip = palmas_irq_chip;
575         d->irq_chip.name = dev_name(palmas->dev);
576         d->irq_regs = &palmas_irq_regs;
577
578         d->irqs = palmas_irqs;
579         d->num_irqs = num_irqs;
580         d->num_mask_regs = 4;
581         d->num_edge_regs = 8;
582         d->wake_count = 0;
583         *data = d;
584
585         for (i = 0; i < d->num_irqs; i++) {
586                 d->mask_def_value[d->irqs[i].mask_reg_index] |=
587                                                 d->irqs[i].interrupt_mask;
588                 d->edge_def_value[d->irqs[i].edge_reg_index] |=
589                                                 d->irqs[i].edge_mask;
590         }
591
592         /* Mask all interrupts */
593         for (i = 0; i < d->num_mask_regs; i++) {
594                 d->mask_value[i] = d->mask_def_value[i];
595                 ret = palmas_update_bits(d->palmas,
596                                 d->irq_regs->mask_reg[i].reg_base,
597                                 d->irq_regs->mask_reg[i].reg_add,
598                                 d->mask_def_value[i], d->mask_value[i]);
599                 if (ret < 0)
600                         dev_err(d->palmas->dev, "Failed to update masks in %x\n",
601                                         d->irq_regs->mask_reg[i].reg_add);
602         }
603
604         /* Set edge registers */
605         for (i = 0; i < d->num_edge_regs; i++) {
606                 if (!d->edge_def_value[i])
607                         continue;
608
609                 ret = palmas_update_bits(d->palmas,
610                                 d->irq_regs->edge_reg[i].reg_base,
611                                 d->irq_regs->edge_reg[i].reg_add,
612                                 d->edge_def_value[i], 0);
613                 if (ret < 0)
614                         dev_err(palmas->dev, "Failed to sync edge in %x\n",
615                                         d->irq_regs->edge_reg[i].reg_add);
616         }
617
618         /* Clear all interrupts */
619         for (i = 0; i < d->num_mask_regs; i++) {
620                 ret = palmas_read(d->palmas,
621                                 d->irq_regs->status_reg[i].reg_base,
622                                 d->irq_regs->status_reg[i].reg_add,
623                                 &status_value);
624
625                 if (ret != 0) {
626                         dev_err(palmas->dev, "Failed to read status %x\n",
627                                 d->irq_regs->status_reg[i].reg_add);
628                 }
629         }
630
631         if (irq_base)
632                 d->domain = irq_domain_add_legacy(palmas->dev->of_node,
633                                                   num_irqs, irq_base, 0,
634                                                   &palmas_domain_ops, d);
635         else
636                 d->domain = irq_domain_add_linear(palmas->dev->of_node,
637                                                   num_irqs,
638                                                   &palmas_domain_ops, d);
639         if (!d->domain) {
640                 dev_err(palmas->dev, "Failed to create IRQ domain\n");
641                 return -ENOMEM;
642         }
643
644         ret = request_threaded_irq(irq, NULL, palmas_irq_thread, irq_flags,
645                                    dev_name(palmas->dev), d);
646         if (ret != 0) {
647                 dev_err(palmas->dev,
648                         "Failed to request IRQ %d: %d\n", irq, ret);
649                 return ret;
650         }
651
652         return 0;
653 }
654
655 static void palmas_del_irq_chip(int irq, struct palmas_irq_chip_data *d)
656 {
657         if (d)
658                 free_irq(irq, d);
659 }
660
661 int palmas_irq_get_virq(struct palmas *palmas, int irq)
662 {
663         struct palmas_irq_chip_data *data = palmas->irq_chip_data;
664
665         if (!data->irqs[irq].interrupt_mask)
666                 return -EINVAL;
667
668         return irq_create_mapping(data->domain, irq);
669 }
670 EXPORT_SYMBOL_GPL(palmas_irq_get_virq);
671
672 struct palmas_sleep_requestor_info {
673         int id;
674         int reg_offset;
675         int bit_pos;
676 };
677
678 #define SLEEP_REQUESTOR(_id, _offset, _pos)             \
679         [PALMAS_SLEEP_REQSTR_ID_##_id] = {              \
680                 .id = PALMAS_SLEEP_REQSTR_ID_##_id,     \
681                 .reg_offset = _offset,                  \
682                 .bit_pos = _pos,                        \
683         }
684
685 static struct palmas_sleep_requestor_info sleep_reqt_info[] = {
686         SLEEP_REQUESTOR(REGEN1, 0, 0),
687         SLEEP_REQUESTOR(REGEN2, 0, 1),
688         SLEEP_REQUESTOR(SYSEN1, 0, 2),
689         SLEEP_REQUESTOR(SYSEN2, 0, 3),
690         SLEEP_REQUESTOR(CLK32KG, 0, 4),
691         SLEEP_REQUESTOR(CLK32KGAUDIO, 0, 5),
692         SLEEP_REQUESTOR(REGEN3, 0, 6),
693         SLEEP_REQUESTOR(SMPS12, 1, 0),
694         SLEEP_REQUESTOR(SMPS3, 1, 1),
695         SLEEP_REQUESTOR(SMPS45, 1, 2),
696         SLEEP_REQUESTOR(SMPS6, 1, 3),
697         SLEEP_REQUESTOR(SMPS7, 1, 4),
698         SLEEP_REQUESTOR(SMPS8, 1, 5),
699         SLEEP_REQUESTOR(SMPS9, 1, 6),
700         SLEEP_REQUESTOR(SMPS10, 1, 7),
701         SLEEP_REQUESTOR(LDO1, 2, 0),
702         SLEEP_REQUESTOR(LDO2, 2, 1),
703         SLEEP_REQUESTOR(LDO3, 2, 2),
704         SLEEP_REQUESTOR(LDO4, 2, 3),
705         SLEEP_REQUESTOR(LDO5, 2, 4),
706         SLEEP_REQUESTOR(LDO6, 2, 5),
707         SLEEP_REQUESTOR(LDO7, 2, 6),
708         SLEEP_REQUESTOR(LDO8, 2, 7),
709         SLEEP_REQUESTOR(LDO9, 3, 0),
710         SLEEP_REQUESTOR(LDOLN, 3, 1),
711         SLEEP_REQUESTOR(LDOUSB, 3, 2),
712 };
713
714 struct palmas_clk32k_info {
715         unsigned int control_reg;
716         unsigned int sleep_reqstr_id;
717 };
718
719 static struct palmas_clk32k_info palmas_clk32k_info[] = {
720         {
721                 .control_reg = PALMAS_CLK32KG_CTRL,
722                 .sleep_reqstr_id = PALMAS_SLEEP_REQSTR_ID_CLK32KG,
723         }, {
724                 .control_reg = PALMAS_CLK32KGAUDIO_CTRL,
725                 .sleep_reqstr_id = PALMAS_SLEEP_REQSTR_ID_CLK32KGAUDIO,
726         },
727 };
728
729 static int palmas_resource_write(struct palmas *palmas, unsigned int reg,
730         unsigned int value)
731 {
732         unsigned int addr = PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE, reg);
733
734         return regmap_write(palmas->regmap[0], addr, value);
735 }
736
737 static int palmas_resource_update(struct palmas *palmas, unsigned int reg,
738         unsigned int mask, unsigned int value)
739 {
740         unsigned int addr = PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE, reg);
741
742         return regmap_update_bits(palmas->regmap[0], addr, mask, value);
743 }
744
745 static int palmas_control_update(struct palmas *palmas, unsigned int reg,
746         unsigned int mask, unsigned int value)
747 {
748         unsigned int addr = PALMAS_BASE_TO_REG(PALMAS_PMU_CONTROL_BASE, reg);
749
750         return regmap_update_bits(palmas->regmap[0], addr, mask, value);
751 }
752
753 int palmas_ext_power_req_config(struct palmas *palmas,
754                 int id, int ext_pwr_ctrl, bool enable)
755 {
756         int preq_mask_bit = 0;
757         int ret;
758         int base_reg = 0;
759         int bit_pos;
760
761         if (!(ext_pwr_ctrl & EXT_PWR_REQ))
762                 return 0;
763
764         if (id >= PALMAS_SLEEP_REQSTR_ID_MAX)
765                 return 0;
766
767         if (ext_pwr_ctrl & PALMAS_EXT_CONTROL_NSLEEP) {
768                 base_reg = PALMAS_NSLEEP_RES_ASSIGN;
769                 preq_mask_bit = 0;
770         } else if (ext_pwr_ctrl & PALMAS_EXT_CONTROL_ENABLE1) {
771                 base_reg = PALMAS_ENABLE1_RES_ASSIGN;
772                 preq_mask_bit = 1;
773         } else if (ext_pwr_ctrl & PALMAS_EXT_CONTROL_ENABLE2) {
774                 base_reg = PALMAS_ENABLE2_RES_ASSIGN;
775                 preq_mask_bit = 2;
776         }
777
778         bit_pos = sleep_reqt_info[id].bit_pos;
779         base_reg += sleep_reqt_info[id].reg_offset;
780         if (enable)
781                 ret = palmas_resource_update(palmas, base_reg,
782                                 BIT(bit_pos), BIT(bit_pos));
783         else
784                 ret = palmas_resource_update(palmas, base_reg,
785                                 BIT(bit_pos), 0);
786         if (ret < 0) {
787                 dev_err(palmas->dev, "Update on resource reg failed\n");
788                 return ret;
789         }
790
791         /* Unmask the PREQ */
792         ret = palmas_control_update(palmas, PALMAS_POWER_CTRL,
793                                 BIT(preq_mask_bit), 0);
794         if (ret < 0) {
795                 dev_err(palmas->dev, "Power control register update fails\n");
796                 return ret;
797         }
798
799         return ret;
800 }
801 EXPORT_SYMBOL_GPL(palmas_ext_power_req_config);
802
803 static void palmas_init_ext_control(struct palmas *palmas)
804 {
805         int ret;
806         int i;
807
808         /* Clear all external control for this rail */
809         for (i = 0; i < 12; ++i) {
810                 ret = palmas_resource_write(palmas,
811                                 PALMAS_NSLEEP_RES_ASSIGN + i, 0);
812                 if (ret < 0)
813                         dev_err(palmas->dev,
814                                 "Error in clearing res assign register\n");
815         }
816
817         /* Mask the PREQ */
818         ret = palmas_control_update(palmas, PALMAS_POWER_CTRL, 0x7, 0x7);
819         if (ret < 0)
820                 dev_err(palmas->dev, "Power control reg write failed\n");
821 }
822
823 static void palmas_clk32k_init(struct palmas *palmas,
824         struct palmas_platform_data *pdata)
825 {
826         int ret;
827         struct palmas_clk32k_init_data *clk32_idata = pdata->clk32k_init_data;
828         int data_size = pdata->clk32k_init_data_size;
829         unsigned int reg;
830         int i;
831         int id;
832
833         if (!clk32_idata || !data_size)
834                 return;
835
836         for (i = 0; i < data_size; ++i) {
837                 struct palmas_clk32k_init_data *clk32_pd =  &clk32_idata[i];
838
839                 reg = palmas_clk32k_info[clk32_pd->clk32k_id].control_reg;
840                 if (clk32_pd->enable)
841                         ret = palmas_resource_update(palmas, reg,
842                                         PALMAS_CLK32KG_CTRL_MODE_ACTIVE,
843                                         PALMAS_CLK32KG_CTRL_MODE_ACTIVE);
844                 else
845                         ret = palmas_resource_update(palmas, reg,
846                                         PALMAS_CLK32KG_CTRL_MODE_ACTIVE, 0);
847                 if (ret < 0) {
848                         dev_err(palmas->dev, "Error in updating clk reg\n");
849                         return;
850                 }
851
852                 /* Sleep control */
853                 id = palmas_clk32k_info[clk32_pd->clk32k_id].sleep_reqstr_id;
854                 if (clk32_pd->sleep_control) {
855                         ret = palmas_ext_power_req_config(palmas, id,
856                                         clk32_pd->sleep_control, true);
857                         if (ret < 0) {
858                                 dev_err(palmas->dev,
859                                         "Error in ext power control reg\n");
860                                 return;
861                         }
862
863                         ret = palmas_resource_update(palmas, reg,
864                                         PALMAS_CLK32KG_CTRL_MODE_SLEEP,
865                                         PALMAS_CLK32KG_CTRL_MODE_SLEEP);
866                         if (ret < 0) {
867                                 dev_err(palmas->dev,
868                                         "Error in updating clk reg\n");
869                                 return;
870                         }
871                 } else {
872
873                         ret = palmas_resource_update(palmas, reg,
874                                         PALMAS_CLK32KG_CTRL_MODE_SLEEP, 0);
875                         if (ret < 0) {
876                                 dev_err(palmas->dev,
877                                         "Error in updating clk reg\n");
878                                 return;
879                         }
880                 }
881         }
882 }
883
884 static struct palmas *palmas_dev;
885 static void palmas_power_off(void)
886 {
887         if (!palmas_dev)
888                 return;
889
890         palmas_control_update(palmas_dev, PALMAS_DEV_CTRL, 1, 0);
891 }
892
893 static int palmas_read_version_information(struct palmas *palmas)
894 {
895         unsigned int sw_rev, des_rev;
896         int ret;
897
898         ret = palmas_read(palmas, PALMAS_PMU_CONTROL_BASE,
899                                 PALMAS_SW_REVISION, &sw_rev);
900         if (ret < 0) {
901                 dev_err(palmas->dev, "SW_REVISION read failed: %d\n", ret);
902                 return ret;
903         }
904
905         ret = palmas_read(palmas, PALMAS_PAGE3_BASE,
906                                 PALMAS_INTERNAL_DESIGNREV, &des_rev);
907         if (ret < 0) {
908                 dev_err(palmas->dev,
909                         "INTERNAL_DESIGNREV read failed: %d\n", ret);
910                 return ret;
911         }
912
913         palmas->sw_otp_version = sw_rev;
914
915         dev_info(palmas->dev, "Internal DesignRev 0x%02X, SWRev 0x%02X\n",
916                         des_rev, sw_rev);
917         des_rev = PALMAS_INTERNAL_DESIGNREV_DESIGNREV(des_rev);
918         switch (des_rev) {
919         case 0:
920                 palmas->es_major_version = 1;
921                 palmas->es_minor_version = 0;
922                 palmas->design_revision = 0xA0;
923                 break;
924         case 1:
925                 palmas->es_major_version = 2;
926                 palmas->es_minor_version = 0;
927                 palmas->design_revision = 0xB0;
928                 break;
929         case 2:
930                 palmas->es_major_version = 2;
931                 palmas->es_minor_version = 1;
932                 palmas->design_revision = 0xB1;
933                 break;
934         case 3:
935                 palmas->es_major_version = 2;
936                 palmas->es_minor_version = 2;
937                 palmas->design_revision = 0xB2;
938                 break;
939         default:
940                 dev_err(palmas->dev, "Invalid design revision\n");
941                 return -EINVAL;
942         }
943
944         dev_info(palmas->dev, "ES version %d.%d: ChipRevision 0x%02X%02X\n",
945                 palmas->es_major_version, palmas->es_minor_version,
946                 palmas->design_revision, palmas->sw_otp_version);
947         return 0;
948 }
949
950 static int __devinit palmas_i2c_probe(struct i2c_client *i2c,
951                             const struct i2c_device_id *id)
952 {
953         struct palmas *palmas;
954         struct palmas_platform_data *pdata;
955         int ret = 0, i;
956         unsigned int reg, addr;
957         int slave;
958         int irq_flag;
959         struct mfd_cell *children;
960
961         pdata = dev_get_platdata(&i2c->dev);
962         if (!pdata)
963                 return -EINVAL;
964
965         palmas = devm_kzalloc(&i2c->dev, sizeof(struct palmas), GFP_KERNEL);
966         if (palmas == NULL)
967                 return -ENOMEM;
968
969         i2c_set_clientdata(i2c, palmas);
970         palmas->dev = &i2c->dev;
971         palmas->id = id->driver_data;
972         palmas->irq = i2c->irq;
973
974         for (i = 0; i < PALMAS_NUM_CLIENTS; i++) {
975                 if (i == 0)
976                         palmas->i2c_clients[i] = i2c;
977                 else {
978                         palmas->i2c_clients[i] =
979                                         i2c_new_dummy(i2c->adapter,
980                                                         i2c->addr + i);
981                         if (!palmas->i2c_clients[i]) {
982                                 dev_err(palmas->dev,
983                                         "can't attach client %d\n", i);
984                                 ret = -ENOMEM;
985                                 goto err;
986                         }
987                 }
988                 palmas->regmap[i] = devm_regmap_init_i2c(palmas->i2c_clients[i],
989                                 &palmas_regmap_config[i]);
990                 if (IS_ERR(palmas->regmap[i])) {
991                         ret = PTR_ERR(palmas->regmap[i]);
992                         dev_err(palmas->dev,
993                                 "Failed to allocate regmap %d, err: %d\n",
994                                 i, ret);
995                         goto err;
996                 }
997         }
998
999         ret = palmas_read_version_information(palmas);
1000         if (ret < 0)
1001                 goto err;
1002
1003         /* Change interrupt line output polarity */
1004         slave = PALMAS_BASE_TO_SLAVE(PALMAS_PU_PD_OD_BASE);
1005         addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE, PALMAS_POLARITY_CTRL);
1006         regmap_read(palmas->regmap[slave], addr, &reg);
1007         if (pdata->irq_type & IRQ_TYPE_LEVEL_HIGH)
1008                 reg |= PALMAS_POLARITY_CTRL_INT_POLARITY;
1009         else
1010                 reg &= ~PALMAS_POLARITY_CTRL_INT_POLARITY;
1011         regmap_write(palmas->regmap[slave], addr, reg);
1012
1013         /* Change IRQ into clear on read mode for efficiency */
1014         slave = PALMAS_BASE_TO_SLAVE(PALMAS_INTERRUPT_BASE);
1015         addr = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE, PALMAS_INT_CTRL);
1016         reg = PALMAS_INT_CTRL_INT_CLEAR;
1017
1018         regmap_write(palmas->regmap[slave], addr, reg);
1019
1020         irq_flag = pdata->irq_type;
1021         irq_flag |= IRQF_ONESHOT;
1022         ret = palmas_add_irq_chip(palmas, palmas->irq,
1023                         irq_flag, pdata->irq_base, &palmas->irq_chip_data);
1024         if (ret < 0)
1025                 goto err;
1026
1027         reg = pdata->power_ctrl;
1028
1029         slave = PALMAS_BASE_TO_SLAVE(PALMAS_PMU_CONTROL_BASE);
1030         addr = PALMAS_BASE_TO_REG(PALMAS_PMU_CONTROL_BASE, PALMAS_POWER_CTRL);
1031
1032         ret = regmap_write(palmas->regmap[slave], addr, reg);
1033         if (ret)
1034                 goto err;
1035
1036
1037         palmas_init_ext_control(palmas);
1038
1039         palmas_clk32k_init(palmas, pdata);
1040
1041         children = kmemdup(palmas_children, sizeof(palmas_children),
1042                            GFP_KERNEL);
1043         if (!children) {
1044                 ret = -ENOMEM;
1045                 goto err;
1046         }
1047
1048         children[PALMAS_PMIC_ID].platform_data = pdata->pmic_pdata;
1049         children[PALMAS_PMIC_ID].pdata_size = sizeof(*pdata->pmic_pdata);
1050
1051         ret = mfd_add_devices(palmas->dev, -1,
1052                               children, ARRAY_SIZE(palmas_children),
1053                               NULL, palmas->irq_chip_data->irq_base);
1054         kfree(children);
1055
1056         if (ret < 0)
1057                 goto err;
1058
1059         if (pdata->use_power_off && !pm_power_off)
1060                 pm_power_off = palmas_power_off;
1061
1062         if (pdata->auto_ldousb_en)
1063                 /* VBUS detection enables the LDOUSB */
1064                 palmas_control_update(palmas, PALMAS_EXT_CHRG_CTRL, 1,
1065                                         PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN);
1066
1067         palmas_dev = palmas;
1068         return ret;
1069
1070 err:
1071         mfd_remove_devices(palmas->dev);
1072         kfree(palmas);
1073         return ret;
1074 }
1075
1076 static int palmas_i2c_remove(struct i2c_client *i2c)
1077 {
1078         struct palmas *palmas = i2c_get_clientdata(i2c);
1079
1080         mfd_remove_devices(palmas->dev);
1081         palmas_del_irq_chip(palmas->irq, palmas->irq_chip_data);
1082
1083         return 0;
1084 }
1085
1086 static const struct i2c_device_id palmas_i2c_id[] = {
1087         { "palmas", },
1088         { "twl6035", },
1089         { "twl6037", },
1090         { "tps65913", },
1091         { /* end */ }
1092 };
1093 MODULE_DEVICE_TABLE(i2c, palmas_i2c_id);
1094
1095 static struct of_device_id __devinitdata of_palmas_match_tbl[] = {
1096         { .compatible = "ti,palmas", },
1097         { /* end */ }
1098 };
1099
1100 static struct i2c_driver palmas_i2c_driver = {
1101         .driver = {
1102                    .name = "palmas",
1103                    .of_match_table = of_palmas_match_tbl,
1104                    .owner = THIS_MODULE,
1105         },
1106         .probe = palmas_i2c_probe,
1107         .remove = palmas_i2c_remove,
1108         .id_table = palmas_i2c_id,
1109 };
1110
1111 static int __init palmas_i2c_init(void)
1112 {
1113         return i2c_add_driver(&palmas_i2c_driver);
1114 }
1115 /* init early so consumer devices can complete system boot */
1116 subsys_initcall(palmas_i2c_init);
1117
1118 static void __exit palmas_i2c_exit(void)
1119 {
1120         i2c_del_driver(&palmas_i2c_driver);
1121 }
1122 module_exit(palmas_i2c_exit);
1123
1124 MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
1125 MODULE_DESCRIPTION("Palmas chip family multi-function driver");
1126 MODULE_LICENSE("GPL");