drm/i915: Wait for LVDS panel power sequence
[linux-2.6.git] / drivers / mfd / jz4740-adc.c
1 /*
2  * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3  * JZ4740 SoC ADC driver
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under  the terms of the GNU General  Public License as published by the
7  * Free Software Foundation;  either version 2 of the License, or (at your
8  * option) any later version.
9  *
10  * You should have received a copy of the GNU General Public License along
11  * with this program; if not, write to the Free Software Foundation, Inc.,
12  * 675 Mass Ave, Cambridge, MA 02139, USA.
13  *
14  * This driver synchronizes access to the JZ4740 ADC core between the
15  * JZ4740 battery and hwmon drivers.
16  */
17
18 #include <linux/err.h>
19 #include <linux/irq.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26
27 #include <linux/clk.h>
28 #include <linux/mfd/core.h>
29
30 #include <linux/jz4740-adc.h>
31
32
33 #define JZ_REG_ADC_ENABLE       0x00
34 #define JZ_REG_ADC_CFG          0x04
35 #define JZ_REG_ADC_CTRL         0x08
36 #define JZ_REG_ADC_STATUS       0x0c
37
38 #define JZ_REG_ADC_TOUCHSCREEN_BASE     0x10
39 #define JZ_REG_ADC_BATTERY_BASE 0x1c
40 #define JZ_REG_ADC_HWMON_BASE   0x20
41
42 #define JZ_ADC_ENABLE_TOUCH     BIT(2)
43 #define JZ_ADC_ENABLE_BATTERY   BIT(1)
44 #define JZ_ADC_ENABLE_ADCIN     BIT(0)
45
46 enum {
47         JZ_ADC_IRQ_ADCIN = 0,
48         JZ_ADC_IRQ_BATTERY,
49         JZ_ADC_IRQ_TOUCH,
50         JZ_ADC_IRQ_PENUP,
51         JZ_ADC_IRQ_PENDOWN,
52 };
53
54 struct jz4740_adc {
55         struct resource *mem;
56         void __iomem *base;
57
58         int irq;
59         struct irq_chip_generic *gc;
60
61         struct clk *clk;
62         atomic_t clk_ref;
63
64         spinlock_t lock;
65 };
66
67 static void jz4740_adc_irq_demux(unsigned int irq, struct irq_desc *desc)
68 {
69         struct irq_chip_generic *gc = irq_desc_get_handler_data(desc);
70         uint8_t status;
71         unsigned int i;
72
73         status = readb(gc->reg_base + JZ_REG_ADC_STATUS);
74
75         for (i = 0; i < 5; ++i) {
76                 if (status & BIT(i))
77                         generic_handle_irq(gc->irq_base + i);
78         }
79 }
80
81
82 /* Refcounting for the ADC clock is done in here instead of in the clock
83  * framework, because it is the only clock which is shared between multiple
84  * devices and thus is the only clock which needs refcounting */
85 static inline void jz4740_adc_clk_enable(struct jz4740_adc *adc)
86 {
87         if (atomic_inc_return(&adc->clk_ref) == 1)
88                 clk_enable(adc->clk);
89 }
90
91 static inline void jz4740_adc_clk_disable(struct jz4740_adc *adc)
92 {
93         if (atomic_dec_return(&adc->clk_ref) == 0)
94                 clk_disable(adc->clk);
95 }
96
97 static inline void jz4740_adc_set_enabled(struct jz4740_adc *adc, int engine,
98         bool enabled)
99 {
100         unsigned long flags;
101         uint8_t val;
102
103         spin_lock_irqsave(&adc->lock, flags);
104
105         val = readb(adc->base + JZ_REG_ADC_ENABLE);
106         if (enabled)
107                 val |= BIT(engine);
108         else
109                 val &= ~BIT(engine);
110         writeb(val, adc->base + JZ_REG_ADC_ENABLE);
111
112         spin_unlock_irqrestore(&adc->lock, flags);
113 }
114
115 static int jz4740_adc_cell_enable(struct platform_device *pdev)
116 {
117         struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent);
118
119         jz4740_adc_clk_enable(adc);
120         jz4740_adc_set_enabled(adc, pdev->id, true);
121
122         return 0;
123 }
124
125 static int jz4740_adc_cell_disable(struct platform_device *pdev)
126 {
127         struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent);
128
129         jz4740_adc_set_enabled(adc, pdev->id, false);
130         jz4740_adc_clk_disable(adc);
131
132         return 0;
133 }
134
135 int jz4740_adc_set_config(struct device *dev, uint32_t mask, uint32_t val)
136 {
137         struct jz4740_adc *adc = dev_get_drvdata(dev);
138         unsigned long flags;
139         uint32_t cfg;
140
141         if (!adc)
142                 return -ENODEV;
143
144         spin_lock_irqsave(&adc->lock, flags);
145
146         cfg = readl(adc->base + JZ_REG_ADC_CFG);
147
148         cfg &= ~mask;
149         cfg |= val;
150
151         writel(cfg, adc->base + JZ_REG_ADC_CFG);
152
153         spin_unlock_irqrestore(&adc->lock, flags);
154
155         return 0;
156 }
157 EXPORT_SYMBOL_GPL(jz4740_adc_set_config);
158
159 static struct resource jz4740_hwmon_resources[] = {
160         {
161                 .start = JZ_ADC_IRQ_ADCIN,
162                 .flags = IORESOURCE_IRQ,
163         },
164         {
165                 .start  = JZ_REG_ADC_HWMON_BASE,
166                 .end    = JZ_REG_ADC_HWMON_BASE + 3,
167                 .flags  = IORESOURCE_MEM,
168         },
169 };
170
171 static struct resource jz4740_battery_resources[] = {
172         {
173                 .start = JZ_ADC_IRQ_BATTERY,
174                 .flags = IORESOURCE_IRQ,
175         },
176         {
177                 .start  = JZ_REG_ADC_BATTERY_BASE,
178                 .end    = JZ_REG_ADC_BATTERY_BASE + 3,
179                 .flags  = IORESOURCE_MEM,
180         },
181 };
182
183 const struct mfd_cell jz4740_adc_cells[] = {
184         {
185                 .id = 0,
186                 .name = "jz4740-hwmon",
187                 .num_resources = ARRAY_SIZE(jz4740_hwmon_resources),
188                 .resources = jz4740_hwmon_resources,
189
190                 .enable = jz4740_adc_cell_enable,
191                 .disable = jz4740_adc_cell_disable,
192         },
193         {
194                 .id = 1,
195                 .name = "jz4740-battery",
196                 .num_resources = ARRAY_SIZE(jz4740_battery_resources),
197                 .resources = jz4740_battery_resources,
198
199                 .enable = jz4740_adc_cell_enable,
200                 .disable = jz4740_adc_cell_disable,
201         },
202 };
203
204 static int __devinit jz4740_adc_probe(struct platform_device *pdev)
205 {
206         struct irq_chip_generic *gc;
207         struct irq_chip_type *ct;
208         struct jz4740_adc *adc;
209         struct resource *mem_base;
210         int ret;
211         int irq_base;
212
213         adc = kmalloc(sizeof(*adc), GFP_KERNEL);
214         if (!adc) {
215                 dev_err(&pdev->dev, "Failed to allocate driver structure\n");
216                 return -ENOMEM;
217         }
218
219         adc->irq = platform_get_irq(pdev, 0);
220         if (adc->irq < 0) {
221                 ret = adc->irq;
222                 dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
223                 goto err_free;
224         }
225
226         irq_base = platform_get_irq(pdev, 1);
227         if (irq_base < 0) {
228                 ret = irq_base;
229                 dev_err(&pdev->dev, "Failed to get irq base: %d\n", ret);
230                 goto err_free;
231         }
232
233         mem_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
234         if (!mem_base) {
235                 ret = -ENOENT;
236                 dev_err(&pdev->dev, "Failed to get platform mmio resource\n");
237                 goto err_free;
238         }
239
240         /* Only request the shared registers for the MFD driver */
241         adc->mem = request_mem_region(mem_base->start, JZ_REG_ADC_STATUS,
242                                         pdev->name);
243         if (!adc->mem) {
244                 ret = -EBUSY;
245                 dev_err(&pdev->dev, "Failed to request mmio memory region\n");
246                 goto err_free;
247         }
248
249         adc->base = ioremap_nocache(adc->mem->start, resource_size(adc->mem));
250         if (!adc->base) {
251                 ret = -EBUSY;
252                 dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
253                 goto err_release_mem_region;
254         }
255
256         adc->clk = clk_get(&pdev->dev, "adc");
257         if (IS_ERR(adc->clk)) {
258                 ret = PTR_ERR(adc->clk);
259                 dev_err(&pdev->dev, "Failed to get clock: %d\n", ret);
260                 goto err_iounmap;
261         }
262
263         spin_lock_init(&adc->lock);
264         atomic_set(&adc->clk_ref, 0);
265
266         platform_set_drvdata(pdev, adc);
267
268         gc = irq_alloc_generic_chip("INTC", 1, irq_base, adc->base,
269                 handle_level_irq);
270
271         ct = gc->chip_types;
272         ct->regs.mask = JZ_REG_ADC_CTRL;
273         ct->regs.ack = JZ_REG_ADC_STATUS;
274         ct->chip.irq_mask = irq_gc_mask_set_bit;
275         ct->chip.irq_unmask = irq_gc_mask_clr_bit;
276         ct->chip.irq_ack = irq_gc_ack;
277
278         irq_setup_generic_chip(gc, IRQ_MSK(5), 0, 0, IRQ_NOPROBE | IRQ_LEVEL);
279
280         adc->gc = gc;
281
282         irq_set_handler_data(adc->irq, gc);
283         irq_set_chained_handler(adc->irq, jz4740_adc_irq_demux);
284
285         writeb(0x00, adc->base + JZ_REG_ADC_ENABLE);
286         writeb(0xff, adc->base + JZ_REG_ADC_CTRL);
287
288         ret = mfd_add_devices(&pdev->dev, 0, jz4740_adc_cells,
289                 ARRAY_SIZE(jz4740_adc_cells), mem_base, irq_base);
290         if (ret < 0)
291                 goto err_clk_put;
292
293         return 0;
294
295 err_clk_put:
296         clk_put(adc->clk);
297 err_iounmap:
298         platform_set_drvdata(pdev, NULL);
299         iounmap(adc->base);
300 err_release_mem_region:
301         release_mem_region(adc->mem->start, resource_size(adc->mem));
302 err_free:
303         kfree(adc);
304
305         return ret;
306 }
307
308 static int __devexit jz4740_adc_remove(struct platform_device *pdev)
309 {
310         struct jz4740_adc *adc = platform_get_drvdata(pdev);
311
312         mfd_remove_devices(&pdev->dev);
313
314         irq_remove_generic_chip(adc->gc, IRQ_MSK(5), IRQ_NOPROBE | IRQ_LEVEL, 0);
315         kfree(adc->gc);
316         irq_set_handler_data(adc->irq, NULL);
317         irq_set_chained_handler(adc->irq, NULL);
318
319         iounmap(adc->base);
320         release_mem_region(adc->mem->start, resource_size(adc->mem));
321
322         clk_put(adc->clk);
323
324         platform_set_drvdata(pdev, NULL);
325
326         kfree(adc);
327
328         return 0;
329 }
330
331 struct platform_driver jz4740_adc_driver = {
332         .probe  = jz4740_adc_probe,
333         .remove = __devexit_p(jz4740_adc_remove),
334         .driver = {
335                 .name = "jz4740-adc",
336                 .owner = THIS_MODULE,
337         },
338 };
339
340 static int __init jz4740_adc_init(void)
341 {
342         return platform_driver_register(&jz4740_adc_driver);
343 }
344 module_init(jz4740_adc_init);
345
346 static void __exit jz4740_adc_exit(void)
347 {
348         platform_driver_unregister(&jz4740_adc_driver);
349 }
350 module_exit(jz4740_adc_exit);
351
352 MODULE_DESCRIPTION("JZ4740 SoC ADC driver");
353 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
354 MODULE_LICENSE("GPL");
355 MODULE_ALIAS("platform:jz4740-adc");