mfd: let asic3 use mem resource instead of bus_shift
[linux-2.6.git] / drivers / mfd / asic3.c
1 /*
2  * driver/mfd/asic3.c
3  *
4  * Compaq ASIC3 support.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * Copyright 2001 Compaq Computer Corporation.
11  * Copyright 2004-2005 Phil Blundell
12  * Copyright 2007-2008 OpenedHand Ltd.
13  *
14  * Authors: Phil Blundell <pb@handhelds.org>,
15  *          Samuel Ortiz <sameo@openedhand.com>
16  *
17  */
18
19 #include <linux/version.h>
20 #include <linux/kernel.h>
21 #include <linux/irq.h>
22 #include <linux/gpio.h>
23 #include <linux/io.h>
24 #include <linux/spinlock.h>
25 #include <linux/platform_device.h>
26
27 #include <linux/mfd/asic3.h>
28
29 struct asic3 {
30         void __iomem *mapping;
31         unsigned int bus_shift;
32         unsigned int irq_nr;
33         unsigned int irq_base;
34         spinlock_t lock;
35         u16 irq_bothedge[4];
36         struct gpio_chip gpio;
37         struct device *dev;
38 };
39
40 static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
41
42 static inline void asic3_write_register(struct asic3 *asic,
43                                  unsigned int reg, u32 value)
44 {
45         iowrite16(value, asic->mapping +
46                   (reg >> asic->bus_shift));
47 }
48
49 static inline u32 asic3_read_register(struct asic3 *asic,
50                                unsigned int reg)
51 {
52         return ioread16(asic->mapping +
53                         (reg >> asic->bus_shift));
54 }
55
56 /* IRQs */
57 #define MAX_ASIC_ISR_LOOPS    20
58 #define ASIC3_GPIO_BASE_INCR \
59         (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
60
61 static void asic3_irq_flip_edge(struct asic3 *asic,
62                                 u32 base, int bit)
63 {
64         u16 edge;
65         unsigned long flags;
66
67         spin_lock_irqsave(&asic->lock, flags);
68         edge = asic3_read_register(asic,
69                                    base + ASIC3_GPIO_EDGE_TRIGGER);
70         edge ^= bit;
71         asic3_write_register(asic,
72                              base + ASIC3_GPIO_EDGE_TRIGGER, edge);
73         spin_unlock_irqrestore(&asic->lock, flags);
74 }
75
76 static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
77 {
78         int iter, i;
79         unsigned long flags;
80         struct asic3 *asic;
81
82         desc->chip->ack(irq);
83
84         asic = desc->handler_data;
85
86         for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
87                 u32 status;
88                 int bank;
89
90                 spin_lock_irqsave(&asic->lock, flags);
91                 status = asic3_read_register(asic,
92                                              ASIC3_OFFSET(INTR, P_INT_STAT));
93                 spin_unlock_irqrestore(&asic->lock, flags);
94
95                 /* Check all ten register bits */
96                 if ((status & 0x3ff) == 0)
97                         break;
98
99                 /* Handle GPIO IRQs */
100                 for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
101                         if (status & (1 << bank)) {
102                                 unsigned long base, istat;
103
104                                 base = ASIC3_GPIO_A_BASE
105                                        + bank * ASIC3_GPIO_BASE_INCR;
106
107                                 spin_lock_irqsave(&asic->lock, flags);
108                                 istat = asic3_read_register(asic,
109                                                             base +
110                                                             ASIC3_GPIO_INT_STATUS);
111                                 /* Clearing IntStatus */
112                                 asic3_write_register(asic,
113                                                      base +
114                                                      ASIC3_GPIO_INT_STATUS, 0);
115                                 spin_unlock_irqrestore(&asic->lock, flags);
116
117                                 for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
118                                         int bit = (1 << i);
119                                         unsigned int irqnr;
120
121                                         if (!(istat & bit))
122                                                 continue;
123
124                                         irqnr = asic->irq_base +
125                                                 (ASIC3_GPIOS_PER_BANK * bank)
126                                                 + i;
127                                         desc = irq_desc + irqnr;
128                                         desc->handle_irq(irqnr, desc);
129                                         if (asic->irq_bothedge[bank] & bit)
130                                                 asic3_irq_flip_edge(asic, base,
131                                                                     bit);
132                                 }
133                         }
134                 }
135
136                 /* Handle remaining IRQs in the status register */
137                 for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
138                         /* They start at bit 4 and go up */
139                         if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) {
140                                 desc = irq_desc + asic->irq_base + i;
141                                 desc->handle_irq(asic->irq_base + i,
142                                                  desc);
143                         }
144                 }
145         }
146
147         if (iter >= MAX_ASIC_ISR_LOOPS)
148                 dev_err(asic->dev, "interrupt processing overrun\n");
149 }
150
151 static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
152 {
153         int n;
154
155         n = (irq - asic->irq_base) >> 4;
156
157         return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
158 }
159
160 static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
161 {
162         return (irq - asic->irq_base) & 0xf;
163 }
164
165 static void asic3_mask_gpio_irq(unsigned int irq)
166 {
167         struct asic3 *asic = get_irq_chip_data(irq);
168         u32 val, bank, index;
169         unsigned long flags;
170
171         bank = asic3_irq_to_bank(asic, irq);
172         index = asic3_irq_to_index(asic, irq);
173
174         spin_lock_irqsave(&asic->lock, flags);
175         val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
176         val |= 1 << index;
177         asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
178         spin_unlock_irqrestore(&asic->lock, flags);
179 }
180
181 static void asic3_mask_irq(unsigned int irq)
182 {
183         struct asic3 *asic = get_irq_chip_data(irq);
184         int regval;
185         unsigned long flags;
186
187         spin_lock_irqsave(&asic->lock, flags);
188         regval = asic3_read_register(asic,
189                                      ASIC3_INTR_BASE +
190                                      ASIC3_INTR_INT_MASK);
191
192         regval &= ~(ASIC3_INTMASK_MASK0 <<
193                     (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
194
195         asic3_write_register(asic,
196                              ASIC3_INTR_BASE +
197                              ASIC3_INTR_INT_MASK,
198                              regval);
199         spin_unlock_irqrestore(&asic->lock, flags);
200 }
201
202 static void asic3_unmask_gpio_irq(unsigned int irq)
203 {
204         struct asic3 *asic = get_irq_chip_data(irq);
205         u32 val, bank, index;
206         unsigned long flags;
207
208         bank = asic3_irq_to_bank(asic, irq);
209         index = asic3_irq_to_index(asic, irq);
210
211         spin_lock_irqsave(&asic->lock, flags);
212         val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
213         val &= ~(1 << index);
214         asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
215         spin_unlock_irqrestore(&asic->lock, flags);
216 }
217
218 static void asic3_unmask_irq(unsigned int irq)
219 {
220         struct asic3 *asic = get_irq_chip_data(irq);
221         int regval;
222         unsigned long flags;
223
224         spin_lock_irqsave(&asic->lock, flags);
225         regval = asic3_read_register(asic,
226                                      ASIC3_INTR_BASE +
227                                      ASIC3_INTR_INT_MASK);
228
229         regval |= (ASIC3_INTMASK_MASK0 <<
230                    (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
231
232         asic3_write_register(asic,
233                              ASIC3_INTR_BASE +
234                              ASIC3_INTR_INT_MASK,
235                              regval);
236         spin_unlock_irqrestore(&asic->lock, flags);
237 }
238
239 static int asic3_gpio_irq_type(unsigned int irq, unsigned int type)
240 {
241         struct asic3 *asic = get_irq_chip_data(irq);
242         u32 bank, index;
243         u16 trigger, level, edge, bit;
244         unsigned long flags;
245
246         bank = asic3_irq_to_bank(asic, irq);
247         index = asic3_irq_to_index(asic, irq);
248         bit = 1<<index;
249
250         spin_lock_irqsave(&asic->lock, flags);
251         level = asic3_read_register(asic,
252                                     bank + ASIC3_GPIO_LEVEL_TRIGGER);
253         edge = asic3_read_register(asic,
254                                    bank + ASIC3_GPIO_EDGE_TRIGGER);
255         trigger = asic3_read_register(asic,
256                                       bank + ASIC3_GPIO_TRIGGER_TYPE);
257         asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit;
258
259         if (type == IRQT_RISING) {
260                 trigger |= bit;
261                 edge |= bit;
262         } else if (type == IRQT_FALLING) {
263                 trigger |= bit;
264                 edge &= ~bit;
265         } else if (type == IRQT_BOTHEDGE) {
266                 trigger |= bit;
267                 if (asic3_gpio_get(&asic->gpio, irq - asic->irq_base))
268                         edge &= ~bit;
269                 else
270                         edge |= bit;
271                 asic->irq_bothedge[(irq - asic->irq_base) >> 4] |= bit;
272         } else if (type == IRQT_LOW) {
273                 trigger &= ~bit;
274                 level &= ~bit;
275         } else if (type == IRQT_HIGH) {
276                 trigger &= ~bit;
277                 level |= bit;
278         } else {
279                 /*
280                  * if type == IRQT_NOEDGE, we should mask interrupts, but
281                  * be careful to not unmask them if mask was also called.
282                  * Probably need internal state for mask.
283                  */
284                 dev_notice(asic->dev, "irq type not changed\n");
285         }
286         asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
287                              level);
288         asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
289                              edge);
290         asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
291                              trigger);
292         spin_unlock_irqrestore(&asic->lock, flags);
293         return 0;
294 }
295
296 static struct irq_chip asic3_gpio_irq_chip = {
297         .name           = "ASIC3-GPIO",
298         .ack            = asic3_mask_gpio_irq,
299         .mask           = asic3_mask_gpio_irq,
300         .unmask         = asic3_unmask_gpio_irq,
301         .set_type       = asic3_gpio_irq_type,
302 };
303
304 static struct irq_chip asic3_irq_chip = {
305         .name           = "ASIC3",
306         .ack            = asic3_mask_irq,
307         .mask           = asic3_mask_irq,
308         .unmask         = asic3_unmask_irq,
309 };
310
311 static int __init asic3_irq_probe(struct platform_device *pdev)
312 {
313         struct asic3 *asic = platform_get_drvdata(pdev);
314         unsigned long clksel = 0;
315         unsigned int irq, irq_base;
316         int map_size;
317
318         asic->irq_nr = platform_get_irq(pdev, 0);
319         if (asic->irq_nr < 0)
320                 return asic->irq_nr;
321
322         /* turn on clock to IRQ controller */
323         clksel |= CLOCK_SEL_CX;
324         asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
325                              clksel);
326
327         irq_base = asic->irq_base;
328
329         for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
330                 if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
331                         set_irq_chip(irq, &asic3_gpio_irq_chip);
332                 else
333                         set_irq_chip(irq, &asic3_irq_chip);
334
335                 set_irq_chip_data(irq, asic);
336                 set_irq_handler(irq, handle_level_irq);
337                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
338         }
339
340         asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
341                              ASIC3_INTMASK_GINTMASK);
342
343         set_irq_chained_handler(asic->irq_nr, asic3_irq_demux);
344         set_irq_type(asic->irq_nr, IRQT_RISING);
345         set_irq_data(asic->irq_nr, asic);
346
347         return 0;
348 }
349
350 static void asic3_irq_remove(struct platform_device *pdev)
351 {
352         struct asic3 *asic = platform_get_drvdata(pdev);
353         unsigned int irq, irq_base;
354
355         irq_base = asic->irq_base;
356
357         for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
358                 set_irq_flags(irq, 0);
359                 set_irq_handler(irq, NULL);
360                 set_irq_chip(irq, NULL);
361                 set_irq_chip_data(irq, NULL);
362         }
363         set_irq_chained_handler(asic->irq_nr, NULL);
364 }
365
366 /* GPIOs */
367 static int asic3_gpio_direction(struct gpio_chip *chip,
368                                 unsigned offset, int out)
369 {
370         u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
371         unsigned int gpio_base;
372         unsigned long flags;
373         struct asic3 *asic;
374
375         asic = container_of(chip, struct asic3, gpio);
376         gpio_base = ASIC3_GPIO_TO_BASE(offset);
377
378         if (gpio_base > ASIC3_GPIO_D_BASE) {
379                 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
380                         gpio_base, offset);
381                 return -EINVAL;
382         }
383
384         spin_lock_irqsave(&asic->lock, flags);
385
386         out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
387
388         /* Input is 0, Output is 1 */
389         if (out)
390                 out_reg |= mask;
391         else
392                 out_reg &= ~mask;
393
394         asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
395
396         spin_unlock_irqrestore(&asic->lock, flags);
397
398         return 0;
399
400 }
401
402 static int asic3_gpio_direction_input(struct gpio_chip *chip,
403                                       unsigned offset)
404 {
405         return asic3_gpio_direction(chip, offset, 0);
406 }
407
408 static int asic3_gpio_direction_output(struct gpio_chip *chip,
409                                        unsigned offset, int value)
410 {
411         return asic3_gpio_direction(chip, offset, 1);
412 }
413
414 static int asic3_gpio_get(struct gpio_chip *chip,
415                           unsigned offset)
416 {
417         unsigned int gpio_base;
418         u32 mask = ASIC3_GPIO_TO_MASK(offset);
419         struct asic3 *asic;
420
421         asic = container_of(chip, struct asic3, gpio);
422         gpio_base = ASIC3_GPIO_TO_BASE(offset);
423
424         if (gpio_base > ASIC3_GPIO_D_BASE) {
425                 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
426                         gpio_base, offset);
427                 return -EINVAL;
428         }
429
430         return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask;
431 }
432
433 static void asic3_gpio_set(struct gpio_chip *chip,
434                            unsigned offset, int value)
435 {
436         u32 mask, out_reg;
437         unsigned int gpio_base;
438         unsigned long flags;
439         struct asic3 *asic;
440
441         asic = container_of(chip, struct asic3, gpio);
442         gpio_base = ASIC3_GPIO_TO_BASE(offset);
443
444         if (gpio_base > ASIC3_GPIO_D_BASE) {
445                 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
446                         gpio_base, offset);
447                 return;
448         }
449
450         mask = ASIC3_GPIO_TO_MASK(offset);
451
452         spin_lock_irqsave(&asic->lock, flags);
453
454         out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
455
456         if (value)
457                 out_reg |= mask;
458         else
459                 out_reg &= ~mask;
460
461         asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
462
463         spin_unlock_irqrestore(&asic->lock, flags);
464
465         return;
466 }
467
468 static __init int asic3_gpio_probe(struct platform_device *pdev,
469                                    u16 *gpio_config, int num)
470 {
471         struct asic3 *asic = platform_get_drvdata(pdev);
472         u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
473         u16 out_reg[ASIC3_NUM_GPIO_BANKS];
474         u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
475         int i;
476
477         memzero(alt_reg, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
478         memzero(out_reg, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
479         memzero(dir_reg, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
480
481         /* Enable all GPIOs */
482         asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
483         asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
484         asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
485         asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
486
487         for (i = 0; i < num; i++) {
488                 u8 alt, pin, dir, init, bank_num, bit_num;
489                 u16 config = gpio_config[i];
490
491                 pin = ASIC3_CONFIG_GPIO_PIN(config);
492                 alt = ASIC3_CONFIG_GPIO_ALT(config);
493                 dir = ASIC3_CONFIG_GPIO_DIR(config);
494                 init = ASIC3_CONFIG_GPIO_INIT(config);
495
496                 bank_num = ASIC3_GPIO_TO_BANK(pin);
497                 bit_num = ASIC3_GPIO_TO_BIT(pin);
498
499                 alt_reg[bank_num] |= (alt << bit_num);
500                 out_reg[bank_num] |= (init << bit_num);
501                 dir_reg[bank_num] |= (dir << bit_num);
502         }
503
504         for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
505                 asic3_write_register(asic,
506                                      ASIC3_BANK_TO_BASE(i) +
507                                      ASIC3_GPIO_DIRECTION,
508                                      dir_reg[i]);
509                 asic3_write_register(asic,
510                                      ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
511                                      out_reg[i]);
512                 asic3_write_register(asic,
513                                      ASIC3_BANK_TO_BASE(i) +
514                                      ASIC3_GPIO_ALT_FUNCTION,
515                                      alt_reg[i]);
516         }
517
518         return gpiochip_add(&asic->gpio);
519 }
520
521 static int asic3_gpio_remove(struct platform_device *pdev)
522 {
523         struct asic3 *asic = platform_get_drvdata(pdev);
524
525         return gpiochip_remove(&asic->gpio);
526 }
527
528
529 /* Core */
530 static int __init asic3_probe(struct platform_device *pdev)
531 {
532         struct asic3_platform_data *pdata = pdev->dev.platform_data;
533         struct asic3 *asic;
534         struct resource *mem;
535         unsigned long clksel;
536         int ret = 0;
537
538         asic = kzalloc(sizeof(struct asic3), GFP_KERNEL);
539         if (asic == NULL) {
540                 printk(KERN_ERR "kzalloc failed\n");
541                 return -ENOMEM;
542         }
543
544         spin_lock_init(&asic->lock);
545         platform_set_drvdata(pdev, asic);
546         asic->dev = &pdev->dev;
547
548         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
549         if (!mem) {
550                 ret = -ENOMEM;
551                 dev_err(asic->dev, "no MEM resource\n");
552                 goto out_free;
553         }
554
555         map_size = mem->end - mem->start + 1;
556         asic->mapping = ioremap(mem->start, map_size);
557         if (!asic->mapping) {
558                 ret = -ENOMEM;
559                 dev_err(asic->dev, "Couldn't ioremap\n");
560                 goto out_free;
561         }
562
563         asic->irq_base = pdata->irq_base;
564
565         /* calculate bus shift from mem resource */
566         asic->bus_shift = 2 - (map_size >> 12);
567
568         clksel = 0;
569         asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
570
571         ret = asic3_irq_probe(pdev);
572         if (ret < 0) {
573                 dev_err(asic->dev, "Couldn't probe IRQs\n");
574                 goto out_unmap;
575         }
576
577         asic->gpio.base = pdata->gpio_base;
578         asic->gpio.ngpio = ASIC3_NUM_GPIOS;
579         asic->gpio.get = asic3_gpio_get;
580         asic->gpio.set = asic3_gpio_set;
581         asic->gpio.direction_input = asic3_gpio_direction_input;
582         asic->gpio.direction_output = asic3_gpio_direction_output;
583
584         ret = asic3_gpio_probe(pdev,
585                                pdata->gpio_config,
586                                pdata->gpio_config_num);
587         if (ret < 0) {
588                 dev_err(asic->dev, "GPIO probe failed\n");
589                 goto out_irq;
590         }
591
592         dev_info(asic->dev, "ASIC3 Core driver\n");
593
594         return 0;
595
596  out_irq:
597         asic3_irq_remove(pdev);
598
599  out_unmap:
600         iounmap(asic->mapping);
601
602  out_free:
603         kfree(asic);
604
605         return ret;
606 }
607
608 static int asic3_remove(struct platform_device *pdev)
609 {
610         int ret;
611         struct asic3 *asic = platform_get_drvdata(pdev);
612
613         ret = asic3_gpio_remove(pdev);
614         if (ret < 0)
615                 return ret;
616         asic3_irq_remove(pdev);
617
618         asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
619
620         iounmap(asic->mapping);
621
622         kfree(asic);
623
624         return 0;
625 }
626
627 static void asic3_shutdown(struct platform_device *pdev)
628 {
629 }
630
631 static struct platform_driver asic3_device_driver = {
632         .driver         = {
633                 .name   = "asic3",
634         },
635         .remove         = __devexit_p(asic3_remove),
636         .shutdown       = asic3_shutdown,
637 };
638
639 static int __init asic3_init(void)
640 {
641         int retval = 0;
642         retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
643         return retval;
644 }
645
646 subsys_initcall(asic3_init);