mfd: asic3: enable DS1WM cell
[linux-2.6.git] / drivers / mfd / asic3.c
1 /*
2  * driver/mfd/asic3.c
3  *
4  * Compaq ASIC3 support.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * Copyright 2001 Compaq Computer Corporation.
11  * Copyright 2004-2005 Phil Blundell
12  * Copyright 2007-2008 OpenedHand Ltd.
13  *
14  * Authors: Phil Blundell <pb@handhelds.org>,
15  *          Samuel Ortiz <sameo@openedhand.com>
16  *
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/irq.h>
22 #include <linux/gpio.h>
23 #include <linux/io.h>
24 #include <linux/spinlock.h>
25 #include <linux/platform_device.h>
26
27 #include <linux/mfd/asic3.h>
28 #include <linux/mfd/core.h>
29 #include <linux/mfd/ds1wm.h>
30
31 enum {
32         ASIC3_CLOCK_SPI,
33         ASIC3_CLOCK_OWM,
34         ASIC3_CLOCK_PWM0,
35         ASIC3_CLOCK_PWM1,
36         ASIC3_CLOCK_LED0,
37         ASIC3_CLOCK_LED1,
38         ASIC3_CLOCK_LED2,
39         ASIC3_CLOCK_SD_HOST,
40         ASIC3_CLOCK_SD_BUS,
41         ASIC3_CLOCK_SMBUS,
42         ASIC3_CLOCK_EX0,
43         ASIC3_CLOCK_EX1,
44 };
45
46 struct asic3_clk {
47         int enabled;
48         unsigned int cdex;
49         unsigned long rate;
50 };
51
52 #define INIT_CDEX(_name, _rate) \
53         [ASIC3_CLOCK_##_name] = {               \
54                 .cdex = CLOCK_CDEX_##_name,     \
55                 .rate = _rate,                  \
56         }
57
58 struct asic3_clk asic3_clk_init[] __initdata = {
59         INIT_CDEX(SPI, 0),
60         INIT_CDEX(OWM, 5000000),
61         INIT_CDEX(PWM0, 0),
62         INIT_CDEX(PWM1, 0),
63         INIT_CDEX(LED0, 0),
64         INIT_CDEX(LED1, 0),
65         INIT_CDEX(LED2, 0),
66         INIT_CDEX(SD_HOST, 24576000),
67         INIT_CDEX(SD_BUS, 12288000),
68         INIT_CDEX(SMBUS, 0),
69         INIT_CDEX(EX0, 32768),
70         INIT_CDEX(EX1, 24576000),
71 };
72
73 struct asic3 {
74         void __iomem *mapping;
75         unsigned int bus_shift;
76         unsigned int irq_nr;
77         unsigned int irq_base;
78         spinlock_t lock;
79         u16 irq_bothedge[4];
80         struct gpio_chip gpio;
81         struct device *dev;
82
83         struct asic3_clk clocks[ARRAY_SIZE(asic3_clk_init)];
84 };
85
86 static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
87
88 static inline void asic3_write_register(struct asic3 *asic,
89                                  unsigned int reg, u32 value)
90 {
91         iowrite16(value, asic->mapping +
92                   (reg >> asic->bus_shift));
93 }
94
95 static inline u32 asic3_read_register(struct asic3 *asic,
96                                unsigned int reg)
97 {
98         return ioread16(asic->mapping +
99                         (reg >> asic->bus_shift));
100 }
101
102 void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set)
103 {
104         unsigned long flags;
105         u32 val;
106
107         spin_lock_irqsave(&asic->lock, flags);
108         val = asic3_read_register(asic, reg);
109         if (set)
110                 val |= bits;
111         else
112                 val &= ~bits;
113         asic3_write_register(asic, reg, val);
114         spin_unlock_irqrestore(&asic->lock, flags);
115 }
116
117 /* IRQs */
118 #define MAX_ASIC_ISR_LOOPS    20
119 #define ASIC3_GPIO_BASE_INCR \
120         (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
121
122 static void asic3_irq_flip_edge(struct asic3 *asic,
123                                 u32 base, int bit)
124 {
125         u16 edge;
126         unsigned long flags;
127
128         spin_lock_irqsave(&asic->lock, flags);
129         edge = asic3_read_register(asic,
130                                    base + ASIC3_GPIO_EDGE_TRIGGER);
131         edge ^= bit;
132         asic3_write_register(asic,
133                              base + ASIC3_GPIO_EDGE_TRIGGER, edge);
134         spin_unlock_irqrestore(&asic->lock, flags);
135 }
136
137 static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
138 {
139         int iter, i;
140         unsigned long flags;
141         struct asic3 *asic;
142
143         desc->chip->ack(irq);
144
145         asic = desc->handler_data;
146
147         for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
148                 u32 status;
149                 int bank;
150
151                 spin_lock_irqsave(&asic->lock, flags);
152                 status = asic3_read_register(asic,
153                                              ASIC3_OFFSET(INTR, P_INT_STAT));
154                 spin_unlock_irqrestore(&asic->lock, flags);
155
156                 /* Check all ten register bits */
157                 if ((status & 0x3ff) == 0)
158                         break;
159
160                 /* Handle GPIO IRQs */
161                 for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
162                         if (status & (1 << bank)) {
163                                 unsigned long base, istat;
164
165                                 base = ASIC3_GPIO_A_BASE
166                                        + bank * ASIC3_GPIO_BASE_INCR;
167
168                                 spin_lock_irqsave(&asic->lock, flags);
169                                 istat = asic3_read_register(asic,
170                                                             base +
171                                                             ASIC3_GPIO_INT_STATUS);
172                                 /* Clearing IntStatus */
173                                 asic3_write_register(asic,
174                                                      base +
175                                                      ASIC3_GPIO_INT_STATUS, 0);
176                                 spin_unlock_irqrestore(&asic->lock, flags);
177
178                                 for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
179                                         int bit = (1 << i);
180                                         unsigned int irqnr;
181
182                                         if (!(istat & bit))
183                                                 continue;
184
185                                         irqnr = asic->irq_base +
186                                                 (ASIC3_GPIOS_PER_BANK * bank)
187                                                 + i;
188                                         desc = irq_to_desc(irqnr);
189                                         desc->handle_irq(irqnr, desc);
190                                         if (asic->irq_bothedge[bank] & bit)
191                                                 asic3_irq_flip_edge(asic, base,
192                                                                     bit);
193                                 }
194                         }
195                 }
196
197                 /* Handle remaining IRQs in the status register */
198                 for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
199                         /* They start at bit 4 and go up */
200                         if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) {
201                                 desc = irq_to_desc(asic->irq_base + i);
202                                 desc->handle_irq(asic->irq_base + i,
203                                                  desc);
204                         }
205                 }
206         }
207
208         if (iter >= MAX_ASIC_ISR_LOOPS)
209                 dev_err(asic->dev, "interrupt processing overrun\n");
210 }
211
212 static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
213 {
214         int n;
215
216         n = (irq - asic->irq_base) >> 4;
217
218         return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
219 }
220
221 static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
222 {
223         return (irq - asic->irq_base) & 0xf;
224 }
225
226 static void asic3_mask_gpio_irq(unsigned int irq)
227 {
228         struct asic3 *asic = get_irq_chip_data(irq);
229         u32 val, bank, index;
230         unsigned long flags;
231
232         bank = asic3_irq_to_bank(asic, irq);
233         index = asic3_irq_to_index(asic, irq);
234
235         spin_lock_irqsave(&asic->lock, flags);
236         val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
237         val |= 1 << index;
238         asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
239         spin_unlock_irqrestore(&asic->lock, flags);
240 }
241
242 static void asic3_mask_irq(unsigned int irq)
243 {
244         struct asic3 *asic = get_irq_chip_data(irq);
245         int regval;
246         unsigned long flags;
247
248         spin_lock_irqsave(&asic->lock, flags);
249         regval = asic3_read_register(asic,
250                                      ASIC3_INTR_BASE +
251                                      ASIC3_INTR_INT_MASK);
252
253         regval &= ~(ASIC3_INTMASK_MASK0 <<
254                     (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
255
256         asic3_write_register(asic,
257                              ASIC3_INTR_BASE +
258                              ASIC3_INTR_INT_MASK,
259                              regval);
260         spin_unlock_irqrestore(&asic->lock, flags);
261 }
262
263 static void asic3_unmask_gpio_irq(unsigned int irq)
264 {
265         struct asic3 *asic = get_irq_chip_data(irq);
266         u32 val, bank, index;
267         unsigned long flags;
268
269         bank = asic3_irq_to_bank(asic, irq);
270         index = asic3_irq_to_index(asic, irq);
271
272         spin_lock_irqsave(&asic->lock, flags);
273         val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
274         val &= ~(1 << index);
275         asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
276         spin_unlock_irqrestore(&asic->lock, flags);
277 }
278
279 static void asic3_unmask_irq(unsigned int irq)
280 {
281         struct asic3 *asic = get_irq_chip_data(irq);
282         int regval;
283         unsigned long flags;
284
285         spin_lock_irqsave(&asic->lock, flags);
286         regval = asic3_read_register(asic,
287                                      ASIC3_INTR_BASE +
288                                      ASIC3_INTR_INT_MASK);
289
290         regval |= (ASIC3_INTMASK_MASK0 <<
291                    (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
292
293         asic3_write_register(asic,
294                              ASIC3_INTR_BASE +
295                              ASIC3_INTR_INT_MASK,
296                              regval);
297         spin_unlock_irqrestore(&asic->lock, flags);
298 }
299
300 static int asic3_gpio_irq_type(unsigned int irq, unsigned int type)
301 {
302         struct asic3 *asic = get_irq_chip_data(irq);
303         u32 bank, index;
304         u16 trigger, level, edge, bit;
305         unsigned long flags;
306
307         bank = asic3_irq_to_bank(asic, irq);
308         index = asic3_irq_to_index(asic, irq);
309         bit = 1<<index;
310
311         spin_lock_irqsave(&asic->lock, flags);
312         level = asic3_read_register(asic,
313                                     bank + ASIC3_GPIO_LEVEL_TRIGGER);
314         edge = asic3_read_register(asic,
315                                    bank + ASIC3_GPIO_EDGE_TRIGGER);
316         trigger = asic3_read_register(asic,
317                                       bank + ASIC3_GPIO_TRIGGER_TYPE);
318         asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit;
319
320         if (type == IRQ_TYPE_EDGE_RISING) {
321                 trigger |= bit;
322                 edge |= bit;
323         } else if (type == IRQ_TYPE_EDGE_FALLING) {
324                 trigger |= bit;
325                 edge &= ~bit;
326         } else if (type == IRQ_TYPE_EDGE_BOTH) {
327                 trigger |= bit;
328                 if (asic3_gpio_get(&asic->gpio, irq - asic->irq_base))
329                         edge &= ~bit;
330                 else
331                         edge |= bit;
332                 asic->irq_bothedge[(irq - asic->irq_base) >> 4] |= bit;
333         } else if (type == IRQ_TYPE_LEVEL_LOW) {
334                 trigger &= ~bit;
335                 level &= ~bit;
336         } else if (type == IRQ_TYPE_LEVEL_HIGH) {
337                 trigger &= ~bit;
338                 level |= bit;
339         } else {
340                 /*
341                  * if type == IRQ_TYPE_NONE, we should mask interrupts, but
342                  * be careful to not unmask them if mask was also called.
343                  * Probably need internal state for mask.
344                  */
345                 dev_notice(asic->dev, "irq type not changed\n");
346         }
347         asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
348                              level);
349         asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
350                              edge);
351         asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
352                              trigger);
353         spin_unlock_irqrestore(&asic->lock, flags);
354         return 0;
355 }
356
357 static struct irq_chip asic3_gpio_irq_chip = {
358         .name           = "ASIC3-GPIO",
359         .ack            = asic3_mask_gpio_irq,
360         .mask           = asic3_mask_gpio_irq,
361         .unmask         = asic3_unmask_gpio_irq,
362         .set_type       = asic3_gpio_irq_type,
363 };
364
365 static struct irq_chip asic3_irq_chip = {
366         .name           = "ASIC3",
367         .ack            = asic3_mask_irq,
368         .mask           = asic3_mask_irq,
369         .unmask         = asic3_unmask_irq,
370 };
371
372 static int __init asic3_irq_probe(struct platform_device *pdev)
373 {
374         struct asic3 *asic = platform_get_drvdata(pdev);
375         unsigned long clksel = 0;
376         unsigned int irq, irq_base;
377         int ret;
378
379         ret = platform_get_irq(pdev, 0);
380         if (ret < 0)
381                 return ret;
382         asic->irq_nr = ret;
383
384         /* turn on clock to IRQ controller */
385         clksel |= CLOCK_SEL_CX;
386         asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
387                              clksel);
388
389         irq_base = asic->irq_base;
390
391         for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
392                 if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
393                         set_irq_chip(irq, &asic3_gpio_irq_chip);
394                 else
395                         set_irq_chip(irq, &asic3_irq_chip);
396
397                 set_irq_chip_data(irq, asic);
398                 set_irq_handler(irq, handle_level_irq);
399                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
400         }
401
402         asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
403                              ASIC3_INTMASK_GINTMASK);
404
405         set_irq_chained_handler(asic->irq_nr, asic3_irq_demux);
406         set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING);
407         set_irq_data(asic->irq_nr, asic);
408
409         return 0;
410 }
411
412 static void asic3_irq_remove(struct platform_device *pdev)
413 {
414         struct asic3 *asic = platform_get_drvdata(pdev);
415         unsigned int irq, irq_base;
416
417         irq_base = asic->irq_base;
418
419         for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
420                 set_irq_flags(irq, 0);
421                 set_irq_handler(irq, NULL);
422                 set_irq_chip(irq, NULL);
423                 set_irq_chip_data(irq, NULL);
424         }
425         set_irq_chained_handler(asic->irq_nr, NULL);
426 }
427
428 /* GPIOs */
429 static int asic3_gpio_direction(struct gpio_chip *chip,
430                                 unsigned offset, int out)
431 {
432         u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
433         unsigned int gpio_base;
434         unsigned long flags;
435         struct asic3 *asic;
436
437         asic = container_of(chip, struct asic3, gpio);
438         gpio_base = ASIC3_GPIO_TO_BASE(offset);
439
440         if (gpio_base > ASIC3_GPIO_D_BASE) {
441                 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
442                         gpio_base, offset);
443                 return -EINVAL;
444         }
445
446         spin_lock_irqsave(&asic->lock, flags);
447
448         out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
449
450         /* Input is 0, Output is 1 */
451         if (out)
452                 out_reg |= mask;
453         else
454                 out_reg &= ~mask;
455
456         asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
457
458         spin_unlock_irqrestore(&asic->lock, flags);
459
460         return 0;
461
462 }
463
464 static int asic3_gpio_direction_input(struct gpio_chip *chip,
465                                       unsigned offset)
466 {
467         return asic3_gpio_direction(chip, offset, 0);
468 }
469
470 static int asic3_gpio_direction_output(struct gpio_chip *chip,
471                                        unsigned offset, int value)
472 {
473         return asic3_gpio_direction(chip, offset, 1);
474 }
475
476 static int asic3_gpio_get(struct gpio_chip *chip,
477                           unsigned offset)
478 {
479         unsigned int gpio_base;
480         u32 mask = ASIC3_GPIO_TO_MASK(offset);
481         struct asic3 *asic;
482
483         asic = container_of(chip, struct asic3, gpio);
484         gpio_base = ASIC3_GPIO_TO_BASE(offset);
485
486         if (gpio_base > ASIC3_GPIO_D_BASE) {
487                 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
488                         gpio_base, offset);
489                 return -EINVAL;
490         }
491
492         return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask;
493 }
494
495 static void asic3_gpio_set(struct gpio_chip *chip,
496                            unsigned offset, int value)
497 {
498         u32 mask, out_reg;
499         unsigned int gpio_base;
500         unsigned long flags;
501         struct asic3 *asic;
502
503         asic = container_of(chip, struct asic3, gpio);
504         gpio_base = ASIC3_GPIO_TO_BASE(offset);
505
506         if (gpio_base > ASIC3_GPIO_D_BASE) {
507                 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
508                         gpio_base, offset);
509                 return;
510         }
511
512         mask = ASIC3_GPIO_TO_MASK(offset);
513
514         spin_lock_irqsave(&asic->lock, flags);
515
516         out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
517
518         if (value)
519                 out_reg |= mask;
520         else
521                 out_reg &= ~mask;
522
523         asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
524
525         spin_unlock_irqrestore(&asic->lock, flags);
526
527         return;
528 }
529
530 static __init int asic3_gpio_probe(struct platform_device *pdev,
531                                    u16 *gpio_config, int num)
532 {
533         struct asic3 *asic = platform_get_drvdata(pdev);
534         u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
535         u16 out_reg[ASIC3_NUM_GPIO_BANKS];
536         u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
537         int i;
538
539         memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
540         memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
541         memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
542
543         /* Enable all GPIOs */
544         asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
545         asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
546         asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
547         asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
548
549         for (i = 0; i < num; i++) {
550                 u8 alt, pin, dir, init, bank_num, bit_num;
551                 u16 config = gpio_config[i];
552
553                 pin = ASIC3_CONFIG_GPIO_PIN(config);
554                 alt = ASIC3_CONFIG_GPIO_ALT(config);
555                 dir = ASIC3_CONFIG_GPIO_DIR(config);
556                 init = ASIC3_CONFIG_GPIO_INIT(config);
557
558                 bank_num = ASIC3_GPIO_TO_BANK(pin);
559                 bit_num = ASIC3_GPIO_TO_BIT(pin);
560
561                 alt_reg[bank_num] |= (alt << bit_num);
562                 out_reg[bank_num] |= (init << bit_num);
563                 dir_reg[bank_num] |= (dir << bit_num);
564         }
565
566         for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
567                 asic3_write_register(asic,
568                                      ASIC3_BANK_TO_BASE(i) +
569                                      ASIC3_GPIO_DIRECTION,
570                                      dir_reg[i]);
571                 asic3_write_register(asic,
572                                      ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
573                                      out_reg[i]);
574                 asic3_write_register(asic,
575                                      ASIC3_BANK_TO_BASE(i) +
576                                      ASIC3_GPIO_ALT_FUNCTION,
577                                      alt_reg[i]);
578         }
579
580         return gpiochip_add(&asic->gpio);
581 }
582
583 static int asic3_gpio_remove(struct platform_device *pdev)
584 {
585         struct asic3 *asic = platform_get_drvdata(pdev);
586
587         return gpiochip_remove(&asic->gpio);
588 }
589
590 static int asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk)
591 {
592         unsigned long flags;
593         u32 cdex;
594
595         spin_lock_irqsave(&asic->lock, flags);
596         if (clk->enabled++ == 0) {
597                 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
598                 cdex |= clk->cdex;
599                 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
600         }
601         spin_unlock_irqrestore(&asic->lock, flags);
602
603         return 0;
604 }
605
606 static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk)
607 {
608         unsigned long flags;
609         u32 cdex;
610
611         WARN_ON(clk->enabled == 0);
612
613         spin_lock_irqsave(&asic->lock, flags);
614         if (--clk->enabled == 0) {
615                 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
616                 cdex &= ~clk->cdex;
617                 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
618         }
619         spin_unlock_irqrestore(&asic->lock, flags);
620 }
621
622 /* MFD cells (SPI, PWM, LED, DS1WM, MMC) */
623 static struct ds1wm_driver_data ds1wm_pdata = {
624         .active_high = 1,
625 };
626
627 static struct resource ds1wm_resources[] = {
628         {
629                 .start = ASIC3_OWM_BASE,
630                 .end   = ASIC3_OWM_BASE + 0x13,
631                 .flags = IORESOURCE_MEM,
632         },
633         {
634                 .start = ASIC3_IRQ_OWM,
635                 .start = ASIC3_IRQ_OWM,
636                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
637         },
638 };
639
640 static int ds1wm_enable(struct platform_device *pdev)
641 {
642         struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
643
644         /* Turn on external clocks and the OWM clock */
645         asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
646         asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
647         asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
648         msleep(1);
649
650         /* Reset and enable DS1WM */
651         asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
652                            ASIC3_EXTCF_OWM_RESET, 1);
653         msleep(1);
654         asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
655                            ASIC3_EXTCF_OWM_RESET, 0);
656         msleep(1);
657         asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
658                            ASIC3_EXTCF_OWM_EN, 1);
659         msleep(1);
660
661         return 0;
662 }
663
664 static int ds1wm_disable(struct platform_device *pdev)
665 {
666         struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
667
668         asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
669                            ASIC3_EXTCF_OWM_EN, 0);
670
671         asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
672         asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
673         asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
674
675         return 0;
676 }
677
678 static struct mfd_cell asic3_cell_ds1wm = {
679         .name          = "ds1wm",
680         .enable        = ds1wm_enable,
681         .disable       = ds1wm_disable,
682         .driver_data   = &ds1wm_pdata,
683         .num_resources = ARRAY_SIZE(ds1wm_resources),
684         .resources     = ds1wm_resources,
685 };
686
687 static int __init asic3_mfd_probe(struct platform_device *pdev,
688                                   struct resource *mem)
689 {
690         struct asic3 *asic = platform_get_drvdata(pdev);
691         int ret;
692
693         /* DS1WM */
694         asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
695                            ASIC3_EXTCF_OWM_SMB, 0);
696
697         ds1wm_resources[0].start >>= asic->bus_shift;
698         ds1wm_resources[0].end   >>= asic->bus_shift;
699
700         asic3_cell_ds1wm.platform_data = &asic3_cell_ds1wm;
701         asic3_cell_ds1wm.data_size = sizeof(asic3_cell_ds1wm);
702
703         ret = mfd_add_devices(&pdev->dev, pdev->id,
704                         &asic3_cell_ds1wm, 1, mem, asic->irq_base);
705
706         return ret;
707 }
708
709 static void asic3_mfd_remove(struct platform_device *pdev)
710 {
711         mfd_remove_devices(&pdev->dev);
712 }
713
714 /* Core */
715 static int __init asic3_probe(struct platform_device *pdev)
716 {
717         struct asic3_platform_data *pdata = pdev->dev.platform_data;
718         struct asic3 *asic;
719         struct resource *mem;
720         unsigned long clksel;
721         int ret = 0;
722
723         asic = kzalloc(sizeof(struct asic3), GFP_KERNEL);
724         if (asic == NULL) {
725                 printk(KERN_ERR "kzalloc failed\n");
726                 return -ENOMEM;
727         }
728
729         spin_lock_init(&asic->lock);
730         platform_set_drvdata(pdev, asic);
731         asic->dev = &pdev->dev;
732
733         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
734         if (!mem) {
735                 ret = -ENOMEM;
736                 dev_err(asic->dev, "no MEM resource\n");
737                 goto out_free;
738         }
739
740         asic->mapping = ioremap(mem->start, resource_size(mem));
741         if (!asic->mapping) {
742                 ret = -ENOMEM;
743                 dev_err(asic->dev, "Couldn't ioremap\n");
744                 goto out_free;
745         }
746
747         asic->irq_base = pdata->irq_base;
748
749         /* calculate bus shift from mem resource */
750         asic->bus_shift = 2 - (resource_size(mem) >> 12);
751
752         clksel = 0;
753         asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
754
755         ret = asic3_irq_probe(pdev);
756         if (ret < 0) {
757                 dev_err(asic->dev, "Couldn't probe IRQs\n");
758                 goto out_unmap;
759         }
760
761         asic->gpio.base = pdata->gpio_base;
762         asic->gpio.ngpio = ASIC3_NUM_GPIOS;
763         asic->gpio.get = asic3_gpio_get;
764         asic->gpio.set = asic3_gpio_set;
765         asic->gpio.direction_input = asic3_gpio_direction_input;
766         asic->gpio.direction_output = asic3_gpio_direction_output;
767
768         ret = asic3_gpio_probe(pdev,
769                                pdata->gpio_config,
770                                pdata->gpio_config_num);
771         if (ret < 0) {
772                 dev_err(asic->dev, "GPIO probe failed\n");
773                 goto out_irq;
774         }
775
776         /* Making a per-device copy is only needed for the
777          * theoretical case of multiple ASIC3s on one board:
778          */
779         memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init));
780
781         asic3_mfd_probe(pdev, mem);
782
783         dev_info(asic->dev, "ASIC3 Core driver\n");
784
785         return 0;
786
787  out_irq:
788         asic3_irq_remove(pdev);
789
790  out_unmap:
791         iounmap(asic->mapping);
792
793  out_free:
794         kfree(asic);
795
796         return ret;
797 }
798
799 static int asic3_remove(struct platform_device *pdev)
800 {
801         int ret;
802         struct asic3 *asic = platform_get_drvdata(pdev);
803
804         asic3_mfd_remove(pdev);
805
806         ret = asic3_gpio_remove(pdev);
807         if (ret < 0)
808                 return ret;
809         asic3_irq_remove(pdev);
810
811         asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
812
813         iounmap(asic->mapping);
814
815         kfree(asic);
816
817         return 0;
818 }
819
820 static void asic3_shutdown(struct platform_device *pdev)
821 {
822 }
823
824 static struct platform_driver asic3_device_driver = {
825         .driver         = {
826                 .name   = "asic3",
827         },
828         .remove         = __devexit_p(asic3_remove),
829         .shutdown       = asic3_shutdown,
830 };
831
832 static int __init asic3_init(void)
833 {
834         int retval = 0;
835         retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
836         return retval;
837 }
838
839 subsys_initcall(asic3_init);