media: soc_camera: tegra: fix one building warning
[linux-2.6.git] / drivers / media / video / tegra_v4l2_camera.c
1 /*
2  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
15  */
16
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/clk.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/nvhost.h>
23
24 #include <mach/iomap.h>
25
26 #include <media/soc_camera.h>
27 #include <media/soc_mediabus.h>
28 #include <media/videobuf2-dma-nvmap.h>
29 #include <media/tegra_v4l2_camera.h>
30
31 #include "dev.h"
32 #include "bus_client.h"
33 #include "host1x/host1x_syncpt.h"
34
35 #define TEGRA_CAM_DRV_NAME "vi"
36 #define TEGRA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
37
38 #define TEGRA_SYNCPT_VI_WAIT_TIMEOUT                    200
39 #define TEGRA_SYNCPT_CSI_WAIT_TIMEOUT                   200
40
41 #define TEGRA_SYNCPT_RETRY_COUNT                        10
42
43 #define TEGRA_VIP_H_ACTIVE_START                        0x98
44 #define TEGRA_VIP_V_ACTIVE_START                        0x10
45
46 /* SYNCPTs 12-17 are reserved for VI. */
47 #define TEGRA_VI_SYNCPT_VI                              NVSYNCPT_VI_ISP_2
48 #define TEGRA_VI_SYNCPT_CSI                             NVSYNCPT_VI_ISP_3
49
50 /* Tegra CSI-MIPI registers. */
51 #define TEGRA_VI_OUT_1_INCR_SYNCPT                      0x0000
52 #define TEGRA_VI_OUT_1_INCR_SYNCPT_CNTRL                0x0004
53 #define TEGRA_VI_OUT_1_INCR_SYNCPT_ERROR                0x0008
54 #define TEGRA_VI_OUT_2_INCR_SYNCPT                      0x0020
55 #define TEGRA_VI_OUT_2_INCR_SYNCPT_CNTRL                0x0024
56 #define TEGRA_VI_OUT_2_INCR_SYNCPT_ERROR                0x0028
57 #define TEGRA_VI_MISC_INCR_SYNCPT                       0x0040
58 #define TEGRA_VI_MISC_INCR_SYNCPT_CNTRL                 0x0044
59 #define TEGRA_VI_MISC_INCR_SYNCPT_ERROR                 0x0048
60 #define TEGRA_VI_CONT_SYNCPT_OUT_1                      0x0060
61 #define TEGRA_VI_CONT_SYNCPT_OUT_2                      0x0064
62 #define TEGRA_VI_CONT_SYNCPT_VIP_VSYNC                  0x0068
63 #define TEGRA_VI_CONT_SYNCPT_VI2EPP                     0x006c
64 #define TEGRA_VI_CONT_SYNCPT_CSI_PPA_FRAME_START        0x0070
65 #define TEGRA_VI_CONT_SYNCPT_CSI_PPA_FRAME_END          0x0074
66 #define TEGRA_VI_CONT_SYNCPT_CSI_PPB_FRAME_START        0x0078
67 #define TEGRA_VI_CONT_SYNCPT_CSI_PPB_FRAME_END          0x007c
68 #define TEGRA_VI_CTXSW                                  0x0080
69 #define TEGRA_VI_INTSTATUS                              0x0084
70 #define TEGRA_VI_VI_INPUT_CONTROL                       0x0088
71 #define TEGRA_VI_VI_CORE_CONTROL                        0x008c
72 #define TEGRA_VI_VI_FIRST_OUTPUT_CONTROL                0x0090
73 #define TEGRA_VI_VI_SECOND_OUTPUT_CONTROL               0x0094
74 #define TEGRA_VI_HOST_INPUT_FRAME_SIZE                  0x0098
75 #define TEGRA_VI_HOST_H_ACTIVE                          0x009c
76 #define TEGRA_VI_HOST_V_ACTIVE                          0x00a0
77 #define TEGRA_VI_VIP_H_ACTIVE                           0x00a4
78 #define TEGRA_VI_VIP_V_ACTIVE                           0x00a8
79 #define TEGRA_VI_VI_PEER_CONTROL                        0x00ac
80 #define TEGRA_VI_VI_DMA_SELECT                          0x00b0
81 #define TEGRA_VI_HOST_DMA_WRITE_BUFFER                  0x00b4
82 #define TEGRA_VI_HOST_DMA_BASE_ADDRESS                  0x00b8
83 #define TEGRA_VI_HOST_DMA_WRITE_BUFFER_STATUS           0x00bc
84 #define TEGRA_VI_HOST_DMA_WRITE_PEND_BUFCOUNT           0x00c0
85 #define TEGRA_VI_VB0_START_ADDRESS_FIRST                0x00c4
86 #define TEGRA_VI_VB0_BASE_ADDRESS_FIRST                 0x00c8
87 #define TEGRA_VI_VB0_START_ADDRESS_U                    0x00cc
88 #define TEGRA_VI_VB0_BASE_ADDRESS_U                     0x00d0
89 #define TEGRA_VI_VB0_START_ADDRESS_V                    0x00d4
90 #define TEGRA_VI_VB0_BASE_ADDRESS_V                     0x00d8
91 #define TEGRA_VI_VB_SCRATCH_ADDRESS_UV                  0x00dc
92 #define TEGRA_VI_FIRST_OUTPUT_FRAME_SIZE                0x00e0
93 #define TEGRA_VI_VB0_COUNT_FIRST                        0x00e4
94 #define TEGRA_VI_VB0_SIZE_FIRST                         0x00e8
95 #define TEGRA_VI_VB0_BUFFER_STRIDE_FIRST                0x00ec
96 #define TEGRA_VI_VB0_START_ADDRESS_SECOND               0x00f0
97 #define TEGRA_VI_VB0_BASE_ADDRESS_SECOND                0x00f4
98 #define TEGRA_VI_SECOND_OUTPUT_FRAME_SIZE               0x00f8
99 #define TEGRA_VI_VB0_COUNT_SECOND                       0x00fc
100 #define TEGRA_VI_VB0_SIZE_SECOND                        0x0100
101 #define TEGRA_VI_VB0_BUFFER_STRIDE_SECOND               0x0104
102 #define TEGRA_VI_H_LPF_CONTROL                          0x0108
103 #define TEGRA_VI_H_DOWNSCALE_CONTROL                    0x010c
104 #define TEGRA_VI_V_DOWNSCALE_CONTROL                    0x0110
105 #define TEGRA_VI_CSC_Y                                  0x0114
106 #define TEGRA_VI_CSC_UV_R                               0x0118
107 #define TEGRA_VI_CSC_UV_G                               0x011c
108 #define TEGRA_VI_CSC_UV_B                               0x0120
109 #define TEGRA_VI_CSC_ALPHA                              0x0124
110 #define TEGRA_VI_HOST_VSYNC                             0x0128
111 #define TEGRA_VI_COMMAND                                0x012c
112 #define TEGRA_VI_HOST_FIFO_STATUS                       0x0130
113 #define TEGRA_VI_INTERRUPT_MASK                         0x0134
114 #define TEGRA_VI_INTERRUPT_TYPE_SELECT                  0x0138
115 #define TEGRA_VI_INTERRUPT_POLARITY_SELECT              0x013c
116 #define TEGRA_VI_INTERRUPT_STATUS                       0x0140
117 #define TEGRA_VI_VIP_INPUT_STATUS                       0x0144
118 #define TEGRA_VI_VIDEO_BUFFER_STATUS                    0x0148
119 #define TEGRA_VI_SYNC_OUTPUT                            0x014c
120 #define TEGRA_VI_VVS_OUTPUT_DELAY                       0x0150
121 #define TEGRA_VI_PWM_CONTROL                            0x0154
122 #define TEGRA_VI_PWM_SELECT_PULSE_A                     0x0158
123 #define TEGRA_VI_PWM_SELECT_PULSE_B                     0x015c
124 #define TEGRA_VI_PWM_SELECT_PULSE_C                     0x0160
125 #define TEGRA_VI_PWM_SELECT_PULSE_D                     0x0164
126 #define TEGRA_VI_VI_DATA_INPUT_CONTROL                  0x0168
127 #define TEGRA_VI_PIN_INPUT_ENABLE                       0x016c
128 #define TEGRA_VI_PIN_OUTPUT_ENABLE                      0x0170
129 #define TEGRA_VI_PIN_INVERSION                          0x0174
130 #define TEGRA_VI_PIN_INPUT_DATA                         0x0178
131 #define TEGRA_VI_PIN_OUTPUT_DATA                        0x017c
132 #define TEGRA_VI_PIN_OUTPUT_SELECT                      0x0180
133 #define TEGRA_VI_RAISE_VIP_BUFFER_FIRST_OUTPUT          0x0184
134 #define TEGRA_VI_RAISE_VIP_FRAME_FIRST_OUTPUT           0x0188
135 #define TEGRA_VI_RAISE_VIP_BUFFER_SECOND_OUTPUT         0x018c
136 #define TEGRA_VI_RAISE_VIP_FRAME_SECOND_OUTPUT          0x0190
137 #define TEGRA_VI_RAISE_HOST_FIRST_OUTPUT                0x0194
138 #define TEGRA_VI_RAISE_HOST_SECOND_OUTPUT               0x0198
139 #define TEGRA_VI_RAISE_EPP                              0x019c
140 #define TEGRA_VI_CAMERA_CONTROL                         0x01a0
141 #define TEGRA_VI_VI_ENABLE                              0x01a4
142 #define TEGRA_VI_VI_ENABLE_2                            0x01a8
143 #define TEGRA_VI_VI_RAISE                               0x01ac
144 #define TEGRA_VI_Y_FIFO_WRITE                           0x01b0
145 #define TEGRA_VI_U_FIFO_WRITE                           0x01b4
146 #define TEGRA_VI_V_FIFO_WRITE                           0x01b8
147 #define TEGRA_VI_VI_MCCIF_FIFOCTRL                      0x01bc
148 #define TEGRA_VI_TIMEOUT_WCOAL_VI                       0x01c0
149 #define TEGRA_VI_MCCIF_VIRUV_HP                         0x01c4
150 #define TEGRA_VI_MCCIF_VIWSB_HP                         0x01c8
151 #define TEGRA_VI_MCCIF_VIWU_HP                          0x01cc
152 #define TEGRA_VI_MCCIF_VIWV_HP                          0x01d0
153 #define TEGRA_VI_MCCIF_VIWY_HP                          0x01d4
154 #define TEGRA_VI_CSI_PPA_RAISE_FRAME_START              0x01d8
155 #define TEGRA_VI_CSI_PPA_RAISE_FRAME_END                0x01dc
156 #define TEGRA_VI_CSI_PPB_RAISE_FRAME_START              0x01e0
157 #define TEGRA_VI_CSI_PBB_RAISE_FRAME_END                0x01e4
158 #define TEGRA_VI_CSI_PPA_H_ACTIVE                       0x01e8
159 #define TEGRA_VI_CSI_PPA_V_ACTIVE                       0x01ec
160 #define TEGRA_VI_CSI_PPB_H_ACTIVE                       0x01f0
161 #define TEGRA_VI_CSI_PPB_V_ACTIVE                       0x01f4
162 #define TEGRA_VI_ISP_H_ACTIVE                           0x01f8
163 #define TEGRA_VI_ISP_V_ACTIVE                           0x01fc
164 #define TEGRA_VI_STREAM_1_RESOURCE_DEFINE               0x0200
165 #define TEGRA_VI_STREAM_2_RESOURCE_DEFINE               0x0204
166 #define TEGRA_VI_RAISE_STREAM_1_DONE                    0x0208
167 #define TEGRA_VI_RAISE_STREAM_2_DONE                    0x020c
168 #define TEGRA_VI_TS_MODE                                0x0210
169 #define TEGRA_VI_TS_CONTROL                             0x0214
170 #define TEGRA_VI_TS_PACKET_COUNT                        0x0218
171 #define TEGRA_VI_TS_ERROR_COUNT                         0x021c
172 #define TEGRA_VI_TS_CPU_FLOW_CTL                        0x0220
173 #define TEGRA_VI_VB0_CHROMA_BUFFER_STRIDE_FIRST         0x0224
174 #define TEGRA_VI_VB0_CHROMA_LINE_STRIDE_FIRST           0x0228
175 #define TEGRA_VI_EPP_LINES_PER_BUFFER                   0x022c
176 #define TEGRA_VI_BUFFER_RELEASE_OUTPUT1                 0x0230
177 #define TEGRA_VI_BUFFER_RELEASE_OUTPUT2                 0x0234
178 #define TEGRA_VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1     0x0238
179 #define TEGRA_VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2     0x023c
180 #define TEGRA_VI_TERMINATE_BW_FIRST                     0x0240
181 #define TEGRA_VI_TERMINATE_BW_SECOND                    0x0244
182 #define TEGRA_VI_VB0_FIRST_BUFFER_ADDR_MODE             0x0248
183 #define TEGRA_VI_VB0_SECOND_BUFFER_ADDR_MODE            0x024c
184 #define TEGRA_VI_RESERVE_0                              0x0250
185 #define TEGRA_VI_RESERVE_1                              0x0254
186 #define TEGRA_VI_RESERVE_2                              0x0258
187 #define TEGRA_VI_RESERVE_3                              0x025c
188 #define TEGRA_VI_RESERVE_4                              0x0260
189 #define TEGRA_VI_MCCIF_VIRUV_HYST                       0x0264
190 #define TEGRA_VI_MCCIF_VIWSB_HYST                       0x0268
191 #define TEGRA_VI_MCCIF_VIWU_HYST                        0x026c
192 #define TEGRA_VI_MCCIF_VIWV_HYST                        0x0270
193 #define TEGRA_VI_MCCIF_VIWY_HYST                        0x0274
194
195 #define TEGRA_CSI_VI_INPUT_STREAM_CONTROL               0x0800
196 #define TEGRA_CSI_HOST_INPUT_STREAM_CONTROL             0x0808
197 #define TEGRA_CSI_INPUT_STREAM_A_CONTROL                0x0810
198 #define TEGRA_CSI_PIXEL_STREAM_A_CONTROL0               0x0818
199 #define TEGRA_CSI_PIXEL_STREAM_A_CONTROL1               0x081c
200 #define TEGRA_CSI_PIXEL_STREAM_A_WORD_COUNT             0x0820
201 #define TEGRA_CSI_PIXEL_STREAM_A_GAP                    0x0824
202 #define TEGRA_CSI_PIXEL_STREAM_PPA_COMMAND              0x0828
203 #define TEGRA_CSI_INPUT_STREAM_B_CONTROL                0x083c
204 #define TEGRA_CSI_PIXEL_STREAM_B_CONTROL0               0x0844
205 #define TEGRA_CSI_PIXEL_STREAM_B_CONTROL1               0x0848
206 #define TEGRA_CSI_PIXEL_STREAM_B_WORD_COUNT             0x084c
207 #define TEGRA_CSI_PIXEL_STREAM_B_GAP                    0x0850
208 #define TEGRA_CSI_PIXEL_STREAM_PPB_COMMAND              0x0854
209 #define TEGRA_CSI_PHY_CIL_COMMAND                       0x0868
210 #define TEGRA_CSI_PHY_CILA_CONTROL0                     0x086c
211 #define TEGRA_CSI_PHY_CILB_CONTROL0                     0x0870
212 #define TEGRA_CSI_CSI_PIXEL_PARSER_STATUS               0x0878
213 #define TEGRA_CSI_CSI_CIL_STATUS                        0x087c
214 #define TEGRA_CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK       0x0880
215 #define TEGRA_CSI_CSI_CIL_INTERRUPT_MASK                0x0884
216 #define TEGRA_CSI_CSI_READONLY_STATUS                   0x0888
217 #define TEGRA_CSI_ESCAPE_MODE_COMMAND                   0x088c
218 #define TEGRA_CSI_ESCAPE_MODE_DATA                      0x0890
219 #define TEGRA_CSI_CILA_PAD_CONFIG0                      0x0894
220 #define TEGRA_CSI_CILA_PAD_CONFIG1                      0x0898
221 #define TEGRA_CSI_CILB_PAD_CONFIG0                      0x089c
222 #define TEGRA_CSI_CILB_PAD_CONFIG1                      0x08a0
223 #define TEGRA_CSI_CIL_PAD_CONFIG                        0x08a4
224 #define TEGRA_CSI_CILA_MIPI_CAL_CONFIG                  0x08a8
225 #define TEGRA_CSI_CILB_MIPI_CAL_CONFIG                  0x08ac
226 #define TEGRA_CSI_CIL_MIPI_CAL_STATUS                   0x08b0
227 #define TEGRA_CSI_CLKEN_OVERRIDE                        0x08b4
228 #define TEGRA_CSI_DEBUG_CONTROL                         0x08b8
229 #define TEGRA_CSI_DEBUG_COUNTER_0                       0x08bc
230 #define TEGRA_CSI_DEBUG_COUNTER_1                       0x08c0
231 #define TEGRA_CSI_DEBUG_COUNTER_2                       0x08c4
232 #define TEGRA_CSI_PIXEL_STREAM_A_EXPECTED_FRAME         0x08c8
233 #define TEGRA_CSI_PIXEL_STREAM_B_EXPECTED_FRAME         0x08cc
234 #define TEGRA_CSI_DSI_MIPI_CAL_CONFIG                   0x08d0
235
236 #define TC_VI_REG_RD(DEV, REG) readl(DEV->vi_base + REG)
237 #define TC_VI_REG_WT(DEV, REG, VAL) writel(VAL, DEV->vi_base + REG)
238
239 #define tegra_camera_port_is_valid(port) \
240         (((port) >= TEGRA_CAMERA_PORT_CSI_A) && \
241          ((port) <= TEGRA_CAMERA_PORT_VIP))
242
243 #define tegra_camera_port_is_csi(port) \
244         (((port) == TEGRA_CAMERA_PORT_CSI_A) || \
245          ((port) == TEGRA_CAMERA_PORT_CSI_B))
246
247 /*
248  * Structures
249  */
250
251 /* buffer for one video frame */
252 struct tegra_buffer {
253         struct vb2_buffer               vb; /* v4l buffer must be first */
254         struct list_head                queue;
255
256         /*
257          * Various buffer addresses shadowed so we don't have to recalculate
258          * per frame.  These are calculated during videobuf_prepare.
259          */
260         dma_addr_t                      buffer_addr;
261         dma_addr_t                      buffer_addr_u;
262         dma_addr_t                      buffer_addr_v;
263         dma_addr_t                      start_addr;
264         dma_addr_t                      start_addr_u;
265         dma_addr_t                      start_addr_v;
266 };
267
268 struct tegra_camera_dev {
269         struct soc_camera_host          ici;
270         struct soc_camera_device        *icd;
271         struct nvhost_device            *ndev;
272         struct tegra_camera_platform_data *pdata;
273
274         struct clk                      *clk_vi;
275         struct clk                      *clk_vi_sensor;
276         struct clk                      *clk_csi;
277         struct clk                      *clk_isp;
278         struct clk                      *clk_csus;
279
280         void __iomem                    *vi_base;
281         spinlock_t                      videobuf_queue_lock;
282         struct list_head                capture;
283         struct vb2_buffer               *active;
284         struct vb2_alloc_ctx            *alloc_ctx;
285         enum v4l2_field                 field;
286         int                             sequence;
287
288         struct work_struct              work;
289         struct mutex                    work_mutex;
290
291         u32                             syncpt_vi;
292         u32                             syncpt_csi;
293
294         /* Debug */
295         int num_frames;
296 };
297
298 static const struct soc_mbus_pixelfmt tegra_camera_formats[] = {
299         {
300                 .fourcc                 = V4L2_PIX_FMT_UYVY,
301                 .name                   = "YUV422 (UYVY) packed",
302                 .bits_per_sample        = 16,
303                 .packing                = SOC_MBUS_PACKING_NONE,
304                 .order                  = SOC_MBUS_ORDER_LE,
305         },
306         {
307                 .fourcc                 = V4L2_PIX_FMT_VYUY,
308                 .name                   = "YUV422 (VYUY) packed",
309                 .bits_per_sample        = 16,
310                 .packing                = SOC_MBUS_PACKING_NONE,
311                 .order                  = SOC_MBUS_ORDER_LE,
312         },
313         {
314                 .fourcc                 = V4L2_PIX_FMT_YUYV,
315                 .name                   = "YUV422 (YUYV) packed",
316                 .bits_per_sample        = 16,
317                 .packing                = SOC_MBUS_PACKING_NONE,
318                 .order                  = SOC_MBUS_ORDER_LE,
319         },
320         {
321                 .fourcc                 = V4L2_PIX_FMT_YVYU,
322                 .name                   = "YUV422 (YVYU) packed",
323                 .bits_per_sample        = 16,
324                 .packing                = SOC_MBUS_PACKING_NONE,
325                 .order                  = SOC_MBUS_ORDER_LE,
326         },
327         {
328                 .fourcc                 = V4L2_PIX_FMT_YUV420,
329                 .name                   = "YUV420 (YU12) planar",
330                 .bits_per_sample        = 12,
331                 .packing                = SOC_MBUS_PACKING_NONE,
332                 .order                  = SOC_MBUS_ORDER_LE,
333         },
334         {
335                 .fourcc                 = V4L2_PIX_FMT_YVU420,
336                 .name                   = "YVU420 (YV12) planar",
337                 .bits_per_sample        = 12,
338                 .packing                = SOC_MBUS_PACKING_NONE,
339                 .order                  = SOC_MBUS_ORDER_LE,
340         },
341 };
342
343 static struct tegra_buffer *to_tegra_vb(struct vb2_buffer *vb)
344 {
345         return container_of(vb, struct tegra_buffer, vb);
346 }
347
348 static void tegra_camera_save_syncpts(struct tegra_camera_dev *pcdev)
349 {
350         pcdev->syncpt_csi =
351                 nvhost_syncpt_read_ext(pcdev->ndev,
352                                        TEGRA_VI_SYNCPT_CSI);
353
354         pcdev->syncpt_vi =
355                 nvhost_syncpt_read_ext(pcdev->ndev,
356                                        TEGRA_VI_SYNCPT_VI);
357 }
358
359 static void tegra_camera_incr_syncpts(struct tegra_camera_dev *pcdev)
360 {
361         nvhost_syncpt_cpu_incr_ext(pcdev->ndev,
362                                    TEGRA_VI_SYNCPT_CSI);
363
364         nvhost_syncpt_cpu_incr_ext(pcdev->ndev,
365                                    TEGRA_VI_SYNCPT_VI);
366 }
367
368 static void tegra_camera_capture_setup_csi_a(struct tegra_camera_dev *pcdev,
369                                              int input_format,
370                                              int yuv_input_format)
371 {
372         struct soc_camera_device *icd = pcdev->icd;
373         int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
374                                                 icd->current_fmt->host_fmt);
375
376         TC_VI_REG_WT(pcdev, TEGRA_VI_VI_CORE_CONTROL, 0x02000000);
377
378         TC_VI_REG_WT(pcdev, TEGRA_VI_VI_INPUT_CONTROL,
379                 (yuv_input_format << 8) |
380                 (input_format << 2));
381
382         TC_VI_REG_WT(pcdev, TEGRA_VI_H_DOWNSCALE_CONTROL, 0x00000004);
383         TC_VI_REG_WT(pcdev, TEGRA_VI_V_DOWNSCALE_CONTROL, 0x00000004);
384
385         /* CSI-A H_ACTIVE and V_ACTIVE */
386         TC_VI_REG_WT(pcdev, TEGRA_VI_CSI_PPA_H_ACTIVE,
387                      (icd->user_width << 16));
388         TC_VI_REG_WT(pcdev, TEGRA_VI_CSI_PPA_V_ACTIVE,
389                      (icd->user_height << 16));
390
391         /* CSI A */
392         TC_VI_REG_WT(pcdev, TEGRA_CSI_VI_INPUT_STREAM_CONTROL, 0x00000000);
393         TC_VI_REG_WT(pcdev, TEGRA_CSI_HOST_INPUT_STREAM_CONTROL, 0x00000000);
394         TC_VI_REG_WT(pcdev, TEGRA_CSI_INPUT_STREAM_A_CONTROL, 0x00000000);
395         TC_VI_REG_WT(pcdev, TEGRA_CSI_PIXEL_STREAM_A_CONTROL0, 0x00000000);
396         TC_VI_REG_WT(pcdev, TEGRA_CSI_PIXEL_STREAM_A_CONTROL1, 0x00000000);
397         TC_VI_REG_WT(pcdev, TEGRA_CSI_PIXEL_STREAM_A_WORD_COUNT, 0x00000000);
398         TC_VI_REG_WT(pcdev, TEGRA_CSI_PIXEL_STREAM_A_GAP, 0x00000000);
399         TC_VI_REG_WT(pcdev, TEGRA_CSI_PIXEL_STREAM_PPA_COMMAND, 0x00000000);
400
401         TC_VI_REG_WT(pcdev, TEGRA_CSI_CILA_PAD_CONFIG0, 0x00000000);
402         TC_VI_REG_WT(pcdev, TEGRA_CSI_CILA_PAD_CONFIG1, 0x00000000);
403         TC_VI_REG_WT(pcdev, TEGRA_CSI_CIL_PAD_CONFIG, 0x00000000);
404         TC_VI_REG_WT(pcdev, TEGRA_CSI_CILA_MIPI_CAL_CONFIG, 0x00000000);
405         TC_VI_REG_WT(pcdev, TEGRA_CSI_CIL_MIPI_CAL_STATUS, 0x00000000);
406         TC_VI_REG_WT(pcdev, TEGRA_CSI_CLKEN_OVERRIDE, 0x00000000);
407
408         /* pad1s enabled, virtual channel ID 00 */
409         TC_VI_REG_WT(pcdev, TEGRA_CSI_PIXEL_STREAM_A_CONTROL0,
410                 (0x1 << 16) | /* Output 1 pixel per clock */
411                 (0x1e << 8) | /* If hdr shows wrong fmt, use YUV422 */
412                 (0x1 << 7) | /* Check header CRC */
413                 (0x1 << 6) | /* Use word count field in the header */
414                 (0x1 << 5) | /* Look at data identifier byte in hdr */
415                 (0x1 << 4)); /* Expect packet header */
416
417         TC_VI_REG_WT(pcdev, TEGRA_CSI_PIXEL_STREAM_A_CONTROL1,
418                 0x1); /* Frame # for top field detect for interlaced */
419
420         TC_VI_REG_WT(pcdev, TEGRA_CSI_PIXEL_STREAM_A_WORD_COUNT,
421                 bytes_per_line);
422         TC_VI_REG_WT(pcdev, TEGRA_CSI_PIXEL_STREAM_A_GAP, 0x00140000);
423
424         TC_VI_REG_WT(pcdev, TEGRA_CSI_PIXEL_STREAM_A_EXPECTED_FRAME,
425                 (icd->user_height << 16) |
426                 (0x100 << 4) | /* Wait 0x100 vi clks for timeout */
427                 0x1); /* Enable line timeout */
428
429         TC_VI_REG_WT(pcdev, TEGRA_CSI_INPUT_STREAM_A_CONTROL,
430                      (0x3f << 16) | /* Skip packet threshold */
431                      (pcdev->pdata->lanes - 1));
432
433         /* Use 0x00000022 for continuous clock mode. */
434         TC_VI_REG_WT(pcdev, TEGRA_CSI_PHY_CILA_CONTROL0,
435                 (pcdev->pdata->continuous_clk << 5) |
436                 0x5); /* Clock settle time */
437
438         TC_VI_REG_WT(pcdev, TEGRA_VI_CONT_SYNCPT_CSI_PPA_FRAME_END,
439                 (0x1 << 8) | /* Enable continuous syncpt */
440                 TEGRA_VI_SYNCPT_CSI);
441
442         TC_VI_REG_WT(pcdev, TEGRA_VI_CONT_SYNCPT_OUT_1,
443                 (0x1 << 8) | /* Enable continuous syncpt */
444                 TEGRA_VI_SYNCPT_VI);
445
446         TC_VI_REG_WT(pcdev, TEGRA_CSI_PHY_CIL_COMMAND, 0x00020001);
447
448         TC_VI_REG_WT(pcdev, TEGRA_CSI_PIXEL_STREAM_PPA_COMMAND, 0x0000f002);
449 }
450
451 static void tegra_camera_capture_setup_csi_b(struct tegra_camera_dev *pcdev,
452                                              int input_format,
453                                              int yuv_input_format)
454 {
455         struct soc_camera_device *icd = pcdev->icd;
456         int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
457                                                 icd->current_fmt->host_fmt);
458
459         TC_VI_REG_WT(pcdev, TEGRA_VI_VI_CORE_CONTROL, 0x04000000);
460
461         TC_VI_REG_WT(pcdev, TEGRA_VI_VI_INPUT_CONTROL,
462                 (yuv_input_format << 8) |
463                 (input_format << 2));
464
465         TC_VI_REG_WT(pcdev, TEGRA_VI_H_DOWNSCALE_CONTROL, 0x00000008);
466         TC_VI_REG_WT(pcdev, TEGRA_VI_V_DOWNSCALE_CONTROL, 0x00000008);
467
468         /* CSI-B H_ACTIVE and V_ACTIVE */
469         TC_VI_REG_WT(pcdev, TEGRA_VI_CSI_PPB_H_ACTIVE,
470                 (icd->user_width << 16));
471         TC_VI_REG_WT(pcdev, TEGRA_VI_CSI_PPB_V_ACTIVE,
472                 (icd->user_height << 16));
473
474         /* CSI B */
475         TC_VI_REG_WT(pcdev, TEGRA_CSI_VI_INPUT_STREAM_CONTROL, 0x00000000);
476         TC_VI_REG_WT(pcdev, TEGRA_CSI_HOST_INPUT_STREAM_CONTROL, 0x00000000);
477         TC_VI_REG_WT(pcdev, TEGRA_CSI_INPUT_STREAM_B_CONTROL, 0x00000000);
478         TC_VI_REG_WT(pcdev, TEGRA_CSI_PIXEL_STREAM_B_CONTROL0, 0x00000000);
479         TC_VI_REG_WT(pcdev, TEGRA_CSI_PIXEL_STREAM_B_CONTROL1, 0x00000000);
480         TC_VI_REG_WT(pcdev, TEGRA_CSI_PIXEL_STREAM_B_WORD_COUNT, 0x00000000);
481         TC_VI_REG_WT(pcdev, TEGRA_CSI_PIXEL_STREAM_B_GAP, 0x00000000);
482         TC_VI_REG_WT(pcdev, TEGRA_CSI_PIXEL_STREAM_PPB_COMMAND, 0x00000000);
483
484         TC_VI_REG_WT(pcdev, TEGRA_CSI_CILB_PAD_CONFIG0, 0x00000000);
485         TC_VI_REG_WT(pcdev, TEGRA_CSI_CILB_PAD_CONFIG1, 0x00000000);
486         TC_VI_REG_WT(pcdev, TEGRA_CSI_CIL_PAD_CONFIG, 0x00000000);
487         TC_VI_REG_WT(pcdev, TEGRA_CSI_CILB_MIPI_CAL_CONFIG, 0x00000000);
488         TC_VI_REG_WT(pcdev, TEGRA_CSI_CIL_MIPI_CAL_STATUS, 0x00000000);
489         TC_VI_REG_WT(pcdev, TEGRA_CSI_CLKEN_OVERRIDE, 0x00000000);
490
491         /* pad1s enabled, virtual channel ID 00 */
492         TC_VI_REG_WT(pcdev, TEGRA_CSI_PIXEL_STREAM_B_CONTROL0,
493                 (0x1 << 16) | /* Output 1 pixel per clock */
494                 (0x1e << 8) | /* If hdr shows wrong fmt, use YUV422 */
495                 (0x1 << 7) | /* Check header CRC */
496                 (0x1 << 6) | /* Use word count field in the header */
497                 (0x1 << 5) | /* Look at data identifier byte in hdr */
498                 (0x1 << 4) | /* Expect packet header */
499                 0x1); /* Set PPB stream source to CSI B */
500
501         TC_VI_REG_WT(pcdev, TEGRA_CSI_PIXEL_STREAM_B_CONTROL1,
502                 0x1); /* Frame # for top field detect for interlaced */
503
504         TC_VI_REG_WT(pcdev, TEGRA_CSI_PIXEL_STREAM_B_WORD_COUNT,
505                 bytes_per_line);
506         TC_VI_REG_WT(pcdev, TEGRA_CSI_PIXEL_STREAM_B_GAP, 0x00140000);
507
508         TC_VI_REG_WT(pcdev, TEGRA_CSI_PIXEL_STREAM_B_EXPECTED_FRAME,
509                 (icd->user_height << 16) |
510                 (0x100 << 4) | /* Wait 0x100 vi clks for timeout */
511                 0x1); /* Enable line timeout */
512
513         TC_VI_REG_WT(pcdev, TEGRA_CSI_INPUT_STREAM_B_CONTROL,
514                      (0x3f << 16) | /* Skip packet threshold */
515                      (pcdev->pdata->lanes - 1));
516
517         /* Use 0x00000022 for continuous clock mode. */
518         TC_VI_REG_WT(pcdev, TEGRA_CSI_PHY_CILB_CONTROL0,
519                 (pcdev->pdata->continuous_clk << 5) |
520                 0x5); /* Clock settle time */
521
522         TC_VI_REG_WT(pcdev, TEGRA_VI_CONT_SYNCPT_CSI_PPB_FRAME_END,
523                 (0x1 << 8) | /* Enable continuous syncpt */
524                 TEGRA_VI_SYNCPT_CSI);
525
526         TC_VI_REG_WT(pcdev, TEGRA_VI_CONT_SYNCPT_OUT_1,
527                 (0x1 << 8) | /* Enable continuous syncpt */
528                 TEGRA_VI_SYNCPT_VI);
529
530         TC_VI_REG_WT(pcdev, TEGRA_CSI_PHY_CIL_COMMAND, 0x00010002);
531
532         TC_VI_REG_WT(pcdev, TEGRA_CSI_PIXEL_STREAM_PPB_COMMAND, 0x0000f002);
533 }
534
535 static void tegra_camera_capture_setup_vip(struct tegra_camera_dev *pcdev,
536                                              int input_format,
537                                              int yuv_input_format)
538 {
539         struct soc_camera_device *icd = pcdev->icd;
540
541         TC_VI_REG_WT(pcdev, TEGRA_VI_VI_CORE_CONTROL, 0x00000000);
542
543         TC_VI_REG_WT(pcdev, TEGRA_VI_VI_INPUT_CONTROL,
544                 (1 << 27) | /* field detect */
545                 (1 << 25) | /* hsync/vsync decoded from data (BT.656) */
546                 (yuv_input_format << 8) |
547                 (1 << 1) | /* VIP_INPUT_ENABLE */
548                 (input_format << 2));
549
550         TC_VI_REG_WT(pcdev, TEGRA_VI_H_DOWNSCALE_CONTROL, 0x00000000);
551         TC_VI_REG_WT(pcdev, TEGRA_VI_V_DOWNSCALE_CONTROL, 0x00000000);
552
553         /* VIP H_ACTIVE and V_ACTIVE */
554         TC_VI_REG_WT(pcdev, TEGRA_VI_VIP_H_ACTIVE,
555                 (icd->user_width << 16) |
556                 TEGRA_VIP_H_ACTIVE_START);
557         TC_VI_REG_WT(pcdev, TEGRA_VI_VIP_V_ACTIVE,
558                 (icd->user_height << 16) |
559                 TEGRA_VIP_V_ACTIVE_START);
560
561         /*
562          * For VIP, D9..D2 is mapped to the video decoder's P7..P0.
563          * Disable/mask out the other Dn wires.
564          */
565         TC_VI_REG_WT(pcdev, TEGRA_VI_PIN_INPUT_ENABLE, 0x000003fc);
566         TC_VI_REG_WT(pcdev, TEGRA_VI_VI_DATA_INPUT_CONTROL, 0x000003fc);
567         TC_VI_REG_WT(pcdev, TEGRA_VI_PIN_INVERSION, 0x00000000);
568
569         TC_VI_REG_WT(pcdev, TEGRA_VI_CONT_SYNCPT_VIP_VSYNC,
570                 (0x1 << 8) | /* Enable continuous syncpt */
571                 TEGRA_VI_SYNCPT_VI);
572
573         TC_VI_REG_WT(pcdev, TEGRA_VI_CAMERA_CONTROL, 0x00000004);
574 }
575
576 static void tegra_camera_capture_setup(struct tegra_camera_dev *pcdev)
577 {
578         struct soc_camera_device *icd = pcdev->icd;
579         const struct soc_camera_format_xlate *current_fmt = icd->current_fmt;
580         enum v4l2_mbus_pixelcode input_code = current_fmt->code;
581         u32 output_fourcc = current_fmt->host_fmt->fourcc;
582         int yuv_input_format = 0x0;
583         int input_format = 0x0; /* Default to YUV422 */
584         int yuv_output_format = 0x0;
585         int output_format = 0x3; /* Default to YUV422 */
586         int port = pcdev->pdata->port;
587         int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
588                                                 icd->current_fmt->host_fmt);
589
590         switch (input_code) {
591         case V4L2_MBUS_FMT_UYVY8_2X8:
592                 yuv_input_format = 0x2;
593                 break;
594         case V4L2_MBUS_FMT_VYUY8_2X8:
595                 yuv_input_format = 0x3;
596                 break;
597         case V4L2_MBUS_FMT_YUYV8_2X8:
598                 yuv_input_format = 0x0;
599                 break;
600         case V4L2_MBUS_FMT_YVYU8_2X8:
601                 yuv_input_format = 0x1;
602                 break;
603         default:
604                 BUG_ON(1);
605         }
606
607         switch (output_fourcc) {
608         case V4L2_PIX_FMT_UYVY:
609                 yuv_output_format = 0x0;
610                 break;
611         case V4L2_PIX_FMT_VYUY:
612                 yuv_output_format = 0x1;
613                 break;
614         case V4L2_PIX_FMT_YUYV:
615                 yuv_output_format = 0x2;
616                 break;
617         case V4L2_PIX_FMT_YVYU:
618                 yuv_output_format = 0x3;
619                 break;
620         case V4L2_PIX_FMT_YUV420:
621         case V4L2_PIX_FMT_YVU420:
622                 output_format = 0x6; /* YUV420 planar */
623                 break;
624         default:
625                 BUG_ON(1);
626         }
627
628         BUG_ON(!tegra_camera_port_is_valid(port));
629
630         /*
631          * Set up low pass filter.  Use 0x240 for chromaticity and 0x240
632          * for luminance, which is the default and means not to touch
633          * anything.
634          */
635         TC_VI_REG_WT(pcdev, TEGRA_VI_H_LPF_CONTROL, 0x02400240);
636
637         /* Set up raise-on-edge, so we get an interrupt on end of frame. */
638         TC_VI_REG_WT(pcdev, TEGRA_VI_VI_RAISE, 0x00000001);
639
640         if (port == TEGRA_CAMERA_PORT_CSI_A)
641                 tegra_camera_capture_setup_csi_a(pcdev, input_format,
642                                                  yuv_input_format);
643         else if (port == TEGRA_CAMERA_PORT_CSI_B)
644                 tegra_camera_capture_setup_csi_b(pcdev, input_format,
645                                                  yuv_input_format);
646         else
647                 tegra_camera_capture_setup_vip(pcdev, input_format,
648                                                yuv_input_format);
649
650         TC_VI_REG_WT(pcdev, TEGRA_VI_VI_FIRST_OUTPUT_CONTROL,
651                 (pcdev->pdata->flip_v ? (0x1 << 20) : 0) |
652                 (pcdev->pdata->flip_h ? (0x1 << 19) : 0) |
653                 (yuv_output_format << 17) |
654                 output_format);
655
656         /*
657          * Set up frame size.  Bits 31:16 are the number of lines, and
658          * bits 15:0 are the number of pixels per line.
659          */
660         TC_VI_REG_WT(pcdev, TEGRA_VI_FIRST_OUTPUT_FRAME_SIZE,
661                 (icd->user_height << 16) | icd->user_width);
662
663         /* First output memory enabled */
664         TC_VI_REG_WT(pcdev, TEGRA_VI_VI_ENABLE, 0x00000000);
665
666         /* Set the number of frames in the buffer. */
667         TC_VI_REG_WT(pcdev, TEGRA_VI_VB0_COUNT_FIRST, 0x00000001);
668
669         /* Set up buffer frame size. */
670         TC_VI_REG_WT(pcdev, TEGRA_VI_VB0_SIZE_FIRST,
671                 (icd->user_height << 16) | icd->user_width);
672
673         TC_VI_REG_WT(pcdev, TEGRA_VI_VB0_BUFFER_STRIDE_FIRST,
674                 (icd->user_height * bytes_per_line));
675
676         TC_VI_REG_WT(pcdev, TEGRA_VI_VI_ENABLE, 0x00000000);
677 }
678
679 static int tegra_camera_capture_start(struct tegra_camera_dev *pcdev,
680                                       struct tegra_buffer *buf)
681 {
682         struct soc_camera_device *icd = pcdev->icd;
683         int port = pcdev->pdata->port;
684         int err;
685
686         pcdev->syncpt_csi++;
687         pcdev->syncpt_vi++;
688
689         switch (icd->current_fmt->host_fmt->fourcc) {
690         case V4L2_PIX_FMT_YUV420:
691         case V4L2_PIX_FMT_YVU420:
692                 TC_VI_REG_WT(pcdev, TEGRA_VI_VB0_BASE_ADDRESS_U,
693                              buf->buffer_addr_u);
694                 TC_VI_REG_WT(pcdev, TEGRA_VI_VB0_START_ADDRESS_U,
695                              buf->start_addr_u);
696
697                 TC_VI_REG_WT(pcdev, TEGRA_VI_VB0_BASE_ADDRESS_V,
698                              buf->buffer_addr_v);
699                 TC_VI_REG_WT(pcdev, TEGRA_VI_VB0_START_ADDRESS_V,
700                              buf->start_addr_v);
701
702         case V4L2_PIX_FMT_UYVY:
703         case V4L2_PIX_FMT_VYUY:
704         case V4L2_PIX_FMT_YUYV:
705         case V4L2_PIX_FMT_YVYU:
706                 TC_VI_REG_WT(pcdev, TEGRA_VI_VB0_BASE_ADDRESS_FIRST,
707                              buf->buffer_addr);
708                 TC_VI_REG_WT(pcdev, TEGRA_VI_VB0_START_ADDRESS_FIRST,
709                              buf->start_addr);
710
711                 break;
712
713         default:
714                 BUG_ON(1);
715         }
716
717         BUG_ON(!tegra_camera_port_is_valid(port));
718
719         if (port == TEGRA_CAMERA_PORT_CSI_A)
720                 TC_VI_REG_WT(pcdev, TEGRA_CSI_PIXEL_STREAM_PPA_COMMAND,
721                              0x0000f005);
722         else if (port == TEGRA_CAMERA_PORT_CSI_B)
723                 TC_VI_REG_WT(pcdev, TEGRA_CSI_PIXEL_STREAM_PPB_COMMAND,
724                              0x0000f005);
725         else
726                 TC_VI_REG_WT(pcdev, TEGRA_VI_CAMERA_CONTROL,
727                              0x00000001);
728
729         /*
730          * Only wait on CSI frame end syncpt if we're using CSI.  Otherwise,
731          * wait on VIP VSYNC syncpt.
732          */
733         if (tegra_camera_port_is_csi(port))
734                 err = nvhost_syncpt_wait_timeout_ext(pcdev->ndev,
735                         TEGRA_VI_SYNCPT_CSI,
736                         pcdev->syncpt_csi,
737                         TEGRA_SYNCPT_CSI_WAIT_TIMEOUT,
738                         NULL);
739         else
740                 err = nvhost_syncpt_wait_timeout_ext(pcdev->ndev,
741                         TEGRA_VI_SYNCPT_VI,
742                         pcdev->syncpt_csi,
743                         TEGRA_SYNCPT_VI_WAIT_TIMEOUT,
744                         NULL);
745
746         if (!err)
747                 return 0;
748
749         if (tegra_camera_port_is_csi(port)) {
750                 u32 ppstatus;
751                 u32 cilstatus;
752                 u32 rostatus;
753
754                 dev_err(&pcdev->ndev->dev, "Timeout on CSI syncpt\n");
755                 dev_err(&pcdev->ndev->dev, "buffer_addr = 0x%08x\n",
756                         buf->buffer_addr);
757
758                 ppstatus = TC_VI_REG_RD(pcdev,
759                         TEGRA_CSI_CSI_PIXEL_PARSER_STATUS);
760                 cilstatus = TC_VI_REG_RD(pcdev,
761                          TEGRA_CSI_CSI_CIL_STATUS);
762                 rostatus = TC_VI_REG_RD(pcdev,
763                         TEGRA_CSI_CSI_READONLY_STATUS);
764
765                 dev_err(&pcdev->ndev->dev,
766                         "PPSTATUS = 0x%08x, "
767                         "CILSTATUS = 0x%08x, "
768                         "ROSTATUS = 0x%08x\n",
769                         ppstatus, cilstatus, rostatus);
770         } else {
771                 u32 vip_input_status;
772
773                 dev_err(&pcdev->ndev->dev, "Timeout on VI syncpt\n");
774                 dev_err(&pcdev->ndev->dev, "buffer_addr = 0x%08x\n",
775                         buf->buffer_addr);
776
777                 vip_input_status = TC_VI_REG_RD(pcdev,
778                         TEGRA_VI_VIP_INPUT_STATUS);
779
780                 dev_err(&pcdev->ndev->dev,
781                         "VIP_INPUT_STATUS = 0x%08x\n",
782                         vip_input_status);
783         }
784
785         return err;
786 }
787
788 static int tegra_camera_capture_stop(struct tegra_camera_dev *pcdev)
789 {
790         int port = pcdev->pdata->port;
791         int err;
792
793         BUG_ON(!tegra_camera_port_is_valid(port));
794
795         if (port == TEGRA_CAMERA_PORT_CSI_A)
796                 TC_VI_REG_WT(pcdev, TEGRA_CSI_PIXEL_STREAM_PPA_COMMAND,
797                              0x0000f002);
798         else if (port == TEGRA_CAMERA_PORT_CSI_B)
799                 TC_VI_REG_WT(pcdev, TEGRA_CSI_PIXEL_STREAM_PPB_COMMAND,
800                              0x0000f002);
801         else
802                 TC_VI_REG_WT(pcdev, TEGRA_VI_CAMERA_CONTROL,
803                              0x00000005);
804
805         if (tegra_camera_port_is_csi(port))
806                 err = nvhost_syncpt_wait_timeout_ext(pcdev->ndev,
807                         TEGRA_VI_SYNCPT_VI,
808                         pcdev->syncpt_vi,
809                         TEGRA_SYNCPT_VI_WAIT_TIMEOUT,
810                         NULL);
811         else
812                 err = 0;
813
814         if (err) {
815                 u32 buffer_addr;
816                 u32 ppstatus;
817                 u32 cilstatus;
818
819                 dev_err(&pcdev->ndev->dev, "Timeout on VI syncpt\n");
820                 buffer_addr = TC_VI_REG_RD(pcdev,
821                                            TEGRA_VI_VB0_BASE_ADDRESS_FIRST);
822                 dev_err(&pcdev->ndev->dev, "buffer_addr = 0x%08x\n",
823                         buffer_addr);
824
825                 ppstatus = TC_VI_REG_RD(pcdev,
826                                         TEGRA_CSI_CSI_PIXEL_PARSER_STATUS);
827                 cilstatus = TC_VI_REG_RD(pcdev,
828                                          TEGRA_CSI_CSI_CIL_STATUS);
829                 dev_err(&pcdev->ndev->dev,
830                         "PPSTATUS = 0x%08x, CILSTATUS = 0x%08x\n",
831                         ppstatus, cilstatus);
832         }
833
834         return err;
835 }
836
837 static int tegra_camera_capture_frame(struct tegra_camera_dev *pcdev)
838 {
839         struct vb2_buffer *vb;
840         struct tegra_buffer *buf;
841         int retry = TEGRA_SYNCPT_RETRY_COUNT;
842         int port = pcdev->pdata->port;
843         int err;
844
845         if (!pcdev->active)
846                 return 0;
847
848         vb = pcdev->active;
849         buf = to_tegra_vb(vb);
850
851         while (retry) {
852                 err = tegra_camera_capture_start(pcdev, buf);
853                 if (!err)
854                         err = tegra_camera_capture_stop(pcdev);
855
856                 if (err != 0) {
857                         retry--;
858
859                         /* Stop streaming. */
860                         if (port == TEGRA_CAMERA_PORT_CSI_A) {
861                                 TC_VI_REG_WT(pcdev,
862                                              TEGRA_CSI_PIXEL_STREAM_PPA_COMMAND,
863                                              0x0000f002);
864                                 /* Clear status registers. */
865                                 TC_VI_REG_WT(pcdev,
866                                              TEGRA_CSI_CSI_PIXEL_PARSER_STATUS,
867                                              0xffffffff);
868                                 TC_VI_REG_WT(pcdev,
869                                              TEGRA_CSI_CSI_CIL_STATUS,
870                                              0xffffffff);
871                         } else if (port == TEGRA_CAMERA_PORT_CSI_B) {
872                                 TC_VI_REG_WT(pcdev,
873                                              TEGRA_CSI_PIXEL_STREAM_PPB_COMMAND,
874                                              0x0000f002);
875                                 /* Clear status registers. */
876                                 TC_VI_REG_WT(pcdev,
877                                              TEGRA_CSI_CSI_PIXEL_PARSER_STATUS,
878                                              0xffffffff);
879                                 TC_VI_REG_WT(pcdev,
880                                              TEGRA_CSI_CSI_CIL_STATUS,
881                                              0xffffffff);
882                         } else {
883                                 TC_VI_REG_WT(pcdev,
884                                              TEGRA_VI_CAMERA_CONTROL,
885                                              0x00000005);
886                         }
887
888
889                         tegra_camera_incr_syncpts(pcdev);
890                         tegra_camera_save_syncpts(pcdev);
891
892                         continue;
893                 }
894
895                 break;
896         }
897
898         spin_lock_irq(&pcdev->videobuf_queue_lock);
899
900         /*
901          * If vb->state is VB2_BUF_STATE_ERROR, then the vb has already been
902          * removed, so we shouldn't remove it again.
903          */
904         if (vb->state != VB2_BUF_STATE_ERROR)
905                 list_del_init(&buf->queue);
906
907         if (!list_empty(&pcdev->capture))
908                 pcdev->active = &list_entry(pcdev->capture.next,
909                                             struct tegra_buffer, queue)->vb;
910         else
911                 pcdev->active = NULL;
912
913         do_gettimeofday(&vb->v4l2_buf.timestamp);
914         vb->v4l2_buf.field = pcdev->field;
915         vb->v4l2_buf.sequence = pcdev->sequence++;
916
917         vb2_buffer_done(vb, err < 0 ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
918
919         pcdev->num_frames++;
920
921         spin_unlock_irq(&pcdev->videobuf_queue_lock);
922
923         return err;
924 }
925
926 static void tegra_camera_work(struct work_struct *work)
927 {
928         struct tegra_camera_dev *pcdev =
929                 container_of(work, struct tegra_camera_dev, work);
930
931         mutex_lock(&pcdev->work_mutex);
932
933         while (pcdev->active)
934                 tegra_camera_capture_frame(pcdev);
935
936         mutex_unlock(&pcdev->work_mutex);
937 }
938
939 static void tegra_camera_activate(struct tegra_camera_dev *pcdev)
940 {
941 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
942         u32 val;
943         void __iomem *apb_misc;
944 #endif
945
946         nvhost_module_busy_ext(pcdev->ndev);
947
948         /* Turn on relevant clocks. */
949         clk_enable(pcdev->clk_vi);
950         clk_enable(pcdev->clk_vi_sensor);
951         clk_enable(pcdev->clk_csi);
952         clk_enable(pcdev->clk_isp);
953         clk_enable(pcdev->clk_csus);
954
955 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
956         apb_misc = IO_ADDRESS(TEGRA_APB_MISC_BASE);
957         val = readl(apb_misc + 0x42c);
958         writel(val | 0x1, apb_misc + 0x42c);
959 #endif
960
961         /* Save current syncpt values. */
962         tegra_camera_save_syncpts(pcdev);
963 }
964
965 static void tegra_camera_deactivate(struct tegra_camera_dev *pcdev)
966 {
967         mutex_lock(&pcdev->work_mutex);
968
969         /* Cancel active buffer. */
970         if (pcdev->active) {
971                 list_del_init(&to_tegra_vb(pcdev->active)->queue);
972                 vb2_buffer_done(pcdev->active, VB2_BUF_STATE_ERROR);
973                 pcdev->active = NULL;
974         }
975
976         mutex_unlock(&pcdev->work_mutex);
977
978         /* Turn off relevant clocks. */
979         clk_disable(pcdev->clk_vi);
980         clk_disable(pcdev->clk_vi_sensor);
981         clk_disable(pcdev->clk_csi);
982         clk_disable(pcdev->clk_isp);
983         clk_disable(pcdev->clk_csus);
984
985         nvhost_module_idle_ext(pcdev->ndev);
986 }
987
988 static void tegra_camera_init_buffer(struct tegra_camera_dev *pcdev,
989                                      struct tegra_buffer *buf)
990 {
991         struct soc_camera_device *icd = pcdev->icd;
992         int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
993                                                 icd->current_fmt->host_fmt);
994
995         switch (icd->current_fmt->host_fmt->fourcc) {
996         case V4L2_PIX_FMT_UYVY:
997         case V4L2_PIX_FMT_VYUY:
998         case V4L2_PIX_FMT_YUYV:
999         case V4L2_PIX_FMT_YVYU:
1000                 buf->buffer_addr = vb2_dma_nvmap_plane_paddr(&buf->vb, 0);
1001                 buf->start_addr = buf->buffer_addr;
1002
1003                 if (pcdev->pdata->flip_v)
1004                         buf->start_addr += bytes_per_line *
1005                                            (icd->user_height-1);
1006
1007                 if (pcdev->pdata->flip_h)
1008                         buf->start_addr += bytes_per_line - 1;
1009
1010                 break;
1011
1012         case V4L2_PIX_FMT_YUV420:
1013         case V4L2_PIX_FMT_YVU420:
1014                 buf->buffer_addr = vb2_dma_nvmap_plane_paddr(&buf->vb, 0);
1015                 buf->buffer_addr_u = buf->buffer_addr +
1016                                      icd->user_width * icd->user_height;
1017                 buf->buffer_addr_v = buf->buffer_addr_u +
1018                                      (icd->user_width * icd->user_height) / 4;
1019
1020                 /* For YVU420, we swap the locations of the U and V planes. */
1021                 if (icd->current_fmt->host_fmt->fourcc == V4L2_PIX_FMT_YVU420) {
1022                         dma_addr_t temp = buf->buffer_addr_u;
1023                         buf->buffer_addr_u = buf->buffer_addr_v;
1024                         buf->buffer_addr_v = temp;
1025                 }
1026
1027                 buf->start_addr = buf->buffer_addr;
1028                 buf->start_addr_u = buf->buffer_addr_u;
1029                 buf->start_addr_v = buf->buffer_addr_v;
1030
1031                 if (pcdev->pdata->flip_v) {
1032                         buf->start_addr += icd->user_width *
1033                                            (icd->user_height - 1);
1034
1035                         buf->start_addr_u += ((icd->user_width/2) *
1036                                               ((icd->user_height/2) - 1));
1037
1038                         buf->start_addr_v += ((icd->user_width/2) *
1039                                               ((icd->user_height/2) - 1));
1040                 }
1041
1042                 if (pcdev->pdata->flip_h) {
1043                         buf->start_addr += icd->user_width - 1;
1044
1045                         buf->start_addr_u += (icd->user_width/2) - 1;
1046
1047                         buf->start_addr_v += (icd->user_width/2) - 1;
1048                 }
1049
1050                 break;
1051
1052         default:
1053                 BUG_ON(1);
1054         }
1055 }
1056
1057 /*
1058  *  Videobuf operations
1059  */
1060 static int tegra_camera_videobuf_setup(struct vb2_queue *vq,
1061                                        unsigned int *num_buffers,
1062                                        unsigned int *num_planes,
1063                                        unsigned long sizes[],
1064                                        void *alloc_ctxs[])
1065 {
1066         struct soc_camera_device *icd = container_of(vq,
1067                                                      struct soc_camera_device,
1068                                                      vb2_vidq);
1069         struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1070         struct tegra_camera_dev *pcdev = ici->priv;
1071         int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
1072                                                 icd->current_fmt->host_fmt);
1073
1074         dev_dbg(icd->parent, "In tegra_camera_videobuf_setup()\n");
1075
1076         if (bytes_per_line < 0)
1077                 return bytes_per_line;
1078
1079         *num_planes = 1;
1080
1081         pcdev->sequence = 0;
1082         sizes[0] = bytes_per_line * icd->user_height;
1083         alloc_ctxs[0] = pcdev->alloc_ctx;
1084
1085         if (!*num_buffers)
1086                 *num_buffers = 2;
1087
1088         dev_dbg(icd->parent, "num_buffers=%u, size=%lu\n",
1089                 *num_buffers, sizes[0]);
1090
1091         tegra_camera_capture_setup(pcdev);
1092
1093         dev_dbg(icd->parent, "Finished tegra_camera_videobuf_setup()\n");
1094
1095         return 0;
1096 }
1097
1098 static int tegra_camera_videobuf_prepare(struct vb2_buffer *vb)
1099 {
1100         struct soc_camera_device *icd = container_of(vb->vb2_queue,
1101                                                      struct soc_camera_device,
1102                                                      vb2_vidq);
1103         struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1104         struct tegra_camera_dev *pcdev = ici->priv;
1105         struct tegra_buffer *buf;
1106         int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
1107                                                 icd->current_fmt->host_fmt);
1108         unsigned long size;
1109
1110         dev_dbg(icd->parent, "In tegra_camera_videobuf_prepare()\n");
1111
1112         if (bytes_per_line < 0)
1113                 return bytes_per_line;
1114
1115         buf = to_tegra_vb(vb);
1116
1117         dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
1118                 vb, vb2_plane_vaddr(vb, 0), vb2_plane_size(vb, 0));
1119
1120 #ifdef PREFILL_BUFFER
1121         /*
1122          * This can be useful if you want to see if we actually fill
1123          * the buffer with something
1124          */
1125         if (vb2_plane_vaddr(vb, 0))
1126                 memset(vb2_plane_vaddr(vb, 0), 0xbd, vb2_plane_size(vb, 0));
1127 #endif
1128
1129         BUG_ON(NULL == icd->current_fmt);
1130
1131         size = icd->user_height * bytes_per_line;
1132
1133         if (vb2_plane_size(vb, 0) < size) {
1134                 dev_err(icd->parent, "Buffer too small (%lu < %lu)\n",
1135                         vb2_plane_size(vb, 0), size);
1136                 return -ENOBUFS;
1137         }
1138
1139         vb2_set_plane_payload(vb, 0, size);
1140
1141         tegra_camera_init_buffer(pcdev, buf);
1142
1143         dev_dbg(icd->parent, "Finished tegra_camera_videobuf_prepare()\n");
1144
1145         return 0;
1146 }
1147
1148 static void tegra_camera_videobuf_queue(struct vb2_buffer *vb)
1149 {
1150         struct soc_camera_device *icd = container_of(vb->vb2_queue,
1151                                                      struct soc_camera_device,
1152                                                      vb2_vidq);
1153         struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1154         struct tegra_camera_dev *pcdev = ici->priv;
1155         struct tegra_buffer *buf = to_tegra_vb(vb);
1156
1157         dev_dbg(icd->parent, "In tegra_camera_videobuf_queue()\n");
1158
1159         dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
1160                 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
1161
1162         spin_lock_irq(&pcdev->videobuf_queue_lock);
1163         list_add_tail(&buf->queue, &pcdev->capture);
1164
1165         if (!pcdev->active) {
1166                 pcdev->active = vb;
1167                 schedule_work(&pcdev->work);
1168         }
1169         spin_unlock_irq(&pcdev->videobuf_queue_lock);
1170
1171         dev_dbg(icd->parent, "Finished tegra_camera_videobuf_queue()\n");
1172 }
1173
1174 static void tegra_camera_videobuf_release(struct vb2_buffer *vb)
1175 {
1176         struct soc_camera_device *icd = container_of(vb->vb2_queue,
1177                                                      struct soc_camera_device,
1178                                                      vb2_vidq);
1179         struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1180         struct tegra_buffer *buf = to_tegra_vb(vb);
1181         struct tegra_camera_dev *pcdev = ici->priv;
1182
1183         dev_dbg(icd->parent, "In tegra_camera_videobuf_release()\n");
1184
1185         mutex_lock(&pcdev->work_mutex);
1186
1187         spin_lock_irq(&pcdev->videobuf_queue_lock);
1188
1189         if (pcdev->active == vb)
1190                 pcdev->active = NULL;
1191
1192         /*
1193          * Doesn't hurt also if the list is empty, but it hurts, if queuing the
1194          * buffer failed, and .buf_init() hasn't been called
1195          */
1196         if (buf->queue.next)
1197                 list_del_init(&buf->queue);
1198
1199         spin_unlock_irq(&pcdev->videobuf_queue_lock);
1200
1201         mutex_unlock(&pcdev->work_mutex);
1202
1203         dev_dbg(icd->parent, "Finished tegra_camera_videobuf_release()\n");
1204 }
1205
1206 static int tegra_camera_videobuf_init(struct vb2_buffer *vb)
1207 {
1208         /* This is for locking debugging only */
1209         INIT_LIST_HEAD(&to_tegra_vb(vb)->queue);
1210
1211         return 0;
1212 }
1213
1214 static int tegra_camera_stop_streaming(struct vb2_queue *q)
1215 {
1216         struct soc_camera_device *icd = container_of(q,
1217                                                      struct soc_camera_device,
1218                                                      vb2_vidq);
1219         struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1220         struct tegra_camera_dev *pcdev = ici->priv;
1221         struct list_head *buf_head, *tmp;
1222
1223         mutex_lock(&pcdev->work_mutex);
1224
1225         spin_lock_irq(&pcdev->videobuf_queue_lock);
1226
1227         pcdev->active = NULL;
1228
1229         list_for_each_safe(buf_head, tmp, &pcdev->capture)
1230                 list_del_init(buf_head);
1231
1232         spin_unlock_irq(&pcdev->videobuf_queue_lock);
1233
1234         mutex_unlock(&pcdev->work_mutex);
1235
1236         return 0;
1237 }
1238
1239 static struct vb2_ops tegra_camera_videobuf_ops = {
1240         .queue_setup    = tegra_camera_videobuf_setup,
1241         .buf_prepare    = tegra_camera_videobuf_prepare,
1242         .buf_queue      = tegra_camera_videobuf_queue,
1243         .buf_cleanup    = tegra_camera_videobuf_release,
1244         .buf_init       = tegra_camera_videobuf_init,
1245         .wait_prepare   = soc_camera_unlock,
1246         .wait_finish    = soc_camera_lock,
1247         .stop_streaming = tegra_camera_stop_streaming,
1248 };
1249
1250 /*
1251  *  SOC camera host operations
1252  */
1253 static int tegra_camera_init_videobuf(struct vb2_queue *q,
1254                                       struct soc_camera_device *icd)
1255 {
1256         dev_dbg(icd->parent, "In tegra_camera_init_videobuf()\n");
1257
1258         q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1259         q->io_modes = VB2_MMAP | VB2_USERPTR;
1260         q->drv_priv = icd;
1261         q->ops = &tegra_camera_videobuf_ops;
1262         q->mem_ops = &vb2_dma_nvmap_memops;
1263         q->buf_struct_size = sizeof(struct tegra_buffer);
1264
1265         dev_dbg(icd->parent, "Finished tegra_camera_init_videobuf()\n");
1266
1267         return vb2_queue_init(q);
1268 }
1269
1270 /*
1271  * Called with .video_lock held
1272  */
1273 static int tegra_camera_add_device(struct soc_camera_device *icd)
1274 {
1275         struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1276         struct tegra_camera_dev *pcdev = ici->priv;
1277         int err;
1278
1279         if (pcdev->icd)
1280                 return -EBUSY;
1281
1282         pm_runtime_get_sync(ici->v4l2_dev.dev);
1283
1284         if (pcdev->pdata->enable_camera) {
1285                 err = pcdev->pdata->enable_camera(pcdev->ndev);
1286                 if (IS_ERR_VALUE(err))
1287                         return err;
1288         }
1289
1290         tegra_camera_activate(pcdev);
1291
1292         pcdev->icd = icd;
1293
1294         pcdev->num_frames = 0;
1295
1296         dev_dbg(icd->parent, "TEGRA Camera host attached to camera %d\n",
1297                 icd->devnum);
1298
1299         return 0;
1300 }
1301
1302 /* Called with .video_lock held */
1303 static void tegra_camera_remove_device(struct soc_camera_device *icd)
1304 {
1305         struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1306         struct tegra_camera_dev *pcdev = ici->priv;
1307
1308         tegra_camera_deactivate(pcdev);
1309
1310         pcdev->icd = NULL;
1311
1312         if (pcdev->pdata->disable_camera)
1313                 pcdev->pdata->disable_camera(pcdev->ndev);
1314
1315         pm_runtime_put_sync(ici->v4l2_dev.dev);
1316
1317         dev_dbg(icd->parent, "Frames captured: %d\n", pcdev->num_frames);
1318
1319         dev_dbg(icd->parent, "TEGRA camera host detached from camera %d\n",
1320                 icd->devnum);
1321 }
1322
1323 static int tegra_camera_set_bus_param(struct soc_camera_device *icd,
1324                                         __u32 pixfmt)
1325 {
1326         return 0;
1327 }
1328
1329 static int tegra_camera_get_formats(struct soc_camera_device *icd,
1330                                     unsigned int idx,
1331                                     struct soc_camera_format_xlate *xlate)
1332 {
1333         struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1334         struct device *dev = icd->parent;
1335         int formats = 0;
1336         int ret;
1337         enum v4l2_mbus_pixelcode code;
1338         const struct soc_mbus_pixelfmt *fmt;
1339         int k;
1340
1341         ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
1342         if (ret != 0)
1343                 /* No more formats */
1344                 return 0;
1345
1346         fmt = soc_mbus_get_fmtdesc(code);
1347         if (!fmt) {
1348                 dev_err(dev, "Invalid format code #%u: %d\n", idx, code);
1349                 return 0;
1350         }
1351
1352         switch (code) {
1353         case V4L2_MBUS_FMT_UYVY8_2X8:
1354         case V4L2_MBUS_FMT_VYUY8_2X8:
1355         case V4L2_MBUS_FMT_YUYV8_2X8:
1356         case V4L2_MBUS_FMT_YVYU8_2X8:
1357                 formats += ARRAY_SIZE(tegra_camera_formats);
1358                 for (k = 0;
1359                      xlate && (k < ARRAY_SIZE(tegra_camera_formats));
1360                      k++) {
1361                         xlate->host_fmt = &tegra_camera_formats[k];
1362                         xlate->code     = code;
1363                         xlate++;
1364
1365                         dev_info(dev, "Providing format %s using code %d\n",
1366                                  tegra_camera_formats[k].name, code);
1367                 }
1368                 break;
1369         default:
1370                 dev_info(dev, "Not supporting %s\n", fmt->name);
1371                 return 0;
1372         }
1373
1374         return formats;
1375 }
1376
1377 static void tegra_camera_put_formats(struct soc_camera_device *icd)
1378 {
1379         kfree(icd->host_priv);
1380         icd->host_priv = NULL;
1381 }
1382
1383 static int tegra_camera_set_fmt(struct soc_camera_device *icd,
1384                               struct v4l2_format *f)
1385 {
1386         struct device *dev = icd->parent;
1387         struct soc_camera_host *ici = to_soc_camera_host(dev);
1388         struct tegra_camera_dev *pcdev = ici->priv;
1389
1390         struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1391         const struct soc_camera_format_xlate *xlate = NULL;
1392         struct v4l2_pix_format *pix = &f->fmt.pix;
1393         struct v4l2_mbus_framefmt mf;
1394         int ret;
1395
1396         dev_dbg(dev, "In tegra_camera_set_fmt()\n");
1397
1398         xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1399         if (!xlate) {
1400                 dev_warn(dev, "Format %x not found\n", pix->pixelformat);
1401                 return -EINVAL;
1402         }
1403
1404         mf.width        = pix->width;
1405         mf.height       = pix->height;
1406         mf.field        = pix->field;
1407         mf.colorspace   = pix->colorspace;
1408         mf.code         = xlate->code;
1409
1410         ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
1411         if (IS_ERR_VALUE(ret)) {
1412                 dev_warn(dev, "Failed to configure for format %x\n",
1413                          pix->pixelformat);
1414                 return ret;
1415         }
1416
1417         if (mf.code != xlate->code) {
1418                 dev_warn(dev, "mf.code = %d, xlate->code = %d, mismatch\n",
1419                         mf.code, xlate->code);
1420                 return -EINVAL;
1421         }
1422
1423         icd->user_width         = mf.width;
1424         icd->user_height        = mf.height;
1425         icd->current_fmt        = xlate;
1426
1427         pcdev->field = pix->field;
1428
1429         dev_dbg(dev, "Finished tegra_camera_set_fmt(), returning %d\n", ret);
1430
1431         return ret;
1432 }
1433
1434 static int tegra_camera_try_fmt(struct soc_camera_device *icd,
1435                                 struct v4l2_format *f)
1436 {
1437         struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1438         const struct soc_camera_format_xlate *xlate;
1439         struct v4l2_pix_format *pix = &f->fmt.pix;
1440         struct v4l2_mbus_framefmt mf;
1441         __u32 pixfmt = pix->pixelformat;
1442         int ret;
1443
1444         dev_dbg(icd->parent, "In tegra_camera_try_fmt()\n");
1445
1446         xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1447         if (!xlate) {
1448                 dev_warn(icd->parent, "Format %x not found\n", pixfmt);
1449                 return -EINVAL;
1450         }
1451
1452         pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
1453                                                     xlate->host_fmt);
1454         if (pix->bytesperline < 0)
1455                 return pix->bytesperline;
1456         pix->sizeimage = pix->height * pix->bytesperline;
1457
1458         /* limit to sensor capabilities */
1459         mf.width        = pix->width;
1460         mf.height       = pix->height;
1461         mf.field        = pix->field;
1462         mf.colorspace   = pix->colorspace;
1463         mf.code         = xlate->code;
1464
1465         ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
1466         if (IS_ERR_VALUE(ret))
1467                 return ret;
1468
1469         pix->width      = mf.width;
1470         pix->height     = mf.height;
1471         pix->colorspace = mf.colorspace;
1472         /*
1473          * width and height could have been changed, therefore update the
1474          * bytesperline and sizeimage here.
1475          */
1476         pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
1477                                                     xlate->host_fmt);
1478         pix->sizeimage = pix->height * pix->bytesperline;
1479
1480         switch (mf.field) {
1481         case V4L2_FIELD_ANY:
1482         case V4L2_FIELD_NONE:
1483                 pix->field      = V4L2_FIELD_NONE;
1484                 break;
1485         default:
1486                 /* TODO: support interlaced at least in pass-through mode */
1487                 dev_err(icd->parent, "Field type %d unsupported.\n",
1488                         mf.field);
1489                 return -EINVAL;
1490         }
1491
1492         dev_dbg(icd->parent,
1493                 "Finished tegra_camera_try_fmt(), returning %d\n", ret);
1494
1495         return ret;
1496 }
1497
1498 static int tegra_camera_reqbufs(struct soc_camera_device *icd,
1499                                 struct v4l2_requestbuffers *p)
1500 {
1501         return 0;
1502 }
1503
1504 static unsigned int tegra_camera_poll(struct file *file, poll_table *pt)
1505 {
1506         struct soc_camera_device *icd = file->private_data;
1507
1508         return vb2_poll(&icd->vb2_vidq, file, pt);
1509 }
1510
1511 static int tegra_camera_querycap(struct soc_camera_host *ici,
1512                                  struct v4l2_capability *cap)
1513 {
1514         strlcpy(cap->card, TEGRA_CAM_DRV_NAME, sizeof(cap->card));
1515         cap->version = TEGRA_CAM_VERSION_CODE;
1516         cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1517
1518         return 0;
1519 }
1520
1521 static struct soc_camera_host_ops tegra_soc_camera_host_ops = {
1522         .owner          = THIS_MODULE,
1523         .init_videobuf2 = tegra_camera_init_videobuf,
1524         .add            = tegra_camera_add_device,
1525         .remove         = tegra_camera_remove_device,
1526         .set_bus_param  = tegra_camera_set_bus_param,
1527         .get_formats    = tegra_camera_get_formats,
1528         .put_formats    = tegra_camera_put_formats,
1529         .set_fmt        = tegra_camera_set_fmt,
1530         .try_fmt        = tegra_camera_try_fmt,
1531         .reqbufs        = tegra_camera_reqbufs,
1532         .poll           = tegra_camera_poll,
1533         .querycap       = tegra_camera_querycap,
1534 };
1535
1536 static int __devinit tegra_camera_probe(struct nvhost_device *ndev,
1537                                         struct nvhost_device_id *id_table)
1538 {
1539         struct tegra_camera_dev *pcdev;
1540         int err = 0;
1541
1542         pcdev = kzalloc(sizeof(struct tegra_camera_dev), GFP_KERNEL);
1543         if (!pcdev) {
1544                 dev_err(&ndev->dev, "Could not allocate pcdev\n");
1545                 err = -ENOMEM;
1546                 goto exit;
1547         }
1548
1549         pcdev->pdata                    = ndev->dev.platform_data;
1550         pcdev->ndev                     = ndev;
1551
1552         pcdev->ici.priv         = pcdev;
1553         pcdev->ici.v4l2_dev.dev = &ndev->dev;
1554         pcdev->ici.nr           = ndev->id;
1555         pcdev->ici.drv_name     = dev_name(&ndev->dev);
1556         pcdev->ici.ops          = &tegra_soc_camera_host_ops;
1557
1558         INIT_LIST_HEAD(&pcdev->capture);
1559         INIT_WORK(&pcdev->work, tegra_camera_work);
1560         spin_lock_init(&pcdev->videobuf_queue_lock);
1561         mutex_init(&pcdev->work_mutex);
1562
1563         nvhost_set_drvdata(ndev, pcdev);
1564
1565         if (!tegra_camera_port_is_valid(pcdev->pdata->port)) {
1566                 dev_err(&ndev->dev, "Invalid camera port %d in platform data\n",
1567                         pcdev->pdata->port);
1568                 goto exit_free_pcdev;
1569         }
1570
1571         pcdev->clk_vi = clk_get_sys("tegra_camera", "vi");
1572         if (IS_ERR_OR_NULL(pcdev->clk_vi)) {
1573                 dev_err(&ndev->dev, "Failed to get vi clock.\n");
1574                 goto exit_free_pcdev;
1575         }
1576
1577         pcdev->clk_vi_sensor = clk_get_sys("tegra_camera", "vi_sensor");
1578         if (IS_ERR_OR_NULL(pcdev->clk_vi_sensor)) {
1579                 dev_err(&ndev->dev, "Failed to get vi_sensor clock.\n");
1580                 goto exit_put_clk_vi;
1581         }
1582
1583         pcdev->clk_csi = clk_get_sys("tegra_camera", "csi");
1584         if (IS_ERR_OR_NULL(pcdev->clk_csi)) {
1585                 dev_err(&ndev->dev, "Failed to get csi clock.\n");
1586                 goto exit_put_clk_vi_sensor;
1587         }
1588
1589         pcdev->clk_isp = clk_get_sys("tegra_camera", "isp");
1590         if (IS_ERR_OR_NULL(pcdev->clk_isp)) {
1591                 dev_err(&ndev->dev, "Failed to get isp clock.\n");
1592                 goto exit_put_clk_csi;
1593         }
1594
1595         pcdev->clk_csus = clk_get_sys("tegra_camera", "csus");
1596         if (IS_ERR_OR_NULL(pcdev->clk_csus)) {
1597                 dev_err(&ndev->dev, "Failed to get csus clock.\n");
1598                 goto exit_put_clk_isp;
1599         }
1600
1601         clk_set_rate(pcdev->clk_vi, 150000000);
1602         clk_set_rate(pcdev->clk_vi_sensor, 24000000);
1603
1604         err = nvhost_client_device_get_resources(ndev);
1605         if (err)
1606                 goto exit_put_clk_csus;
1607
1608         nvhost_client_device_init(ndev);
1609
1610         pcdev->vi_base = ndev->aperture;
1611
1612         pm_suspend_ignore_children(&ndev->dev, true);
1613         pm_runtime_enable(&ndev->dev);
1614         pm_runtime_resume(&ndev->dev);
1615
1616         pcdev->alloc_ctx = vb2_dma_nvmap_init_ctx(NULL);
1617         if (IS_ERR(pcdev->alloc_ctx)) {
1618                 err = PTR_ERR(pcdev->alloc_ctx);
1619                 goto exit_put_resources;
1620         }
1621
1622         err = soc_camera_host_register(&pcdev->ici);
1623         if (IS_ERR_VALUE(err))
1624                 goto exit_cleanup_alloc_ctx;
1625
1626         dev_notice(&ndev->dev, "Tegra camera driver loaded.\n");
1627
1628         return err;
1629
1630 exit_cleanup_alloc_ctx:
1631         vb2_dma_nvmap_cleanup_ctx(&ndev->dev);
1632 exit_put_resources:
1633         pm_runtime_disable(&ndev->dev);
1634         nvhost_client_device_put_resources(ndev);
1635 exit_put_clk_csus:
1636         clk_put(pcdev->clk_csus);
1637 exit_put_clk_isp:
1638         clk_put(pcdev->clk_isp);
1639 exit_put_clk_csi:
1640         clk_put(pcdev->clk_csi);
1641 exit_put_clk_vi_sensor:
1642         clk_put(pcdev->clk_vi_sensor);
1643 exit_put_clk_vi:
1644         clk_put(pcdev->clk_vi);
1645 exit_free_pcdev:
1646         kfree(pcdev);
1647 exit:
1648         return err;
1649 }
1650
1651 static int __devexit tegra_camera_remove(struct nvhost_device *ndev)
1652 {
1653         struct soc_camera_host *ici = to_soc_camera_host(&ndev->dev);
1654         struct tegra_camera_dev *pcdev = container_of(ici,
1655                                         struct tegra_camera_dev, ici);
1656         struct resource *res;
1657
1658         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
1659         if (!res)
1660                 return -EBUSY;
1661
1662         soc_camera_host_unregister(ici);
1663
1664         vb2_dma_nvmap_cleanup_ctx(&ndev->dev);
1665
1666         pm_runtime_disable(&ndev->dev);
1667
1668         nvhost_client_device_put_resources(ndev);
1669
1670         clk_put(pcdev->clk_csus);
1671         clk_put(pcdev->clk_isp);
1672         clk_put(pcdev->clk_csi);
1673         clk_put(pcdev->clk_vi_sensor);
1674         clk_put(pcdev->clk_vi);
1675
1676         kfree(pcdev);
1677
1678         dev_notice(&ndev->dev, "Tegra camera host driver unloaded\n");
1679
1680         return 0;
1681 }
1682
1683 #ifdef CONFIG_PM_FISH
1684 static int tegra_camera_suspend(struct nvhost_device *ndev, pm_message_t state)
1685 {
1686         struct soc_camera_host *ici = to_soc_camera_host(&ndev->dev);
1687         struct tegra_camera_dev *pcdev = container_of(ici,
1688                                         struct tegra_camera_dev, ici);
1689
1690         mutex_lock(&pcdev->work_mutex);
1691
1692         /* We only need to do something if a camera sensor is attached. */
1693         if (pcdev->icd) {
1694                 /* Suspend the camera sensor. */
1695                 WARN_ON(!pcdev->icd->ops->suspend);
1696                 pcdev->icd->ops->suspend(pcdev->icd, state);
1697
1698                 /* Power off the camera subsystem. */
1699                 pcdev->pdata->disable_camera(pcdev->ndev);
1700
1701                 nvhost_module_idle_ext(nvhost_get_parent(ndev));
1702         }
1703
1704         return 0;
1705 }
1706
1707 static int tegra_camera_resume(struct nvhost_device *ndev)
1708 {
1709         struct soc_camera_host *ici = to_soc_camera_host(&ndev->dev);
1710         struct tegra_camera_dev *pcdev = container_of(ici,
1711                                         struct tegra_camera_dev, ici);
1712
1713         /* We only need to do something if a camera sensor is attached. */
1714         if (pcdev->icd) {
1715                 nvhost_module_busy_ext(nvhost_get_parent(ndev));
1716
1717                 /* Power on the camera subsystem. */
1718                 pcdev->pdata->enable_camera(pcdev->ndev);
1719
1720                 /* Resume the camera host. */
1721                 tegra_camera_save_syncpts(pcdev);
1722                 tegra_camera_capture_setup(pcdev);
1723
1724                 /* Resume the camera sensor. */
1725                 WARN_ON(!pcdev->icd->ops->resume);
1726                 pcdev->icd->ops->resume(pcdev->icd);
1727         }
1728
1729         mutex_unlock(&pcdev->work_mutex);
1730
1731         return 0;
1732 }
1733 #endif
1734
1735 static struct nvhost_driver tegra_camera_driver = {
1736         .driver = {
1737                 .name   = TEGRA_CAM_DRV_NAME,
1738                 .owner  = THIS_MODULE,
1739         },
1740         .probe          = tegra_camera_probe,
1741         .remove         = __devexit_p(tegra_camera_remove),
1742 #ifdef CONFIG_PM_FISH
1743         .suspend        = tegra_camera_suspend,
1744         .resume         = tegra_camera_resume,
1745 #endif
1746 };
1747
1748
1749 static int __init tegra_camera_init(void)
1750 {
1751         return nvhost_driver_register(&tegra_camera_driver);
1752 }
1753
1754 static void __exit tegra_camera_exit(void)
1755 {
1756         nvhost_driver_unregister(&tegra_camera_driver);
1757 }
1758
1759 module_init(tegra_camera_init);
1760 module_exit(tegra_camera_exit);
1761
1762 MODULE_DESCRIPTION("TEGRA SoC Camera Host driver");
1763 MODULE_AUTHOR("Andrew Chew <achew@nvidia.com>");
1764 MODULE_LICENSE("GPL v2");
1765 MODULE_ALIAS("nvhost:" TEGRA_CAM_DRV_NAME);