Revert "media: camera config changes"
[linux-2.6.git] / drivers / media / video / tegra / tegra_dtv.c
1 /*
2  * tegra_dtv.c - Tegra DTV interface driver
3  *
4  * Author: Adam Jiang <chaoj@nvidia.com>
5  * Copyright (c) 2011, NVIDIA Corporation.
6  * Copyright (c) 2012, NVIDIA Corporation.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * version 2 as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful, but
13  * WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20  * 02110-1301 USA
21  *
22  */
23
24 #include <linux/kernel.h>
25 #include <linux/io.h>
26 #include <linux/clk.h>
27 #include <linux/fs.h>
28 #include <linux/completion.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/vmalloc.h>
31 #include <linux/slab.h>
32 #include <linux/spinlock.h>
33 #include <linux/mutex.h>
34 #include <linux/workqueue.h>
35 #include <linux/wakelock.h>
36 #include <linux/platform_device.h>
37 #include <linux/miscdevice.h>
38 #include <linux/debugfs.h>
39 #include <linux/seq_file.h>
40 #include <linux/delay.h>
41
42 #include <media/tegra_dtv.h>
43
44 #include <linux/uaccess.h>
45 #include <mach/iomap.h>
46 #include <mach/dma.h>
47
48 /* offsets from TEGRA_DTV_BASE */
49 #define DTV_SPI_CONTROL         0x40
50 #define DTV_MODE                0x44
51 #define DTV_CTRL                0x48
52 #define DTV_PACKET_COUNT        0x4c
53 #define DTV_ERROR_COUNT         0x50
54 #define DTV_INTERRUPT_STATUS    0x54
55 #define DTV_STATUS              0x58
56 #define DTV_RX_FIFO             0x5c
57
58 /* DTV_SPI_CONTROL */
59 #define DTV_SPI_CONTROL_ENABLE_DTV  1
60
61 /* DTV_MODE_0 */
62 #define DTV_MODE_BYTE_SWIZZLE_SHIFT 6
63 #define DTV_MODE_BYTE_SWIZZLE       (1 << DTV_MODE_BYTE_SWIZZLE_SHIFT)
64 #define DTV_MODE_BIT_SWIZZLE_SHIFT  5
65 #define DTV_MODE_BIT_SWIZZLE        (1 << DTV_MODE_BIT_SWIZZLE_SHIFT)
66 #define DTV_MODE_CLK_EDGE_SHIFT     4
67 #define DTV_MODE_CLK_EDGE_MASK      1
68 #define DTV_MODE_CLK_EDGE_NEG       (1 << DTV_MODE_CLK_EDGE_SHIFT)
69 #define DTV_MODE_PRTL_SEL_SHIFT     2
70 #define DTV_MODE_PRTL_SEL_MASK      (0x3 << DTV_MODE_PRTL_SEL_SHIFT)
71 #define DTV_MODE_CLK_MODE_SHIFT     1
72 #define DTV_MODE_CLK_MODE_MASK      (0x1 << DTV_MODE_CLK_MODE_SHIFT)
73 #define DTV_MODE_PRTL_ENABLE        1
74
75 /* DTV_CONTROL_0 */
76 #define DTV_CTRL_FEC_SIZE_SHIFT         24
77 #define DTV_CTRL_FEC_SIZE_MASK          (0x7F << DTV_CTRL_FEC_SIZE_SHIFT)
78 #define DTV_CTRL_BODY_SIZE_SHIFT        16
79 #define DTV_CTRL_BODY_SIZE_MASK         (0xFF << DTV_CTRL_BODY_SIZE_SHIFT)
80 #define DTV_CTRL_FIFO_ATTN_LEVEL_SHIFT  8
81 #define DTV_CTRL_FIFO_ATTN_LEVEL_MASK   (0x1F << DTV_CTRL_FIFO_ATTN_LEVEL_SHIFT)
82 #define DTV_CTRL_FIFO_ATTN_ONE_WORD     (0 << DTV_CTRL_FIFO_ATTN_LEVEL_SHIFT)
83 #define DTV_CTRL_FIFO_ATTN_TWO_WORD     (1 << DTV_CTRL_FIFO_ATTN_LEVEL_SHIFT)
84 #define DTV_CTRL_FIFO_ATTN_THREE_WORD   (2 << DTV_CTRL_FIFO_ATTN_LEVEL_SHIFT)
85 #define DTV_CTRL_FIFO_ATTN_FOUR_WORD    (3 << DTV_CTRL_FIFO_ATTN_LEVEL_SHIFT)
86 #define DTV_CTRL_BODY_VALID_SEL_SHIFT   6
87 #define DTV_CTRL_BODY_VALID_SEL_MASK    (1 << DTV_CTRL_BODY_VALID_SEL_SHIFT)
88 #define DTV_CTRL_START_SEL_SHIFT        4
89 #define DTV_CTRL_START_SEL_MASK         (1 << DTV_CTRL_START_SEL_SHIFT)
90 #define DTV_CTRL_ERROR_POLARITY_SHIFT   2
91 #define DTV_CTRL_ERROR_POLARITY_MASK    (1 << DTV_CTRL_ERROR_POLARITY_SHIFT)
92 #define DTV_CTRL_PSYNC_POLARITY_SHIFT   1
93 #define DTV_CTRL_PSYNC_POLARITY_MASK    (1 << DTV_CTRL_PSYNC_POLARITY_SHIFT)
94 #define DTV_CTRL_VALID_POLARITY_SHIFT   0
95 #define DTV_CTRL_VALID_POLARITY_MASK    (1 << DTV_CTRL_VALID_POLARITY_SHIFT)
96
97 /* DTV_INTERRUPT_STATUS_0 */
98 #define DTV_INTERRUPT_PACKET_UNDERRUN_ERR 8
99 #define DTV_INTERRUPT_BODY_OVERRUN_ERR    4
100 #define DTV_INTERRUPT_BODY_UNDERRUN_ERR   2
101 #define DTV_INTERRUPT_UPSTREAM_ERR        1
102
103 /* DTV_STATUS_0 */
104 #define DTV_STATUS_RXF_UNDERRUN 4
105 #define DTV_STATUS_RXF_EMPTY    2
106 #define DTV_STATUS_RXF_FULL     1
107
108 #define TEGRA_DTV_NAME "tegra_dtv"
109
110 /* default sw config */
111 #define DTV_BUF_SIZE_ORDER                PAGE_SHIFT
112 #define DTV_MAX_NUM_BUFS                  4
113
114 #define DTV_FIFO_ATN_LVL_LOW_GEAR         0
115 #define DTV_FIFO_ATN_LVL_SECOND_GEAR      1
116 #define DTV_FIFO_ATN_LVL_THIRD_GEAR       2
117 #define DTV_FIFO_ATN_LVL_TOP_GEAR         3
118
119 struct dtv_stream {
120         struct mutex    mtx;
121
122         bool                     xferring;      /* is DMA in progress */
123         unsigned                 num_bufs;
124         void                    *buffer[DTV_MAX_NUM_BUFS];
125         dma_addr_t               buf_phy[DTV_MAX_NUM_BUFS];
126         struct completion        comp[DTV_MAX_NUM_BUFS];
127         struct tegra_dma_req     dma_req[DTV_MAX_NUM_BUFS];
128         int                      last_queued;
129
130         int     fifo_atn_level;
131
132         struct tegra_dma_channel        *dma_chan;
133         bool                             stopped;
134         struct completion                stop_completion;
135         spinlock_t                       dma_req_lock;
136         size_t                           buf_size;
137
138         struct work_struct      work;
139         struct wake_lock        wake_lock;
140         char                    wake_lock_name[16];
141 };
142
143 struct tegra_dtv_context {
144         struct tegra_dtv_hw_config config;
145         struct clk                *clk;
146         int                        clk_enabled;
147
148         phys_addr_t                phys;
149         void * __iomem base;
150         unsigned long              dma_req_sel;
151
152         struct dtv_stream          stream;
153         /* debugfs */
154         struct dentry             *d;
155         /* for refer back */
156         struct platform_device    *pdev;
157         struct miscdevice          miscdev;
158 };
159
160 static inline struct tegra_dtv_context *to_ctx(struct dtv_stream *s)
161 {
162         return container_of(s, struct tegra_dtv_context, stream);
163 }
164
165 /* access control */
166 static atomic_t tegra_dtv_instance_nr = ATOMIC_INIT(1);
167
168 static inline u32 tegra_dtv_readl(struct tegra_dtv_context *dtv,
169                                             unsigned long reg)
170 {
171         BUG_ON(!dtv->clk_enabled);
172         return readl(dtv->base + reg);
173 }
174
175 static inline void tegra_dtv_writel(struct tegra_dtv_context *dtv,
176                                     u32 val, unsigned long reg)
177 {
178         BUG_ON(!dtv->clk_enabled);
179         writel(val, dtv->base + reg);
180 }
181
182 /* process */
183 static inline void prevent_suspend(struct dtv_stream *s)
184 {
185         pr_debug("%s called.\n", __func__);
186         cancel_work_sync(&s->work);
187         wake_lock(&s->wake_lock);
188 }
189
190 static void tegra_dtv_worker(struct work_struct *w)
191 {
192         struct dtv_stream *s = container_of(w, struct dtv_stream, work);
193         pr_debug("%s called.\n", __func__);
194         wake_unlock(&s->wake_lock);
195 }
196
197 static inline void wakeup_suspend(struct dtv_stream *s)
198 {
199         schedule_work(&s->work);
200 }
201
202 static inline bool wait_till_stopped(struct dtv_stream *s)
203 {
204         int ret;
205
206         pr_debug("%s: wait for completion\n", __func__);
207
208         ret = wait_for_completion_timeout(
209                 &s->stop_completion, HZ);
210         if (!ret)
211                 pr_err("%s: wait timed out", __func__);
212         if (ret < 0)
213                 pr_err("%s: wait error %d\n", __func__, ret);
214
215         wakeup_suspend(s);
216
217         pr_debug("%s: done: %d\n", __func__, ret);
218
219         return true;
220 }
221
222 /* dma transfer */
223 static inline bool are_xfers_pending(struct dtv_stream *s)
224 {
225         int i;
226
227         pr_debug("%s called\n", __func__);
228
229         for (i = 0; i < s->num_bufs; i++)
230                 if (!completion_done(&s->comp[i]))
231                         return true;
232         return false;
233 }
234
235 static void tegra_dtv_rx_dma_complete(struct tegra_dma_req *req)
236 {
237         unsigned long flags;
238         unsigned req_num;
239         struct dtv_stream *s = req->dev;
240
241         spin_lock_irqsave(&s->dma_req_lock, flags);
242
243         pr_debug("%s called.\n", __func__);
244
245         req_num = req - s->dma_req;
246         pr_debug("%s: complete buffer %d size %d bytes\n",
247                  __func__, req_num, req->bytes_transferred);
248         BUG_ON(req_num >= s->num_bufs);
249
250         complete(&s->comp[req_num]);
251
252         if (!are_xfers_pending(s))
253                 pr_debug("%s: overflow.\n", __func__);
254
255         spin_unlock_irqrestore(&s->dma_req_lock, flags);
256 }
257
258 /* hw */
259 static inline void _dtv_enable_protocol(struct tegra_dtv_context *dtv_ctx)
260 {
261         u32 val;
262
263         val = tegra_dtv_readl(dtv_ctx, DTV_MODE);
264         val &= ~0x01;
265         val |= DTV_MODE_PRTL_ENABLE;
266         tegra_dtv_writel(dtv_ctx, val, DTV_MODE);
267 }
268
269 static inline void _dtv_disable_protocol(struct tegra_dtv_context *dtv_ctx)
270 {
271         u32 val;
272
273         val = tegra_dtv_readl(dtv_ctx, DTV_MODE);
274         val &= ~DTV_MODE_PRTL_ENABLE;
275         tegra_dtv_writel(dtv_ctx, val, DTV_MODE);
276 }
277
278 static inline u32 _dtv_get_status(struct tegra_dtv_context *dtv_ctx)
279 {
280         return tegra_dtv_readl(dtv_ctx, DTV_STATUS);
281 }
282
283 static inline void _dtv_set_attn_level(struct tegra_dtv_context *dtv_ctx)
284 {
285         /* TODO: consider have this set to corresponding transfer request */
286         u32 val;
287
288         val = tegra_dtv_readl(dtv_ctx, DTV_CTRL);
289         val &= ~DTV_CTRL_FIFO_ATTN_LEVEL_MASK;
290         val |= DTV_CTRL_FIFO_ATTN_FOUR_WORD;
291         tegra_dtv_writel(dtv_ctx, val, DTV_CTRL);
292 }
293
294 /* ioctl */
295 static inline void _dtv_set_hw_params(struct tegra_dtv_context *dtv_ctx)
296 {
297         u32 val = 0;
298         u32 reg;
299         struct tegra_dtv_hw_config *cfg = &dtv_ctx->config;
300
301         val = (cfg->clk_edge << DTV_MODE_CLK_EDGE_SHIFT) |
302                 (cfg->protocol_sel << DTV_MODE_PRTL_SEL_SHIFT) |
303                 (cfg->clk_mode << DTV_MODE_CLK_MODE_SHIFT);
304         reg = tegra_dtv_readl(dtv_ctx, DTV_MODE);
305         reg &= ~(DTV_MODE_CLK_EDGE_MASK |
306                  DTV_MODE_PRTL_SEL_MASK |
307                  DTV_MODE_CLK_MODE_MASK);
308         reg |= val;
309         tegra_dtv_writel(dtv_ctx, reg, DTV_MODE);
310
311         val = 0;
312         reg = 0;
313         val = (cfg->fec_size << DTV_CTRL_FEC_SIZE_SHIFT) |
314                 (cfg->body_size << DTV_CTRL_BODY_SIZE_SHIFT) |
315                 (cfg->body_valid_sel << DTV_CTRL_BODY_VALID_SEL_SHIFT) |
316                 (cfg->start_sel << DTV_CTRL_START_SEL_SHIFT) |
317                 (cfg->err_pol << DTV_CTRL_ERROR_POLARITY_SHIFT) |
318                 (cfg->psync_pol << DTV_CTRL_PSYNC_POLARITY_SHIFT) |
319                 (cfg->valid_pol << DTV_CTRL_VALID_POLARITY_SHIFT);
320         reg = tegra_dtv_readl(dtv_ctx, DTV_CTRL);
321         reg &= ~(DTV_CTRL_FEC_SIZE_MASK |
322                  DTV_CTRL_BODY_SIZE_MASK |
323                  DTV_CTRL_BODY_VALID_SEL_MASK |
324                  DTV_CTRL_START_SEL_MASK |
325                  DTV_CTRL_ERROR_POLARITY_MASK |
326                  DTV_CTRL_PSYNC_POLARITY_MASK |
327                  DTV_CTRL_VALID_POLARITY_MASK);
328         reg |= val;
329         tegra_dtv_writel(dtv_ctx, reg, DTV_CTRL);
330 }
331
332 #define DTV_GET_REG_VAL(x, reg, seg)                            \
333         ((x & reg##_##seg##_MASK) >> reg##_##seg##_SHIFT)
334
335 static inline void _dtv_get_hw_params(struct tegra_dtv_context *dtv_ctx,
336                                       struct tegra_dtv_hw_config *cfg)
337 {
338         u32 reg;
339
340         reg = tegra_dtv_readl(dtv_ctx, DTV_MODE);
341         cfg->clk_edge = DTV_GET_REG_VAL(reg, DTV_MODE, CLK_EDGE);
342         cfg->protocol_sel = DTV_GET_REG_VAL(reg, DTV_MODE, PRTL_SEL);
343         cfg->clk_mode = DTV_GET_REG_VAL(reg, DTV_MODE, CLK_MODE);
344
345         reg = tegra_dtv_readl(dtv_ctx, DTV_CTRL);
346         cfg->fec_size = DTV_GET_REG_VAL(reg, DTV_CTRL, FEC_SIZE);
347         cfg->body_size = DTV_GET_REG_VAL(reg, DTV_CTRL, BODY_SIZE);
348         cfg->body_valid_sel = DTV_GET_REG_VAL(reg, DTV_CTRL, BODY_VALID_SEL);
349         cfg->start_sel = DTV_GET_REG_VAL(reg, DTV_CTRL, START_SEL);
350         cfg->err_pol = DTV_GET_REG_VAL(reg, DTV_CTRL, ERROR_POLARITY);
351         cfg->psync_pol = DTV_GET_REG_VAL(reg, DTV_CTRL, PSYNC_POLARITY);
352         cfg->valid_pol = DTV_GET_REG_VAL(reg, DTV_CTRL, VALID_POLARITY);
353 }
354
355 /* must call with stream->dma_req_lock held. */
356 static int stop_xfer_unsafe(struct dtv_stream *s)
357 {
358         int spin = 0;
359         struct tegra_dtv_context *dtv_ctx = to_ctx(s);
360
361         pr_debug("%s called\n", __func__);
362         tegra_dma_cancel(s->dma_chan);
363         _dtv_disable_protocol(dtv_ctx);
364         while ((_dtv_get_status(dtv_ctx) & DTV_STATUS_RXF_FULL) &&
365                spin < 100) {
366                 udelay(10);
367                 if (spin++ > 50)
368                         pr_info("%s : spin %d\n", __func__, spin);
369         }
370         if (spin == 100)
371                 pr_warn("%s : spinny\n", __func__);
372
373         return 0;
374 }
375
376 /* must call with stream->mtx held */
377 static void __force_xfer_stop(struct dtv_stream *s)
378 {
379         int i;
380
381         pr_debug("%s called.\n", __func__);
382
383         if (!s->stopped) {
384                 s->stopped = true;
385                 if (are_xfers_pending(s))
386                         wait_till_stopped(s);
387                 for (i = 0; i < s->num_bufs; i++) {
388                         init_completion(&s->comp[i]);
389                         complete(&s->comp[i]);
390                 }
391         }
392
393         tegra_dma_cancel(s->dma_chan);
394         s->xferring = false;
395
396         pr_debug("%s: done\n", __func__);
397 }
398
399 static long tegra_dtv_ioctl(struct file *file, unsigned int cmd,
400                             unsigned long arg)
401 {
402         int ret = 0;
403         struct tegra_dtv_context *dtv_ctx;
404         struct dtv_stream *s;
405
406         dtv_ctx = (struct tegra_dtv_context *) file->private_data;
407         s = &dtv_ctx->stream;
408
409         /* process may sleep on this */
410         mutex_lock(&s->mtx);
411
412         switch (cmd) {
413         case TEGRA_DTV_IOCTL_START:
414                 pr_debug("%s: run serial ts handling.\n", __func__);
415                 s->stopped = false;
416                 break;
417         case TEGRA_DTV_IOCTL_STOP:
418                 pr_debug("%s: stop serial ts handling.\n", __func__);
419                 if (s->xferring) {
420                         stop_xfer_unsafe(s);
421                         complete(&s->stop_completion);
422                         __force_xfer_stop(s);
423                         s->stopped = true;
424                 }
425                 break;
426         case TEGRA_DTV_IOCTL_SET_HW_CONFIG:
427         {
428                 struct tegra_dtv_hw_config cfg;
429
430                 if (s->xferring) {
431                         pr_err("%s: tranfering is in progress.\n", __func__);
432                         ret = -EBUSY;
433                         break;
434                 }
435
436                 if (copy_from_user(&cfg, (const void __user  *) arg,
437                                    sizeof(cfg))) {
438                         ret = -EFAULT;
439                         break;
440                 }
441
442                 dtv_ctx->config = cfg;
443                 _dtv_set_hw_params(dtv_ctx);
444                 break;
445         }
446         case TEGRA_DTV_IOCTL_GET_HW_CONFIG:
447         {
448                 struct tegra_dtv_hw_config cfg;
449
450                 _dtv_get_hw_params(dtv_ctx, &cfg);
451
452                 if (copy_to_user((void __user  *)arg, &cfg,
453                                  sizeof(cfg)))
454                         ret = -EFAULT;
455                 break;
456         }
457         default:
458                 ret = -EINVAL;
459         }
460
461         mutex_unlock(&s->mtx);
462
463         return ret;
464 }
465
466 /* must call with stream->dma_req_lock held. */
467 static int start_xfer_unsafe(struct dtv_stream *s, size_t size)
468 {
469         int i;
470         u32 reg;
471         struct tegra_dtv_context *dtv_ctx = to_ctx(s);
472
473         BUG_ON(are_xfers_pending(s));
474
475         pr_debug("%s called.\n", __func__);
476
477         for (i = 0; i < s->num_bufs; i++) {
478                 init_completion(&s->comp[i]);
479                 s->dma_req[i].dest_addr = s->buf_phy[i];
480                 s->dma_req[i].size = size;
481                 tegra_dma_enqueue_req(s->dma_chan, &s->dma_req[i]);
482         }
483
484         s->last_queued = s->num_bufs - 1;
485
486         /* too late ? */
487         _dtv_set_attn_level(dtv_ctx);
488         _dtv_enable_protocol(dtv_ctx);
489
490         reg = tegra_dtv_readl(dtv_ctx, DTV_MODE);
491         pr_debug("DTV_MODE = 0x%08x\n", reg);
492
493         return 0;
494 }
495
496 static int try_start_fill_buf(struct dtv_stream *s, size_t size)
497 {
498         int ret = 0;
499         unsigned long flags;
500
501         pr_debug("%s called\n", __func__);
502
503         prevent_suspend(s);
504
505         spin_lock_irqsave(&s->dma_req_lock, flags);
506         if (!s->stopped && !are_xfers_pending(s)) {
507                 ret = start_xfer_unsafe(s, size);
508                 if (ret) {
509                         pr_err("%s: start tranfer failed.\n", __func__);
510                         /* let process not wait stupid */
511                         wakeup_suspend(s);
512                 }
513         }
514         spin_unlock_irqrestore(&s->dma_req_lock, flags);
515
516         return ret;
517 }
518
519 static ssize_t tegra_dtv_read(struct file *file, char __user *buf,
520                               size_t size, loff_t *off)
521 {
522         ssize_t ret;
523         ssize_t xfer_size = 0;
524         int     buf_no;
525         struct tegra_dma_req *req;
526         struct tegra_dtv_context *dtv_ctx;
527
528         dtv_ctx = (struct tegra_dtv_context *) file->private_data;
529
530         mutex_lock(&dtv_ctx->stream.mtx);
531
532         if (!IS_ALIGNED(size, 4) || size < 4 ||
533             size > dtv_ctx->stream.buf_size) {
534                 pr_err("%s: invalid user size %d\n", __func__, size);
535                 ret = -EINVAL;
536                 mutex_unlock(&dtv_ctx->stream.mtx);
537                 return ret;
538         }
539
540         pr_debug("%s: read %d bytes.\n", __func__, size);
541
542         if (dtv_ctx->stream.stopped) {
543                 pr_debug("%s: tegra dtv transferring is stopped.\n",
544                          __func__);
545                 ret = 0;
546                 mutex_unlock(&dtv_ctx->stream.mtx);
547                 return ret;
548         }
549
550         /* start dma transfer */
551         ret = try_start_fill_buf(&dtv_ctx->stream, size);
552         if (ret < 0 && ret != -EALREADY) {
553                 pr_err("%s: could not start recording.\n", __func__);
554                 mutex_unlock(&dtv_ctx->stream.mtx);
555                 return ret;
556         }
557         dtv_ctx->stream.xferring = true;
558
559         buf_no = (dtv_ctx->stream.last_queued + 1) % dtv_ctx->stream.num_bufs;
560         pr_debug("%s: buf_no = %d\n", __func__, buf_no);
561
562         /* Wait for the buffers to be filled up. The maximum timeout
563           *value should be caculated dynamically based on
564          * buf_size(dtv_ctx->stream).buf_size. For isdb-t 1seg signal,
565           *it bit rate is 300 - 456 kpbs, if buf_size = 4096 bytes, then
566          * to fill up one buffer takes ~77ms.
567          */
568         ret = wait_for_completion_interruptible_timeout(
569                 &dtv_ctx->stream.comp[buf_no], HZ);
570         if (!ret) {
571                 pr_err("%s: timeout", __func__);
572                 ret = -ETIMEDOUT;
573                 mutex_unlock(&dtv_ctx->stream.mtx);
574                 return ret;
575         } else if (ret < 0) {
576                 pr_err("%s: wait error %d", __func__, ret);
577                 mutex_unlock(&dtv_ctx->stream.mtx);
578                 return ret;
579         }
580
581         req = &dtv_ctx->stream.dma_req[buf_no];
582
583         /* xfer cannot exceed buffer size */
584         xfer_size = size > req->size ? req->size : size;
585         req->size = size;
586         dma_sync_single_for_cpu(NULL,
587                                 dtv_ctx->stream.dma_req[buf_no].dest_addr,
588                                 dtv_ctx->stream.dma_req[buf_no].size,
589                                 DMA_FROM_DEVICE);
590         ret = copy_to_user(buf, dtv_ctx->stream.buffer[buf_no], xfer_size);
591         if (ret) {
592                 ret = -EFAULT;
593                 mutex_unlock(&dtv_ctx->stream.mtx);
594                 return ret;
595         }
596
597         /* not stopped, reinitial stop */
598         init_completion(&dtv_ctx->stream.stop_completion);
599
600         dtv_ctx->stream.last_queued = buf_no;
601
602         /* refill copied buffer */
603         ret = tegra_dma_enqueue_req(dtv_ctx->stream.dma_chan, req);
604         BUG_ON(ret);
605
606         ret = xfer_size;
607         *off += xfer_size;
608
609         mutex_unlock(&dtv_ctx->stream.mtx);
610
611         pr_debug("%s : done with ret = %d\n", __func__, ret);
612
613         return ret;
614 }
615
616 static int tegra_dtv_open(struct inode *inode, struct file *file)
617 {
618         int i;
619         struct miscdevice *miscdev = file->private_data;
620         struct tegra_dtv_context *dtv_ctx =
621                 container_of(miscdev, struct tegra_dtv_context, miscdev);
622         file->private_data = dtv_ctx;
623
624         dtv_ctx = (struct tegra_dtv_context *) file->private_data;
625
626         pr_debug("%s called\n", __func__);
627
628         /* can be opened once */
629         if (!atomic_dec_and_test(&tegra_dtv_instance_nr)) {
630                 atomic_inc(&tegra_dtv_instance_nr);
631                 pr_err("tegra_dtv device can only be opened once.\n");
632                 return -EBUSY;
633         }
634
635         mutex_lock(&dtv_ctx->stream.mtx);
636
637         dtv_ctx->stream.stopped = false;
638
639         /* cleanup completion */
640         for (i = 0; i < dtv_ctx->stream.num_bufs; i++) {
641                 init_completion(&dtv_ctx->stream.comp[i]);
642                 /* complete all */
643                 complete(&dtv_ctx->stream.comp[i]);
644         }
645
646         mutex_unlock(&dtv_ctx->stream.mtx);
647
648         return 0;
649 }
650
651 static int tegra_dtv_release(struct inode *inode, struct file *file)
652 {
653         struct tegra_dtv_context *dtv_ctx =
654                 (struct tegra_dtv_context *) file->private_data;
655
656         pr_debug("%s called\n", __func__);
657
658         atomic_inc(&tegra_dtv_instance_nr);
659
660         mutex_lock(&dtv_ctx->stream.mtx);
661         if (dtv_ctx->stream.xferring) {
662                 stop_xfer_unsafe(&dtv_ctx->stream);
663                 /* clean up stop condition */
664                 complete(&dtv_ctx->stream.stop_completion);
665                 __force_xfer_stop(&dtv_ctx->stream);
666         }
667         /* wakeup any pending process */
668         wakeup_suspend(&dtv_ctx->stream);
669         mutex_unlock(&dtv_ctx->stream.mtx);
670
671         pr_debug("%s : done\n", __func__);
672
673         return 0;
674 }
675
676 static const struct file_operations tegra_dtv_fops = {
677         .owner = THIS_MODULE,
678         .open = tegra_dtv_open,
679         .read = tegra_dtv_read,
680         .unlocked_ioctl = tegra_dtv_ioctl,
681         .release = tegra_dtv_release,
682 };
683
684 #ifdef CONFIG_DEBUG_FS
685 static int dtv_reg_show(struct seq_file *s, void *unused)
686 {
687         struct tegra_dtv_context *dtv_ctx = s->private;
688
689         seq_printf(s, "tegra_dtv register list\n");
690         seq_printf(s, "-------------------------------\n");
691         seq_printf(s, "DTV_SPI_CONTROL_0: 0x%08x\n",
692                    tegra_dtv_readl(dtv_ctx, DTV_SPI_CONTROL));
693         seq_printf(s, "DTV_MODE_0:        0x%08x\n",
694                    tegra_dtv_readl(dtv_ctx, DTV_MODE));
695         seq_printf(s, "DTV_CONTROL:       0x%08x\n",
696                    tegra_dtv_readl(dtv_ctx, DTV_CTRL));
697         seq_printf(s, "DTV_FIFO:          0x%08x\n",
698                    tegra_dtv_readl(dtv_ctx, DTV_RX_FIFO));
699
700         return 0;
701
702 }
703
704 static int dtv_debugfs_open(struct inode *inode, struct file *file)
705 {
706         return single_open(file, dtv_reg_show, inode->i_private);
707 }
708
709 static const struct file_operations dtv_debugfs_fops = {
710         .open = dtv_debugfs_open,
711         .read = seq_read,
712         .llseek = seq_lseek,
713         .release = single_release,
714 };
715
716 static int dtv_debugfs_init(struct tegra_dtv_context *dtv_ctx)
717 {
718         struct dentry *d;
719
720         d = debugfs_create_file("tegra_dtv", S_IRUGO, NULL, dtv_ctx,
721                                 &dtv_debugfs_fops);
722         if (!d)
723                 return -ENOMEM;
724
725         dtv_ctx->d = d;
726
727         return 0;
728 }
729
730 static void dtv_debugfs_exit(struct tegra_dtv_context *dtv_ctx)
731 {
732         debugfs_remove(dtv_ctx->d);
733 }
734 #else
735 static int dtv_debugfs_init(struct tegra_dtv_context *dtv_ctx) { return 0; }
736 static void dtv_debugfs_exit(struct tegra_dtv_context *dtv_ctx) {};
737 #endif
738
739 static void setup_dma_rx_request(struct tegra_dma_req *req,
740                             struct dtv_stream *s)
741 {
742         struct tegra_dtv_context *dtv_ctx;
743
744         pr_debug("%s before to_ctx\n", __func__);
745         dtv_ctx = to_ctx(s);
746
747         pr_debug("%s called\n", __func__);
748
749         memset(req, 0, sizeof(*req));
750
751         req->complete = tegra_dtv_rx_dma_complete;
752         req->dev = s;
753         req->to_memory = true;
754         req->req_sel = TEGRA_DMA_REQ_SEL_DTV;
755
756         req->source_addr = dtv_ctx->phys + DTV_RX_FIFO;
757         req->source_wrap = 4;
758         req->source_bus_width = 32;
759         req->fixed_burst_size = 1;
760
761         req->dest_wrap = 0;
762         req->dest_bus_width = 32;
763 }
764
765 static int setup_dma(struct tegra_dtv_context *dtv_ctx)
766 {
767         int ret = 0;
768         int i;
769
770         pr_debug("%s called\n", __func__);
771
772         for (i = 0; i < dtv_ctx->stream.num_bufs; i++) {
773                 dtv_ctx->stream.buf_phy[i] = dma_map_single(
774                         &dtv_ctx->pdev->dev,
775                         dtv_ctx->stream.buffer[i],
776                         dtv_ctx->stream.buf_size,
777                         DMA_FROM_DEVICE);
778                 BUG_ON(!dtv_ctx->stream.buf_phy[i]);
779                 setup_dma_rx_request(&dtv_ctx->stream.dma_req[i],
780                                      &dtv_ctx->stream);
781                 dtv_ctx->stream.dma_req[i].dest_addr =
782                         dtv_ctx->stream.buf_phy[i];
783         }
784         dtv_ctx->stream.dma_chan = tegra_dma_allocate_channel(
785                 TEGRA_DMA_MODE_CONTINUOUS_SINGLE,
786                 "tegra_dtv_rx", dtv_ctx->dma_req_sel);
787         if (!dtv_ctx->stream.dma_chan) {
788                 pr_err("%s : cannot allocate input DMA channel: %ld\n",
789                        __func__, PTR_ERR(dtv_ctx->stream.dma_chan));
790                 ret = -ENODEV;
791                 /* release */
792                 for (i = 0; i < dtv_ctx->stream.num_bufs; i++) {
793                         dma_unmap_single(&dtv_ctx->pdev->dev,
794                                          dtv_ctx->stream.buf_phy[i],
795                                          1 << DTV_BUF_SIZE_ORDER,
796                                          DMA_FROM_DEVICE);
797                         dtv_ctx->stream.buf_phy[i] = 0;
798                 }
799                 tegra_dma_free_channel(dtv_ctx->stream.dma_chan);
800                 dtv_ctx->stream.dma_chan = 0;
801
802                 return ret;
803         }
804
805         return ret;
806 }
807
808 static void tear_down_dma(struct tegra_dtv_context *dtv_ctx)
809 {
810         int i;
811
812         pr_debug("%s called\n", __func__);
813
814         for (i = 0; i < dtv_ctx->stream.num_bufs; i++) {
815                 dma_unmap_single(&dtv_ctx->pdev->dev,
816                                  dtv_ctx->stream.buf_phy[i],
817                                  1 << DTV_BUF_SIZE_ORDER,
818                                  DMA_FROM_DEVICE);
819                 dtv_ctx->stream.buf_phy[i] = 0;
820         }
821         tegra_dma_free_channel(dtv_ctx->stream.dma_chan);
822         dtv_ctx->stream.dma_chan = 0;
823 }
824
825 static int init_stream_buffer(struct dtv_stream *s, unsigned num)
826 {
827         int ret;
828         int i, j;
829
830         pr_debug("%s (num %d)\n", __func__, num);
831
832         for (i = 0; i < num; i++) {
833                 kfree(s->buffer[i]);
834                 s->buffer[i] = kmalloc((1 << DTV_BUF_SIZE_ORDER),
835                                        GFP_KERNEL | GFP_DMA);
836                 if (!s->buffer[i]) {
837                         pr_err("%s : cannot allocate buffer.\n", __func__);
838                         for (j = i - 1; j >= 0; j--) {
839                                 kfree(s->buffer[j]);
840                                 s->buffer[j] = 0;
841                         }
842                         ret = -ENOMEM;
843                         return ret;
844                 }
845         }
846         return 0;
847 }
848
849 static void release_stream_buffer(struct dtv_stream *s, unsigned num)
850 {
851         int i;
852
853         pr_debug("%s (num %d)\n", __func__, num);
854
855         for (i = 0; i < num; i++) {
856                 kfree(s->buffer[i]);
857                 s->buffer[i] = 0;
858         }
859 }
860
861 static int setup_stream(struct dtv_stream *stream)
862 {
863         int ret = 0;
864         int i;
865
866         pr_debug("%s called\n", __func__);
867
868         stream->xferring = false;
869         mutex_init(&stream->mtx);
870         init_completion(&stream->stop_completion);
871         spin_lock_init(&stream->dma_req_lock);
872         stream->dma_chan = NULL;
873         stream->fifo_atn_level = DTV_FIFO_ATN_LVL_TOP_GEAR;
874         stream->buf_size = 1 << DTV_BUF_SIZE_ORDER;
875         stream->num_bufs = DTV_MAX_NUM_BUFS;
876         /* init each buffer */
877         for (i = 0; i < stream->num_bufs; i++) {
878                 init_completion(&stream->comp[i]);
879                 /* complete all at this moment */
880                 complete(&stream->comp[i]);
881                 stream->buffer[i] = 0;
882                 stream->buf_phy[i] = 0;
883         }
884         stream->last_queued = 0;
885         ret = init_stream_buffer(stream, stream->num_bufs);
886         if (ret < 0)
887                 return ret;
888
889         INIT_WORK(&stream->work, tegra_dtv_worker);
890         wake_lock_init(&stream->wake_lock, WAKE_LOCK_SUSPEND, "tegra_dtv");
891
892         return ret;
893 }
894
895 static int tegra_dtv_probe(struct platform_device *pdev)
896 {
897         int ret;
898         struct tegra_dtv_context *dtv_ctx;
899         struct clk *clk;
900         struct resource *res;
901
902         pr_info("%s: probing dtv.\n", __func__);
903
904         dtv_ctx = devm_kzalloc(&pdev->dev, sizeof(struct tegra_dtv_context),
905                                GFP_KERNEL);
906         if (!dtv_ctx) {
907                 pr_err("%s: Failed to allocate memory for dtv context.\n",
908                        __func__);
909                 ret = -ENOMEM;
910                 return ret;
911         }
912         platform_set_drvdata(pdev, dtv_ctx);
913
914         /* for refer back */
915         dtv_ctx->pdev = pdev;
916
917         /* enable clk for dtv */
918         clk = clk_get(&pdev->dev, NULL);
919         if (!clk) {
920                 dev_err(&pdev->dev, "cannot get clock for tegra_dtv.\n");
921                 ret = -EIO;
922                 goto fail_no_clk;
923         }
924         dtv_ctx->clk = clk;
925         ret = clk_enable(clk);
926         if (ret < 0) {
927                 dev_err(&pdev->dev, "cannot enable clk for tegra_dtv.\n");
928                 goto fail_clk_enable;
929         }
930         dtv_ctx->clk_enabled = 1;
931
932         /* get resource */
933         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
934         if (unlikely(!res)) {
935                 pr_err("%s: Failed to get resource for dtv.\n",
936                        __func__);
937                 ret = -ENODEV;
938                 goto fail_no_res;
939         }
940
941         if (!devm_request_mem_region(&pdev->dev, res->start,
942                         resource_size(res), dev_name(&pdev->dev))) {
943                 ret = -EBUSY;
944                 return ret;
945         }
946         dtv_ctx->phys = res->start;
947         dtv_ctx->base = devm_ioremap(&pdev->dev, res->start,
948                                      resource_size(res));
949         if (!dtv_ctx->base) {
950                 dev_err(&pdev->dev, "cannot ioremap iomem.\n");
951                 ret = -ENOMEM;
952                 return ret;
953         }
954
955         ret = setup_stream(&dtv_ctx->stream);
956         if (ret < 0)
957                 goto fail_setup_stream;
958
959         ret = setup_dma(dtv_ctx);
960         if (ret < 0)
961                 goto fail_setup_dma;
962
963         /* register as a misc device */
964         dtv_ctx->miscdev.minor = MISC_DYNAMIC_MINOR;
965         dtv_ctx->miscdev.name = TEGRA_DTV_NAME;
966         dtv_ctx->miscdev.fops = &tegra_dtv_fops;
967         ret = misc_register(&dtv_ctx->miscdev);
968         if (ret) {
969                 pr_err("%s: Unable to register misc device.\n",
970                        __func__);
971                 ret = -ENODEV;
972                 goto fail_misc_reg;
973         }
974
975         ret = dtv_debugfs_init(dtv_ctx);
976         if (ret) {
977                 pr_err("%s: Unable to register debugfs entry.\n",
978                        __func__);
979                 goto fail_debugfs_reg;
980         }
981
982         return 0;
983
984 fail_debugfs_reg:
985         dtv_debugfs_exit(dtv_ctx);
986 fail_misc_reg:
987         misc_deregister(&dtv_ctx->miscdev);
988 fail_setup_stream:
989 fail_setup_dma:
990         tear_down_dma(dtv_ctx);
991 fail_no_res:
992 fail_clk_enable:
993 fail_no_clk:
994         if (clk)
995                 clk_put(clk);
996
997         return ret;
998 }
999
1000 static int __devexit tegra_dtv_remove(struct platform_device *pdev)
1001 {
1002         struct tegra_dtv_context *dtv_ctx;
1003
1004         pr_info("%s: remove dtv.\n", __func__);
1005
1006         dtv_ctx = platform_get_drvdata(pdev);
1007
1008         dtv_debugfs_exit(dtv_ctx);
1009         tear_down_dma(dtv_ctx);
1010         release_stream_buffer(&dtv_ctx->stream, dtv_ctx->stream.num_bufs);
1011
1012         clk_put(dtv_ctx->clk);
1013
1014         misc_deregister(&dtv_ctx->miscdev);
1015
1016         return 0;
1017 }
1018
1019 #ifdef CONFIG_PM
1020 static int tegra_dtv_suspend(struct platform_device *pdev, pm_message_t state)
1021 {
1022         struct tegra_dtv_context *dtv_ctx;
1023
1024         pr_info("%s: suspend dtv.\n", __func__);
1025
1026         dtv_ctx = platform_get_drvdata(pdev);
1027
1028         /* stop xferring */
1029         mutex_lock(&dtv_ctx->stream.mtx);
1030         if (dtv_ctx->stream.xferring) {
1031                 stop_xfer_unsafe(&dtv_ctx->stream);
1032                 /* clean up stop condition */
1033                 complete(&dtv_ctx->stream.stop_completion);
1034                 __force_xfer_stop(&dtv_ctx->stream);
1035         }
1036         /* wakeup any pending process */
1037         wakeup_suspend(&dtv_ctx->stream);
1038         mutex_unlock(&dtv_ctx->stream.mtx);
1039
1040         clk_disable(dtv_ctx->clk);
1041
1042         return 0;
1043 }
1044
1045 static int tegra_dtv_resume(struct platform_device *pdev)
1046 {
1047         struct tegra_dtv_context *dtv_ctx;
1048
1049         pr_info("%s: resume dtv.\n", __func__);
1050
1051         dtv_ctx = platform_get_drvdata(pdev);
1052         clk_enable(dtv_ctx->clk);
1053
1054         return 0;
1055 }
1056 #endif /* CONFIG_PM */
1057
1058 static struct platform_driver tegra_dtv_driver = {
1059         .driver = {
1060                 .name = TEGRA_DTV_NAME,
1061                 .owner = THIS_MODULE,
1062         },
1063         .probe = tegra_dtv_probe,
1064         .remove = __devexit_p(tegra_dtv_remove),
1065 #ifdef CONFIG_PM
1066         .suspend = tegra_dtv_suspend,
1067         .resume = tegra_dtv_resume,
1068 #endif
1069 };
1070
1071 static int __init tegra_dtv_init(void)
1072 {
1073         return platform_driver_register(&tegra_dtv_driver);
1074 }
1075
1076 static void __exit tegra_dtv_exit(void)
1077 {
1078         platform_driver_unregister(&tegra_dtv_driver);
1079 }
1080
1081 module_init(tegra_dtv_init);
1082 module_exit(tegra_dtv_exit);
1083
1084 MODULE_AUTHOR("Adam Jiang <chaoj@nvidia.com>");
1085 MODULE_DESCRIPTION("Tegra DTV interface driver");
1086 MODULE_LICENSE("GPL");
1087 MODULE_ALIAS("platform:" TEGRA_DTV_NAME);