DTV: dma: fixed dma burst size issue DTV xmit
[linux-2.6.git] / drivers / media / video / tegra / tegra_dtv.c
1 /*
2  * tegra_dtv.c - Tegra DTV interface driver
3  *
4  * Author: Adam Jiang <chaoj@nvidia.com>
5  * Copyright (c) 2011, NVIDIA Corporation.
6  * Copyright (c) 2012, NVIDIA Corporation.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * version 2 as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful, but
13  * WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20  * 02110-1301 USA
21  *
22  */
23
24 #include <linux/kernel.h>
25 #include <linux/io.h>
26 #include <linux/clk.h>
27 #include <linux/fs.h>
28 #include <linux/completion.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/vmalloc.h>
31 #include <linux/slab.h>
32 #include <linux/spinlock.h>
33 #include <linux/mutex.h>
34 #include <linux/workqueue.h>
35 #include <linux/wakelock.h>
36 #include <linux/platform_device.h>
37 #include <linux/miscdevice.h>
38 #include <linux/debugfs.h>
39 #include <linux/seq_file.h>
40 #include <linux/delay.h>
41
42 #include <media/tegra_dtv.h>
43
44 #include <linux/uaccess.h>
45 #include <mach/iomap.h>
46 #include <mach/dma.h>
47
48 /* offsets from TEGRA_DTV_BASE */
49 #define DTV_SPI_CONTROL         0x40
50 #define DTV_MODE                0x44
51 #define DTV_CTRL                0x48
52 #define DTV_PACKET_COUNT        0x4c
53 #define DTV_ERROR_COUNT         0x50
54 #define DTV_INTERRUPT_STATUS    0x54
55 #define DTV_STATUS              0x58
56 #define DTV_RX_FIFO             0x5c
57
58 /* DTV_SPI_CONTROL */
59 #define DTV_SPI_CONTROL_ENABLE_DTV  1
60
61 /* DTV_MODE_0 */
62 #define DTV_MODE_BYTE_SWIZZLE_SHIFT 6
63 #define DTV_MODE_BYTE_SWIZZLE       (1 << DTV_MODE_BYTE_SWIZZLE_SHIFT)
64 #define DTV_MODE_BIT_SWIZZLE_SHIFT  5
65 #define DTV_MODE_BIT_SWIZZLE        (1 << DTV_MODE_BIT_SWIZZLE_SHIFT)
66 #define DTV_MODE_CLK_EDGE_SHIFT     4
67 #define DTV_MODE_CLK_EDGE_MASK      1
68 #define DTV_MODE_CLK_EDGE_NEG       (1 << DTV_MODE_CLK_EDGE_SHIFT)
69 #define DTV_MODE_PRTL_SEL_SHIFT     2
70 #define DTV_MODE_PRTL_SEL_MASK      (0x3 << DTV_MODE_PRTL_SEL_SHIFT)
71 #define DTV_MODE_CLK_MODE_SHIFT     1
72 #define DTV_MODE_CLK_MODE_MASK      (0x1 << DTV_MODE_CLK_MODE_SHIFT)
73 #define DTV_MODE_PRTL_ENABLE        1
74
75 /* DTV_CONTROL_0 */
76 #define DTV_CTRL_FEC_SIZE_SHIFT         24
77 #define DTV_CTRL_FEC_SIZE_MASK          (0x7F << DTV_CTRL_FEC_SIZE_SHIFT)
78 #define DTV_CTRL_BODY_SIZE_SHIFT        16
79 #define DTV_CTRL_BODY_SIZE_MASK         (0xFF << DTV_CTRL_BODY_SIZE_SHIFT)
80 #define DTV_CTRL_FIFO_ATTN_LEVEL_SHIFT  8
81 #define DTV_CTRL_FIFO_ATTN_LEVEL_MASK   (0x1F << DTV_CTRL_FIFO_ATTN_LEVEL_SHIFT)
82 #define DTV_CTRL_FIFO_ATTN_ONE_WORD     (0 << DTV_CTRL_FIFO_ATTN_LEVEL_SHIFT)
83 #define DTV_CTRL_FIFO_ATTN_TWO_WORD     (1 << DTV_CTRL_FIFO_ATTN_LEVEL_SHIFT)
84 #define DTV_CTRL_FIFO_ATTN_THREE_WORD   (2 << DTV_CTRL_FIFO_ATTN_LEVEL_SHIFT)
85 #define DTV_CTRL_FIFO_ATTN_FOUR_WORD    (3 << DTV_CTRL_FIFO_ATTN_LEVEL_SHIFT)
86 #define DTV_CTRL_BODY_VALID_SEL_SHIFT   6
87 #define DTV_CTRL_BODY_VALID_SEL_MASK    (1 << DTV_CTRL_BODY_VALID_SEL_SHIFT)
88 #define DTV_CTRL_START_SEL_SHIFT        4
89 #define DTV_CTRL_START_SEL_MASK         (1 << DTV_CTRL_START_SEL_SHIFT)
90 #define DTV_CTRL_ERROR_POLARITY_SHIFT   2
91 #define DTV_CTRL_ERROR_POLARITY_MASK    (1 << DTV_CTRL_ERROR_POLARITY_SHIFT)
92 #define DTV_CTRL_PSYNC_POLARITY_SHIFT   1
93 #define DTV_CTRL_PSYNC_POLARITY_MASK    (1 << DTV_CTRL_PSYNC_POLARITY_SHIFT)
94 #define DTV_CTRL_VALID_POLARITY_SHIFT   0
95 #define DTV_CTRL_VALID_POLARITY_MASK    (1 << DTV_CTRL_VALID_POLARITY_SHIFT)
96
97 /* DTV_INTERRUPT_STATUS_0 */
98 #define DTV_INTERRUPT_PACKET_UNDERRUN_ERR 8
99 #define DTV_INTERRUPT_BODY_OVERRUN_ERR    4
100 #define DTV_INTERRUPT_BODY_UNDERRUN_ERR   2
101 #define DTV_INTERRUPT_UPSTREAM_ERR        1
102
103 /* DTV_STATUS_0 */
104 #define DTV_STATUS_RXF_UNDERRUN 4
105 #define DTV_STATUS_RXF_EMPTY    2
106 #define DTV_STATUS_RXF_FULL     1
107
108 #define TEGRA_DTV_NAME "tegra_dtv"
109
110 /* default sw config */
111 #define DTV_BUF_SIZE_ORDER                PAGE_SHIFT
112 #define DTV_MAX_NUM_BUFS                  4
113
114 #define DTV_FIFO_ATN_LVL_LOW_GEAR         0
115 #define DTV_FIFO_ATN_LVL_SECOND_GEAR      1
116 #define DTV_FIFO_ATN_LVL_THIRD_GEAR       2
117 #define DTV_FIFO_ATN_LVL_TOP_GEAR         3
118
119 struct dtv_stream {
120         struct mutex    mtx;
121
122         bool                     xferring;      /* is DMA in progress */
123         unsigned                 num_bufs;
124         void                    *buffer[DTV_MAX_NUM_BUFS];
125         dma_addr_t               buf_phy[DTV_MAX_NUM_BUFS];
126         struct completion        comp[DTV_MAX_NUM_BUFS];
127         struct tegra_dma_req     dma_req[DTV_MAX_NUM_BUFS];
128         int                      last_queued;
129
130         int     fifo_atn_level;
131
132         struct tegra_dma_channel        *dma_chan;
133         bool                             stopped;
134         struct completion                stop_completion;
135         spinlock_t                       dma_req_lock;
136         size_t                           buf_size;
137
138         struct work_struct      work;
139         struct wake_lock        wake_lock;
140         char                    wake_lock_name[16];
141 };
142
143 struct tegra_dtv_context {
144         struct tegra_dtv_hw_config config;
145         struct clk                *clk;
146         int                        clk_enabled;
147
148         phys_addr_t                phys;
149         void * __iomem base;
150         unsigned long              dma_req_sel;
151
152         struct dtv_stream          stream;
153         /* debugfs */
154         struct dentry             *d;
155         /* for refer back */
156         struct platform_device    *pdev;
157 };
158
159 static inline struct tegra_dtv_context *to_ctx(struct dtv_stream *s)
160 {
161         return container_of(s, struct tegra_dtv_context, stream);
162 }
163
164 /* access control */
165 static atomic_t tegra_dtv_instance_nr = ATOMIC_INIT(1);
166
167 static inline u32 tegra_dtv_readl(struct tegra_dtv_context *dtv,
168                                             unsigned long reg)
169 {
170         BUG_ON(!dtv->clk_enabled);
171         return readl(dtv->base + reg);
172 }
173
174 static inline void tegra_dtv_writel(struct tegra_dtv_context *dtv,
175                                     u32 val, unsigned long reg)
176 {
177         BUG_ON(!dtv->clk_enabled);
178         writel(val, dtv->base + reg);
179 }
180
181 /* process */
182 static inline void prevent_suspend(struct dtv_stream *s)
183 {
184         pr_debug("%s called.\n", __func__);
185         cancel_work_sync(&s->work);
186         wake_lock(&s->wake_lock);
187 }
188
189 static void tegra_dtv_worker(struct work_struct *w)
190 {
191         struct dtv_stream *s = container_of(w, struct dtv_stream, work);
192         pr_debug("%s called.\n", __func__);
193         wake_unlock(&s->wake_lock);
194 }
195
196 static inline void wakeup_suspend(struct dtv_stream *s)
197 {
198         schedule_work(&s->work);
199 }
200
201 static inline bool wait_till_stopped(struct dtv_stream *s)
202 {
203         int ret;
204
205         pr_debug("%s: wait for completion\n", __func__);
206
207         ret = wait_for_completion_timeout(
208                 &s->stop_completion, HZ);
209         if (!ret)
210                 pr_err("%s: wait timed out", __func__);
211         if (ret < 0)
212                 pr_err("%s: wait error %d\n", __func__, ret);
213
214         wakeup_suspend(s);
215
216         pr_debug("%s: done: %d\n", __func__, ret);
217
218         return true;
219 }
220
221 /* dma transfer */
222 static inline bool are_xfers_pending(struct dtv_stream *s)
223 {
224         int i;
225
226         pr_debug("%s called\n", __func__);
227
228         for (i = 0; i < s->num_bufs; i++)
229                 if (!completion_done(&s->comp[i]))
230                         return true;
231         return false;
232 }
233
234 static void tegra_dtv_rx_dma_complete(struct tegra_dma_req *req)
235 {
236         unsigned long flags;
237         unsigned req_num;
238         struct dtv_stream *s = req->dev;
239
240         spin_lock_irqsave(&s->dma_req_lock, flags);
241
242         pr_debug("%s called.\n", __func__);
243
244         req_num = req - s->dma_req;
245         pr_debug("%s: complete buffer %d size %d bytes\n",
246                  __func__, req_num, req->bytes_transferred);
247         BUG_ON(req_num >= s->num_bufs);
248
249         complete(&s->comp[req_num]);
250
251         if (!are_xfers_pending(s))
252                 pr_debug("%s: overflow.\n", __func__);
253
254         spin_unlock_irqrestore(&s->dma_req_lock, flags);
255 }
256
257 /* hw */
258 static inline void _dtv_enable_protocol(struct tegra_dtv_context *dtv_ctx)
259 {
260         u32 val;
261
262         val = tegra_dtv_readl(dtv_ctx, DTV_MODE);
263         val &= ~0x01;
264         val |= DTV_MODE_PRTL_ENABLE;
265         tegra_dtv_writel(dtv_ctx, val, DTV_MODE);
266 }
267
268 static inline void _dtv_disable_protocol(struct tegra_dtv_context *dtv_ctx)
269 {
270         u32 val;
271
272         val = tegra_dtv_readl(dtv_ctx, DTV_MODE);
273         val &= ~DTV_MODE_PRTL_ENABLE;
274         tegra_dtv_writel(dtv_ctx, val, DTV_MODE);
275 }
276
277 static inline u32 _dtv_get_status(struct tegra_dtv_context *dtv_ctx)
278 {
279         return tegra_dtv_readl(dtv_ctx, DTV_STATUS);
280 }
281
282 static inline void _dtv_set_attn_level(struct tegra_dtv_context *dtv_ctx)
283 {
284         /* TODO: consider have this set to corresponding transfer request */
285         u32 val;
286
287         val = tegra_dtv_readl(dtv_ctx, DTV_CTRL);
288         val &= ~DTV_CTRL_FIFO_ATTN_LEVEL_MASK;
289         val |= DTV_CTRL_FIFO_ATTN_FOUR_WORD;
290         tegra_dtv_writel(dtv_ctx, val, DTV_CTRL);
291 }
292
293 /* ioctl */
294 static inline void _dtv_set_hw_params(struct tegra_dtv_context *dtv_ctx)
295 {
296         u32 val = 0;
297         u32 reg;
298         struct tegra_dtv_hw_config *cfg = &dtv_ctx->config;
299
300         val = (cfg->clk_edge << DTV_MODE_CLK_EDGE_SHIFT) |
301                 (cfg->protocol_sel << DTV_MODE_PRTL_SEL_SHIFT) |
302                 (cfg->clk_mode << DTV_MODE_CLK_MODE_SHIFT);
303         reg = tegra_dtv_readl(dtv_ctx, DTV_MODE);
304         reg &= ~(DTV_MODE_CLK_EDGE_MASK |
305                  DTV_MODE_PRTL_SEL_MASK |
306                  DTV_MODE_CLK_MODE_MASK);
307         reg |= val;
308         tegra_dtv_writel(dtv_ctx, reg, DTV_MODE);
309
310         val = 0;
311         reg = 0;
312         val = (cfg->fec_size << DTV_CTRL_FEC_SIZE_SHIFT) |
313                 (cfg->body_size << DTV_CTRL_BODY_SIZE_SHIFT) |
314                 (cfg->body_valid_sel << DTV_CTRL_BODY_VALID_SEL_SHIFT) |
315                 (cfg->start_sel << DTV_CTRL_START_SEL_SHIFT) |
316                 (cfg->err_pol << DTV_CTRL_ERROR_POLARITY_SHIFT) |
317                 (cfg->psync_pol << DTV_CTRL_PSYNC_POLARITY_SHIFT) |
318                 (cfg->valid_pol << DTV_CTRL_VALID_POLARITY_SHIFT);
319         reg = tegra_dtv_readl(dtv_ctx, DTV_CTRL);
320         reg &= ~(DTV_CTRL_FEC_SIZE_MASK |
321                  DTV_CTRL_BODY_SIZE_MASK |
322                  DTV_CTRL_BODY_VALID_SEL_MASK |
323                  DTV_CTRL_START_SEL_MASK |
324                  DTV_CTRL_ERROR_POLARITY_MASK |
325                  DTV_CTRL_PSYNC_POLARITY_MASK |
326                  DTV_CTRL_VALID_POLARITY_MASK);
327         reg |= val;
328         tegra_dtv_writel(dtv_ctx, reg, DTV_CTRL);
329 }
330
331 #define DTV_GET_REG_VAL(x, reg, seg)                            \
332         ((x & reg##_##seg##_MASK) >> reg##_##seg##_SHIFT)
333
334 static inline void _dtv_get_hw_params(struct tegra_dtv_context *dtv_ctx,
335                                       struct tegra_dtv_hw_config *cfg)
336 {
337         u32 reg;
338
339         reg = tegra_dtv_readl(dtv_ctx, DTV_MODE);
340         cfg->clk_edge = DTV_GET_REG_VAL(reg, DTV_MODE, CLK_EDGE);
341         cfg->protocol_sel = DTV_GET_REG_VAL(reg, DTV_MODE, PRTL_SEL);
342         cfg->clk_mode = DTV_GET_REG_VAL(reg, DTV_MODE, CLK_MODE);
343
344         reg = tegra_dtv_readl(dtv_ctx, DTV_CTRL);
345         cfg->fec_size = DTV_GET_REG_VAL(reg, DTV_CTRL, FEC_SIZE);
346         cfg->body_size = DTV_GET_REG_VAL(reg, DTV_CTRL, BODY_SIZE);
347         cfg->body_valid_sel = DTV_GET_REG_VAL(reg, DTV_CTRL, BODY_VALID_SEL);
348         cfg->start_sel = DTV_GET_REG_VAL(reg, DTV_CTRL, START_SEL);
349         cfg->err_pol = DTV_GET_REG_VAL(reg, DTV_CTRL, ERROR_POLARITY);
350         cfg->psync_pol = DTV_GET_REG_VAL(reg, DTV_CTRL, PSYNC_POLARITY);
351         cfg->valid_pol = DTV_GET_REG_VAL(reg, DTV_CTRL, VALID_POLARITY);
352 }
353
354 /* must call with stream->dma_req_lock held. */
355 static int stop_xfer_unsafe(struct dtv_stream *s)
356 {
357         int spin = 0;
358         struct tegra_dtv_context *dtv_ctx = to_ctx(s);
359
360         pr_debug("%s called\n", __func__);
361         tegra_dma_cancel(s->dma_chan);
362         _dtv_disable_protocol(dtv_ctx);
363         while ((_dtv_get_status(dtv_ctx) & DTV_STATUS_RXF_FULL) &&
364                spin < 100) {
365                 udelay(10);
366                 if (spin++ > 50)
367                         pr_info("%s : spin %d\n", __func__, spin);
368         }
369         if (spin == 100)
370                 pr_warn("%s : spinny\n", __func__);
371
372         return 0;
373 }
374
375 /* must call with stream->mtx held */
376 static void __force_xfer_stop(struct dtv_stream *s)
377 {
378         int i;
379
380         pr_debug("%s called.\n", __func__);
381
382         if (!s->stopped) {
383                 s->stopped = true;
384                 if (are_xfers_pending(s))
385                         wait_till_stopped(s);
386                 for (i = 0; i < s->num_bufs; i++) {
387                         init_completion(&s->comp[i]);
388                         complete(&s->comp[i]);
389                 }
390         }
391
392         /* just in case. dma should be cancelled before this */
393         if (!tegra_dma_is_empty(s->dma_chan))
394                 pr_err("%s: DMA channel is not empty!\n", __func__);
395         tegra_dma_cancel(s->dma_chan);
396         s->xferring = false;
397
398         pr_debug("%s: done\n", __func__);
399 }
400
401 static long tegra_dtv_ioctl(struct file *file, unsigned int cmd,
402                             unsigned long arg)
403 {
404         int ret = 0;
405         struct tegra_dtv_context *dtv_ctx;
406         struct dtv_stream *s;
407
408         dtv_ctx = (struct tegra_dtv_context *) file->private_data;
409         s = &dtv_ctx->stream;
410
411         /* process may sleep on this */
412         mutex_lock(&s->mtx);
413
414         switch (cmd) {
415         case TEGRA_DTV_IOCTL_START:
416                 pr_debug("%s: run serial ts handling.\n", __func__);
417                 s->stopped = false;
418                 break;
419         case TEGRA_DTV_IOCTL_STOP:
420                 pr_debug("%s: stop serial ts handling.\n", __func__);
421                 if (s->xferring) {
422                         stop_xfer_unsafe(s);
423                         complete(&s->stop_completion);
424                         __force_xfer_stop(s);
425                         s->stopped = true;
426                 }
427                 break;
428         case TEGRA_DTV_IOCTL_SET_HW_CONFIG:
429         {
430                 struct tegra_dtv_hw_config cfg;
431
432                 if (s->xferring) {
433                         pr_err("%s: tranfering is in progress.\n", __func__);
434                         ret = -EBUSY;
435                         break;
436                 }
437
438                 if (copy_from_user(&cfg, (const void __user  *) arg,
439                                    sizeof(cfg))) {
440                         ret = -EFAULT;
441                         break;
442                 }
443
444                 dtv_ctx->config = cfg;
445                 _dtv_set_hw_params(dtv_ctx);
446                 break;
447         }
448         case TEGRA_DTV_IOCTL_GET_HW_CONFIG:
449         {
450                 struct tegra_dtv_hw_config cfg;
451
452                 _dtv_get_hw_params(dtv_ctx, &cfg);
453
454                 if (copy_to_user((void __user  *)arg, &cfg,
455                                  sizeof(cfg)))
456                         ret = -EFAULT;
457                 break;
458         }
459         default:
460                 ret = -EINVAL;
461         }
462
463         mutex_unlock(&s->mtx);
464
465         return ret;
466 }
467
468 /* must call with stream->dma_req_lock held. */
469 static int start_xfer_unsafe(struct dtv_stream *s, size_t size)
470 {
471         int i;
472         u32 reg;
473         struct tegra_dtv_context *dtv_ctx = to_ctx(s);
474
475         BUG_ON(are_xfers_pending(s));
476
477         pr_debug("%s called.\n", __func__);
478
479         for (i = 0; i < s->num_bufs; i++) {
480                 init_completion(&s->comp[i]);
481                 s->dma_req[i].dest_addr = s->buf_phy[i];
482                 s->dma_req[i].size = size;
483                 tegra_dma_enqueue_req(s->dma_chan, &s->dma_req[i]);
484         }
485
486         s->last_queued = s->num_bufs - 1;
487
488         /* too late ? */
489         _dtv_set_attn_level(dtv_ctx);
490         _dtv_enable_protocol(dtv_ctx);
491
492         reg = tegra_dtv_readl(dtv_ctx, DTV_MODE);
493         pr_debug("DTV_MODE = 0x%08x\n", reg);
494
495         return 0;
496 }
497
498 static int try_start_fill_buf(struct dtv_stream *s, size_t size)
499 {
500         int ret = 0;
501         unsigned long flags;
502
503         pr_debug("%s called\n", __func__);
504
505         prevent_suspend(s);
506
507         spin_lock_irqsave(&s->dma_req_lock, flags);
508         if (!s->stopped && !are_xfers_pending(s)) {
509                 ret = start_xfer_unsafe(s, size);
510                 if (ret) {
511                         pr_err("%s: start tranfer failed.\n", __func__);
512                         /* let process not wait stupid */
513                         wakeup_suspend(s);
514                 }
515         }
516         spin_unlock_irqrestore(&s->dma_req_lock, flags);
517
518         return ret;
519 }
520
521 static ssize_t tegra_dtv_read(struct file *file, char __user *buf,
522                               size_t size, loff_t *off)
523 {
524         ssize_t ret;
525         ssize_t xfer_size = 0;
526         int     buf_no;
527         struct tegra_dma_req *req;
528         struct tegra_dtv_context *dtv_ctx;
529
530         dtv_ctx = (struct tegra_dtv_context *) file->private_data;
531
532         mutex_lock(&dtv_ctx->stream.mtx);
533
534         if (!IS_ALIGNED(size, 4) || size < 4 ||
535             size > dtv_ctx->stream.buf_size) {
536                 pr_err("%s: invalid user size %d\n", __func__, size);
537                 ret = -EINVAL;
538                 mutex_unlock(&dtv_ctx->stream.mtx);
539                 return ret;
540         }
541
542         pr_debug("%s: read %d bytes.\n", __func__, size);
543
544         if (dtv_ctx->stream.stopped) {
545                 pr_debug("%s: tegra dtv transferring is stopped.\n",
546                          __func__);
547                 ret = 0;
548                 mutex_unlock(&dtv_ctx->stream.mtx);
549                 return ret;
550         }
551
552         /* start dma transfer */
553         ret = try_start_fill_buf(&dtv_ctx->stream, size);
554         if (ret < 0 && ret != -EALREADY) {
555                 pr_err("%s: could not start recording.\n", __func__);
556                 mutex_unlock(&dtv_ctx->stream.mtx);
557                 return ret;
558         }
559         dtv_ctx->stream.xferring = true;
560
561         buf_no = (dtv_ctx->stream.last_queued + 1) % dtv_ctx->stream.num_bufs;
562         pr_debug("%s: buf_no = %d\n", __func__, buf_no);
563
564         /* Wait for the buffers to be filled up. The maximum timeout
565           *value should be caculated dynamically based on
566          * buf_size(dtv_ctx->stream).buf_size. For isdb-t 1seg signal,
567           *it bit rate is 300 - 456 kpbs, if buf_size = 4096 bytes, then
568          * to fill up one buffer takes ~77ms.
569          */
570         ret = wait_for_completion_interruptible_timeout(
571                 &dtv_ctx->stream.comp[buf_no], HZ);
572         if (!ret) {
573                 pr_err("%s: timeout", __func__);
574                 ret = -ETIMEDOUT;
575                 mutex_unlock(&dtv_ctx->stream.mtx);
576                 return ret;
577         } else if (ret < 0) {
578                 pr_err("%s: wait error %d", __func__, ret);
579                 mutex_unlock(&dtv_ctx->stream.mtx);
580                 return ret;
581         }
582
583         req = &dtv_ctx->stream.dma_req[buf_no];
584
585         /* xfer cannot exceed buffer size */
586         xfer_size = size > req->size ? req->size : size;
587         req->size = size;
588         dma_sync_single_for_cpu(NULL,
589                                 dtv_ctx->stream.dma_req[buf_no].dest_addr,
590                                 dtv_ctx->stream.dma_req[buf_no].size,
591                                 DMA_FROM_DEVICE);
592         ret = copy_to_user(buf, dtv_ctx->stream.buffer[buf_no], xfer_size);
593         if (ret) {
594                 ret = -EFAULT;
595                 mutex_unlock(&dtv_ctx->stream.mtx);
596                 return ret;
597         }
598
599         /* not stopped, reinitial stop */
600         init_completion(&dtv_ctx->stream.stop_completion);
601
602         dtv_ctx->stream.last_queued = buf_no;
603
604         /* refill copied buffer */
605         ret = tegra_dma_enqueue_req(dtv_ctx->stream.dma_chan, req);
606         BUG_ON(ret);
607
608         ret = xfer_size;
609         *off += xfer_size;
610
611         mutex_unlock(&dtv_ctx->stream.mtx);
612
613         pr_debug("%s : done with ret = %d\n", __func__, ret);
614
615         return ret;
616 }
617
618 static int tegra_dtv_open(struct inode *inode, struct file *file)
619 {
620         int i;
621         struct tegra_dtv_context *dtv_ctx;
622
623         dtv_ctx = (struct tegra_dtv_context *) file->private_data;
624
625         pr_debug("%s called\n", __func__);
626
627         /* can be opened once */
628         if (!atomic_dec_and_test(&tegra_dtv_instance_nr)) {
629                 atomic_inc(&tegra_dtv_instance_nr);
630                 pr_err("tegra_dtv device can only be opened once.\n");
631                 return -EBUSY;
632         }
633
634         mutex_lock(&dtv_ctx->stream.mtx);
635
636         dtv_ctx->stream.stopped = false;
637
638         /* cleanup completion */
639         for (i = 0; i < dtv_ctx->stream.num_bufs; i++) {
640                 init_completion(&dtv_ctx->stream.comp[i]);
641                 /* complete all */
642                 complete(&dtv_ctx->stream.comp[i]);
643         }
644
645         mutex_unlock(&dtv_ctx->stream.mtx);
646
647         return 0;
648 }
649
650 static int tegra_dtv_release(struct inode *inode, struct file *file)
651 {
652         struct tegra_dtv_context *dtv_ctx =
653                 (struct tegra_dtv_context *) file->private_data;
654
655         pr_debug("%s called\n", __func__);
656
657         atomic_inc(&tegra_dtv_instance_nr);
658
659         mutex_lock(&dtv_ctx->stream.mtx);
660         if (dtv_ctx->stream.xferring) {
661                 stop_xfer_unsafe(&dtv_ctx->stream);
662                 /* clean up stop condition */
663                 complete(&dtv_ctx->stream.stop_completion);
664                 __force_xfer_stop(&dtv_ctx->stream);
665         }
666         /* wakeup any pending process */
667         wakeup_suspend(&dtv_ctx->stream);
668         mutex_unlock(&dtv_ctx->stream.mtx);
669
670         pr_debug("%s : done\n", __func__);
671
672         return 0;
673 }
674
675 static const struct file_operations tegra_dtv_fops = {
676         .owner = THIS_MODULE,
677         .open = tegra_dtv_open,
678         .read = tegra_dtv_read,
679         .unlocked_ioctl = tegra_dtv_ioctl,
680         .release = tegra_dtv_release,
681 };
682
683 static struct miscdevice tegra_dtv_misc_device = {
684         .minor = MISC_DYNAMIC_MINOR,
685         .name = TEGRA_DTV_NAME,
686         .fops = &tegra_dtv_fops,
687 };
688
689 #ifdef CONFIG_DEBUG_FS
690 static int dtv_reg_show(struct seq_file *s, void *unused)
691 {
692         struct tegra_dtv_context *dtv_ctx = s->private;
693
694         seq_printf(s, "tegra_dtv register list\n");
695         seq_printf(s, "-------------------------------\n");
696         seq_printf(s, "DTV_SPI_CONTROL_0: 0x%08x\n",
697                    tegra_dtv_readl(dtv_ctx, DTV_SPI_CONTROL));
698         seq_printf(s, "DTV_MODE_0:        0x%08x\n",
699                    tegra_dtv_readl(dtv_ctx, DTV_MODE));
700         seq_printf(s, "DTV_CONTROL:       0x%08x\n",
701                    tegra_dtv_readl(dtv_ctx, DTV_CTRL));
702         seq_printf(s, "DTV_FIFO:          0x%08x\n",
703                    tegra_dtv_readl(dtv_ctx, DTV_RX_FIFO));
704
705         return 0;
706
707 }
708
709 static int dtv_debugfs_open(struct inode *inode, struct file *file)
710 {
711         return single_open(file, dtv_reg_show, inode->i_private);
712 }
713
714 static const struct file_operations dtv_debugfs_fops = {
715         .open = dtv_debugfs_open,
716         .read = seq_read,
717         .llseek = seq_lseek,
718         .release = single_release,
719 };
720
721 static int dtv_debugfs_init(struct tegra_dtv_context *dtv_ctx)
722 {
723         struct dentry *d;
724
725         d = debugfs_create_file("tegra_dtv", S_IRUGO, NULL, dtv_ctx,
726                                 &dtv_debugfs_fops);
727         if (!d)
728                 return -ENOMEM;
729
730         dtv_ctx->d = d;
731
732         return 0;
733 }
734
735 static void dtv_debugfs_exit(struct tegra_dtv_context *dtv_ctx)
736 {
737         debugfs_remove(dtv_ctx->d);
738 }
739 #else
740 static int dtv_debugfs_init(struct tegra_dtv_context *dtv_ctx) { return 0 }
741 static void dtv_debugfs_exit(struct tegra_dtv_context *dtv_ctx) {};
742 #endif
743
744 static void setup_dma_rx_request(struct tegra_dma_req *req,
745                             struct dtv_stream *s)
746 {
747         struct tegra_dtv_context *dtv_ctx;
748
749         pr_debug("%s before to_ctx\n", __func__);
750         dtv_ctx = to_ctx(s);
751
752         pr_debug("%s called\n", __func__);
753
754         memset(req, 0, sizeof(*req));
755
756         req->complete = tegra_dtv_rx_dma_complete;
757         req->dev = s;
758         req->to_memory = true;
759         req->req_sel = TEGRA_DMA_REQ_SEL_DTV;
760
761         req->source_addr = dtv_ctx->phys + DTV_RX_FIFO;
762         req->source_wrap = 4;
763         req->source_bus_width = 32;
764         req->fixed_burst_size = 1;
765
766         req->dest_wrap = 0;
767         req->dest_bus_width = 32;
768 }
769
770 static int setup_dma(struct tegra_dtv_context *dtv_ctx)
771 {
772         int ret = 0;
773         int i;
774
775         pr_debug("%s called\n", __func__);
776
777         for (i = 0; i < dtv_ctx->stream.num_bufs; i++) {
778                 dtv_ctx->stream.buf_phy[i] = dma_map_single(
779                         &dtv_ctx->pdev->dev,
780                         dtv_ctx->stream.buffer[i],
781                         dtv_ctx->stream.buf_size,
782                         DMA_FROM_DEVICE);
783                 BUG_ON(!dtv_ctx->stream.buf_phy[i]);
784                 setup_dma_rx_request(&dtv_ctx->stream.dma_req[i],
785                                      &dtv_ctx->stream);
786                 dtv_ctx->stream.dma_req[i].dest_addr =
787                         dtv_ctx->stream.buf_phy[i];
788         }
789         dtv_ctx->stream.dma_chan = tegra_dma_allocate_channel(
790                 TEGRA_DMA_MODE_CONTINUOUS_SINGLE,
791                 "tegra_dtv_rx", dtv_ctx->dma_req_sel);
792         if (!dtv_ctx->stream.dma_chan) {
793                 pr_err("%s : cannot allocate input DMA channel: %ld\n",
794                        __func__, PTR_ERR(dtv_ctx->stream.dma_chan));
795                 ret = -ENODEV;
796                 /* release */
797                 for (i = 0; i < dtv_ctx->stream.num_bufs; i++) {
798                         dma_unmap_single(&dtv_ctx->pdev->dev,
799                                          dtv_ctx->stream.buf_phy[i],
800                                          1 << DTV_BUF_SIZE_ORDER,
801                                          DMA_FROM_DEVICE);
802                         dtv_ctx->stream.buf_phy[i] = 0;
803                 }
804                 tegra_dma_free_channel(dtv_ctx->stream.dma_chan);
805                 dtv_ctx->stream.dma_chan = 0;
806
807                 return ret;
808         }
809
810         return ret;
811 }
812
813 static void tear_down_dma(struct tegra_dtv_context *dtv_ctx)
814 {
815         int i;
816
817         pr_debug("%s called\n", __func__);
818
819         for (i = 0; i < dtv_ctx->stream.num_bufs; i++) {
820                 dma_unmap_single(&dtv_ctx->pdev->dev,
821                                  dtv_ctx->stream.buf_phy[i],
822                                  1 << DTV_BUF_SIZE_ORDER,
823                                  DMA_FROM_DEVICE);
824                 dtv_ctx->stream.buf_phy[i] = 0;
825         }
826         tegra_dma_free_channel(dtv_ctx->stream.dma_chan);
827         dtv_ctx->stream.dma_chan = 0;
828 }
829
830 static int init_stream_buffer(struct dtv_stream *s, unsigned num)
831 {
832         int ret;
833         int i, j;
834
835         pr_debug("%s (num %d)\n", __func__, num);
836
837         for (i = 0; i < num; i++) {
838                 kfree(s->buffer[i]);
839                 s->buffer[i] = kmalloc((1 << DTV_BUF_SIZE_ORDER),
840                                        GFP_KERNEL | GFP_DMA);
841                 if (!s->buffer[i]) {
842                         pr_err("%s : cannot allocate buffer.\n", __func__);
843                         for (j = i - 1; j >= 0; j--) {
844                                 kfree(s->buffer[j]);
845                                 s->buffer[j] = 0;
846                         }
847                         ret = -ENOMEM;
848                         return ret;
849                 }
850         }
851         return 0;
852 }
853
854 static void release_stream_buffer(struct dtv_stream *s, unsigned num)
855 {
856         int i;
857
858         pr_debug("%s (num %d)\n", __func__, num);
859
860         for (i = 0; i < num; i++) {
861                 kfree(s->buffer[i]);
862                 s->buffer[i] = 0;
863         }
864 }
865
866 static int setup_stream(struct dtv_stream *stream)
867 {
868         int ret = 0;
869         int i;
870
871         pr_debug("%s called\n", __func__);
872
873         stream->xferring = false;
874         mutex_init(&stream->mtx);
875         init_completion(&stream->stop_completion);
876         spin_lock_init(&stream->dma_req_lock);
877         stream->dma_chan = NULL;
878         stream->fifo_atn_level = DTV_FIFO_ATN_LVL_TOP_GEAR;
879         stream->buf_size = 1 << DTV_BUF_SIZE_ORDER;
880         stream->num_bufs = DTV_MAX_NUM_BUFS;
881         /* init each buffer */
882         for (i = 0; i < stream->num_bufs; i++) {
883                 init_completion(&stream->comp[i]);
884                 /* complete all at this moment */
885                 complete(&stream->comp[i]);
886                 stream->buffer[i] = 0;
887                 stream->buf_phy[i] = 0;
888         }
889         stream->last_queued = 0;
890         ret = init_stream_buffer(stream, stream->num_bufs);
891         if (ret < 0)
892                 return ret;
893
894         INIT_WORK(&stream->work, tegra_dtv_worker);
895         wake_lock_init(&stream->wake_lock, WAKE_LOCK_SUSPEND, "tegra_dtv");
896
897         return ret;
898 }
899
900 static int tegra_dtv_probe(struct platform_device *pdev)
901 {
902         int ret;
903         struct tegra_dtv_context *dtv_ctx;
904         struct clk *clk;
905         struct resource *res;
906
907         pr_info("%s: probing dtv.\n", __func__);
908
909         dtv_ctx = devm_kzalloc(&pdev->dev, sizeof(struct tegra_dtv_context),
910                                GFP_KERNEL);
911         if (!dtv_ctx) {
912                 pr_err("%s: Failed to allocate memory for dtv context.\n",
913                        __func__);
914                 ret = -ENOMEM;
915                 return ret;
916         }
917         platform_set_drvdata(pdev, dtv_ctx);
918
919         /* for refer back */
920         dtv_ctx->pdev = pdev;
921
922         /* enable clk for dtv */
923         clk = clk_get(&pdev->dev, NULL);
924         if (!clk) {
925                 dev_err(&pdev->dev, "cannot get clock for tegra_dtv.\n");
926                 ret = -EIO;
927                 goto fail_no_clk;
928         }
929         ret = clk_enable(clk);
930         if (ret < 0) {
931                 dev_err(&pdev->dev, "cannot enable clk for tegra_dtv.\n");
932                 goto fail_clk_enable;
933         }
934         dtv_ctx->clk_enabled = 1;
935
936         /* get resource */
937         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
938         if (unlikely(!res)) {
939                 pr_err("%s: Failed to get resource for dtv.\n",
940                        __func__);
941                 ret = -ENODEV;
942                 goto fail_no_res;
943         }
944
945         if (!devm_request_mem_region(&pdev->dev, res->start,
946                         resource_size(res), dev_name(&pdev->dev))) {
947                 ret = -EBUSY;
948                 return ret;
949         }
950         dtv_ctx->phys = res->start;
951         dtv_ctx->base = devm_ioremap(&pdev->dev, res->start,
952                                      resource_size(res));
953         if (!dtv_ctx->base) {
954                 dev_err(&pdev->dev, "cannot ioremap iomem.\n");
955                 ret = -ENOMEM;
956                 return ret;
957         }
958
959         ret = setup_stream(&dtv_ctx->stream);
960         if (ret < 0)
961                 goto fail_setup_stream;
962
963         ret = setup_dma(dtv_ctx);
964         if (ret < 0)
965                 goto fail_setup_dma;
966
967         /* register as a misc device */
968         ret = misc_register(&tegra_dtv_misc_device);
969         if (ret) {
970                 pr_err("%s: Unable to register misc device.\n",
971                        __func__);
972                 ret = -ENODEV;
973                 goto fail_misc_reg;
974         }
975
976         ret = dtv_debugfs_init(dtv_ctx);
977         if (ret) {
978                 pr_err("%s: Unable to register debugfs entry.\n",
979                        __func__);
980                 goto fail_debugfs_reg;
981         }
982
983         return 0;
984
985 fail_debugfs_reg:
986         dtv_debugfs_exit(dtv_ctx);
987 fail_misc_reg:
988         misc_deregister(&tegra_dtv_misc_device);
989 fail_setup_stream:
990 fail_setup_dma:
991         tear_down_dma(dtv_ctx);
992 fail_no_res:
993 fail_clk_enable:
994 fail_no_clk:
995         if (clk)
996                 clk_put(clk);
997
998         return ret;
999 }
1000
1001 static int __devexit tegra_dtv_remove(struct platform_device *pdev)
1002 {
1003         struct tegra_dtv_context *dtv_ctx;
1004
1005         pr_info("%s: remove dtv.\n", __func__);
1006
1007         misc_deregister(&tegra_dtv_misc_device);
1008
1009         dtv_ctx = platform_get_drvdata(pdev);
1010
1011         dtv_debugfs_exit(dtv_ctx);
1012         tear_down_dma(dtv_ctx);
1013         release_stream_buffer(&dtv_ctx->stream, dtv_ctx->stream.num_bufs);
1014
1015         return 0;
1016 }
1017
1018 #ifdef CONFIG_PM
1019 static int tegra_dtv_suspend(struct platform_device *pdev, pm_message_t state)
1020 {
1021         return 0;
1022 }
1023
1024 static int tegra_dtv_resume(struct platform_device *pdev)
1025 {
1026         return 0;
1027 }
1028 #endif /* CONFIG_PM */
1029
1030 static struct platform_driver tegra_dtv_driver = {
1031         .driver = {
1032                 .name = TEGRA_DTV_NAME,
1033                 .owner = THIS_MODULE,
1034         },
1035         .probe = tegra_dtv_probe,
1036         .remove = __devexit_p(tegra_dtv_remove),
1037 #ifdef CONFIG_PM
1038         .suspend = tegra_dtv_suspend,
1039         .resume = tegra_dtv_resume,
1040 #endif
1041 };
1042
1043 static int __init tegra_dtv_init(void)
1044 {
1045         return platform_driver_register(&tegra_dtv_driver);
1046 }
1047
1048 static void __exit tegra_dtv_exit(void)
1049 {
1050         platform_driver_unregister(&tegra_dtv_driver);
1051 }
1052
1053 module_init(tegra_dtv_init);
1054 module_exit(tegra_dtv_exit);
1055
1056 MODULE_AUTHOR("Adam Jiang <chaoj@nvidia.com>");
1057 MODULE_DESCRIPTION("Tegra DTV interface driver");
1058 MODULE_LICENSE("GPL");
1059 MODULE_ALIAS("platform:" TEGRA_DTV_NAME);