[media] s5p-fimc: fix ISR and buffer handling for fimc-capture
[linux-2.6.git] / drivers / media / video / s5p-fimc / fimc-core.c
1 /*
2  * S5P camera interface (video postprocessor) driver
3  *
4  * Copyright (c) 2010 Samsung Electronics Co., Ltd
5  *
6  * Sylwester Nawrocki, <s.nawrocki@samsung.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published
10  * by the Free Software Foundation, either version 2 of the License,
11  * or (at your option) any later version.
12  */
13
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/version.h>
17 #include <linux/types.h>
18 #include <linux/errno.h>
19 #include <linux/bug.h>
20 #include <linux/interrupt.h>
21 #include <linux/device.h>
22 #include <linux/platform_device.h>
23 #include <linux/list.h>
24 #include <linux/io.h>
25 #include <linux/slab.h>
26 #include <linux/clk.h>
27 #include <media/v4l2-ioctl.h>
28 #include <media/videobuf2-core.h>
29 #include <media/videobuf2-dma-contig.h>
30
31 #include "fimc-core.h"
32
33 static char *fimc_clocks[MAX_FIMC_CLOCKS] = {
34         "sclk_fimc", "fimc", "sclk_cam"
35 };
36
37 static struct fimc_fmt fimc_formats[] = {
38         {
39                 .name           = "RGB565",
40                 .fourcc         = V4L2_PIX_FMT_RGB565X,
41                 .depth          = { 16 },
42                 .color          = S5P_FIMC_RGB565,
43                 .memplanes      = 1,
44                 .colplanes      = 1,
45                 .mbus_code      = V4L2_MBUS_FMT_RGB565_2X8_BE,
46                 .flags          = FMT_FLAGS_M2M,
47         }, {
48                 .name           = "BGR666",
49                 .fourcc         = V4L2_PIX_FMT_BGR666,
50                 .depth          = { 32 },
51                 .color          = S5P_FIMC_RGB666,
52                 .memplanes      = 1,
53                 .colplanes      = 1,
54                 .flags          = FMT_FLAGS_M2M,
55         }, {
56                 .name           = "XRGB-8-8-8-8, 32 bpp",
57                 .fourcc         = V4L2_PIX_FMT_RGB32,
58                 .depth          = { 32 },
59                 .color          = S5P_FIMC_RGB888,
60                 .memplanes      = 1,
61                 .colplanes      = 1,
62                 .flags          = FMT_FLAGS_M2M,
63         }, {
64                 .name           = "YUV 4:2:2 packed, YCbYCr",
65                 .fourcc         = V4L2_PIX_FMT_YUYV,
66                 .depth          = { 16 },
67                 .color          = S5P_FIMC_YCBYCR422,
68                 .memplanes      = 1,
69                 .colplanes      = 1,
70                 .mbus_code      = V4L2_MBUS_FMT_YUYV8_2X8,
71                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
72         }, {
73                 .name           = "YUV 4:2:2 packed, CbYCrY",
74                 .fourcc         = V4L2_PIX_FMT_UYVY,
75                 .depth          = { 16 },
76                 .color          = S5P_FIMC_CBYCRY422,
77                 .memplanes      = 1,
78                 .colplanes      = 1,
79                 .mbus_code      = V4L2_MBUS_FMT_UYVY8_2X8,
80                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
81         }, {
82                 .name           = "YUV 4:2:2 packed, CrYCbY",
83                 .fourcc         = V4L2_PIX_FMT_VYUY,
84                 .depth          = { 16 },
85                 .color          = S5P_FIMC_CRYCBY422,
86                 .memplanes      = 1,
87                 .colplanes      = 1,
88                 .mbus_code      = V4L2_MBUS_FMT_VYUY8_2X8,
89                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
90         }, {
91                 .name           = "YUV 4:2:2 packed, YCrYCb",
92                 .fourcc         = V4L2_PIX_FMT_YVYU,
93                 .depth          = { 16 },
94                 .color          = S5P_FIMC_YCRYCB422,
95                 .memplanes      = 1,
96                 .colplanes      = 1,
97                 .mbus_code      = V4L2_MBUS_FMT_YVYU8_2X8,
98                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
99         }, {
100                 .name           = "YUV 4:2:2 planar, Y/Cb/Cr",
101                 .fourcc         = V4L2_PIX_FMT_YUV422P,
102                 .depth          = { 12 },
103                 .color          = S5P_FIMC_YCBYCR422,
104                 .memplanes      = 1,
105                 .colplanes      = 3,
106                 .flags          = FMT_FLAGS_M2M,
107         }, {
108                 .name           = "YUV 4:2:2 planar, Y/CbCr",
109                 .fourcc         = V4L2_PIX_FMT_NV16,
110                 .depth          = { 16 },
111                 .color          = S5P_FIMC_YCBYCR422,
112                 .memplanes      = 1,
113                 .colplanes      = 2,
114                 .flags          = FMT_FLAGS_M2M,
115         }, {
116                 .name           = "YUV 4:2:2 planar, Y/CrCb",
117                 .fourcc         = V4L2_PIX_FMT_NV61,
118                 .depth          = { 16 },
119                 .color          = S5P_FIMC_YCRYCB422,
120                 .memplanes      = 1,
121                 .colplanes      = 2,
122                 .flags          = FMT_FLAGS_M2M,
123         }, {
124                 .name           = "YUV 4:2:0 planar, YCbCr",
125                 .fourcc         = V4L2_PIX_FMT_YUV420,
126                 .depth          = { 12 },
127                 .color          = S5P_FIMC_YCBCR420,
128                 .memplanes      = 1,
129                 .colplanes      = 3,
130                 .flags          = FMT_FLAGS_M2M,
131         }, {
132                 .name           = "YUV 4:2:0 planar, Y/CbCr",
133                 .fourcc         = V4L2_PIX_FMT_NV12,
134                 .depth          = { 12 },
135                 .color          = S5P_FIMC_YCBCR420,
136                 .memplanes      = 1,
137                 .colplanes      = 2,
138                 .flags          = FMT_FLAGS_M2M,
139         }, {
140                 .name           = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr",
141                 .fourcc         = V4L2_PIX_FMT_NV12M,
142                 .color          = S5P_FIMC_YCBCR420,
143                 .depth          = { 8, 4 },
144                 .memplanes      = 2,
145                 .colplanes      = 2,
146                 .flags          = FMT_FLAGS_M2M,
147         }, {
148                 .name           = "YUV 4:2:0 non-contiguous 3-planar, Y/Cb/Cr",
149                 .fourcc         = V4L2_PIX_FMT_YUV420M,
150                 .color          = S5P_FIMC_YCBCR420,
151                 .depth          = { 8, 2, 2 },
152                 .memplanes      = 3,
153                 .colplanes      = 3,
154                 .flags          = FMT_FLAGS_M2M,
155         }, {
156                 .name           = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr, tiled",
157                 .fourcc         = V4L2_PIX_FMT_NV12MT,
158                 .color          = S5P_FIMC_YCBCR420,
159                 .depth          = { 8, 4 },
160                 .memplanes      = 2,
161                 .colplanes      = 2,
162                 .flags          = FMT_FLAGS_M2M,
163         },
164 };
165
166 static struct v4l2_queryctrl fimc_ctrls[] = {
167         {
168                 .id             = V4L2_CID_HFLIP,
169                 .type           = V4L2_CTRL_TYPE_BOOLEAN,
170                 .name           = "Horizontal flip",
171                 .minimum        = 0,
172                 .maximum        = 1,
173                 .default_value  = 0,
174         }, {
175                 .id             = V4L2_CID_VFLIP,
176                 .type           = V4L2_CTRL_TYPE_BOOLEAN,
177                 .name           = "Vertical flip",
178                 .minimum        = 0,
179                 .maximum        = 1,
180                 .default_value  = 0,
181         }, {
182                 .id             = V4L2_CID_ROTATE,
183                 .type           = V4L2_CTRL_TYPE_INTEGER,
184                 .name           = "Rotation (CCW)",
185                 .minimum        = 0,
186                 .maximum        = 270,
187                 .step           = 90,
188                 .default_value  = 0,
189         },
190 };
191
192
193 static struct v4l2_queryctrl *get_ctrl(int id)
194 {
195         int i;
196
197         for (i = 0; i < ARRAY_SIZE(fimc_ctrls); ++i)
198                 if (id == fimc_ctrls[i].id)
199                         return &fimc_ctrls[i];
200         return NULL;
201 }
202
203 int fimc_check_scaler_ratio(int sw, int sh, int dw, int dh, int rot)
204 {
205         int tx, ty;
206
207         if (rot == 90 || rot == 270) {
208                 ty = dw;
209                 tx = dh;
210         } else {
211                 tx = dw;
212                 ty = dh;
213         }
214
215         if ((sw >= SCALER_MAX_HRATIO * tx) || (sh >= SCALER_MAX_VRATIO * ty))
216                 return -EINVAL;
217
218         return 0;
219 }
220
221 static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
222 {
223         u32 sh = 6;
224
225         if (src >= 64 * tar)
226                 return -EINVAL;
227
228         while (sh--) {
229                 u32 tmp = 1 << sh;
230                 if (src >= tar * tmp) {
231                         *shift = sh, *ratio = tmp;
232                         return 0;
233                 }
234         }
235
236         *shift = 0, *ratio = 1;
237
238         dbg("s: %d, t: %d, shift: %d, ratio: %d",
239             src, tar, *shift, *ratio);
240         return 0;
241 }
242
243 int fimc_set_scaler_info(struct fimc_ctx *ctx)
244 {
245         struct fimc_scaler *sc = &ctx->scaler;
246         struct fimc_frame *s_frame = &ctx->s_frame;
247         struct fimc_frame *d_frame = &ctx->d_frame;
248         struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
249         int tx, ty, sx, sy;
250         int ret;
251
252         if (ctx->rotation == 90 || ctx->rotation == 270) {
253                 ty = d_frame->width;
254                 tx = d_frame->height;
255         } else {
256                 tx = d_frame->width;
257                 ty = d_frame->height;
258         }
259         if (tx <= 0 || ty <= 0) {
260                 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
261                         "invalid target size: %d x %d", tx, ty);
262                 return -EINVAL;
263         }
264
265         sx = s_frame->width;
266         sy = s_frame->height;
267         if (sx <= 0 || sy <= 0) {
268                 err("invalid source size: %d x %d", sx, sy);
269                 return -EINVAL;
270         }
271
272         sc->real_width = sx;
273         sc->real_height = sy;
274         dbg("sx= %d, sy= %d, tx= %d, ty= %d", sx, sy, tx, ty);
275
276         ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
277         if (ret)
278                 return ret;
279
280         ret = fimc_get_scaler_factor(sy, ty,  &sc->pre_vratio, &sc->vfactor);
281         if (ret)
282                 return ret;
283
284         sc->pre_dst_width = sx / sc->pre_hratio;
285         sc->pre_dst_height = sy / sc->pre_vratio;
286
287         if (variant->has_mainscaler_ext) {
288                 sc->main_hratio = (sx << 14) / (tx << sc->hfactor);
289                 sc->main_vratio = (sy << 14) / (ty << sc->vfactor);
290         } else {
291                 sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
292                 sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
293
294         }
295
296         sc->scaleup_h = (tx >= sx) ? 1 : 0;
297         sc->scaleup_v = (ty >= sy) ? 1 : 0;
298
299         /* check to see if input and output size/format differ */
300         if (s_frame->fmt->color == d_frame->fmt->color
301                 && s_frame->width == d_frame->width
302                 && s_frame->height == d_frame->height)
303                 sc->copy_mode = 1;
304         else
305                 sc->copy_mode = 0;
306
307         return 0;
308 }
309
310 static int stop_streaming(struct vb2_queue *q)
311 {
312         struct fimc_ctx *ctx = q->drv_priv;
313         struct fimc_dev *fimc = ctx->fimc_dev;
314
315         if (!fimc_m2m_pending(fimc))
316                 return 0;
317
318         set_bit(ST_M2M_SHUT, &fimc->state);
319
320         wait_event_timeout(fimc->irq_queue,
321                            !test_bit(ST_M2M_SHUT, &fimc->state),
322                            FIMC_SHUTDOWN_TIMEOUT);
323
324         return 0;
325 }
326
327 static void fimc_capture_handler(struct fimc_dev *fimc)
328 {
329         struct fimc_vid_cap *cap = &fimc->vid_cap;
330         struct fimc_vid_buffer *v_buf;
331
332         if (!list_empty(&cap->active_buf_q) &&
333             test_bit(ST_CAPT_RUN, &fimc->state)) {
334                 v_buf = active_queue_pop(cap);
335                 vb2_buffer_done(&v_buf->vb, VB2_BUF_STATE_DONE);
336         }
337
338         if (test_and_clear_bit(ST_CAPT_SHUT, &fimc->state)) {
339                 wake_up(&fimc->irq_queue);
340                 return;
341         }
342
343         if (!list_empty(&cap->pending_buf_q)) {
344
345                 v_buf = pending_queue_pop(cap);
346                 fimc_hw_set_output_addr(fimc, &v_buf->paddr, cap->buf_index);
347                 v_buf->index = cap->buf_index;
348
349                 /* Move the buffer to the capture active queue */
350                 active_queue_add(cap, v_buf);
351
352                 dbg("next frame: %d, done frame: %d",
353                     fimc_hw_get_frame_index(fimc), v_buf->index);
354
355                 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
356                         cap->buf_index = 0;
357         }
358
359         if (cap->active_buf_cnt == 0) {
360                 clear_bit(ST_CAPT_RUN, &fimc->state);
361
362                 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
363                         cap->buf_index = 0;
364         } else {
365                 set_bit(ST_CAPT_RUN, &fimc->state);
366         }
367
368         dbg("frame: %d, active_buf_cnt: %d",
369             fimc_hw_get_frame_index(fimc), cap->active_buf_cnt);
370 }
371
372 static irqreturn_t fimc_isr(int irq, void *priv)
373 {
374         struct fimc_dev *fimc = priv;
375         struct fimc_vid_cap *cap = &fimc->vid_cap;
376
377         BUG_ON(!fimc);
378         fimc_hw_clear_irq(fimc);
379
380         spin_lock(&fimc->slock);
381
382         if (test_and_clear_bit(ST_M2M_SHUT, &fimc->state)) {
383                 wake_up(&fimc->irq_queue);
384                 goto isr_unlock;
385         } else if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
386                 struct vb2_buffer *src_vb, *dst_vb;
387                 struct fimc_ctx *ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
388
389                 if (!ctx || !ctx->m2m_ctx)
390                         goto isr_unlock;
391
392                 src_vb = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
393                 dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
394                 if (src_vb && dst_vb) {
395                         v4l2_m2m_buf_done(src_vb, VB2_BUF_STATE_DONE);
396                         v4l2_m2m_buf_done(dst_vb, VB2_BUF_STATE_DONE);
397                         v4l2_m2m_job_finish(fimc->m2m.m2m_dev, ctx->m2m_ctx);
398                 }
399                 goto isr_unlock;
400
401         }
402
403         if (test_bit(ST_CAPT_PEND, &fimc->state)) {
404                 fimc_capture_irq_handler(fimc);
405
406                 if (cap->active_buf_cnt == 1) {
407                         fimc_deactivate_capture(fimc);
408                         clear_bit(ST_CAPT_STREAM, &fimc->state);
409                 }
410         }
411
412 isr_unlock:
413         spin_unlock(&fimc->slock);
414         return IRQ_HANDLED;
415 }
416
417 /* The color format (colplanes, memplanes) must be already configured. */
418 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
419                       struct fimc_frame *frame, struct fimc_addr *paddr)
420 {
421         int ret = 0;
422         u32 pix_size;
423
424         if (vb == NULL || frame == NULL)
425                 return -EINVAL;
426
427         pix_size = frame->width * frame->height;
428
429         dbg("memplanes= %d, colplanes= %d, pix_size= %d",
430                 frame->fmt->memplanes, frame->fmt->colplanes, pix_size);
431
432         paddr->y = vb2_dma_contig_plane_paddr(vb, 0);
433
434         if (frame->fmt->memplanes == 1) {
435                 switch (frame->fmt->colplanes) {
436                 case 1:
437                         paddr->cb = 0;
438                         paddr->cr = 0;
439                         break;
440                 case 2:
441                         /* decompose Y into Y/Cb */
442                         paddr->cb = (u32)(paddr->y + pix_size);
443                         paddr->cr = 0;
444                         break;
445                 case 3:
446                         paddr->cb = (u32)(paddr->y + pix_size);
447                         /* decompose Y into Y/Cb/Cr */
448                         if (S5P_FIMC_YCBCR420 == frame->fmt->color)
449                                 paddr->cr = (u32)(paddr->cb
450                                                 + (pix_size >> 2));
451                         else /* 422 */
452                                 paddr->cr = (u32)(paddr->cb
453                                                 + (pix_size >> 1));
454                         break;
455                 default:
456                         return -EINVAL;
457                 }
458         } else {
459                 if (frame->fmt->memplanes >= 2)
460                         paddr->cb = vb2_dma_contig_plane_paddr(vb, 1);
461
462                 if (frame->fmt->memplanes == 3)
463                         paddr->cr = vb2_dma_contig_plane_paddr(vb, 2);
464         }
465
466         dbg("PHYS_ADDR: y= 0x%X  cb= 0x%X cr= 0x%X ret= %d",
467             paddr->y, paddr->cb, paddr->cr, ret);
468
469         return ret;
470 }
471
472 /* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
473 static void fimc_set_yuv_order(struct fimc_ctx *ctx)
474 {
475         /* The one only mode supported in SoC. */
476         ctx->in_order_2p = S5P_FIMC_LSB_CRCB;
477         ctx->out_order_2p = S5P_FIMC_LSB_CRCB;
478
479         /* Set order for 1 plane input formats. */
480         switch (ctx->s_frame.fmt->color) {
481         case S5P_FIMC_YCRYCB422:
482                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CBYCRY;
483                 break;
484         case S5P_FIMC_CBYCRY422:
485                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCRYCB;
486                 break;
487         case S5P_FIMC_CRYCBY422:
488                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCBYCR;
489                 break;
490         case S5P_FIMC_YCBYCR422:
491         default:
492                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CRYCBY;
493                 break;
494         }
495         dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
496
497         switch (ctx->d_frame.fmt->color) {
498         case S5P_FIMC_YCRYCB422:
499                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CBYCRY;
500                 break;
501         case S5P_FIMC_CBYCRY422:
502                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCRYCB;
503                 break;
504         case S5P_FIMC_CRYCBY422:
505                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCBYCR;
506                 break;
507         case S5P_FIMC_YCBYCR422:
508         default:
509                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CRYCBY;
510                 break;
511         }
512         dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
513 }
514
515 static void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f)
516 {
517         struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
518         u32 i, depth = 0;
519
520         for (i = 0; i < f->fmt->colplanes; i++)
521                 depth += f->fmt->depth[i];
522
523         f->dma_offset.y_h = f->offs_h;
524         if (!variant->pix_hoff)
525                 f->dma_offset.y_h *= (depth >> 3);
526
527         f->dma_offset.y_v = f->offs_v;
528
529         f->dma_offset.cb_h = f->offs_h;
530         f->dma_offset.cb_v = f->offs_v;
531
532         f->dma_offset.cr_h = f->offs_h;
533         f->dma_offset.cr_v = f->offs_v;
534
535         if (!variant->pix_hoff) {
536                 if (f->fmt->colplanes == 3) {
537                         f->dma_offset.cb_h >>= 1;
538                         f->dma_offset.cr_h >>= 1;
539                 }
540                 if (f->fmt->color == S5P_FIMC_YCBCR420) {
541                         f->dma_offset.cb_v >>= 1;
542                         f->dma_offset.cr_v >>= 1;
543                 }
544         }
545
546         dbg("in_offset: color= %d, y_h= %d, y_v= %d",
547             f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v);
548 }
549
550 /**
551  * fimc_prepare_config - check dimensions, operation and color mode
552  *                       and pre-calculate offset and the scaling coefficients.
553  *
554  * @ctx: hardware context information
555  * @flags: flags indicating which parameters to check/update
556  *
557  * Return: 0 if dimensions are valid or non zero otherwise.
558  */
559 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags)
560 {
561         struct fimc_frame *s_frame, *d_frame;
562         struct vb2_buffer *vb = NULL;
563         int ret = 0;
564
565         s_frame = &ctx->s_frame;
566         d_frame = &ctx->d_frame;
567
568         if (flags & FIMC_PARAMS) {
569                 /* Prepare the DMA offset ratios for scaler. */
570                 fimc_prepare_dma_offset(ctx, &ctx->s_frame);
571                 fimc_prepare_dma_offset(ctx, &ctx->d_frame);
572
573                 if (s_frame->height > (SCALER_MAX_VRATIO * d_frame->height) ||
574                     s_frame->width > (SCALER_MAX_HRATIO * d_frame->width)) {
575                         err("out of scaler range");
576                         return -EINVAL;
577                 }
578                 fimc_set_yuv_order(ctx);
579         }
580
581         /* Input DMA mode is not allowed when the scaler is disabled. */
582         ctx->scaler.enabled = 1;
583
584         if (flags & FIMC_SRC_ADDR) {
585                 vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
586                 ret = fimc_prepare_addr(ctx, vb, s_frame, &s_frame->paddr);
587                 if (ret)
588                         return ret;
589         }
590
591         if (flags & FIMC_DST_ADDR) {
592                 vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
593                 ret = fimc_prepare_addr(ctx, vb, d_frame, &d_frame->paddr);
594         }
595
596         return ret;
597 }
598
599 static void fimc_dma_run(void *priv)
600 {
601         struct fimc_ctx *ctx = priv;
602         struct fimc_dev *fimc;
603         unsigned long flags;
604         u32 ret;
605
606         if (WARN(!ctx, "null hardware context\n"))
607                 return;
608
609         fimc = ctx->fimc_dev;
610
611         spin_lock_irqsave(&ctx->slock, flags);
612         set_bit(ST_M2M_PEND, &fimc->state);
613
614         ctx->state |= (FIMC_SRC_ADDR | FIMC_DST_ADDR);
615         ret = fimc_prepare_config(ctx, ctx->state);
616         if (ret) {
617                 err("Wrong parameters");
618                 goto dma_unlock;
619         }
620         /* Reconfigure hardware if the context has changed. */
621         if (fimc->m2m.ctx != ctx) {
622                 ctx->state |= FIMC_PARAMS;
623                 fimc->m2m.ctx = ctx;
624         }
625
626         fimc_hw_set_input_addr(fimc, &ctx->s_frame.paddr);
627
628         if (ctx->state & FIMC_PARAMS) {
629                 fimc_hw_set_input_path(ctx);
630                 fimc_hw_set_in_dma(ctx);
631                 if (fimc_set_scaler_info(ctx)) {
632                         err("Scaler setup error");
633                         goto dma_unlock;
634                 }
635
636                 fimc_hw_set_prescaler(ctx);
637                 fimc_hw_set_mainscaler(ctx);
638                 fimc_hw_set_target_format(ctx);
639                 fimc_hw_set_rotation(ctx);
640                 fimc_hw_set_effect(ctx);
641         }
642
643         fimc_hw_set_output_path(ctx);
644         if (ctx->state & (FIMC_DST_ADDR | FIMC_PARAMS))
645                 fimc_hw_set_output_addr(fimc, &ctx->d_frame.paddr, -1);
646
647         if (ctx->state & FIMC_PARAMS)
648                 fimc_hw_set_out_dma(ctx);
649
650         fimc_activate_capture(ctx);
651
652         ctx->state &= (FIMC_CTX_M2M | FIMC_CTX_CAP |
653                        FIMC_SRC_FMT | FIMC_DST_FMT);
654         fimc_hw_activate_input_dma(fimc, true);
655
656 dma_unlock:
657         spin_unlock_irqrestore(&ctx->slock, flags);
658 }
659
660 static void fimc_job_abort(void *priv)
661 {
662         struct fimc_ctx *ctx = priv;
663         struct fimc_dev *fimc = ctx->fimc_dev;
664
665         if (!fimc_m2m_pending(fimc))
666                 return;
667
668         set_bit(ST_M2M_SHUT, &fimc->state);
669
670         wait_event_timeout(fimc->irq_queue,
671                            !test_bit(ST_M2M_SHUT, &fimc->state),
672                            FIMC_SHUTDOWN_TIMEOUT);
673 }
674
675 static int fimc_queue_setup(struct vb2_queue *vq, unsigned int *num_buffers,
676                             unsigned int *num_planes, unsigned long sizes[],
677                             void *allocators[])
678 {
679         struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
680         struct fimc_frame *f;
681         int i;
682
683         f = ctx_get_frame(ctx, vq->type);
684         if (IS_ERR(f))
685                 return PTR_ERR(f);
686
687         /*
688          * Return number of non-contigous planes (plane buffers)
689          * depending on the configured color format.
690          */
691         if (f->fmt)
692                 *num_planes = f->fmt->memplanes;
693
694         for (i = 0; i < f->fmt->memplanes; i++) {
695                 sizes[i] = (f->width * f->height * f->fmt->depth[i]) >> 3;
696                 allocators[i] = ctx->fimc_dev->alloc_ctx;
697         }
698
699         if (*num_buffers == 0)
700                 *num_buffers = 1;
701
702         return 0;
703 }
704
705 static int fimc_buf_prepare(struct vb2_buffer *vb)
706 {
707         struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
708         struct fimc_frame *frame;
709         int i;
710
711         frame = ctx_get_frame(ctx, vb->vb2_queue->type);
712         if (IS_ERR(frame))
713                 return PTR_ERR(frame);
714
715         for (i = 0; i < frame->fmt->memplanes; i++)
716                 vb2_set_plane_payload(vb, i, frame->payload[i]);
717
718         return 0;
719 }
720
721 static void fimc_buf_queue(struct vb2_buffer *vb)
722 {
723         struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
724
725         dbg("ctx: %p, ctx->state: 0x%x", ctx, ctx->state);
726
727         if (ctx->m2m_ctx)
728                 v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
729 }
730
731 static void fimc_lock(struct vb2_queue *vq)
732 {
733         struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
734         mutex_lock(&ctx->fimc_dev->lock);
735 }
736
737 static void fimc_unlock(struct vb2_queue *vq)
738 {
739         struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
740         mutex_unlock(&ctx->fimc_dev->lock);
741 }
742
743 struct vb2_ops fimc_qops = {
744         .queue_setup     = fimc_queue_setup,
745         .buf_prepare     = fimc_buf_prepare,
746         .buf_queue       = fimc_buf_queue,
747         .wait_prepare    = fimc_unlock,
748         .wait_finish     = fimc_lock,
749         .stop_streaming  = stop_streaming,
750 };
751
752 static int fimc_m2m_querycap(struct file *file, void *priv,
753                            struct v4l2_capability *cap)
754 {
755         struct fimc_ctx *ctx = file->private_data;
756         struct fimc_dev *fimc = ctx->fimc_dev;
757
758         strncpy(cap->driver, fimc->pdev->name, sizeof(cap->driver) - 1);
759         strncpy(cap->card, fimc->pdev->name, sizeof(cap->card) - 1);
760         cap->bus_info[0] = 0;
761         cap->version = KERNEL_VERSION(1, 0, 0);
762         cap->capabilities = V4L2_CAP_STREAMING |
763                 V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
764                 V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_VIDEO_OUTPUT_MPLANE;
765
766         return 0;
767 }
768
769 int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
770                                 struct v4l2_fmtdesc *f)
771 {
772         struct fimc_fmt *fmt;
773
774         if (f->index >= ARRAY_SIZE(fimc_formats))
775                 return -EINVAL;
776
777         fmt = &fimc_formats[f->index];
778         strncpy(f->description, fmt->name, sizeof(f->description) - 1);
779         f->pixelformat = fmt->fourcc;
780
781         return 0;
782 }
783
784 int fimc_vidioc_g_fmt_mplane(struct file *file, void *priv,
785                              struct v4l2_format *f)
786 {
787         struct fimc_ctx *ctx = priv;
788         struct fimc_frame *frame;
789
790         frame = ctx_get_frame(ctx, f->type);
791         if (IS_ERR(frame))
792                 return PTR_ERR(frame);
793
794         f->fmt.pix.width        = frame->width;
795         f->fmt.pix.height       = frame->height;
796         f->fmt.pix.field        = V4L2_FIELD_NONE;
797         f->fmt.pix.pixelformat  = frame->fmt->fourcc;
798
799         return 0;
800 }
801
802 struct fimc_fmt *find_format(struct v4l2_format *f, unsigned int mask)
803 {
804         struct fimc_fmt *fmt;
805         unsigned int i;
806
807         for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
808                 fmt = &fimc_formats[i];
809                 if (fmt->fourcc == f->fmt.pix.pixelformat &&
810                    (fmt->flags & mask))
811                         break;
812         }
813
814         return (i == ARRAY_SIZE(fimc_formats)) ? NULL : fmt;
815 }
816
817 struct fimc_fmt *find_mbus_format(struct v4l2_mbus_framefmt *f,
818                                   unsigned int mask)
819 {
820         struct fimc_fmt *fmt;
821         unsigned int i;
822
823         for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
824                 fmt = &fimc_formats[i];
825                 if (fmt->mbus_code == f->code && (fmt->flags & mask))
826                         break;
827         }
828
829         return (i == ARRAY_SIZE(fimc_formats)) ? NULL : fmt;
830 }
831
832
833 int fimc_vidioc_try_fmt_mplane(struct file *file, void *priv,
834                                struct v4l2_format *f)
835 {
836         struct fimc_ctx *ctx = priv;
837         struct fimc_dev *fimc = ctx->fimc_dev;
838         struct samsung_fimc_variant *variant = fimc->variant;
839         struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
840         struct fimc_fmt *fmt;
841         u32 max_width, mod_x, mod_y, mask;
842         int i, is_output = 0;
843
844
845         if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
846                 if (ctx->state & FIMC_CTX_CAP)
847                         return -EINVAL;
848                 is_output = 1;
849         } else if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
850                 return -EINVAL;
851         }
852
853         dbg("w: %d, h: %d", pix->width, pix->height);
854
855         mask = is_output ? FMT_FLAGS_M2M : FMT_FLAGS_M2M | FMT_FLAGS_CAM;
856         fmt = find_format(f, mask);
857         if (!fmt) {
858                 v4l2_err(&fimc->m2m.v4l2_dev, "Fourcc format (0x%X) invalid.\n",
859                          pix->pixelformat);
860                 return -EINVAL;
861         }
862
863         if (pix->field == V4L2_FIELD_ANY)
864                 pix->field = V4L2_FIELD_NONE;
865         else if (V4L2_FIELD_NONE != pix->field)
866                 return -EINVAL;
867
868         if (is_output) {
869                 max_width = variant->pix_limit->scaler_dis_w;
870                 mod_x = ffs(variant->min_inp_pixsize) - 1;
871         } else {
872                 max_width = variant->pix_limit->out_rot_dis_w;
873                 mod_x = ffs(variant->min_out_pixsize) - 1;
874         }
875
876         if (tiled_fmt(fmt)) {
877                 mod_x = 6; /* 64 x 32 pixels tile */
878                 mod_y = 5;
879         } else {
880                 if (fimc->id == 1 && variant->pix_hoff)
881                         mod_y = fimc_fmt_is_rgb(fmt->color) ? 0 : 1;
882                 else
883                         mod_y = mod_x;
884         }
885
886         dbg("mod_x: %d, mod_y: %d, max_w: %d", mod_x, mod_y, max_width);
887
888         v4l_bound_align_image(&pix->width, 16, max_width, mod_x,
889                 &pix->height, 8, variant->pix_limit->scaler_dis_w, mod_y, 0);
890
891         pix->num_planes = fmt->memplanes;
892
893         for (i = 0; i < pix->num_planes; ++i) {
894                 int bpl = pix->plane_fmt[i].bytesperline;
895
896                 dbg("[%d] bpl: %d, depth: %d, w: %d, h: %d",
897                     i, bpl, fmt->depth[i], pix->width, pix->height);
898
899                 if (!bpl || (bpl * 8 / fmt->depth[i]) > pix->width)
900                         bpl = (pix->width * fmt->depth[0]) >> 3;
901
902                 if (!pix->plane_fmt[i].sizeimage)
903                         pix->plane_fmt[i].sizeimage = pix->height * bpl;
904
905                 pix->plane_fmt[i].bytesperline = bpl;
906
907                 dbg("[%d]: bpl: %d, sizeimage: %d",
908                     i, pix->plane_fmt[i].bytesperline,
909                     pix->plane_fmt[i].sizeimage);
910         }
911
912         return 0;
913 }
914
915 static int fimc_m2m_s_fmt_mplane(struct file *file, void *priv,
916                                  struct v4l2_format *f)
917 {
918         struct fimc_ctx *ctx = priv;
919         struct fimc_dev *fimc = ctx->fimc_dev;
920         struct vb2_queue *vq;
921         struct fimc_frame *frame;
922         struct v4l2_pix_format_mplane *pix;
923         unsigned long flags;
924         int i, ret = 0;
925         u32 tmp;
926
927         ret = fimc_vidioc_try_fmt_mplane(file, priv, f);
928         if (ret)
929                 return ret;
930
931         vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
932
933         if (vb2_is_streaming(vq)) {
934                 v4l2_err(&fimc->m2m.v4l2_dev, "queue (%d) busy\n", f->type);
935                 return -EBUSY;
936         }
937
938         if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
939                 frame = &ctx->s_frame;
940         } else if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
941                 frame = &ctx->d_frame;
942         } else {
943                 v4l2_err(&fimc->m2m.v4l2_dev,
944                          "Wrong buffer/video queue type (%d)\n", f->type);
945                 return -EINVAL;
946         }
947
948         pix = &f->fmt.pix_mp;
949         frame->fmt = find_format(f, FMT_FLAGS_M2M);
950         if (!frame->fmt)
951                 return -EINVAL;
952
953         for (i = 0; i < frame->fmt->colplanes; i++)
954                 frame->payload[i] = pix->plane_fmt[i].bytesperline * pix->height;
955
956         frame->f_width  = pix->plane_fmt[0].bytesperline * 8 /
957                 frame->fmt->depth[0];
958         frame->f_height = pix->height;
959         frame->width    = pix->width;
960         frame->height   = pix->height;
961         frame->o_width  = pix->width;
962         frame->o_height = pix->height;
963         frame->offs_h   = 0;
964         frame->offs_v   = 0;
965
966         spin_lock_irqsave(&ctx->slock, flags);
967         tmp = (frame == &ctx->d_frame) ? FIMC_DST_FMT : FIMC_SRC_FMT;
968         ctx->state |= FIMC_PARAMS | tmp;
969         spin_unlock_irqrestore(&ctx->slock, flags);
970
971         dbg("f_w: %d, f_h: %d", frame->f_width, frame->f_height);
972
973         return 0;
974 }
975
976 static int fimc_m2m_reqbufs(struct file *file, void *priv,
977                           struct v4l2_requestbuffers *reqbufs)
978 {
979         struct fimc_ctx *ctx = priv;
980         return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
981 }
982
983 static int fimc_m2m_querybuf(struct file *file, void *priv,
984                            struct v4l2_buffer *buf)
985 {
986         struct fimc_ctx *ctx = priv;
987         return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
988 }
989
990 static int fimc_m2m_qbuf(struct file *file, void *priv,
991                           struct v4l2_buffer *buf)
992 {
993         struct fimc_ctx *ctx = priv;
994
995         return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
996 }
997
998 static int fimc_m2m_dqbuf(struct file *file, void *priv,
999                            struct v4l2_buffer *buf)
1000 {
1001         struct fimc_ctx *ctx = priv;
1002         return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
1003 }
1004
1005 static int fimc_m2m_streamon(struct file *file, void *priv,
1006                            enum v4l2_buf_type type)
1007 {
1008         struct fimc_ctx *ctx = priv;
1009
1010         /* The source and target color format need to be set */
1011         if (V4L2_TYPE_IS_OUTPUT(type)) {
1012                 if (~ctx->state & FIMC_SRC_FMT)
1013                         return -EINVAL;
1014         } else if (~ctx->state & FIMC_DST_FMT) {
1015                 return -EINVAL;
1016         }
1017
1018         return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
1019 }
1020
1021 static int fimc_m2m_streamoff(struct file *file, void *priv,
1022                             enum v4l2_buf_type type)
1023 {
1024         struct fimc_ctx *ctx = priv;
1025         return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
1026 }
1027
1028 int fimc_vidioc_queryctrl(struct file *file, void *priv,
1029                             struct v4l2_queryctrl *qc)
1030 {
1031         struct fimc_ctx *ctx = priv;
1032         struct v4l2_queryctrl *c;
1033         int ret = -EINVAL;
1034
1035         c = get_ctrl(qc->id);
1036         if (c) {
1037                 *qc = *c;
1038                 return 0;
1039         }
1040
1041         if (ctx->state & FIMC_CTX_CAP) {
1042                 return v4l2_subdev_call(ctx->fimc_dev->vid_cap.sd,
1043                                         core, queryctrl, qc);
1044         }
1045         return ret;
1046 }
1047
1048 int fimc_vidioc_g_ctrl(struct file *file, void *priv,
1049                          struct v4l2_control *ctrl)
1050 {
1051         struct fimc_ctx *ctx = priv;
1052         struct fimc_dev *fimc = ctx->fimc_dev;
1053
1054         switch (ctrl->id) {
1055         case V4L2_CID_HFLIP:
1056                 ctrl->value = (FLIP_X_AXIS & ctx->flip) ? 1 : 0;
1057                 break;
1058         case V4L2_CID_VFLIP:
1059                 ctrl->value = (FLIP_Y_AXIS & ctx->flip) ? 1 : 0;
1060                 break;
1061         case V4L2_CID_ROTATE:
1062                 ctrl->value = ctx->rotation;
1063                 break;
1064         default:
1065                 if (ctx->state & FIMC_CTX_CAP) {
1066                         return v4l2_subdev_call(fimc->vid_cap.sd, core,
1067                                                 g_ctrl, ctrl);
1068                 } else {
1069                         v4l2_err(&fimc->m2m.v4l2_dev,
1070                                  "Invalid control\n");
1071                         return -EINVAL;
1072                 }
1073         }
1074         dbg("ctrl->value= %d", ctrl->value);
1075
1076         return 0;
1077 }
1078
1079 int check_ctrl_val(struct fimc_ctx *ctx,  struct v4l2_control *ctrl)
1080 {
1081         struct v4l2_queryctrl *c;
1082         c = get_ctrl(ctrl->id);
1083         if (!c)
1084                 return -EINVAL;
1085
1086         if (ctrl->value < c->minimum || ctrl->value > c->maximum
1087                 || (c->step != 0 && ctrl->value % c->step != 0)) {
1088                 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
1089                 "Invalid control value\n");
1090                 return -ERANGE;
1091         }
1092
1093         return 0;
1094 }
1095
1096 int fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_control *ctrl)
1097 {
1098         struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
1099         struct fimc_dev *fimc = ctx->fimc_dev;
1100         unsigned long flags;
1101         int ret = 0;
1102
1103         spin_lock_irqsave(&ctx->slock, flags);
1104
1105         switch (ctrl->id) {
1106         case V4L2_CID_HFLIP:
1107                 if (ctrl->value)
1108                         ctx->flip |= FLIP_X_AXIS;
1109                 else
1110                         ctx->flip &= ~FLIP_X_AXIS;
1111                 break;
1112
1113         case V4L2_CID_VFLIP:
1114                 if (ctrl->value)
1115                         ctx->flip |= FLIP_Y_AXIS;
1116                 else
1117                         ctx->flip &= ~FLIP_Y_AXIS;
1118                 break;
1119
1120         case V4L2_CID_ROTATE:
1121                 if (!(~ctx->state & (FIMC_DST_FMT | FIMC_SRC_FMT))) {
1122                         ret = fimc_check_scaler_ratio(ctx->s_frame.width,
1123                                                       ctx->s_frame.height,
1124                                                       ctx->d_frame.width,
1125                                                       ctx->d_frame.height,
1126                                                       ctrl->value);
1127                         if (ret) {
1128                                 v4l2_err(&fimc->m2m.v4l2_dev,
1129                                          "Out of scaler range");
1130                                 spin_unlock_irqrestore(&ctx->slock, flags);
1131                                 return -EINVAL;
1132                         }
1133                 }
1134
1135                 /* Check for the output rotator availability */
1136                 if ((ctrl->value == 90 || ctrl->value == 270) &&
1137                     (ctx->in_path == FIMC_DMA && !variant->has_out_rot)) {
1138                         spin_unlock_irqrestore(&ctx->slock, flags);
1139                         return -EINVAL;
1140                 } else {
1141                         ctx->rotation = ctrl->value;
1142                 }
1143                 break;
1144
1145         default:
1146                 spin_unlock_irqrestore(&ctx->slock, flags);
1147                 v4l2_err(&fimc->m2m.v4l2_dev, "Invalid control\n");
1148                 return -EINVAL;
1149         }
1150         ctx->state |= FIMC_PARAMS;
1151         spin_unlock_irqrestore(&ctx->slock, flags);
1152
1153         return 0;
1154 }
1155
1156 static int fimc_m2m_s_ctrl(struct file *file, void *priv,
1157                            struct v4l2_control *ctrl)
1158 {
1159         struct fimc_ctx *ctx = priv;
1160         int ret = 0;
1161
1162         ret = check_ctrl_val(ctx, ctrl);
1163         if (ret)
1164                 return ret;
1165
1166         ret = fimc_s_ctrl(ctx, ctrl);
1167         return 0;
1168 }
1169
1170 static int fimc_m2m_cropcap(struct file *file, void *fh,
1171                         struct v4l2_cropcap *cr)
1172 {
1173         struct fimc_frame *frame;
1174         struct fimc_ctx *ctx = fh;
1175
1176         frame = ctx_get_frame(ctx, cr->type);
1177         if (IS_ERR(frame))
1178                 return PTR_ERR(frame);
1179
1180         cr->bounds.left         = 0;
1181         cr->bounds.top          = 0;
1182         cr->bounds.width        = frame->f_width;
1183         cr->bounds.height       = frame->f_height;
1184         cr->defrect             = cr->bounds;
1185
1186         return 0;
1187 }
1188
1189 static int fimc_m2m_g_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1190 {
1191         struct fimc_frame *frame;
1192         struct fimc_ctx *ctx = file->private_data;
1193
1194         frame = ctx_get_frame(ctx, cr->type);
1195         if (IS_ERR(frame))
1196                 return PTR_ERR(frame);
1197
1198         cr->c.left = frame->offs_h;
1199         cr->c.top = frame->offs_v;
1200         cr->c.width = frame->width;
1201         cr->c.height = frame->height;
1202
1203         return 0;
1204 }
1205
1206 int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr)
1207 {
1208         struct fimc_dev *fimc = ctx->fimc_dev;
1209         struct fimc_frame *f;
1210         u32 min_size, halign, depth = 0;
1211         int i;
1212
1213         if (cr->c.top < 0 || cr->c.left < 0) {
1214                 v4l2_err(&fimc->m2m.v4l2_dev,
1215                         "doesn't support negative values for top & left\n");
1216                 return -EINVAL;
1217         }
1218
1219         if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1220                 f = (ctx->state & FIMC_CTX_CAP) ? &ctx->s_frame : &ctx->d_frame;
1221         else if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE &&
1222                  ctx->state & FIMC_CTX_M2M)
1223                 f = &ctx->s_frame;
1224         else
1225                 return -EINVAL;
1226
1227         min_size = (f == &ctx->s_frame) ?
1228                 fimc->variant->min_inp_pixsize : fimc->variant->min_out_pixsize;
1229
1230         if (ctx->state & FIMC_CTX_M2M) {
1231                 if (fimc->id == 1 && fimc->variant->pix_hoff)
1232                         halign = fimc_fmt_is_rgb(f->fmt->color) ? 0 : 1;
1233                 else
1234                         halign = ffs(min_size) - 1;
1235         /* there are more strict aligment requirements at camera interface */
1236         } else {
1237                 min_size = 16;
1238                 halign = 4;
1239         }
1240
1241         for (i = 0; i < f->fmt->colplanes; i++)
1242                 depth += f->fmt->depth[i];
1243
1244         v4l_bound_align_image(&cr->c.width, min_size, f->o_width,
1245                               ffs(min_size) - 1,
1246                               &cr->c.height, min_size, f->o_height,
1247                               halign, 64/(ALIGN(depth, 8)));
1248
1249         /* adjust left/top if cropping rectangle is out of bounds */
1250         if (cr->c.left + cr->c.width > f->o_width)
1251                 cr->c.left = f->o_width - cr->c.width;
1252         if (cr->c.top + cr->c.height > f->o_height)
1253                 cr->c.top = f->o_height - cr->c.height;
1254
1255         cr->c.left = round_down(cr->c.left, min_size);
1256         cr->c.top  = round_down(cr->c.top,
1257                                 ctx->state & FIMC_CTX_M2M ? 8 : 16);
1258
1259         dbg("l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d",
1260             cr->c.left, cr->c.top, cr->c.width, cr->c.height,
1261             f->f_width, f->f_height);
1262
1263         return 0;
1264 }
1265
1266
1267 static int fimc_m2m_s_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1268 {
1269         struct fimc_ctx *ctx = file->private_data;
1270         struct fimc_dev *fimc = ctx->fimc_dev;
1271         unsigned long flags;
1272         struct fimc_frame *f;
1273         int ret;
1274
1275         ret = fimc_try_crop(ctx, cr);
1276         if (ret)
1277                 return ret;
1278
1279         f = (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ?
1280                 &ctx->s_frame : &ctx->d_frame;
1281
1282         spin_lock_irqsave(&ctx->slock, flags);
1283         /* Check to see if scaling ratio is within supported range */
1284         if (!(~ctx->state & (FIMC_DST_FMT | FIMC_SRC_FMT))) {
1285                 if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1286                         ret = fimc_check_scaler_ratio(cr->c.width, cr->c.height,
1287                                                       ctx->d_frame.width,
1288                                                       ctx->d_frame.height,
1289                                                       ctx->rotation);
1290                 } else {
1291                         ret = fimc_check_scaler_ratio(ctx->s_frame.width,
1292                                                       ctx->s_frame.height,
1293                                                       cr->c.width, cr->c.height,
1294                                                       ctx->rotation);
1295                 }
1296
1297                 if (ret) {
1298                         v4l2_err(&fimc->m2m.v4l2_dev, "Out of scaler range");
1299                         spin_unlock_irqrestore(&ctx->slock, flags);
1300                         return -EINVAL;
1301                 }
1302         }
1303
1304         ctx->state |= FIMC_PARAMS;
1305
1306         f->offs_h = cr->c.left;
1307         f->offs_v = cr->c.top;
1308         f->width  = cr->c.width;
1309         f->height = cr->c.height;
1310
1311         spin_unlock_irqrestore(&ctx->slock, flags);
1312         return 0;
1313 }
1314
1315 static const struct v4l2_ioctl_ops fimc_m2m_ioctl_ops = {
1316         .vidioc_querycap                = fimc_m2m_querycap,
1317
1318         .vidioc_enum_fmt_vid_cap_mplane = fimc_vidioc_enum_fmt_mplane,
1319         .vidioc_enum_fmt_vid_out_mplane = fimc_vidioc_enum_fmt_mplane,
1320
1321         .vidioc_g_fmt_vid_cap_mplane    = fimc_vidioc_g_fmt_mplane,
1322         .vidioc_g_fmt_vid_out_mplane    = fimc_vidioc_g_fmt_mplane,
1323
1324         .vidioc_try_fmt_vid_cap_mplane  = fimc_vidioc_try_fmt_mplane,
1325         .vidioc_try_fmt_vid_out_mplane  = fimc_vidioc_try_fmt_mplane,
1326
1327         .vidioc_s_fmt_vid_cap_mplane    = fimc_m2m_s_fmt_mplane,
1328         .vidioc_s_fmt_vid_out_mplane    = fimc_m2m_s_fmt_mplane,
1329
1330         .vidioc_reqbufs                 = fimc_m2m_reqbufs,
1331         .vidioc_querybuf                = fimc_m2m_querybuf,
1332
1333         .vidioc_qbuf                    = fimc_m2m_qbuf,
1334         .vidioc_dqbuf                   = fimc_m2m_dqbuf,
1335
1336         .vidioc_streamon                = fimc_m2m_streamon,
1337         .vidioc_streamoff               = fimc_m2m_streamoff,
1338
1339         .vidioc_queryctrl               = fimc_vidioc_queryctrl,
1340         .vidioc_g_ctrl                  = fimc_vidioc_g_ctrl,
1341         .vidioc_s_ctrl                  = fimc_m2m_s_ctrl,
1342
1343         .vidioc_g_crop                  = fimc_m2m_g_crop,
1344         .vidioc_s_crop                  = fimc_m2m_s_crop,
1345         .vidioc_cropcap                 = fimc_m2m_cropcap
1346
1347 };
1348
1349 static int queue_init(void *priv, struct vb2_queue *src_vq,
1350                       struct vb2_queue *dst_vq)
1351 {
1352         struct fimc_ctx *ctx = priv;
1353         int ret;
1354
1355         memset(src_vq, 0, sizeof(*src_vq));
1356         src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
1357         src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1358         src_vq->drv_priv = ctx;
1359         src_vq->ops = &fimc_qops;
1360         src_vq->mem_ops = &vb2_dma_contig_memops;
1361         src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1362
1363         ret = vb2_queue_init(src_vq);
1364         if (ret)
1365                 return ret;
1366
1367         memset(dst_vq, 0, sizeof(*dst_vq));
1368         dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1369         dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1370         dst_vq->drv_priv = ctx;
1371         dst_vq->ops = &fimc_qops;
1372         dst_vq->mem_ops = &vb2_dma_contig_memops;
1373         dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1374
1375         return vb2_queue_init(dst_vq);
1376 }
1377
1378 static int fimc_m2m_open(struct file *file)
1379 {
1380         struct fimc_dev *fimc = video_drvdata(file);
1381         struct fimc_ctx *ctx = NULL;
1382
1383         dbg("pid: %d, state: 0x%lx, refcnt: %d",
1384                 task_pid_nr(current), fimc->state, fimc->vid_cap.refcnt);
1385
1386         /*
1387          * Return if the corresponding video capture node
1388          * is already opened.
1389          */
1390         if (fimc->vid_cap.refcnt > 0)
1391                 return -EBUSY;
1392
1393         fimc->m2m.refcnt++;
1394         set_bit(ST_OUTDMA_RUN, &fimc->state);
1395
1396         ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
1397         if (!ctx)
1398                 return -ENOMEM;
1399
1400         file->private_data = ctx;
1401         ctx->fimc_dev = fimc;
1402         /* Default color format */
1403         ctx->s_frame.fmt = &fimc_formats[0];
1404         ctx->d_frame.fmt = &fimc_formats[0];
1405         /* Setup the device context for mem2mem mode. */
1406         ctx->state = FIMC_CTX_M2M;
1407         ctx->flags = 0;
1408         ctx->in_path = FIMC_DMA;
1409         ctx->out_path = FIMC_DMA;
1410         spin_lock_init(&ctx->slock);
1411
1412         ctx->m2m_ctx = v4l2_m2m_ctx_init(fimc->m2m.m2m_dev, ctx, queue_init);
1413         if (IS_ERR(ctx->m2m_ctx)) {
1414                 int err = PTR_ERR(ctx->m2m_ctx);
1415                 kfree(ctx);
1416                 return err;
1417         }
1418
1419         return 0;
1420 }
1421
1422 static int fimc_m2m_release(struct file *file)
1423 {
1424         struct fimc_ctx *ctx = file->private_data;
1425         struct fimc_dev *fimc = ctx->fimc_dev;
1426
1427         dbg("pid: %d, state: 0x%lx, refcnt= %d",
1428                 task_pid_nr(current), fimc->state, fimc->m2m.refcnt);
1429
1430         v4l2_m2m_ctx_release(ctx->m2m_ctx);
1431         kfree(ctx);
1432         if (--fimc->m2m.refcnt <= 0)
1433                 clear_bit(ST_OUTDMA_RUN, &fimc->state);
1434
1435         return 0;
1436 }
1437
1438 static unsigned int fimc_m2m_poll(struct file *file,
1439                                      struct poll_table_struct *wait)
1440 {
1441         struct fimc_ctx *ctx = file->private_data;
1442
1443         return v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
1444 }
1445
1446
1447 static int fimc_m2m_mmap(struct file *file, struct vm_area_struct *vma)
1448 {
1449         struct fimc_ctx *ctx = file->private_data;
1450
1451         return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
1452 }
1453
1454 static const struct v4l2_file_operations fimc_m2m_fops = {
1455         .owner          = THIS_MODULE,
1456         .open           = fimc_m2m_open,
1457         .release        = fimc_m2m_release,
1458         .poll           = fimc_m2m_poll,
1459         .unlocked_ioctl = video_ioctl2,
1460         .mmap           = fimc_m2m_mmap,
1461 };
1462
1463 static struct v4l2_m2m_ops m2m_ops = {
1464         .device_run     = fimc_dma_run,
1465         .job_abort      = fimc_job_abort,
1466 };
1467
1468 static int fimc_register_m2m_device(struct fimc_dev *fimc)
1469 {
1470         struct video_device *vfd;
1471         struct platform_device *pdev;
1472         struct v4l2_device *v4l2_dev;
1473         int ret = 0;
1474
1475         if (!fimc)
1476                 return -ENODEV;
1477
1478         pdev = fimc->pdev;
1479         v4l2_dev = &fimc->m2m.v4l2_dev;
1480
1481         /* set name if it is empty */
1482         if (!v4l2_dev->name[0])
1483                 snprintf(v4l2_dev->name, sizeof(v4l2_dev->name),
1484                          "%s.m2m", dev_name(&pdev->dev));
1485
1486         ret = v4l2_device_register(&pdev->dev, v4l2_dev);
1487         if (ret)
1488                 goto err_m2m_r1;
1489
1490         vfd = video_device_alloc();
1491         if (!vfd) {
1492                 v4l2_err(v4l2_dev, "Failed to allocate video device\n");
1493                 goto err_m2m_r1;
1494         }
1495
1496         vfd->fops       = &fimc_m2m_fops;
1497         vfd->ioctl_ops  = &fimc_m2m_ioctl_ops;
1498         vfd->minor      = -1;
1499         vfd->release    = video_device_release;
1500         vfd->lock       = &fimc->lock;
1501
1502         snprintf(vfd->name, sizeof(vfd->name), "%s:m2m", dev_name(&pdev->dev));
1503
1504         video_set_drvdata(vfd, fimc);
1505         platform_set_drvdata(pdev, fimc);
1506
1507         fimc->m2m.vfd = vfd;
1508         fimc->m2m.m2m_dev = v4l2_m2m_init(&m2m_ops);
1509         if (IS_ERR(fimc->m2m.m2m_dev)) {
1510                 v4l2_err(v4l2_dev, "failed to initialize v4l2-m2m device\n");
1511                 ret = PTR_ERR(fimc->m2m.m2m_dev);
1512                 goto err_m2m_r2;
1513         }
1514
1515         ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
1516         if (ret) {
1517                 v4l2_err(v4l2_dev,
1518                          "%s(): failed to register video device\n", __func__);
1519                 goto err_m2m_r3;
1520         }
1521         v4l2_info(v4l2_dev,
1522                   "FIMC m2m driver registered as /dev/video%d\n", vfd->num);
1523
1524         return 0;
1525
1526 err_m2m_r3:
1527         v4l2_m2m_release(fimc->m2m.m2m_dev);
1528 err_m2m_r2:
1529         video_device_release(fimc->m2m.vfd);
1530 err_m2m_r1:
1531         v4l2_device_unregister(v4l2_dev);
1532
1533         return ret;
1534 }
1535
1536 static void fimc_unregister_m2m_device(struct fimc_dev *fimc)
1537 {
1538         if (fimc) {
1539                 v4l2_m2m_release(fimc->m2m.m2m_dev);
1540                 video_unregister_device(fimc->m2m.vfd);
1541
1542                 v4l2_device_unregister(&fimc->m2m.v4l2_dev);
1543         }
1544 }
1545
1546 static void fimc_clk_release(struct fimc_dev *fimc)
1547 {
1548         int i;
1549         for (i = 0; i < fimc->num_clocks; i++) {
1550                 if (fimc->clock[i]) {
1551                         clk_disable(fimc->clock[i]);
1552                         clk_put(fimc->clock[i]);
1553                 }
1554         }
1555 }
1556
1557 static int fimc_clk_get(struct fimc_dev *fimc)
1558 {
1559         int i;
1560         for (i = 0; i < fimc->num_clocks; i++) {
1561                 fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clocks[i]);
1562
1563                 if (!IS_ERR_OR_NULL(fimc->clock[i])) {
1564                         clk_enable(fimc->clock[i]);
1565                         continue;
1566                 }
1567                 dev_err(&fimc->pdev->dev, "failed to get fimc clock: %s\n",
1568                         fimc_clocks[i]);
1569                 return -ENXIO;
1570         }
1571         return 0;
1572 }
1573
1574 static int fimc_probe(struct platform_device *pdev)
1575 {
1576         struct fimc_dev *fimc;
1577         struct resource *res;
1578         struct samsung_fimc_driverdata *drv_data;
1579         int ret = 0;
1580         int cap_input_index = -1;
1581
1582         dev_dbg(&pdev->dev, "%s():\n", __func__);
1583
1584         drv_data = (struct samsung_fimc_driverdata *)
1585                 platform_get_device_id(pdev)->driver_data;
1586
1587         if (pdev->id >= drv_data->num_entities) {
1588                 dev_err(&pdev->dev, "Invalid platform device id: %d\n",
1589                         pdev->id);
1590                 return -EINVAL;
1591         }
1592
1593         fimc = kzalloc(sizeof(struct fimc_dev), GFP_KERNEL);
1594         if (!fimc)
1595                 return -ENOMEM;
1596
1597         fimc->id = pdev->id;
1598         fimc->variant = drv_data->variant[fimc->id];
1599         fimc->pdev = pdev;
1600         fimc->pdata = pdev->dev.platform_data;
1601         fimc->state = ST_IDLE;
1602
1603         init_waitqueue_head(&fimc->irq_queue);
1604         spin_lock_init(&fimc->slock);
1605
1606         mutex_init(&fimc->lock);
1607
1608         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1609         if (!res) {
1610                 dev_err(&pdev->dev, "failed to find the registers\n");
1611                 ret = -ENOENT;
1612                 goto err_info;
1613         }
1614
1615         fimc->regs_res = request_mem_region(res->start, resource_size(res),
1616                         dev_name(&pdev->dev));
1617         if (!fimc->regs_res) {
1618                 dev_err(&pdev->dev, "failed to obtain register region\n");
1619                 ret = -ENOENT;
1620                 goto err_info;
1621         }
1622
1623         fimc->regs = ioremap(res->start, resource_size(res));
1624         if (!fimc->regs) {
1625                 dev_err(&pdev->dev, "failed to map registers\n");
1626                 ret = -ENXIO;
1627                 goto err_req_region;
1628         }
1629
1630         fimc->num_clocks = MAX_FIMC_CLOCKS - 1;
1631         /*
1632          * Check if vide capture node needs to be registered for this device
1633          * instance.
1634          */
1635         if (fimc->pdata) {
1636                 int i;
1637                 for (i = 0; i < FIMC_MAX_CAMIF_CLIENTS; ++i)
1638                         if (fimc->pdata->isp_info[i])
1639                                 break;
1640                 if (i < FIMC_MAX_CAMIF_CLIENTS) {
1641                         cap_input_index = i;
1642                         fimc->num_clocks++;
1643                 }
1644         }
1645
1646         ret = fimc_clk_get(fimc);
1647         if (ret)
1648                 goto err_regs_unmap;
1649         clk_set_rate(fimc->clock[CLK_BUS], drv_data->lclk_frequency);
1650
1651         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1652         if (!res) {
1653                 dev_err(&pdev->dev, "failed to get IRQ resource\n");
1654                 ret = -ENXIO;
1655                 goto err_clk;
1656         }
1657         fimc->irq = res->start;
1658
1659         fimc_hw_reset(fimc);
1660
1661         ret = request_irq(fimc->irq, fimc_isr, 0, pdev->name, fimc);
1662         if (ret) {
1663                 dev_err(&pdev->dev, "failed to install irq (%d)\n", ret);
1664                 goto err_clk;
1665         }
1666
1667         /* Initialize contiguous memory allocator */
1668         fimc->alloc_ctx = vb2_dma_contig_init_ctx(&fimc->pdev->dev);
1669         if (IS_ERR(fimc->alloc_ctx)) {
1670                 ret = PTR_ERR(fimc->alloc_ctx);
1671                 goto err_irq;
1672         }
1673
1674         ret = fimc_register_m2m_device(fimc);
1675         if (ret)
1676                 goto err_irq;
1677
1678         /* At least one camera sensor is required to register capture node */
1679         if (cap_input_index >= 0) {
1680                 ret = fimc_register_capture_device(fimc);
1681                 if (ret)
1682                         goto err_m2m;
1683                 clk_disable(fimc->clock[CLK_CAM]);
1684         }
1685         /*
1686          * Exclude the additional output DMA address registers by masking
1687          * them out on HW revisions that provide extended capabilites.
1688          */
1689         if (fimc->variant->out_buf_count > 4)
1690                 fimc_hw_set_dma_seq(fimc, 0xF);
1691
1692         dev_dbg(&pdev->dev, "%s(): fimc-%d registered successfully\n",
1693                 __func__, fimc->id);
1694
1695         return 0;
1696
1697 err_m2m:
1698         fimc_unregister_m2m_device(fimc);
1699 err_irq:
1700         free_irq(fimc->irq, fimc);
1701 err_clk:
1702         fimc_clk_release(fimc);
1703 err_regs_unmap:
1704         iounmap(fimc->regs);
1705 err_req_region:
1706         release_resource(fimc->regs_res);
1707         kfree(fimc->regs_res);
1708 err_info:
1709         kfree(fimc);
1710
1711         return ret;
1712 }
1713
1714 static int __devexit fimc_remove(struct platform_device *pdev)
1715 {
1716         struct fimc_dev *fimc =
1717                 (struct fimc_dev *)platform_get_drvdata(pdev);
1718
1719         free_irq(fimc->irq, fimc);
1720         fimc_hw_reset(fimc);
1721
1722         fimc_unregister_m2m_device(fimc);
1723         fimc_unregister_capture_device(fimc);
1724
1725         fimc_clk_release(fimc);
1726
1727         vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
1728
1729         iounmap(fimc->regs);
1730         release_resource(fimc->regs_res);
1731         kfree(fimc->regs_res);
1732         kfree(fimc);
1733
1734         dev_info(&pdev->dev, "%s driver unloaded\n", pdev->name);
1735         return 0;
1736 }
1737
1738 /* Image pixel limits, similar across several FIMC HW revisions. */
1739 static struct fimc_pix_limit s5p_pix_limit[3] = {
1740         [0] = {
1741                 .scaler_en_w    = 3264,
1742                 .scaler_dis_w   = 8192,
1743                 .in_rot_en_h    = 1920,
1744                 .in_rot_dis_w   = 8192,
1745                 .out_rot_en_w   = 1920,
1746                 .out_rot_dis_w  = 4224,
1747         },
1748         [1] = {
1749                 .scaler_en_w    = 4224,
1750                 .scaler_dis_w   = 8192,
1751                 .in_rot_en_h    = 1920,
1752                 .in_rot_dis_w   = 8192,
1753                 .out_rot_en_w   = 1920,
1754                 .out_rot_dis_w  = 4224,
1755         },
1756         [2] = {
1757                 .scaler_en_w    = 1920,
1758                 .scaler_dis_w   = 8192,
1759                 .in_rot_en_h    = 1280,
1760                 .in_rot_dis_w   = 8192,
1761                 .out_rot_en_w   = 1280,
1762                 .out_rot_dis_w  = 1920,
1763         },
1764 };
1765
1766 static struct samsung_fimc_variant fimc0_variant_s5p = {
1767         .has_inp_rot     = 1,
1768         .has_out_rot     = 1,
1769         .min_inp_pixsize = 16,
1770         .min_out_pixsize = 16,
1771         .hor_offs_align  = 8,
1772         .out_buf_count   = 4,
1773         .pix_limit       = &s5p_pix_limit[0],
1774 };
1775
1776 static struct samsung_fimc_variant fimc2_variant_s5p = {
1777         .min_inp_pixsize = 16,
1778         .min_out_pixsize = 16,
1779         .hor_offs_align  = 8,
1780         .out_buf_count   = 4,
1781         .pix_limit = &s5p_pix_limit[1],
1782 };
1783
1784 static struct samsung_fimc_variant fimc0_variant_s5pv210 = {
1785         .pix_hoff        = 1,
1786         .has_inp_rot     = 1,
1787         .has_out_rot     = 1,
1788         .min_inp_pixsize = 16,
1789         .min_out_pixsize = 16,
1790         .hor_offs_align  = 8,
1791         .out_buf_count   = 4,
1792         .pix_limit       = &s5p_pix_limit[1],
1793 };
1794
1795 static struct samsung_fimc_variant fimc1_variant_s5pv210 = {
1796         .pix_hoff        = 1,
1797         .has_inp_rot     = 1,
1798         .has_out_rot     = 1,
1799         .has_mainscaler_ext = 1,
1800         .min_inp_pixsize = 16,
1801         .min_out_pixsize = 16,
1802         .hor_offs_align  = 1,
1803         .out_buf_count   = 4,
1804         .pix_limit       = &s5p_pix_limit[2],
1805 };
1806
1807 static struct samsung_fimc_variant fimc2_variant_s5pv210 = {
1808         .pix_hoff        = 1,
1809         .min_inp_pixsize = 16,
1810         .min_out_pixsize = 16,
1811         .hor_offs_align  = 8,
1812         .out_buf_count   = 4,
1813         .pix_limit       = &s5p_pix_limit[2],
1814 };
1815
1816 static struct samsung_fimc_variant fimc0_variant_s5pv310 = {
1817         .pix_hoff        = 1,
1818         .has_inp_rot     = 1,
1819         .has_out_rot     = 1,
1820         .has_cistatus2   = 1,
1821         .has_mainscaler_ext = 1,
1822         .min_inp_pixsize = 16,
1823         .min_out_pixsize = 16,
1824         .hor_offs_align  = 1,
1825         .out_buf_count   = 32,
1826         .pix_limit       = &s5p_pix_limit[1],
1827 };
1828
1829 static struct samsung_fimc_variant fimc2_variant_s5pv310 = {
1830         .pix_hoff        = 1,
1831         .has_cistatus2   = 1,
1832         .has_mainscaler_ext = 1,
1833         .min_inp_pixsize = 16,
1834         .min_out_pixsize = 16,
1835         .hor_offs_align  = 1,
1836         .out_buf_count   = 32,
1837         .pix_limit       = &s5p_pix_limit[2],
1838 };
1839
1840 /* S5PC100 */
1841 static struct samsung_fimc_driverdata fimc_drvdata_s5p = {
1842         .variant = {
1843                 [0] = &fimc0_variant_s5p,
1844                 [1] = &fimc0_variant_s5p,
1845                 [2] = &fimc2_variant_s5p,
1846         },
1847         .num_entities = 3,
1848         .lclk_frequency = 133000000UL,
1849 };
1850
1851 /* S5PV210, S5PC110 */
1852 static struct samsung_fimc_driverdata fimc_drvdata_s5pv210 = {
1853         .variant = {
1854                 [0] = &fimc0_variant_s5pv210,
1855                 [1] = &fimc1_variant_s5pv210,
1856                 [2] = &fimc2_variant_s5pv210,
1857         },
1858         .num_entities = 3,
1859         .lclk_frequency = 166000000UL,
1860 };
1861
1862 /* S5PV310, S5PC210 */
1863 static struct samsung_fimc_driverdata fimc_drvdata_s5pv310 = {
1864         .variant = {
1865                 [0] = &fimc0_variant_s5pv310,
1866                 [1] = &fimc0_variant_s5pv310,
1867                 [2] = &fimc0_variant_s5pv310,
1868                 [3] = &fimc2_variant_s5pv310,
1869         },
1870         .num_entities = 4,
1871         .lclk_frequency = 166000000UL,
1872 };
1873
1874 static struct platform_device_id fimc_driver_ids[] = {
1875         {
1876                 .name           = "s5p-fimc",
1877                 .driver_data    = (unsigned long)&fimc_drvdata_s5p,
1878         }, {
1879                 .name           = "s5pv210-fimc",
1880                 .driver_data    = (unsigned long)&fimc_drvdata_s5pv210,
1881         }, {
1882                 .name           = "s5pv310-fimc",
1883                 .driver_data    = (unsigned long)&fimc_drvdata_s5pv310,
1884         },
1885         {},
1886 };
1887 MODULE_DEVICE_TABLE(platform, fimc_driver_ids);
1888
1889 static struct platform_driver fimc_driver = {
1890         .probe          = fimc_probe,
1891         .remove = __devexit_p(fimc_remove),
1892         .id_table       = fimc_driver_ids,
1893         .driver = {
1894                 .name   = MODULE_NAME,
1895                 .owner  = THIS_MODULE,
1896         }
1897 };
1898
1899 static int __init fimc_init(void)
1900 {
1901         int ret = platform_driver_register(&fimc_driver);
1902         if (ret)
1903                 err("platform_driver_register failed: %d\n", ret);
1904         return ret;
1905 }
1906
1907 static void __exit fimc_exit(void)
1908 {
1909         platform_driver_unregister(&fimc_driver);
1910 }
1911
1912 module_init(fimc_init);
1913 module_exit(fimc_exit);
1914
1915 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
1916 MODULE_DESCRIPTION("S5P FIMC camera host interface/video postprocessor driver");
1917 MODULE_LICENSE("GPL");