Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[linux-2.6.git] / drivers / media / video / s5p-fimc / fimc-core.c
1 /*
2  * Samsung S5P/EXYNOS4 SoC series camera interface (video postprocessor) driver
3  *
4  * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd.
5  * Contact: Sylwester Nawrocki, <s.nawrocki@samsung.com>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published
9  * by the Free Software Foundation, either version 2 of the License,
10  * or (at your option) any later version.
11  */
12
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/errno.h>
17 #include <linux/bug.h>
18 #include <linux/interrupt.h>
19 #include <linux/device.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/list.h>
23 #include <linux/io.h>
24 #include <linux/slab.h>
25 #include <linux/clk.h>
26 #include <media/v4l2-ioctl.h>
27 #include <media/videobuf2-core.h>
28 #include <media/videobuf2-dma-contig.h>
29
30 #include "fimc-core.h"
31 #include "fimc-mdevice.h"
32
33 static char *fimc_clocks[MAX_FIMC_CLOCKS] = {
34         "sclk_fimc", "fimc"
35 };
36
37 static struct fimc_fmt fimc_formats[] = {
38         {
39                 .name           = "RGB565",
40                 .fourcc         = V4L2_PIX_FMT_RGB565,
41                 .depth          = { 16 },
42                 .color          = S5P_FIMC_RGB565,
43                 .memplanes      = 1,
44                 .colplanes      = 1,
45                 .flags          = FMT_FLAGS_M2M,
46         }, {
47                 .name           = "BGR666",
48                 .fourcc         = V4L2_PIX_FMT_BGR666,
49                 .depth          = { 32 },
50                 .color          = S5P_FIMC_RGB666,
51                 .memplanes      = 1,
52                 .colplanes      = 1,
53                 .flags          = FMT_FLAGS_M2M,
54         }, {
55                 .name           = "XRGB-8-8-8-8, 32 bpp",
56                 .fourcc         = V4L2_PIX_FMT_RGB32,
57                 .depth          = { 32 },
58                 .color          = S5P_FIMC_RGB888,
59                 .memplanes      = 1,
60                 .colplanes      = 1,
61                 .flags          = FMT_FLAGS_M2M,
62         }, {
63                 .name           = "YUV 4:2:2 packed, YCbYCr",
64                 .fourcc         = V4L2_PIX_FMT_YUYV,
65                 .depth          = { 16 },
66                 .color          = S5P_FIMC_YCBYCR422,
67                 .memplanes      = 1,
68                 .colplanes      = 1,
69                 .mbus_code      = V4L2_MBUS_FMT_YUYV8_2X8,
70                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
71         }, {
72                 .name           = "YUV 4:2:2 packed, CbYCrY",
73                 .fourcc         = V4L2_PIX_FMT_UYVY,
74                 .depth          = { 16 },
75                 .color          = S5P_FIMC_CBYCRY422,
76                 .memplanes      = 1,
77                 .colplanes      = 1,
78                 .mbus_code      = V4L2_MBUS_FMT_UYVY8_2X8,
79                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
80         }, {
81                 .name           = "YUV 4:2:2 packed, CrYCbY",
82                 .fourcc         = V4L2_PIX_FMT_VYUY,
83                 .depth          = { 16 },
84                 .color          = S5P_FIMC_CRYCBY422,
85                 .memplanes      = 1,
86                 .colplanes      = 1,
87                 .mbus_code      = V4L2_MBUS_FMT_VYUY8_2X8,
88                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
89         }, {
90                 .name           = "YUV 4:2:2 packed, YCrYCb",
91                 .fourcc         = V4L2_PIX_FMT_YVYU,
92                 .depth          = { 16 },
93                 .color          = S5P_FIMC_YCRYCB422,
94                 .memplanes      = 1,
95                 .colplanes      = 1,
96                 .mbus_code      = V4L2_MBUS_FMT_YVYU8_2X8,
97                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
98         }, {
99                 .name           = "YUV 4:2:2 planar, Y/Cb/Cr",
100                 .fourcc         = V4L2_PIX_FMT_YUV422P,
101                 .depth          = { 12 },
102                 .color          = S5P_FIMC_YCBYCR422,
103                 .memplanes      = 1,
104                 .colplanes      = 3,
105                 .flags          = FMT_FLAGS_M2M,
106         }, {
107                 .name           = "YUV 4:2:2 planar, Y/CbCr",
108                 .fourcc         = V4L2_PIX_FMT_NV16,
109                 .depth          = { 16 },
110                 .color          = S5P_FIMC_YCBYCR422,
111                 .memplanes      = 1,
112                 .colplanes      = 2,
113                 .flags          = FMT_FLAGS_M2M,
114         }, {
115                 .name           = "YUV 4:2:2 planar, Y/CrCb",
116                 .fourcc         = V4L2_PIX_FMT_NV61,
117                 .depth          = { 16 },
118                 .color          = S5P_FIMC_YCRYCB422,
119                 .memplanes      = 1,
120                 .colplanes      = 2,
121                 .flags          = FMT_FLAGS_M2M,
122         }, {
123                 .name           = "YUV 4:2:0 planar, YCbCr",
124                 .fourcc         = V4L2_PIX_FMT_YUV420,
125                 .depth          = { 12 },
126                 .color          = S5P_FIMC_YCBCR420,
127                 .memplanes      = 1,
128                 .colplanes      = 3,
129                 .flags          = FMT_FLAGS_M2M,
130         }, {
131                 .name           = "YUV 4:2:0 planar, Y/CbCr",
132                 .fourcc         = V4L2_PIX_FMT_NV12,
133                 .depth          = { 12 },
134                 .color          = S5P_FIMC_YCBCR420,
135                 .memplanes      = 1,
136                 .colplanes      = 2,
137                 .flags          = FMT_FLAGS_M2M,
138         }, {
139                 .name           = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr",
140                 .fourcc         = V4L2_PIX_FMT_NV12M,
141                 .color          = S5P_FIMC_YCBCR420,
142                 .depth          = { 8, 4 },
143                 .memplanes      = 2,
144                 .colplanes      = 2,
145                 .flags          = FMT_FLAGS_M2M,
146         }, {
147                 .name           = "YUV 4:2:0 non-contiguous 3-planar, Y/Cb/Cr",
148                 .fourcc         = V4L2_PIX_FMT_YUV420M,
149                 .color          = S5P_FIMC_YCBCR420,
150                 .depth          = { 8, 2, 2 },
151                 .memplanes      = 3,
152                 .colplanes      = 3,
153                 .flags          = FMT_FLAGS_M2M,
154         }, {
155                 .name           = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr, tiled",
156                 .fourcc         = V4L2_PIX_FMT_NV12MT,
157                 .color          = S5P_FIMC_YCBCR420,
158                 .depth          = { 8, 4 },
159                 .memplanes      = 2,
160                 .colplanes      = 2,
161                 .flags          = FMT_FLAGS_M2M,
162         }, {
163                 .name           = "JPEG encoded data",
164                 .fourcc         = V4L2_PIX_FMT_JPEG,
165                 .color          = S5P_FIMC_JPEG,
166                 .depth          = { 8 },
167                 .memplanes      = 1,
168                 .colplanes      = 1,
169                 .mbus_code      = V4L2_MBUS_FMT_JPEG_1X8,
170                 .flags          = FMT_FLAGS_CAM,
171         },
172 };
173
174 int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh,
175                             int dw, int dh, int rotation)
176 {
177         if (rotation == 90 || rotation == 270)
178                 swap(dw, dh);
179
180         if (!ctx->scaler.enabled)
181                 return (sw == dw && sh == dh) ? 0 : -EINVAL;
182
183         if ((sw >= SCALER_MAX_HRATIO * dw) || (sh >= SCALER_MAX_VRATIO * dh))
184                 return -EINVAL;
185
186         return 0;
187 }
188
189 static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
190 {
191         u32 sh = 6;
192
193         if (src >= 64 * tar)
194                 return -EINVAL;
195
196         while (sh--) {
197                 u32 tmp = 1 << sh;
198                 if (src >= tar * tmp) {
199                         *shift = sh, *ratio = tmp;
200                         return 0;
201                 }
202         }
203         *shift = 0, *ratio = 1;
204         return 0;
205 }
206
207 int fimc_set_scaler_info(struct fimc_ctx *ctx)
208 {
209         struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
210         struct device *dev = &ctx->fimc_dev->pdev->dev;
211         struct fimc_scaler *sc = &ctx->scaler;
212         struct fimc_frame *s_frame = &ctx->s_frame;
213         struct fimc_frame *d_frame = &ctx->d_frame;
214         int tx, ty, sx, sy;
215         int ret;
216
217         if (ctx->rotation == 90 || ctx->rotation == 270) {
218                 ty = d_frame->width;
219                 tx = d_frame->height;
220         } else {
221                 tx = d_frame->width;
222                 ty = d_frame->height;
223         }
224         if (tx <= 0 || ty <= 0) {
225                 dev_err(dev, "Invalid target size: %dx%d", tx, ty);
226                 return -EINVAL;
227         }
228
229         sx = s_frame->width;
230         sy = s_frame->height;
231         if (sx <= 0 || sy <= 0) {
232                 dev_err(dev, "Invalid source size: %dx%d", sx, sy);
233                 return -EINVAL;
234         }
235         sc->real_width = sx;
236         sc->real_height = sy;
237
238         ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
239         if (ret)
240                 return ret;
241
242         ret = fimc_get_scaler_factor(sy, ty,  &sc->pre_vratio, &sc->vfactor);
243         if (ret)
244                 return ret;
245
246         sc->pre_dst_width = sx / sc->pre_hratio;
247         sc->pre_dst_height = sy / sc->pre_vratio;
248
249         if (variant->has_mainscaler_ext) {
250                 sc->main_hratio = (sx << 14) / (tx << sc->hfactor);
251                 sc->main_vratio = (sy << 14) / (ty << sc->vfactor);
252         } else {
253                 sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
254                 sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
255
256         }
257
258         sc->scaleup_h = (tx >= sx) ? 1 : 0;
259         sc->scaleup_v = (ty >= sy) ? 1 : 0;
260
261         /* check to see if input and output size/format differ */
262         if (s_frame->fmt->color == d_frame->fmt->color
263                 && s_frame->width == d_frame->width
264                 && s_frame->height == d_frame->height)
265                 sc->copy_mode = 1;
266         else
267                 sc->copy_mode = 0;
268
269         return 0;
270 }
271
272 static void fimc_m2m_job_finish(struct fimc_ctx *ctx, int vb_state)
273 {
274         struct vb2_buffer *src_vb, *dst_vb;
275
276         if (!ctx || !ctx->m2m_ctx)
277                 return;
278
279         src_vb = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
280         dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
281
282         if (src_vb && dst_vb) {
283                 v4l2_m2m_buf_done(src_vb, vb_state);
284                 v4l2_m2m_buf_done(dst_vb, vb_state);
285                 v4l2_m2m_job_finish(ctx->fimc_dev->m2m.m2m_dev,
286                                     ctx->m2m_ctx);
287         }
288 }
289
290 /* Complete the transaction which has been scheduled for execution. */
291 static int fimc_m2m_shutdown(struct fimc_ctx *ctx)
292 {
293         struct fimc_dev *fimc = ctx->fimc_dev;
294         int ret;
295
296         if (!fimc_m2m_pending(fimc))
297                 return 0;
298
299         fimc_ctx_state_lock_set(FIMC_CTX_SHUT, ctx);
300
301         ret = wait_event_timeout(fimc->irq_queue,
302                            !fimc_ctx_state_is_set(FIMC_CTX_SHUT, ctx),
303                            FIMC_SHUTDOWN_TIMEOUT);
304
305         return ret == 0 ? -ETIMEDOUT : ret;
306 }
307
308 static int start_streaming(struct vb2_queue *q, unsigned int count)
309 {
310         struct fimc_ctx *ctx = q->drv_priv;
311         int ret;
312
313         ret = pm_runtime_get_sync(&ctx->fimc_dev->pdev->dev);
314         return ret > 0 ? 0 : ret;
315 }
316
317 static int stop_streaming(struct vb2_queue *q)
318 {
319         struct fimc_ctx *ctx = q->drv_priv;
320         int ret;
321
322         ret = fimc_m2m_shutdown(ctx);
323         if (ret == -ETIMEDOUT)
324                 fimc_m2m_job_finish(ctx, VB2_BUF_STATE_ERROR);
325
326         pm_runtime_put(&ctx->fimc_dev->pdev->dev);
327         return 0;
328 }
329
330 void fimc_capture_irq_handler(struct fimc_dev *fimc, bool final)
331 {
332         struct fimc_vid_cap *cap = &fimc->vid_cap;
333         struct fimc_vid_buffer *v_buf;
334         struct timeval *tv;
335         struct timespec ts;
336
337         if (test_and_clear_bit(ST_CAPT_SHUT, &fimc->state)) {
338                 wake_up(&fimc->irq_queue);
339                 return;
340         }
341
342         if (!list_empty(&cap->active_buf_q) &&
343             test_bit(ST_CAPT_RUN, &fimc->state) && final) {
344                 ktime_get_real_ts(&ts);
345
346                 v_buf = fimc_active_queue_pop(cap);
347
348                 tv = &v_buf->vb.v4l2_buf.timestamp;
349                 tv->tv_sec = ts.tv_sec;
350                 tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC;
351                 v_buf->vb.v4l2_buf.sequence = cap->frame_count++;
352
353                 vb2_buffer_done(&v_buf->vb, VB2_BUF_STATE_DONE);
354         }
355
356         if (!list_empty(&cap->pending_buf_q)) {
357
358                 v_buf = fimc_pending_queue_pop(cap);
359                 fimc_hw_set_output_addr(fimc, &v_buf->paddr, cap->buf_index);
360                 v_buf->index = cap->buf_index;
361
362                 /* Move the buffer to the capture active queue */
363                 fimc_active_queue_add(cap, v_buf);
364
365                 dbg("next frame: %d, done frame: %d",
366                     fimc_hw_get_frame_index(fimc), v_buf->index);
367
368                 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
369                         cap->buf_index = 0;
370         }
371
372         if (cap->active_buf_cnt == 0) {
373                 if (final)
374                         clear_bit(ST_CAPT_RUN, &fimc->state);
375
376                 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
377                         cap->buf_index = 0;
378         } else {
379                 set_bit(ST_CAPT_RUN, &fimc->state);
380         }
381
382         fimc_capture_config_update(cap->ctx);
383
384         dbg("frame: %d, active_buf_cnt: %d",
385             fimc_hw_get_frame_index(fimc), cap->active_buf_cnt);
386 }
387
388 static irqreturn_t fimc_irq_handler(int irq, void *priv)
389 {
390         struct fimc_dev *fimc = priv;
391         struct fimc_vid_cap *cap = &fimc->vid_cap;
392         struct fimc_ctx *ctx;
393
394         fimc_hw_clear_irq(fimc);
395
396         spin_lock(&fimc->slock);
397
398         if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
399                 if (test_and_clear_bit(ST_M2M_SUSPENDING, &fimc->state)) {
400                         set_bit(ST_M2M_SUSPENDED, &fimc->state);
401                         wake_up(&fimc->irq_queue);
402                         goto out;
403                 }
404                 ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
405                 if (ctx != NULL) {
406                         spin_unlock(&fimc->slock);
407                         fimc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE);
408
409                         spin_lock(&ctx->slock);
410                         if (ctx->state & FIMC_CTX_SHUT) {
411                                 ctx->state &= ~FIMC_CTX_SHUT;
412                                 wake_up(&fimc->irq_queue);
413                         }
414                         spin_unlock(&ctx->slock);
415                 }
416                 return IRQ_HANDLED;
417         } else if (test_bit(ST_CAPT_PEND, &fimc->state)) {
418                 fimc_capture_irq_handler(fimc,
419                                  !test_bit(ST_CAPT_JPEG, &fimc->state));
420                 if (cap->active_buf_cnt == 1) {
421                         fimc_deactivate_capture(fimc);
422                         clear_bit(ST_CAPT_STREAM, &fimc->state);
423                 }
424         }
425 out:
426         spin_unlock(&fimc->slock);
427         return IRQ_HANDLED;
428 }
429
430 /* The color format (colplanes, memplanes) must be already configured. */
431 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
432                       struct fimc_frame *frame, struct fimc_addr *paddr)
433 {
434         int ret = 0;
435         u32 pix_size;
436
437         if (vb == NULL || frame == NULL)
438                 return -EINVAL;
439
440         pix_size = frame->width * frame->height;
441
442         dbg("memplanes= %d, colplanes= %d, pix_size= %d",
443                 frame->fmt->memplanes, frame->fmt->colplanes, pix_size);
444
445         paddr->y = vb2_dma_contig_plane_dma_addr(vb, 0);
446
447         if (frame->fmt->memplanes == 1) {
448                 switch (frame->fmt->colplanes) {
449                 case 1:
450                         paddr->cb = 0;
451                         paddr->cr = 0;
452                         break;
453                 case 2:
454                         /* decompose Y into Y/Cb */
455                         paddr->cb = (u32)(paddr->y + pix_size);
456                         paddr->cr = 0;
457                         break;
458                 case 3:
459                         paddr->cb = (u32)(paddr->y + pix_size);
460                         /* decompose Y into Y/Cb/Cr */
461                         if (S5P_FIMC_YCBCR420 == frame->fmt->color)
462                                 paddr->cr = (u32)(paddr->cb
463                                                 + (pix_size >> 2));
464                         else /* 422 */
465                                 paddr->cr = (u32)(paddr->cb
466                                                 + (pix_size >> 1));
467                         break;
468                 default:
469                         return -EINVAL;
470                 }
471         } else {
472                 if (frame->fmt->memplanes >= 2)
473                         paddr->cb = vb2_dma_contig_plane_dma_addr(vb, 1);
474
475                 if (frame->fmt->memplanes == 3)
476                         paddr->cr = vb2_dma_contig_plane_dma_addr(vb, 2);
477         }
478
479         dbg("PHYS_ADDR: y= 0x%X  cb= 0x%X cr= 0x%X ret= %d",
480             paddr->y, paddr->cb, paddr->cr, ret);
481
482         return ret;
483 }
484
485 /* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
486 void fimc_set_yuv_order(struct fimc_ctx *ctx)
487 {
488         /* The one only mode supported in SoC. */
489         ctx->in_order_2p = S5P_FIMC_LSB_CRCB;
490         ctx->out_order_2p = S5P_FIMC_LSB_CRCB;
491
492         /* Set order for 1 plane input formats. */
493         switch (ctx->s_frame.fmt->color) {
494         case S5P_FIMC_YCRYCB422:
495                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CBYCRY;
496                 break;
497         case S5P_FIMC_CBYCRY422:
498                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCRYCB;
499                 break;
500         case S5P_FIMC_CRYCBY422:
501                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCBYCR;
502                 break;
503         case S5P_FIMC_YCBYCR422:
504         default:
505                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CRYCBY;
506                 break;
507         }
508         dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
509
510         switch (ctx->d_frame.fmt->color) {
511         case S5P_FIMC_YCRYCB422:
512                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CBYCRY;
513                 break;
514         case S5P_FIMC_CBYCRY422:
515                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCRYCB;
516                 break;
517         case S5P_FIMC_CRYCBY422:
518                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCBYCR;
519                 break;
520         case S5P_FIMC_YCBYCR422:
521         default:
522                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CRYCBY;
523                 break;
524         }
525         dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
526 }
527
528 void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f)
529 {
530         struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
531         u32 i, depth = 0;
532
533         for (i = 0; i < f->fmt->colplanes; i++)
534                 depth += f->fmt->depth[i];
535
536         f->dma_offset.y_h = f->offs_h;
537         if (!variant->pix_hoff)
538                 f->dma_offset.y_h *= (depth >> 3);
539
540         f->dma_offset.y_v = f->offs_v;
541
542         f->dma_offset.cb_h = f->offs_h;
543         f->dma_offset.cb_v = f->offs_v;
544
545         f->dma_offset.cr_h = f->offs_h;
546         f->dma_offset.cr_v = f->offs_v;
547
548         if (!variant->pix_hoff) {
549                 if (f->fmt->colplanes == 3) {
550                         f->dma_offset.cb_h >>= 1;
551                         f->dma_offset.cr_h >>= 1;
552                 }
553                 if (f->fmt->color == S5P_FIMC_YCBCR420) {
554                         f->dma_offset.cb_v >>= 1;
555                         f->dma_offset.cr_v >>= 1;
556                 }
557         }
558
559         dbg("in_offset: color= %d, y_h= %d, y_v= %d",
560             f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v);
561 }
562
563 /**
564  * fimc_prepare_config - check dimensions, operation and color mode
565  *                       and pre-calculate offset and the scaling coefficients.
566  *
567  * @ctx: hardware context information
568  * @flags: flags indicating which parameters to check/update
569  *
570  * Return: 0 if dimensions are valid or non zero otherwise.
571  */
572 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags)
573 {
574         struct fimc_frame *s_frame, *d_frame;
575         struct vb2_buffer *vb = NULL;
576         int ret = 0;
577
578         s_frame = &ctx->s_frame;
579         d_frame = &ctx->d_frame;
580
581         if (flags & FIMC_PARAMS) {
582                 /* Prepare the DMA offset ratios for scaler. */
583                 fimc_prepare_dma_offset(ctx, &ctx->s_frame);
584                 fimc_prepare_dma_offset(ctx, &ctx->d_frame);
585
586                 if (s_frame->height > (SCALER_MAX_VRATIO * d_frame->height) ||
587                     s_frame->width > (SCALER_MAX_HRATIO * d_frame->width)) {
588                         err("out of scaler range");
589                         return -EINVAL;
590                 }
591                 fimc_set_yuv_order(ctx);
592         }
593
594         if (flags & FIMC_SRC_ADDR) {
595                 vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
596                 ret = fimc_prepare_addr(ctx, vb, s_frame, &s_frame->paddr);
597                 if (ret)
598                         return ret;
599         }
600
601         if (flags & FIMC_DST_ADDR) {
602                 vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
603                 ret = fimc_prepare_addr(ctx, vb, d_frame, &d_frame->paddr);
604         }
605
606         return ret;
607 }
608
609 static void fimc_dma_run(void *priv)
610 {
611         struct fimc_ctx *ctx = priv;
612         struct fimc_dev *fimc;
613         unsigned long flags;
614         u32 ret;
615
616         if (WARN(!ctx, "null hardware context\n"))
617                 return;
618
619         fimc = ctx->fimc_dev;
620         spin_lock_irqsave(&fimc->slock, flags);
621         set_bit(ST_M2M_PEND, &fimc->state);
622
623         spin_lock(&ctx->slock);
624         ctx->state |= (FIMC_SRC_ADDR | FIMC_DST_ADDR);
625         ret = fimc_prepare_config(ctx, ctx->state);
626         if (ret)
627                 goto dma_unlock;
628
629         /* Reconfigure hardware if the context has changed. */
630         if (fimc->m2m.ctx != ctx) {
631                 ctx->state |= FIMC_PARAMS;
632                 fimc->m2m.ctx = ctx;
633         }
634         fimc_hw_set_input_addr(fimc, &ctx->s_frame.paddr);
635
636         if (ctx->state & FIMC_PARAMS) {
637                 fimc_hw_set_input_path(ctx);
638                 fimc_hw_set_in_dma(ctx);
639                 ret = fimc_set_scaler_info(ctx);
640                 if (ret) {
641                         spin_unlock(&fimc->slock);
642                         goto dma_unlock;
643                 }
644                 fimc_hw_set_prescaler(ctx);
645                 fimc_hw_set_mainscaler(ctx);
646                 fimc_hw_set_target_format(ctx);
647                 fimc_hw_set_rotation(ctx);
648                 fimc_hw_set_effect(ctx, false);
649         }
650
651         fimc_hw_set_output_path(ctx);
652         if (ctx->state & (FIMC_DST_ADDR | FIMC_PARAMS))
653                 fimc_hw_set_output_addr(fimc, &ctx->d_frame.paddr, -1);
654
655         if (ctx->state & FIMC_PARAMS)
656                 fimc_hw_set_out_dma(ctx);
657
658         fimc_activate_capture(ctx);
659
660         ctx->state &= (FIMC_CTX_M2M | FIMC_CTX_CAP |
661                        FIMC_SRC_FMT | FIMC_DST_FMT);
662         fimc_hw_activate_input_dma(fimc, true);
663 dma_unlock:
664         spin_unlock(&ctx->slock);
665         spin_unlock_irqrestore(&fimc->slock, flags);
666 }
667
668 static void fimc_job_abort(void *priv)
669 {
670         fimc_m2m_shutdown(priv);
671 }
672
673 static int fimc_queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt,
674                             unsigned int *num_buffers, unsigned int *num_planes,
675                             unsigned int sizes[], void *allocators[])
676 {
677         struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
678         struct fimc_frame *f;
679         int i;
680
681         f = ctx_get_frame(ctx, vq->type);
682         if (IS_ERR(f))
683                 return PTR_ERR(f);
684         /*
685          * Return number of non-contigous planes (plane buffers)
686          * depending on the configured color format.
687          */
688         if (!f->fmt)
689                 return -EINVAL;
690
691         *num_planes = f->fmt->memplanes;
692         for (i = 0; i < f->fmt->memplanes; i++) {
693                 sizes[i] = (f->f_width * f->f_height * f->fmt->depth[i]) / 8;
694                 allocators[i] = ctx->fimc_dev->alloc_ctx;
695         }
696         return 0;
697 }
698
699 static int fimc_buf_prepare(struct vb2_buffer *vb)
700 {
701         struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
702         struct fimc_frame *frame;
703         int i;
704
705         frame = ctx_get_frame(ctx, vb->vb2_queue->type);
706         if (IS_ERR(frame))
707                 return PTR_ERR(frame);
708
709         for (i = 0; i < frame->fmt->memplanes; i++)
710                 vb2_set_plane_payload(vb, i, frame->payload[i]);
711
712         return 0;
713 }
714
715 static void fimc_buf_queue(struct vb2_buffer *vb)
716 {
717         struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
718
719         dbg("ctx: %p, ctx->state: 0x%x", ctx, ctx->state);
720
721         if (ctx->m2m_ctx)
722                 v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
723 }
724
725 static void fimc_lock(struct vb2_queue *vq)
726 {
727         struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
728         mutex_lock(&ctx->fimc_dev->lock);
729 }
730
731 static void fimc_unlock(struct vb2_queue *vq)
732 {
733         struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
734         mutex_unlock(&ctx->fimc_dev->lock);
735 }
736
737 static struct vb2_ops fimc_qops = {
738         .queue_setup     = fimc_queue_setup,
739         .buf_prepare     = fimc_buf_prepare,
740         .buf_queue       = fimc_buf_queue,
741         .wait_prepare    = fimc_unlock,
742         .wait_finish     = fimc_lock,
743         .stop_streaming  = stop_streaming,
744         .start_streaming = start_streaming,
745 };
746
747 /*
748  * V4L2 controls handling
749  */
750 #define ctrl_to_ctx(__ctrl) \
751         container_of((__ctrl)->handler, struct fimc_ctx, ctrl_handler)
752
753 static int fimc_s_ctrl(struct v4l2_ctrl *ctrl)
754 {
755         struct fimc_ctx *ctx = ctrl_to_ctx(ctrl);
756         struct fimc_dev *fimc = ctx->fimc_dev;
757         struct samsung_fimc_variant *variant = fimc->variant;
758         unsigned long flags;
759         int ret = 0;
760
761         if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
762                 return 0;
763
764         switch (ctrl->id) {
765         case V4L2_CID_HFLIP:
766                 spin_lock_irqsave(&ctx->slock, flags);
767                 ctx->hflip = ctrl->val;
768                 break;
769
770         case V4L2_CID_VFLIP:
771                 spin_lock_irqsave(&ctx->slock, flags);
772                 ctx->vflip = ctrl->val;
773                 break;
774
775         case V4L2_CID_ROTATE:
776                 if (fimc_capture_pending(fimc) ||
777                     fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
778                         ret = fimc_check_scaler_ratio(ctx, ctx->s_frame.width,
779                                         ctx->s_frame.height, ctx->d_frame.width,
780                                         ctx->d_frame.height, ctrl->val);
781                 }
782                 if (ret) {
783                         v4l2_err(fimc->m2m.vfd, "Out of scaler range\n");
784                         return -EINVAL;
785                 }
786                 if ((ctrl->val == 90 || ctrl->val == 270) &&
787                     !variant->has_out_rot)
788                         return -EINVAL;
789                 spin_lock_irqsave(&ctx->slock, flags);
790                 ctx->rotation = ctrl->val;
791                 break;
792
793         default:
794                 v4l2_err(fimc->v4l2_dev, "Invalid control: 0x%X\n", ctrl->id);
795                 return -EINVAL;
796         }
797         ctx->state |= FIMC_PARAMS;
798         set_bit(ST_CAPT_APPLY_CFG, &fimc->state);
799         spin_unlock_irqrestore(&ctx->slock, flags);
800         return 0;
801 }
802
803 static const struct v4l2_ctrl_ops fimc_ctrl_ops = {
804         .s_ctrl = fimc_s_ctrl,
805 };
806
807 int fimc_ctrls_create(struct fimc_ctx *ctx)
808 {
809         if (ctx->ctrls_rdy)
810                 return 0;
811         v4l2_ctrl_handler_init(&ctx->ctrl_handler, 3);
812
813         ctx->ctrl_rotate = v4l2_ctrl_new_std(&ctx->ctrl_handler, &fimc_ctrl_ops,
814                                      V4L2_CID_HFLIP, 0, 1, 1, 0);
815         ctx->ctrl_hflip = v4l2_ctrl_new_std(&ctx->ctrl_handler, &fimc_ctrl_ops,
816                                     V4L2_CID_VFLIP, 0, 1, 1, 0);
817         ctx->ctrl_vflip = v4l2_ctrl_new_std(&ctx->ctrl_handler, &fimc_ctrl_ops,
818                                     V4L2_CID_ROTATE, 0, 270, 90, 0);
819         ctx->ctrls_rdy = ctx->ctrl_handler.error == 0;
820
821         return ctx->ctrl_handler.error;
822 }
823
824 void fimc_ctrls_delete(struct fimc_ctx *ctx)
825 {
826         if (ctx->ctrls_rdy) {
827                 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
828                 ctx->ctrls_rdy = false;
829         }
830 }
831
832 void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active)
833 {
834         if (!ctx->ctrls_rdy)
835                 return;
836
837         mutex_lock(&ctx->ctrl_handler.lock);
838         v4l2_ctrl_activate(ctx->ctrl_rotate, active);
839         v4l2_ctrl_activate(ctx->ctrl_hflip, active);
840         v4l2_ctrl_activate(ctx->ctrl_vflip, active);
841
842         if (active) {
843                 ctx->rotation = ctx->ctrl_rotate->val;
844                 ctx->hflip    = ctx->ctrl_hflip->val;
845                 ctx->vflip    = ctx->ctrl_vflip->val;
846         } else {
847                 ctx->rotation = 0;
848                 ctx->hflip    = 0;
849                 ctx->vflip    = 0;
850         }
851         mutex_unlock(&ctx->ctrl_handler.lock);
852 }
853
854 /*
855  * V4L2 ioctl handlers
856  */
857 static int fimc_m2m_querycap(struct file *file, void *fh,
858                              struct v4l2_capability *cap)
859 {
860         struct fimc_ctx *ctx = fh_to_ctx(fh);
861         struct fimc_dev *fimc = ctx->fimc_dev;
862
863         strncpy(cap->driver, fimc->pdev->name, sizeof(cap->driver) - 1);
864         strncpy(cap->card, fimc->pdev->name, sizeof(cap->card) - 1);
865         cap->bus_info[0] = 0;
866         cap->capabilities = V4L2_CAP_STREAMING |
867                 V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_VIDEO_OUTPUT_MPLANE;
868
869         return 0;
870 }
871
872 static int fimc_m2m_enum_fmt_mplane(struct file *file, void *priv,
873                                     struct v4l2_fmtdesc *f)
874 {
875         struct fimc_fmt *fmt;
876
877         fmt = fimc_find_format(NULL, NULL, FMT_FLAGS_M2M, f->index);
878         if (!fmt)
879                 return -EINVAL;
880
881         strncpy(f->description, fmt->name, sizeof(f->description) - 1);
882         f->pixelformat = fmt->fourcc;
883         return 0;
884 }
885
886 int fimc_fill_format(struct fimc_frame *frame, struct v4l2_format *f)
887 {
888         struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
889         int i;
890
891         pixm->width = frame->o_width;
892         pixm->height = frame->o_height;
893         pixm->field = V4L2_FIELD_NONE;
894         pixm->pixelformat = frame->fmt->fourcc;
895         pixm->colorspace = V4L2_COLORSPACE_JPEG;
896         pixm->num_planes = frame->fmt->memplanes;
897
898         for (i = 0; i < pixm->num_planes; ++i) {
899                 int bpl = frame->f_width;
900                 if (frame->fmt->colplanes == 1) /* packed formats */
901                         bpl = (bpl * frame->fmt->depth[0]) / 8;
902                 pixm->plane_fmt[i].bytesperline = bpl;
903                 pixm->plane_fmt[i].sizeimage = (frame->o_width *
904                         frame->o_height * frame->fmt->depth[i]) / 8;
905         }
906         return 0;
907 }
908
909 void fimc_fill_frame(struct fimc_frame *frame, struct v4l2_format *f)
910 {
911         struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
912
913         frame->f_width  = pixm->plane_fmt[0].bytesperline;
914         if (frame->fmt->colplanes == 1)
915                 frame->f_width = (frame->f_width * 8) / frame->fmt->depth[0];
916         frame->f_height = pixm->height;
917         frame->width    = pixm->width;
918         frame->height   = pixm->height;
919         frame->o_width  = pixm->width;
920         frame->o_height = pixm->height;
921         frame->offs_h   = 0;
922         frame->offs_v   = 0;
923 }
924
925 /**
926  * fimc_adjust_mplane_format - adjust bytesperline/sizeimage for each plane
927  * @fmt: fimc pixel format description (input)
928  * @width: requested pixel width
929  * @height: requested pixel height
930  * @pix: multi-plane format to adjust
931  */
932 void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height,
933                                struct v4l2_pix_format_mplane *pix)
934 {
935         u32 bytesperline = 0;
936         int i;
937
938         pix->colorspace = V4L2_COLORSPACE_JPEG;
939         pix->field = V4L2_FIELD_NONE;
940         pix->num_planes = fmt->memplanes;
941         pix->height = height;
942         pix->width = width;
943
944         for (i = 0; i < pix->num_planes; ++i) {
945                 u32 bpl = pix->plane_fmt[i].bytesperline;
946                 u32 *sizeimage = &pix->plane_fmt[i].sizeimage;
947
948                 if (fmt->colplanes > 1 && (bpl == 0 || bpl < pix->width))
949                         bpl = pix->width; /* Planar */
950
951                 if (fmt->colplanes == 1 && /* Packed */
952                     (bpl == 0 || ((bpl * 8) / fmt->depth[i]) < pix->width))
953                         bpl = (pix->width * fmt->depth[0]) / 8;
954
955                 if (i == 0) /* Same bytesperline for each plane. */
956                         bytesperline = bpl;
957
958                 pix->plane_fmt[i].bytesperline = bytesperline;
959                 *sizeimage = (pix->width * pix->height * fmt->depth[i]) / 8;
960         }
961 }
962
963 static int fimc_m2m_g_fmt_mplane(struct file *file, void *fh,
964                                  struct v4l2_format *f)
965 {
966         struct fimc_ctx *ctx = fh_to_ctx(fh);
967         struct fimc_frame *frame = ctx_get_frame(ctx, f->type);
968
969         if (IS_ERR(frame))
970                 return PTR_ERR(frame);
971
972         return fimc_fill_format(frame, f);
973 }
974
975 /**
976  * fimc_find_format - lookup fimc color format by fourcc or media bus format
977  * @pixelformat: fourcc to match, ignored if null
978  * @mbus_code: media bus code to match, ignored if null
979  * @mask: the color flags to match
980  * @index: offset in the fimc_formats array, ignored if negative
981  */
982 struct fimc_fmt *fimc_find_format(u32 *pixelformat, u32 *mbus_code,
983                                   unsigned int mask, int index)
984 {
985         struct fimc_fmt *fmt, *def_fmt = NULL;
986         unsigned int i;
987         int id = 0;
988
989         if (index >= ARRAY_SIZE(fimc_formats))
990                 return NULL;
991
992         for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
993                 fmt = &fimc_formats[i];
994                 if (!(fmt->flags & mask))
995                         continue;
996                 if (pixelformat && fmt->fourcc == *pixelformat)
997                         return fmt;
998                 if (mbus_code && fmt->mbus_code == *mbus_code)
999                         return fmt;
1000                 if (index == id)
1001                         def_fmt = fmt;
1002                 id++;
1003         }
1004         return def_fmt;
1005 }
1006
1007 static int fimc_try_fmt_mplane(struct fimc_ctx *ctx, struct v4l2_format *f)
1008 {
1009         struct fimc_dev *fimc = ctx->fimc_dev;
1010         struct samsung_fimc_variant *variant = fimc->variant;
1011         struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1012         struct fimc_fmt *fmt;
1013         u32 max_w, mod_x, mod_y;
1014
1015         if (!IS_M2M(f->type))
1016                 return -EINVAL;
1017
1018         dbg("w: %d, h: %d", pix->width, pix->height);
1019
1020         fmt = fimc_find_format(&pix->pixelformat, NULL, FMT_FLAGS_M2M, 0);
1021         if (WARN(fmt == NULL, "Pixel format lookup failed"))
1022                 return -EINVAL;
1023
1024         if (pix->field == V4L2_FIELD_ANY)
1025                 pix->field = V4L2_FIELD_NONE;
1026         else if (pix->field != V4L2_FIELD_NONE)
1027                 return -EINVAL;
1028
1029         if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1030                 max_w = variant->pix_limit->scaler_dis_w;
1031                 mod_x = ffs(variant->min_inp_pixsize) - 1;
1032         } else {
1033                 max_w = variant->pix_limit->out_rot_dis_w;
1034                 mod_x = ffs(variant->min_out_pixsize) - 1;
1035         }
1036
1037         if (tiled_fmt(fmt)) {
1038                 mod_x = 6; /* 64 x 32 pixels tile */
1039                 mod_y = 5;
1040         } else {
1041                 if (variant->min_vsize_align == 1)
1042                         mod_y = fimc_fmt_is_rgb(fmt->color) ? 0 : 1;
1043                 else
1044                         mod_y = ffs(variant->min_vsize_align) - 1;
1045         }
1046
1047         v4l_bound_align_image(&pix->width, 16, max_w, mod_x,
1048                 &pix->height, 8, variant->pix_limit->scaler_dis_w, mod_y, 0);
1049
1050         fimc_adjust_mplane_format(fmt, pix->width, pix->height, &f->fmt.pix_mp);
1051         return 0;
1052 }
1053
1054 static int fimc_m2m_try_fmt_mplane(struct file *file, void *fh,
1055                                    struct v4l2_format *f)
1056 {
1057         struct fimc_ctx *ctx = fh_to_ctx(fh);
1058
1059         return fimc_try_fmt_mplane(ctx, f);
1060 }
1061
1062 static int fimc_m2m_s_fmt_mplane(struct file *file, void *fh,
1063                                  struct v4l2_format *f)
1064 {
1065         struct fimc_ctx *ctx = fh_to_ctx(fh);
1066         struct fimc_dev *fimc = ctx->fimc_dev;
1067         struct vb2_queue *vq;
1068         struct fimc_frame *frame;
1069         struct v4l2_pix_format_mplane *pix;
1070         int i, ret = 0;
1071
1072         ret = fimc_try_fmt_mplane(ctx, f);
1073         if (ret)
1074                 return ret;
1075
1076         vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
1077
1078         if (vb2_is_busy(vq)) {
1079                 v4l2_err(fimc->m2m.vfd, "queue (%d) busy\n", f->type);
1080                 return -EBUSY;
1081         }
1082
1083         if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
1084                 frame = &ctx->s_frame;
1085         else
1086                 frame = &ctx->d_frame;
1087
1088         pix = &f->fmt.pix_mp;
1089         frame->fmt = fimc_find_format(&pix->pixelformat, NULL,
1090                                       FMT_FLAGS_M2M, 0);
1091         if (!frame->fmt)
1092                 return -EINVAL;
1093
1094         for (i = 0; i < frame->fmt->colplanes; i++) {
1095                 frame->payload[i] =
1096                         (pix->width * pix->height * frame->fmt->depth[i]) / 8;
1097         }
1098
1099         fimc_fill_frame(frame, f);
1100
1101         ctx->scaler.enabled = 1;
1102
1103         if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1104                 fimc_ctx_state_lock_set(FIMC_PARAMS | FIMC_DST_FMT, ctx);
1105         else
1106                 fimc_ctx_state_lock_set(FIMC_PARAMS | FIMC_SRC_FMT, ctx);
1107
1108         dbg("f_w: %d, f_h: %d", frame->f_width, frame->f_height);
1109
1110         return 0;
1111 }
1112
1113 static int fimc_m2m_reqbufs(struct file *file, void *fh,
1114                             struct v4l2_requestbuffers *reqbufs)
1115 {
1116         struct fimc_ctx *ctx = fh_to_ctx(fh);
1117
1118         return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
1119 }
1120
1121 static int fimc_m2m_querybuf(struct file *file, void *fh,
1122                              struct v4l2_buffer *buf)
1123 {
1124         struct fimc_ctx *ctx = fh_to_ctx(fh);
1125
1126         return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
1127 }
1128
1129 static int fimc_m2m_qbuf(struct file *file, void *fh,
1130                          struct v4l2_buffer *buf)
1131 {
1132         struct fimc_ctx *ctx = fh_to_ctx(fh);
1133
1134         return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
1135 }
1136
1137 static int fimc_m2m_dqbuf(struct file *file, void *fh,
1138                           struct v4l2_buffer *buf)
1139 {
1140         struct fimc_ctx *ctx = fh_to_ctx(fh);
1141
1142         return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
1143 }
1144
1145 static int fimc_m2m_streamon(struct file *file, void *fh,
1146                              enum v4l2_buf_type type)
1147 {
1148         struct fimc_ctx *ctx = fh_to_ctx(fh);
1149
1150         /* The source and target color format need to be set */
1151         if (V4L2_TYPE_IS_OUTPUT(type)) {
1152                 if (!fimc_ctx_state_is_set(FIMC_SRC_FMT, ctx))
1153                         return -EINVAL;
1154         } else if (!fimc_ctx_state_is_set(FIMC_DST_FMT, ctx)) {
1155                 return -EINVAL;
1156         }
1157
1158         return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
1159 }
1160
1161 static int fimc_m2m_streamoff(struct file *file, void *fh,
1162                             enum v4l2_buf_type type)
1163 {
1164         struct fimc_ctx *ctx = fh_to_ctx(fh);
1165
1166         return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
1167 }
1168
1169 static int fimc_m2m_cropcap(struct file *file, void *fh,
1170                             struct v4l2_cropcap *cr)
1171 {
1172         struct fimc_ctx *ctx = fh_to_ctx(fh);
1173         struct fimc_frame *frame;
1174
1175         frame = ctx_get_frame(ctx, cr->type);
1176         if (IS_ERR(frame))
1177                 return PTR_ERR(frame);
1178
1179         cr->bounds.left         = 0;
1180         cr->bounds.top          = 0;
1181         cr->bounds.width        = frame->o_width;
1182         cr->bounds.height       = frame->o_height;
1183         cr->defrect             = cr->bounds;
1184
1185         return 0;
1186 }
1187
1188 static int fimc_m2m_g_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1189 {
1190         struct fimc_ctx *ctx = fh_to_ctx(fh);
1191         struct fimc_frame *frame;
1192
1193         frame = ctx_get_frame(ctx, cr->type);
1194         if (IS_ERR(frame))
1195                 return PTR_ERR(frame);
1196
1197         cr->c.left = frame->offs_h;
1198         cr->c.top = frame->offs_v;
1199         cr->c.width = frame->width;
1200         cr->c.height = frame->height;
1201
1202         return 0;
1203 }
1204
1205 static int fimc_m2m_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr)
1206 {
1207         struct fimc_dev *fimc = ctx->fimc_dev;
1208         struct fimc_frame *f;
1209         u32 min_size, halign, depth = 0;
1210         int i;
1211
1212         if (cr->c.top < 0 || cr->c.left < 0) {
1213                 v4l2_err(fimc->m2m.vfd,
1214                         "doesn't support negative values for top & left\n");
1215                 return -EINVAL;
1216         }
1217         if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1218                 f = &ctx->d_frame;
1219         else if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
1220                 f = &ctx->s_frame;
1221         else
1222                 return -EINVAL;
1223
1224         min_size = (f == &ctx->s_frame) ?
1225                 fimc->variant->min_inp_pixsize : fimc->variant->min_out_pixsize;
1226
1227         /* Get pixel alignment constraints. */
1228         if (fimc->variant->min_vsize_align == 1)
1229                 halign = fimc_fmt_is_rgb(f->fmt->color) ? 0 : 1;
1230         else
1231                 halign = ffs(fimc->variant->min_vsize_align) - 1;
1232
1233         for (i = 0; i < f->fmt->colplanes; i++)
1234                 depth += f->fmt->depth[i];
1235
1236         v4l_bound_align_image(&cr->c.width, min_size, f->o_width,
1237                               ffs(min_size) - 1,
1238                               &cr->c.height, min_size, f->o_height,
1239                               halign, 64/(ALIGN(depth, 8)));
1240
1241         /* adjust left/top if cropping rectangle is out of bounds */
1242         if (cr->c.left + cr->c.width > f->o_width)
1243                 cr->c.left = f->o_width - cr->c.width;
1244         if (cr->c.top + cr->c.height > f->o_height)
1245                 cr->c.top = f->o_height - cr->c.height;
1246
1247         cr->c.left = round_down(cr->c.left, min_size);
1248         cr->c.top  = round_down(cr->c.top, fimc->variant->hor_offs_align);
1249
1250         dbg("l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d",
1251             cr->c.left, cr->c.top, cr->c.width, cr->c.height,
1252             f->f_width, f->f_height);
1253
1254         return 0;
1255 }
1256
1257 static int fimc_m2m_s_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1258 {
1259         struct fimc_ctx *ctx = fh_to_ctx(fh);
1260         struct fimc_dev *fimc = ctx->fimc_dev;
1261         struct fimc_frame *f;
1262         int ret;
1263
1264         ret = fimc_m2m_try_crop(ctx, cr);
1265         if (ret)
1266                 return ret;
1267
1268         f = (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ?
1269                 &ctx->s_frame : &ctx->d_frame;
1270
1271         /* Check to see if scaling ratio is within supported range */
1272         if (fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
1273                 if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1274                         ret = fimc_check_scaler_ratio(ctx, cr->c.width,
1275                                         cr->c.height, ctx->d_frame.width,
1276                                         ctx->d_frame.height, ctx->rotation);
1277                 } else {
1278                         ret = fimc_check_scaler_ratio(ctx, ctx->s_frame.width,
1279                                         ctx->s_frame.height, cr->c.width,
1280                                         cr->c.height, ctx->rotation);
1281                 }
1282                 if (ret) {
1283                         v4l2_err(fimc->m2m.vfd, "Out of scaler range\n");
1284                         return -EINVAL;
1285                 }
1286         }
1287
1288         f->offs_h = cr->c.left;
1289         f->offs_v = cr->c.top;
1290         f->width  = cr->c.width;
1291         f->height = cr->c.height;
1292
1293         fimc_ctx_state_lock_set(FIMC_PARAMS, ctx);
1294
1295         return 0;
1296 }
1297
1298 static const struct v4l2_ioctl_ops fimc_m2m_ioctl_ops = {
1299         .vidioc_querycap                = fimc_m2m_querycap,
1300
1301         .vidioc_enum_fmt_vid_cap_mplane = fimc_m2m_enum_fmt_mplane,
1302         .vidioc_enum_fmt_vid_out_mplane = fimc_m2m_enum_fmt_mplane,
1303
1304         .vidioc_g_fmt_vid_cap_mplane    = fimc_m2m_g_fmt_mplane,
1305         .vidioc_g_fmt_vid_out_mplane    = fimc_m2m_g_fmt_mplane,
1306
1307         .vidioc_try_fmt_vid_cap_mplane  = fimc_m2m_try_fmt_mplane,
1308         .vidioc_try_fmt_vid_out_mplane  = fimc_m2m_try_fmt_mplane,
1309
1310         .vidioc_s_fmt_vid_cap_mplane    = fimc_m2m_s_fmt_mplane,
1311         .vidioc_s_fmt_vid_out_mplane    = fimc_m2m_s_fmt_mplane,
1312
1313         .vidioc_reqbufs                 = fimc_m2m_reqbufs,
1314         .vidioc_querybuf                = fimc_m2m_querybuf,
1315
1316         .vidioc_qbuf                    = fimc_m2m_qbuf,
1317         .vidioc_dqbuf                   = fimc_m2m_dqbuf,
1318
1319         .vidioc_streamon                = fimc_m2m_streamon,
1320         .vidioc_streamoff               = fimc_m2m_streamoff,
1321
1322         .vidioc_g_crop                  = fimc_m2m_g_crop,
1323         .vidioc_s_crop                  = fimc_m2m_s_crop,
1324         .vidioc_cropcap                 = fimc_m2m_cropcap
1325
1326 };
1327
1328 static int queue_init(void *priv, struct vb2_queue *src_vq,
1329                       struct vb2_queue *dst_vq)
1330 {
1331         struct fimc_ctx *ctx = priv;
1332         int ret;
1333
1334         memset(src_vq, 0, sizeof(*src_vq));
1335         src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
1336         src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1337         src_vq->drv_priv = ctx;
1338         src_vq->ops = &fimc_qops;
1339         src_vq->mem_ops = &vb2_dma_contig_memops;
1340         src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1341
1342         ret = vb2_queue_init(src_vq);
1343         if (ret)
1344                 return ret;
1345
1346         memset(dst_vq, 0, sizeof(*dst_vq));
1347         dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1348         dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1349         dst_vq->drv_priv = ctx;
1350         dst_vq->ops = &fimc_qops;
1351         dst_vq->mem_ops = &vb2_dma_contig_memops;
1352         dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1353
1354         return vb2_queue_init(dst_vq);
1355 }
1356
1357 static int fimc_m2m_open(struct file *file)
1358 {
1359         struct fimc_dev *fimc = video_drvdata(file);
1360         struct fimc_ctx *ctx;
1361         int ret;
1362
1363         dbg("pid: %d, state: 0x%lx, refcnt: %d",
1364                 task_pid_nr(current), fimc->state, fimc->vid_cap.refcnt);
1365
1366         /*
1367          * Return if the corresponding video capture node
1368          * is already opened.
1369          */
1370         if (fimc->vid_cap.refcnt > 0)
1371                 return -EBUSY;
1372
1373         ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
1374         if (!ctx)
1375                 return -ENOMEM;
1376         v4l2_fh_init(&ctx->fh, fimc->m2m.vfd);
1377         ret = fimc_ctrls_create(ctx);
1378         if (ret)
1379                 goto error_fh;
1380
1381         /* Use separate control handler per file handle */
1382         ctx->fh.ctrl_handler = &ctx->ctrl_handler;
1383         file->private_data = &ctx->fh;
1384         v4l2_fh_add(&ctx->fh);
1385
1386         ctx->fimc_dev = fimc;
1387         /* Default color format */
1388         ctx->s_frame.fmt = &fimc_formats[0];
1389         ctx->d_frame.fmt = &fimc_formats[0];
1390         /* Setup the device context for memory-to-memory mode */
1391         ctx->state = FIMC_CTX_M2M;
1392         ctx->flags = 0;
1393         ctx->in_path = FIMC_DMA;
1394         ctx->out_path = FIMC_DMA;
1395         spin_lock_init(&ctx->slock);
1396
1397         ctx->m2m_ctx = v4l2_m2m_ctx_init(fimc->m2m.m2m_dev, ctx, queue_init);
1398         if (IS_ERR(ctx->m2m_ctx)) {
1399                 ret = PTR_ERR(ctx->m2m_ctx);
1400                 goto error_c;
1401         }
1402
1403         if (fimc->m2m.refcnt++ == 0)
1404                 set_bit(ST_M2M_RUN, &fimc->state);
1405         return 0;
1406
1407 error_c:
1408         fimc_ctrls_delete(ctx);
1409 error_fh:
1410         v4l2_fh_del(&ctx->fh);
1411         v4l2_fh_exit(&ctx->fh);
1412         kfree(ctx);
1413         return ret;
1414 }
1415
1416 static int fimc_m2m_release(struct file *file)
1417 {
1418         struct fimc_ctx *ctx = fh_to_ctx(file->private_data);
1419         struct fimc_dev *fimc = ctx->fimc_dev;
1420
1421         dbg("pid: %d, state: 0x%lx, refcnt= %d",
1422                 task_pid_nr(current), fimc->state, fimc->m2m.refcnt);
1423
1424         v4l2_m2m_ctx_release(ctx->m2m_ctx);
1425         fimc_ctrls_delete(ctx);
1426         v4l2_fh_del(&ctx->fh);
1427         v4l2_fh_exit(&ctx->fh);
1428
1429         if (--fimc->m2m.refcnt <= 0)
1430                 clear_bit(ST_M2M_RUN, &fimc->state);
1431         kfree(ctx);
1432         return 0;
1433 }
1434
1435 static unsigned int fimc_m2m_poll(struct file *file,
1436                                   struct poll_table_struct *wait)
1437 {
1438         struct fimc_ctx *ctx = fh_to_ctx(file->private_data);
1439
1440         return v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
1441 }
1442
1443
1444 static int fimc_m2m_mmap(struct file *file, struct vm_area_struct *vma)
1445 {
1446         struct fimc_ctx *ctx = fh_to_ctx(file->private_data);
1447
1448         return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
1449 }
1450
1451 static const struct v4l2_file_operations fimc_m2m_fops = {
1452         .owner          = THIS_MODULE,
1453         .open           = fimc_m2m_open,
1454         .release        = fimc_m2m_release,
1455         .poll           = fimc_m2m_poll,
1456         .unlocked_ioctl = video_ioctl2,
1457         .mmap           = fimc_m2m_mmap,
1458 };
1459
1460 static struct v4l2_m2m_ops m2m_ops = {
1461         .device_run     = fimc_dma_run,
1462         .job_abort      = fimc_job_abort,
1463 };
1464
1465 int fimc_register_m2m_device(struct fimc_dev *fimc,
1466                              struct v4l2_device *v4l2_dev)
1467 {
1468         struct video_device *vfd;
1469         struct platform_device *pdev;
1470         int ret = 0;
1471
1472         if (!fimc)
1473                 return -ENODEV;
1474
1475         pdev = fimc->pdev;
1476         fimc->v4l2_dev = v4l2_dev;
1477
1478         vfd = video_device_alloc();
1479         if (!vfd) {
1480                 v4l2_err(v4l2_dev, "Failed to allocate video device\n");
1481                 return -ENOMEM;
1482         }
1483
1484         vfd->fops       = &fimc_m2m_fops;
1485         vfd->ioctl_ops  = &fimc_m2m_ioctl_ops;
1486         vfd->v4l2_dev   = v4l2_dev;
1487         vfd->minor      = -1;
1488         vfd->release    = video_device_release;
1489         vfd->lock       = &fimc->lock;
1490
1491         snprintf(vfd->name, sizeof(vfd->name), "%s.m2m", dev_name(&pdev->dev));
1492         video_set_drvdata(vfd, fimc);
1493
1494         fimc->m2m.vfd = vfd;
1495         fimc->m2m.m2m_dev = v4l2_m2m_init(&m2m_ops);
1496         if (IS_ERR(fimc->m2m.m2m_dev)) {
1497                 v4l2_err(v4l2_dev, "failed to initialize v4l2-m2m device\n");
1498                 ret = PTR_ERR(fimc->m2m.m2m_dev);
1499                 goto err_init;
1500         }
1501
1502         ret = media_entity_init(&vfd->entity, 0, NULL, 0);
1503         if (!ret)
1504                 return 0;
1505
1506         v4l2_m2m_release(fimc->m2m.m2m_dev);
1507 err_init:
1508         video_device_release(fimc->m2m.vfd);
1509         return ret;
1510 }
1511
1512 void fimc_unregister_m2m_device(struct fimc_dev *fimc)
1513 {
1514         if (!fimc)
1515                 return;
1516
1517         if (fimc->m2m.m2m_dev)
1518                 v4l2_m2m_release(fimc->m2m.m2m_dev);
1519         if (fimc->m2m.vfd) {
1520                 media_entity_cleanup(&fimc->m2m.vfd->entity);
1521                 /* Can also be called if video device wasn't registered */
1522                 video_unregister_device(fimc->m2m.vfd);
1523         }
1524 }
1525
1526 static void fimc_clk_put(struct fimc_dev *fimc)
1527 {
1528         int i;
1529         for (i = 0; i < fimc->num_clocks; i++) {
1530                 if (fimc->clock[i])
1531                         clk_put(fimc->clock[i]);
1532         }
1533 }
1534
1535 static int fimc_clk_get(struct fimc_dev *fimc)
1536 {
1537         int i;
1538         for (i = 0; i < fimc->num_clocks; i++) {
1539                 fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clocks[i]);
1540                 if (!IS_ERR_OR_NULL(fimc->clock[i]))
1541                         continue;
1542                 dev_err(&fimc->pdev->dev, "failed to get fimc clock: %s\n",
1543                         fimc_clocks[i]);
1544                 return -ENXIO;
1545         }
1546
1547         return 0;
1548 }
1549
1550 static int fimc_m2m_suspend(struct fimc_dev *fimc)
1551 {
1552         unsigned long flags;
1553         int timeout;
1554
1555         spin_lock_irqsave(&fimc->slock, flags);
1556         if (!fimc_m2m_pending(fimc)) {
1557                 spin_unlock_irqrestore(&fimc->slock, flags);
1558                 return 0;
1559         }
1560         clear_bit(ST_M2M_SUSPENDED, &fimc->state);
1561         set_bit(ST_M2M_SUSPENDING, &fimc->state);
1562         spin_unlock_irqrestore(&fimc->slock, flags);
1563
1564         timeout = wait_event_timeout(fimc->irq_queue,
1565                              test_bit(ST_M2M_SUSPENDED, &fimc->state),
1566                              FIMC_SHUTDOWN_TIMEOUT);
1567
1568         clear_bit(ST_M2M_SUSPENDING, &fimc->state);
1569         return timeout == 0 ? -EAGAIN : 0;
1570 }
1571
1572 static int fimc_m2m_resume(struct fimc_dev *fimc)
1573 {
1574         unsigned long flags;
1575
1576         spin_lock_irqsave(&fimc->slock, flags);
1577         /* Clear for full H/W setup in first run after resume */
1578         fimc->m2m.ctx = NULL;
1579         spin_unlock_irqrestore(&fimc->slock, flags);
1580
1581         if (test_and_clear_bit(ST_M2M_SUSPENDED, &fimc->state))
1582                 fimc_m2m_job_finish(fimc->m2m.ctx,
1583                                     VB2_BUF_STATE_ERROR);
1584         return 0;
1585 }
1586
1587 static int fimc_probe(struct platform_device *pdev)
1588 {
1589         struct fimc_dev *fimc;
1590         struct resource *res;
1591         struct samsung_fimc_driverdata *drv_data;
1592         struct s5p_platform_fimc *pdata;
1593         int ret = 0;
1594
1595         dev_dbg(&pdev->dev, "%s():\n", __func__);
1596
1597         drv_data = (struct samsung_fimc_driverdata *)
1598                 platform_get_device_id(pdev)->driver_data;
1599
1600         if (pdev->id >= drv_data->num_entities) {
1601                 dev_err(&pdev->dev, "Invalid platform device id: %d\n",
1602                         pdev->id);
1603                 return -EINVAL;
1604         }
1605
1606         fimc = kzalloc(sizeof(struct fimc_dev), GFP_KERNEL);
1607         if (!fimc)
1608                 return -ENOMEM;
1609
1610         fimc->id = pdev->id;
1611
1612         fimc->variant = drv_data->variant[fimc->id];
1613         fimc->pdev = pdev;
1614         pdata = pdev->dev.platform_data;
1615         fimc->pdata = pdata;
1616
1617
1618         init_waitqueue_head(&fimc->irq_queue);
1619         spin_lock_init(&fimc->slock);
1620         mutex_init(&fimc->lock);
1621
1622         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1623         if (!res) {
1624                 dev_err(&pdev->dev, "failed to find the registers\n");
1625                 ret = -ENOENT;
1626                 goto err_info;
1627         }
1628
1629         fimc->regs_res = request_mem_region(res->start, resource_size(res),
1630                         dev_name(&pdev->dev));
1631         if (!fimc->regs_res) {
1632                 dev_err(&pdev->dev, "failed to obtain register region\n");
1633                 ret = -ENOENT;
1634                 goto err_info;
1635         }
1636
1637         fimc->regs = ioremap(res->start, resource_size(res));
1638         if (!fimc->regs) {
1639                 dev_err(&pdev->dev, "failed to map registers\n");
1640                 ret = -ENXIO;
1641                 goto err_req_region;
1642         }
1643
1644         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1645         if (!res) {
1646                 dev_err(&pdev->dev, "failed to get IRQ resource\n");
1647                 ret = -ENXIO;
1648                 goto err_regs_unmap;
1649         }
1650         fimc->irq = res->start;
1651
1652         fimc->num_clocks = MAX_FIMC_CLOCKS;
1653         ret = fimc_clk_get(fimc);
1654         if (ret)
1655                 goto err_regs_unmap;
1656         clk_set_rate(fimc->clock[CLK_BUS], drv_data->lclk_frequency);
1657         clk_enable(fimc->clock[CLK_BUS]);
1658
1659         platform_set_drvdata(pdev, fimc);
1660
1661         ret = request_irq(fimc->irq, fimc_irq_handler, 0, pdev->name, fimc);
1662         if (ret) {
1663                 dev_err(&pdev->dev, "failed to install irq (%d)\n", ret);
1664                 goto err_clk;
1665         }
1666
1667         pm_runtime_enable(&pdev->dev);
1668         ret = pm_runtime_get_sync(&pdev->dev);
1669         if (ret < 0)
1670                 goto err_irq;
1671         /* Initialize contiguous memory allocator */
1672         fimc->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1673         if (IS_ERR(fimc->alloc_ctx)) {
1674                 ret = PTR_ERR(fimc->alloc_ctx);
1675                 goto err_pm;
1676         }
1677
1678         dev_dbg(&pdev->dev, "FIMC.%d registered successfully\n", fimc->id);
1679
1680         pm_runtime_put(&pdev->dev);
1681         return 0;
1682
1683 err_pm:
1684         pm_runtime_put(&pdev->dev);
1685 err_irq:
1686         free_irq(fimc->irq, fimc);
1687 err_clk:
1688         fimc_clk_put(fimc);
1689 err_regs_unmap:
1690         iounmap(fimc->regs);
1691 err_req_region:
1692         release_resource(fimc->regs_res);
1693         kfree(fimc->regs_res);
1694 err_info:
1695         kfree(fimc);
1696         return ret;
1697 }
1698
1699 static int fimc_runtime_resume(struct device *dev)
1700 {
1701         struct fimc_dev *fimc = dev_get_drvdata(dev);
1702
1703         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1704
1705         /* Enable clocks and perform basic initalization */
1706         clk_enable(fimc->clock[CLK_GATE]);
1707         fimc_hw_reset(fimc);
1708
1709         /* Resume the capture or mem-to-mem device */
1710         if (fimc_capture_busy(fimc))
1711                 return fimc_capture_resume(fimc);
1712         else if (fimc_m2m_pending(fimc))
1713                 return fimc_m2m_resume(fimc);
1714         return 0;
1715 }
1716
1717 static int fimc_runtime_suspend(struct device *dev)
1718 {
1719         struct fimc_dev *fimc = dev_get_drvdata(dev);
1720         int ret = 0;
1721
1722         if (fimc_capture_busy(fimc))
1723                 ret = fimc_capture_suspend(fimc);
1724         else
1725                 ret = fimc_m2m_suspend(fimc);
1726         if (!ret)
1727                 clk_disable(fimc->clock[CLK_GATE]);
1728
1729         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1730         return ret;
1731 }
1732
1733 #ifdef CONFIG_PM_SLEEP
1734 static int fimc_resume(struct device *dev)
1735 {
1736         struct fimc_dev *fimc = dev_get_drvdata(dev);
1737         unsigned long flags;
1738
1739         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1740
1741         /* Do not resume if the device was idle before system suspend */
1742         spin_lock_irqsave(&fimc->slock, flags);
1743         if (!test_and_clear_bit(ST_LPM, &fimc->state) ||
1744             (!fimc_m2m_active(fimc) && !fimc_capture_busy(fimc))) {
1745                 spin_unlock_irqrestore(&fimc->slock, flags);
1746                 return 0;
1747         }
1748         fimc_hw_reset(fimc);
1749         spin_unlock_irqrestore(&fimc->slock, flags);
1750
1751         if (fimc_capture_busy(fimc))
1752                 return fimc_capture_resume(fimc);
1753
1754         return fimc_m2m_resume(fimc);
1755 }
1756
1757 static int fimc_suspend(struct device *dev)
1758 {
1759         struct fimc_dev *fimc = dev_get_drvdata(dev);
1760
1761         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1762
1763         if (test_and_set_bit(ST_LPM, &fimc->state))
1764                 return 0;
1765         if (fimc_capture_busy(fimc))
1766                 return fimc_capture_suspend(fimc);
1767
1768         return fimc_m2m_suspend(fimc);
1769 }
1770 #endif /* CONFIG_PM_SLEEP */
1771
1772 static int __devexit fimc_remove(struct platform_device *pdev)
1773 {
1774         struct fimc_dev *fimc = platform_get_drvdata(pdev);
1775
1776         pm_runtime_disable(&pdev->dev);
1777         pm_runtime_set_suspended(&pdev->dev);
1778
1779         vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
1780
1781         clk_disable(fimc->clock[CLK_BUS]);
1782         fimc_clk_put(fimc);
1783         free_irq(fimc->irq, fimc);
1784         iounmap(fimc->regs);
1785         release_resource(fimc->regs_res);
1786         kfree(fimc->regs_res);
1787         kfree(fimc);
1788
1789         dev_info(&pdev->dev, "driver unloaded\n");
1790         return 0;
1791 }
1792
1793 /* Image pixel limits, similar across several FIMC HW revisions. */
1794 static struct fimc_pix_limit s5p_pix_limit[4] = {
1795         [0] = {
1796                 .scaler_en_w    = 3264,
1797                 .scaler_dis_w   = 8192,
1798                 .in_rot_en_h    = 1920,
1799                 .in_rot_dis_w   = 8192,
1800                 .out_rot_en_w   = 1920,
1801                 .out_rot_dis_w  = 4224,
1802         },
1803         [1] = {
1804                 .scaler_en_w    = 4224,
1805                 .scaler_dis_w   = 8192,
1806                 .in_rot_en_h    = 1920,
1807                 .in_rot_dis_w   = 8192,
1808                 .out_rot_en_w   = 1920,
1809                 .out_rot_dis_w  = 4224,
1810         },
1811         [2] = {
1812                 .scaler_en_w    = 1920,
1813                 .scaler_dis_w   = 8192,
1814                 .in_rot_en_h    = 1280,
1815                 .in_rot_dis_w   = 8192,
1816                 .out_rot_en_w   = 1280,
1817                 .out_rot_dis_w  = 1920,
1818         },
1819         [3] = {
1820                 .scaler_en_w    = 1920,
1821                 .scaler_dis_w   = 8192,
1822                 .in_rot_en_h    = 1366,
1823                 .in_rot_dis_w   = 8192,
1824                 .out_rot_en_w   = 1366,
1825                 .out_rot_dis_w  = 1920,
1826         },
1827 };
1828
1829 static struct samsung_fimc_variant fimc0_variant_s5p = {
1830         .has_inp_rot     = 1,
1831         .has_out_rot     = 1,
1832         .has_cam_if      = 1,
1833         .min_inp_pixsize = 16,
1834         .min_out_pixsize = 16,
1835         .hor_offs_align  = 8,
1836         .min_vsize_align = 16,
1837         .out_buf_count   = 4,
1838         .pix_limit       = &s5p_pix_limit[0],
1839 };
1840
1841 static struct samsung_fimc_variant fimc2_variant_s5p = {
1842         .has_cam_if      = 1,
1843         .min_inp_pixsize = 16,
1844         .min_out_pixsize = 16,
1845         .hor_offs_align  = 8,
1846         .min_vsize_align = 16,
1847         .out_buf_count   = 4,
1848         .pix_limit = &s5p_pix_limit[1],
1849 };
1850
1851 static struct samsung_fimc_variant fimc0_variant_s5pv210 = {
1852         .pix_hoff        = 1,
1853         .has_inp_rot     = 1,
1854         .has_out_rot     = 1,
1855         .has_cam_if      = 1,
1856         .min_inp_pixsize = 16,
1857         .min_out_pixsize = 16,
1858         .hor_offs_align  = 8,
1859         .min_vsize_align = 16,
1860         .out_buf_count   = 4,
1861         .pix_limit       = &s5p_pix_limit[1],
1862 };
1863
1864 static struct samsung_fimc_variant fimc1_variant_s5pv210 = {
1865         .pix_hoff        = 1,
1866         .has_inp_rot     = 1,
1867         .has_out_rot     = 1,
1868         .has_cam_if      = 1,
1869         .has_mainscaler_ext = 1,
1870         .min_inp_pixsize = 16,
1871         .min_out_pixsize = 16,
1872         .hor_offs_align  = 1,
1873         .min_vsize_align = 1,
1874         .out_buf_count   = 4,
1875         .pix_limit       = &s5p_pix_limit[2],
1876 };
1877
1878 static struct samsung_fimc_variant fimc2_variant_s5pv210 = {
1879         .has_cam_if      = 1,
1880         .pix_hoff        = 1,
1881         .min_inp_pixsize = 16,
1882         .min_out_pixsize = 16,
1883         .hor_offs_align  = 8,
1884         .min_vsize_align = 16,
1885         .out_buf_count   = 4,
1886         .pix_limit       = &s5p_pix_limit[2],
1887 };
1888
1889 static struct samsung_fimc_variant fimc0_variant_exynos4 = {
1890         .pix_hoff        = 1,
1891         .has_inp_rot     = 1,
1892         .has_out_rot     = 1,
1893         .has_cam_if      = 1,
1894         .has_cistatus2   = 1,
1895         .has_mainscaler_ext = 1,
1896         .min_inp_pixsize = 16,
1897         .min_out_pixsize = 16,
1898         .hor_offs_align  = 2,
1899         .min_vsize_align = 1,
1900         .out_buf_count   = 32,
1901         .pix_limit       = &s5p_pix_limit[1],
1902 };
1903
1904 static struct samsung_fimc_variant fimc3_variant_exynos4 = {
1905         .pix_hoff        = 1,
1906         .has_cam_if      = 1,
1907         .has_cistatus2   = 1,
1908         .has_mainscaler_ext = 1,
1909         .min_inp_pixsize = 16,
1910         .min_out_pixsize = 16,
1911         .hor_offs_align  = 2,
1912         .min_vsize_align = 1,
1913         .out_buf_count   = 32,
1914         .pix_limit       = &s5p_pix_limit[3],
1915 };
1916
1917 /* S5PC100 */
1918 static struct samsung_fimc_driverdata fimc_drvdata_s5p = {
1919         .variant = {
1920                 [0] = &fimc0_variant_s5p,
1921                 [1] = &fimc0_variant_s5p,
1922                 [2] = &fimc2_variant_s5p,
1923         },
1924         .num_entities = 3,
1925         .lclk_frequency = 133000000UL,
1926 };
1927
1928 /* S5PV210, S5PC110 */
1929 static struct samsung_fimc_driverdata fimc_drvdata_s5pv210 = {
1930         .variant = {
1931                 [0] = &fimc0_variant_s5pv210,
1932                 [1] = &fimc1_variant_s5pv210,
1933                 [2] = &fimc2_variant_s5pv210,
1934         },
1935         .num_entities = 3,
1936         .lclk_frequency = 166000000UL,
1937 };
1938
1939 /* S5PV310, S5PC210 */
1940 static struct samsung_fimc_driverdata fimc_drvdata_exynos4 = {
1941         .variant = {
1942                 [0] = &fimc0_variant_exynos4,
1943                 [1] = &fimc0_variant_exynos4,
1944                 [2] = &fimc0_variant_exynos4,
1945                 [3] = &fimc3_variant_exynos4,
1946         },
1947         .num_entities = 4,
1948         .lclk_frequency = 166000000UL,
1949 };
1950
1951 static struct platform_device_id fimc_driver_ids[] = {
1952         {
1953                 .name           = "s5p-fimc",
1954                 .driver_data    = (unsigned long)&fimc_drvdata_s5p,
1955         }, {
1956                 .name           = "s5pv210-fimc",
1957                 .driver_data    = (unsigned long)&fimc_drvdata_s5pv210,
1958         }, {
1959                 .name           = "exynos4-fimc",
1960                 .driver_data    = (unsigned long)&fimc_drvdata_exynos4,
1961         },
1962         {},
1963 };
1964 MODULE_DEVICE_TABLE(platform, fimc_driver_ids);
1965
1966 static const struct dev_pm_ops fimc_pm_ops = {
1967         SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume)
1968         SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL)
1969 };
1970
1971 static struct platform_driver fimc_driver = {
1972         .probe          = fimc_probe,
1973         .remove         = __devexit_p(fimc_remove),
1974         .id_table       = fimc_driver_ids,
1975         .driver = {
1976                 .name   = FIMC_MODULE_NAME,
1977                 .owner  = THIS_MODULE,
1978                 .pm     = &fimc_pm_ops,
1979         }
1980 };
1981
1982 int __init fimc_register_driver(void)
1983 {
1984         return platform_driver_probe(&fimc_driver, fimc_probe);
1985 }
1986
1987 void __exit fimc_unregister_driver(void)
1988 {
1989         platform_driver_unregister(&fimc_driver);
1990 }