PCI: Cleanup the includes of <linux/pci.h>
[linux-2.6.git] / drivers / media / video / cx88 / cx88-tvaudio.c
1 /*
2
3     cx88x-audio.c - Conexant CX23880/23881 audio downstream driver driver
4
5      (c) 2001 Michael Eskin, Tom Zakrajsek [Windows version]
6      (c) 2002 Yurij Sysoev <yurij@naturesoft.net>
7      (c) 2003 Gerd Knorr <kraxel@bytesex.org>
8
9     -----------------------------------------------------------------------
10
11     Lot of voodoo here.  Even the data sheet doesn't help to
12     understand what is going on here, the documentation for the audio
13     part of the cx2388x chip is *very* bad.
14
15     Some of this comes from party done linux driver sources I got from
16     [undocumented].
17
18     Some comes from the dscaler sources, one of the dscaler driver guy works
19     for Conexant ...
20
21     -----------------------------------------------------------------------
22
23     This program is free software; you can redistribute it and/or modify
24     it under the terms of the GNU General Public License as published by
25     the Free Software Foundation; either version 2 of the License, or
26     (at your option) any later version.
27
28     This program is distributed in the hope that it will be useful,
29     but WITHOUT ANY WARRANTY; without even the implied warranty of
30     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
31     GNU General Public License for more details.
32
33     You should have received a copy of the GNU General Public License
34     along with this program; if not, write to the Free Software
35     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
36 */
37
38 #include <linux/module.h>
39 #include <linux/moduleparam.h>
40 #include <linux/errno.h>
41 #include <linux/freezer.h>
42 #include <linux/kernel.h>
43 #include <linux/slab.h>
44 #include <linux/mm.h>
45 #include <linux/poll.h>
46 #include <linux/signal.h>
47 #include <linux/ioport.h>
48 #include <linux/types.h>
49 #include <linux/interrupt.h>
50 #include <linux/vmalloc.h>
51 #include <linux/init.h>
52 #include <linux/smp_lock.h>
53 #include <linux/delay.h>
54 #include <linux/kthread.h>
55
56 #include "cx88.h"
57
58 static unsigned int audio_debug = 0;
59 module_param(audio_debug, int, 0644);
60 MODULE_PARM_DESC(audio_debug, "enable debug messages [audio]");
61
62 static unsigned int always_analog = 0;
63 module_param(always_analog,int,0644);
64 MODULE_PARM_DESC(always_analog,"force analog audio out");
65
66
67 #define dprintk(fmt, arg...)    if (audio_debug) \
68         printk(KERN_DEBUG "%s/0: " fmt, core->name , ## arg)
69
70 /* ----------------------------------------------------------- */
71
72 static char *aud_ctl_names[64] = {
73         [EN_BTSC_FORCE_MONO] = "BTSC_FORCE_MONO",
74         [EN_BTSC_FORCE_STEREO] = "BTSC_FORCE_STEREO",
75         [EN_BTSC_FORCE_SAP] = "BTSC_FORCE_SAP",
76         [EN_BTSC_AUTO_STEREO] = "BTSC_AUTO_STEREO",
77         [EN_BTSC_AUTO_SAP] = "BTSC_AUTO_SAP",
78         [EN_A2_FORCE_MONO1] = "A2_FORCE_MONO1",
79         [EN_A2_FORCE_MONO2] = "A2_FORCE_MONO2",
80         [EN_A2_FORCE_STEREO] = "A2_FORCE_STEREO",
81         [EN_A2_AUTO_MONO2] = "A2_AUTO_MONO2",
82         [EN_A2_AUTO_STEREO] = "A2_AUTO_STEREO",
83         [EN_EIAJ_FORCE_MONO1] = "EIAJ_FORCE_MONO1",
84         [EN_EIAJ_FORCE_MONO2] = "EIAJ_FORCE_MONO2",
85         [EN_EIAJ_FORCE_STEREO] = "EIAJ_FORCE_STEREO",
86         [EN_EIAJ_AUTO_MONO2] = "EIAJ_AUTO_MONO2",
87         [EN_EIAJ_AUTO_STEREO] = "EIAJ_AUTO_STEREO",
88         [EN_NICAM_FORCE_MONO1] = "NICAM_FORCE_MONO1",
89         [EN_NICAM_FORCE_MONO2] = "NICAM_FORCE_MONO2",
90         [EN_NICAM_FORCE_STEREO] = "NICAM_FORCE_STEREO",
91         [EN_NICAM_AUTO_MONO2] = "NICAM_AUTO_MONO2",
92         [EN_NICAM_AUTO_STEREO] = "NICAM_AUTO_STEREO",
93         [EN_FMRADIO_FORCE_MONO] = "FMRADIO_FORCE_MONO",
94         [EN_FMRADIO_FORCE_STEREO] = "FMRADIO_FORCE_STEREO",
95         [EN_FMRADIO_AUTO_STEREO] = "FMRADIO_AUTO_STEREO",
96 };
97
98 struct rlist {
99         u32 reg;
100         u32 val;
101 };
102
103 static void set_audio_registers(struct cx88_core *core, const struct rlist *l)
104 {
105         int i;
106
107         for (i = 0; l[i].reg; i++) {
108                 switch (l[i].reg) {
109                 case AUD_PDF_DDS_CNST_BYTE2:
110                 case AUD_PDF_DDS_CNST_BYTE1:
111                 case AUD_PDF_DDS_CNST_BYTE0:
112                 case AUD_QAM_MODE:
113                 case AUD_PHACC_FREQ_8MSB:
114                 case AUD_PHACC_FREQ_8LSB:
115                         cx_writeb(l[i].reg, l[i].val);
116                         break;
117                 default:
118                         cx_write(l[i].reg, l[i].val);
119                         break;
120                 }
121         }
122 }
123
124 static void set_audio_start(struct cx88_core *core, u32 mode)
125 {
126         /* mute */
127         cx_write(AUD_VOL_CTL, (1 << 6));
128
129         /* start programming */
130         cx_write(AUD_INIT, mode);
131         cx_write(AUD_INIT_LD, 0x0001);
132         cx_write(AUD_SOFT_RESET, 0x0001);
133 }
134
135 static void set_audio_finish(struct cx88_core *core, u32 ctl)
136 {
137         u32 volume;
138
139         /* restart dma; This avoids buzz in NICAM and is good in others  */
140         cx88_stop_audio_dma(core);
141         cx_write(AUD_RATE_THRES_DMD, 0x000000C0);
142         cx88_start_audio_dma(core);
143
144         if (cx88_boards[core->board].mpeg & CX88_MPEG_BLACKBIRD) {
145                 cx_write(AUD_I2SINPUTCNTL, 4);
146                 cx_write(AUD_BAUDRATE, 1);
147                 /* 'pass-thru mode': this enables the i2s output to the mpeg encoder */
148                 cx_set(AUD_CTL, EN_I2SOUT_ENABLE);
149                 cx_write(AUD_I2SOUTPUTCNTL, 1);
150                 cx_write(AUD_I2SCNTL, 0);
151                 /* cx_write(AUD_APB_IN_RATE_ADJ, 0); */
152         }
153         if ((always_analog) || (!(cx88_boards[core->board].mpeg & CX88_MPEG_BLACKBIRD))) {
154                 ctl |= EN_DAC_ENABLE;
155                 cx_write(AUD_CTL, ctl);
156         }
157
158         /* finish programming */
159         cx_write(AUD_SOFT_RESET, 0x0000);
160
161         /* unmute */
162         volume = cx_sread(SHADOW_AUD_VOL_CTL);
163         cx_swrite(SHADOW_AUD_VOL_CTL, AUD_VOL_CTL, volume);
164 }
165
166 /* ----------------------------------------------------------- */
167
168 static void set_audio_standard_BTSC(struct cx88_core *core, unsigned int sap,
169                                     u32 mode)
170 {
171         static const struct rlist btsc[] = {
172                 {AUD_AFE_12DB_EN, 0x00000001},
173                 {AUD_OUT1_SEL, 0x00000013},
174                 {AUD_OUT1_SHIFT, 0x00000000},
175                 {AUD_POLY0_DDS_CONSTANT, 0x0012010c},
176                 {AUD_DMD_RA_DDS, 0x00c3e7aa},
177                 {AUD_DBX_IN_GAIN, 0x00004734},
178                 {AUD_DBX_WBE_GAIN, 0x00004640},
179                 {AUD_DBX_SE_GAIN, 0x00008d31},
180                 {AUD_DCOC_0_SRC, 0x0000001a},
181                 {AUD_IIR1_4_SEL, 0x00000021},
182                 {AUD_DCOC_PASS_IN, 0x00000003},
183                 {AUD_DCOC_0_SHIFT_IN0, 0x0000000a},
184                 {AUD_DCOC_0_SHIFT_IN1, 0x00000008},
185                 {AUD_DCOC_1_SHIFT_IN0, 0x0000000a},
186                 {AUD_DCOC_1_SHIFT_IN1, 0x00000008},
187                 {AUD_DN0_FREQ, 0x0000283b},
188                 {AUD_DN2_SRC_SEL, 0x00000008},
189                 {AUD_DN2_FREQ, 0x00003000},
190                 {AUD_DN2_AFC, 0x00000002},
191                 {AUD_DN2_SHFT, 0x00000000},
192                 {AUD_IIR2_2_SEL, 0x00000020},
193                 {AUD_IIR2_2_SHIFT, 0x00000000},
194                 {AUD_IIR2_3_SEL, 0x0000001f},
195                 {AUD_IIR2_3_SHIFT, 0x00000000},
196                 {AUD_CRDC1_SRC_SEL, 0x000003ce},
197                 {AUD_CRDC1_SHIFT, 0x00000000},
198                 {AUD_CORDIC_SHIFT_1, 0x00000007},
199                 {AUD_DCOC_1_SRC, 0x0000001b},
200                 {AUD_DCOC1_SHIFT, 0x00000000},
201                 {AUD_RDSI_SEL, 0x00000008},
202                 {AUD_RDSQ_SEL, 0x00000008},
203                 {AUD_RDSI_SHIFT, 0x00000000},
204                 {AUD_RDSQ_SHIFT, 0x00000000},
205                 {AUD_POLYPH80SCALEFAC, 0x00000003},
206                 { /* end of list */ },
207         };
208         static const struct rlist btsc_sap[] = {
209                 {AUD_AFE_12DB_EN, 0x00000001},
210                 {AUD_DBX_IN_GAIN, 0x00007200},
211                 {AUD_DBX_WBE_GAIN, 0x00006200},
212                 {AUD_DBX_SE_GAIN, 0x00006200},
213                 {AUD_IIR1_1_SEL, 0x00000000},
214                 {AUD_IIR1_3_SEL, 0x00000001},
215                 {AUD_DN1_SRC_SEL, 0x00000007},
216                 {AUD_IIR1_4_SHIFT, 0x00000006},
217                 {AUD_IIR2_1_SHIFT, 0x00000000},
218                 {AUD_IIR2_2_SHIFT, 0x00000000},
219                 {AUD_IIR3_0_SHIFT, 0x00000000},
220                 {AUD_IIR3_1_SHIFT, 0x00000000},
221                 {AUD_IIR3_0_SEL, 0x0000000d},
222                 {AUD_IIR3_1_SEL, 0x0000000e},
223                 {AUD_DEEMPH1_SRC_SEL, 0x00000014},
224                 {AUD_DEEMPH1_SHIFT, 0x00000000},
225                 {AUD_DEEMPH1_G0, 0x00004000},
226                 {AUD_DEEMPH1_A0, 0x00000000},
227                 {AUD_DEEMPH1_B0, 0x00000000},
228                 {AUD_DEEMPH1_A1, 0x00000000},
229                 {AUD_DEEMPH1_B1, 0x00000000},
230                 {AUD_OUT0_SEL, 0x0000003f},
231                 {AUD_OUT1_SEL, 0x0000003f},
232                 {AUD_DN1_AFC, 0x00000002},
233                 {AUD_DCOC_0_SHIFT_IN0, 0x0000000a},
234                 {AUD_DCOC_0_SHIFT_IN1, 0x00000008},
235                 {AUD_DCOC_1_SHIFT_IN0, 0x0000000a},
236                 {AUD_DCOC_1_SHIFT_IN1, 0x00000008},
237                 {AUD_IIR1_0_SEL, 0x0000001d},
238                 {AUD_IIR1_2_SEL, 0x0000001e},
239                 {AUD_IIR2_1_SEL, 0x00000002},
240                 {AUD_IIR2_2_SEL, 0x00000004},
241                 {AUD_IIR3_2_SEL, 0x0000000f},
242                 {AUD_DCOC2_SHIFT, 0x00000001},
243                 {AUD_IIR3_2_SHIFT, 0x00000001},
244                 {AUD_DEEMPH0_SRC_SEL, 0x00000014},
245                 {AUD_CORDIC_SHIFT_1, 0x00000006},
246                 {AUD_POLY0_DDS_CONSTANT, 0x000e4db2},
247                 {AUD_DMD_RA_DDS, 0x00f696e6},
248                 {AUD_IIR2_3_SEL, 0x00000025},
249                 {AUD_IIR1_4_SEL, 0x00000021},
250                 {AUD_DN1_FREQ, 0x0000c965},
251                 {AUD_DCOC_PASS_IN, 0x00000003},
252                 {AUD_DCOC_0_SRC, 0x0000001a},
253                 {AUD_DCOC_1_SRC, 0x0000001b},
254                 {AUD_DCOC1_SHIFT, 0x00000000},
255                 {AUD_RDSI_SEL, 0x00000009},
256                 {AUD_RDSQ_SEL, 0x00000009},
257                 {AUD_RDSI_SHIFT, 0x00000000},
258                 {AUD_RDSQ_SHIFT, 0x00000000},
259                 {AUD_POLYPH80SCALEFAC, 0x00000003},
260                 { /* end of list */ },
261         };
262
263         mode |= EN_FMRADIO_EN_RDS;
264
265         if (sap) {
266                 dprintk("%s SAP (status: unknown)\n", __FUNCTION__);
267                 set_audio_start(core, SEL_SAP);
268                 set_audio_registers(core, btsc_sap);
269                 set_audio_finish(core, mode);
270         } else {
271                 dprintk("%s (status: known-good)\n", __FUNCTION__);
272                 set_audio_start(core, SEL_BTSC);
273                 set_audio_registers(core, btsc);
274                 set_audio_finish(core, mode);
275         }
276 }
277
278 static void set_audio_standard_NICAM(struct cx88_core *core, u32 mode)
279 {
280         static const struct rlist nicam_l[] = {
281                 {AUD_AFE_12DB_EN, 0x00000001},
282                 {AUD_RATE_ADJ1, 0x00000060},
283                 {AUD_RATE_ADJ2, 0x000000F9},
284                 {AUD_RATE_ADJ3, 0x000001CC},
285                 {AUD_RATE_ADJ4, 0x000002B3},
286                 {AUD_RATE_ADJ5, 0x00000726},
287                 {AUD_DEEMPHDENOM1_R, 0x0000F3D0},
288                 {AUD_DEEMPHDENOM2_R, 0x00000000},
289                 {AUD_ERRLOGPERIOD_R, 0x00000064},
290                 {AUD_ERRINTRPTTHSHLD1_R, 0x00000FFF},
291                 {AUD_ERRINTRPTTHSHLD2_R, 0x0000001F},
292                 {AUD_ERRINTRPTTHSHLD3_R, 0x0000000F},
293                 {AUD_POLYPH80SCALEFAC, 0x00000003},
294                 {AUD_DMD_RA_DDS, 0x00C00000},
295                 {AUD_PLL_INT, 0x0000001E},
296                 {AUD_PLL_DDS, 0x00000000},
297                 {AUD_PLL_FRAC, 0x0000E542},
298                 {AUD_START_TIMER, 0x00000000},
299                 {AUD_DEEMPHNUMER1_R, 0x000353DE},
300                 {AUD_DEEMPHNUMER2_R, 0x000001B1},
301                 {AUD_PDF_DDS_CNST_BYTE2, 0x06},
302                 {AUD_PDF_DDS_CNST_BYTE1, 0x82},
303                 {AUD_PDF_DDS_CNST_BYTE0, 0x12},
304                 {AUD_QAM_MODE, 0x05},
305                 {AUD_PHACC_FREQ_8MSB, 0x34},
306                 {AUD_PHACC_FREQ_8LSB, 0x4C},
307                 {AUD_DEEMPHGAIN_R, 0x00006680},
308                 {AUD_RATE_THRES_DMD, 0x000000C0},
309                 { /* end of list */ },
310         };
311
312         static const struct rlist nicam_bgdki_common[] = {
313                 {AUD_AFE_12DB_EN, 0x00000001},
314                 {AUD_RATE_ADJ1, 0x00000010},
315                 {AUD_RATE_ADJ2, 0x00000040},
316                 {AUD_RATE_ADJ3, 0x00000100},
317                 {AUD_RATE_ADJ4, 0x00000400},
318                 {AUD_RATE_ADJ5, 0x00001000},
319                 {AUD_ERRLOGPERIOD_R, 0x00000fff},
320                 {AUD_ERRINTRPTTHSHLD1_R, 0x000003ff},
321                 {AUD_ERRINTRPTTHSHLD2_R, 0x000000ff},
322                 {AUD_ERRINTRPTTHSHLD3_R, 0x0000003f},
323                 {AUD_POLYPH80SCALEFAC, 0x00000003},
324                 {AUD_DEEMPHGAIN_R, 0x000023c2},
325                 {AUD_DEEMPHNUMER1_R, 0x0002a7bc},
326                 {AUD_DEEMPHNUMER2_R, 0x0003023e},
327                 {AUD_DEEMPHDENOM1_R, 0x0000f3d0},
328                 {AUD_DEEMPHDENOM2_R, 0x00000000},
329                 {AUD_PDF_DDS_CNST_BYTE2, 0x06},
330                 {AUD_PDF_DDS_CNST_BYTE1, 0x82},
331                 {AUD_QAM_MODE, 0x05},
332                 { /* end of list */ },
333         };
334
335         static const struct rlist nicam_i[] = {
336                 {AUD_PDF_DDS_CNST_BYTE0, 0x12},
337                 {AUD_PHACC_FREQ_8MSB, 0x3a},
338                 {AUD_PHACC_FREQ_8LSB, 0x93},
339                 { /* end of list */ },
340         };
341
342         static const struct rlist nicam_default[] = {
343                 {AUD_PDF_DDS_CNST_BYTE0, 0x16},
344                 {AUD_PHACC_FREQ_8MSB, 0x34},
345                 {AUD_PHACC_FREQ_8LSB, 0x4c},
346                 { /* end of list */ },
347         };
348
349         set_audio_start(core,SEL_NICAM);
350         switch (core->tvaudio) {
351         case WW_L:
352                 dprintk("%s SECAM-L NICAM (status: devel)\n", __FUNCTION__);
353                 set_audio_registers(core, nicam_l);
354                 break;
355         case WW_I:
356                 dprintk("%s PAL-I NICAM (status: known-good)\n", __FUNCTION__);
357                 set_audio_registers(core, nicam_bgdki_common);
358                 set_audio_registers(core, nicam_i);
359                 break;
360         default:
361                 dprintk("%s PAL-BGDK NICAM (status: known-good)\n", __FUNCTION__);
362                 set_audio_registers(core, nicam_bgdki_common);
363                 set_audio_registers(core, nicam_default);
364                 break;
365         };
366
367         mode |= EN_DMTRX_LR | EN_DMTRX_BYPASS;
368         set_audio_finish(core, mode);
369 }
370
371 static void set_audio_standard_A2(struct cx88_core *core, u32 mode)
372 {
373         static const struct rlist a2_bgdk_common[] = {
374                 {AUD_ERRLOGPERIOD_R, 0x00000064},
375                 {AUD_ERRINTRPTTHSHLD1_R, 0x00000fff},
376                 {AUD_ERRINTRPTTHSHLD2_R, 0x0000001f},
377                 {AUD_ERRINTRPTTHSHLD3_R, 0x0000000f},
378                 {AUD_PDF_DDS_CNST_BYTE2, 0x06},
379                 {AUD_PDF_DDS_CNST_BYTE1, 0x82},
380                 {AUD_PDF_DDS_CNST_BYTE0, 0x12},
381                 {AUD_QAM_MODE, 0x05},
382                 {AUD_PHACC_FREQ_8MSB, 0x34},
383                 {AUD_PHACC_FREQ_8LSB, 0x4c},
384                 {AUD_RATE_ADJ1, 0x00000100},
385                 {AUD_RATE_ADJ2, 0x00000200},
386                 {AUD_RATE_ADJ3, 0x00000300},
387                 {AUD_RATE_ADJ4, 0x00000400},
388                 {AUD_RATE_ADJ5, 0x00000500},
389                 {AUD_THR_FR, 0x00000000},
390                 {AAGC_HYST, 0x0000001a},
391                 {AUD_PILOT_BQD_1_K0, 0x0000755b},
392                 {AUD_PILOT_BQD_1_K1, 0x00551340},
393                 {AUD_PILOT_BQD_1_K2, 0x006d30be},
394                 {AUD_PILOT_BQD_1_K3, 0xffd394af},
395                 {AUD_PILOT_BQD_1_K4, 0x00400000},
396                 {AUD_PILOT_BQD_2_K0, 0x00040000},
397                 {AUD_PILOT_BQD_2_K1, 0x002a4841},
398                 {AUD_PILOT_BQD_2_K2, 0x00400000},
399                 {AUD_PILOT_BQD_2_K3, 0x00000000},
400                 {AUD_PILOT_BQD_2_K4, 0x00000000},
401                 {AUD_MODE_CHG_TIMER, 0x00000040},
402                 {AUD_AFE_12DB_EN, 0x00000001},
403                 {AUD_CORDIC_SHIFT_0, 0x00000007},
404                 {AUD_CORDIC_SHIFT_1, 0x00000007},
405                 {AUD_DEEMPH0_G0, 0x00000380},
406                 {AUD_DEEMPH1_G0, 0x00000380},
407                 {AUD_DCOC_0_SRC, 0x0000001a},
408                 {AUD_DCOC0_SHIFT, 0x00000000},
409                 {AUD_DCOC_0_SHIFT_IN0, 0x0000000a},
410                 {AUD_DCOC_0_SHIFT_IN1, 0x00000008},
411                 {AUD_DCOC_PASS_IN, 0x00000003},
412                 {AUD_IIR3_0_SEL, 0x00000021},
413                 {AUD_DN2_AFC, 0x00000002},
414                 {AUD_DCOC_1_SRC, 0x0000001b},
415                 {AUD_DCOC1_SHIFT, 0x00000000},
416                 {AUD_DCOC_1_SHIFT_IN0, 0x0000000a},
417                 {AUD_DCOC_1_SHIFT_IN1, 0x00000008},
418                 {AUD_IIR3_1_SEL, 0x00000023},
419                 {AUD_RDSI_SEL, 0x00000017},
420                 {AUD_RDSI_SHIFT, 0x00000000},
421                 {AUD_RDSQ_SEL, 0x00000017},
422                 {AUD_RDSQ_SHIFT, 0x00000000},
423                 {AUD_PLL_INT, 0x0000001e},
424                 {AUD_PLL_DDS, 0x00000000},
425                 {AUD_PLL_FRAC, 0x0000e542},
426                 {AUD_POLYPH80SCALEFAC, 0x00000001},
427                 {AUD_START_TIMER, 0x00000000},
428                 { /* end of list */ },
429         };
430
431         static const struct rlist a2_bg[] = {
432                 {AUD_DMD_RA_DDS, 0x002a4f2f},
433                 {AUD_C1_UP_THR, 0x00007000},
434                 {AUD_C1_LO_THR, 0x00005400},
435                 {AUD_C2_UP_THR, 0x00005400},
436                 {AUD_C2_LO_THR, 0x00003000},
437                 { /* end of list */ },
438         };
439
440         static const struct rlist a2_dk[] = {
441                 {AUD_DMD_RA_DDS, 0x002a4f2f},
442                 {AUD_C1_UP_THR, 0x00007000},
443                 {AUD_C1_LO_THR, 0x00005400},
444                 {AUD_C2_UP_THR, 0x00005400},
445                 {AUD_C2_LO_THR, 0x00003000},
446                 {AUD_DN0_FREQ, 0x00003a1c},
447                 {AUD_DN2_FREQ, 0x0000d2e0},
448                 { /* end of list */ },
449         };
450
451         static const struct rlist a1_i[] = {
452                 {AUD_ERRLOGPERIOD_R, 0x00000064},
453                 {AUD_ERRINTRPTTHSHLD1_R, 0x00000fff},
454                 {AUD_ERRINTRPTTHSHLD2_R, 0x0000001f},
455                 {AUD_ERRINTRPTTHSHLD3_R, 0x0000000f},
456                 {AUD_PDF_DDS_CNST_BYTE2, 0x06},
457                 {AUD_PDF_DDS_CNST_BYTE1, 0x82},
458                 {AUD_PDF_DDS_CNST_BYTE0, 0x12},
459                 {AUD_QAM_MODE, 0x05},
460                 {AUD_PHACC_FREQ_8MSB, 0x3a},
461                 {AUD_PHACC_FREQ_8LSB, 0x93},
462                 {AUD_DMD_RA_DDS, 0x002a4f2f},
463                 {AUD_PLL_INT, 0x0000001e},
464                 {AUD_PLL_DDS, 0x00000004},
465                 {AUD_PLL_FRAC, 0x0000e542},
466                 {AUD_RATE_ADJ1, 0x00000100},
467                 {AUD_RATE_ADJ2, 0x00000200},
468                 {AUD_RATE_ADJ3, 0x00000300},
469                 {AUD_RATE_ADJ4, 0x00000400},
470                 {AUD_RATE_ADJ5, 0x00000500},
471                 {AUD_THR_FR, 0x00000000},
472                 {AUD_PILOT_BQD_1_K0, 0x0000755b},
473                 {AUD_PILOT_BQD_1_K1, 0x00551340},
474                 {AUD_PILOT_BQD_1_K2, 0x006d30be},
475                 {AUD_PILOT_BQD_1_K3, 0xffd394af},
476                 {AUD_PILOT_BQD_1_K4, 0x00400000},
477                 {AUD_PILOT_BQD_2_K0, 0x00040000},
478                 {AUD_PILOT_BQD_2_K1, 0x002a4841},
479                 {AUD_PILOT_BQD_2_K2, 0x00400000},
480                 {AUD_PILOT_BQD_2_K3, 0x00000000},
481                 {AUD_PILOT_BQD_2_K4, 0x00000000},
482                 {AUD_MODE_CHG_TIMER, 0x00000060},
483                 {AUD_AFE_12DB_EN, 0x00000001},
484                 {AAGC_HYST, 0x0000000a},
485                 {AUD_CORDIC_SHIFT_0, 0x00000007},
486                 {AUD_CORDIC_SHIFT_1, 0x00000007},
487                 {AUD_C1_UP_THR, 0x00007000},
488                 {AUD_C1_LO_THR, 0x00005400},
489                 {AUD_C2_UP_THR, 0x00005400},
490                 {AUD_C2_LO_THR, 0x00003000},
491                 {AUD_DCOC_0_SRC, 0x0000001a},
492                 {AUD_DCOC0_SHIFT, 0x00000000},
493                 {AUD_DCOC_0_SHIFT_IN0, 0x0000000a},
494                 {AUD_DCOC_0_SHIFT_IN1, 0x00000008},
495                 {AUD_DCOC_PASS_IN, 0x00000003},
496                 {AUD_IIR3_0_SEL, 0x00000021},
497                 {AUD_DN2_AFC, 0x00000002},
498                 {AUD_DCOC_1_SRC, 0x0000001b},
499                 {AUD_DCOC1_SHIFT, 0x00000000},
500                 {AUD_DCOC_1_SHIFT_IN0, 0x0000000a},
501                 {AUD_DCOC_1_SHIFT_IN1, 0x00000008},
502                 {AUD_IIR3_1_SEL, 0x00000023},
503                 {AUD_DN0_FREQ, 0x000035a3},
504                 {AUD_DN2_FREQ, 0x000029c7},
505                 {AUD_CRDC0_SRC_SEL, 0x00000511},
506                 {AUD_IIR1_0_SEL, 0x00000001},
507                 {AUD_IIR1_1_SEL, 0x00000000},
508                 {AUD_IIR3_2_SEL, 0x00000003},
509                 {AUD_IIR3_2_SHIFT, 0x00000000},
510                 {AUD_IIR3_0_SEL, 0x00000002},
511                 {AUD_IIR2_0_SEL, 0x00000021},
512                 {AUD_IIR2_0_SHIFT, 0x00000002},
513                 {AUD_DEEMPH0_SRC_SEL, 0x0000000b},
514                 {AUD_DEEMPH1_SRC_SEL, 0x0000000b},
515                 {AUD_POLYPH80SCALEFAC, 0x00000001},
516                 {AUD_START_TIMER, 0x00000000},
517                 { /* end of list */ },
518         };
519
520         static const struct rlist am_l[] = {
521                 {AUD_ERRLOGPERIOD_R, 0x00000064},
522                 {AUD_ERRINTRPTTHSHLD1_R, 0x00000FFF},
523                 {AUD_ERRINTRPTTHSHLD2_R, 0x0000001F},
524                 {AUD_ERRINTRPTTHSHLD3_R, 0x0000000F},
525                 {AUD_PDF_DDS_CNST_BYTE2, 0x48},
526                 {AUD_PDF_DDS_CNST_BYTE1, 0x3D},
527                 {AUD_QAM_MODE, 0x00},
528                 {AUD_PDF_DDS_CNST_BYTE0, 0xf5},
529                 {AUD_PHACC_FREQ_8MSB, 0x3a},
530                 {AUD_PHACC_FREQ_8LSB, 0x4a},
531                 {AUD_DEEMPHGAIN_R, 0x00006680},
532                 {AUD_DEEMPHNUMER1_R, 0x000353DE},
533                 {AUD_DEEMPHNUMER2_R, 0x000001B1},
534                 {AUD_DEEMPHDENOM1_R, 0x0000F3D0},
535                 {AUD_DEEMPHDENOM2_R, 0x00000000},
536                 {AUD_FM_MODE_ENABLE, 0x00000007},
537                 {AUD_POLYPH80SCALEFAC, 0x00000003},
538                 {AUD_AFE_12DB_EN, 0x00000001},
539                 {AAGC_GAIN, 0x00000000},
540                 {AAGC_HYST, 0x00000018},
541                 {AAGC_DEF, 0x00000020},
542                 {AUD_DN0_FREQ, 0x00000000},
543                 {AUD_POLY0_DDS_CONSTANT, 0x000E4DB2},
544                 {AUD_DCOC_0_SRC, 0x00000021},
545                 {AUD_IIR1_0_SEL, 0x00000000},
546                 {AUD_IIR1_0_SHIFT, 0x00000007},
547                 {AUD_IIR1_1_SEL, 0x00000002},
548                 {AUD_IIR1_1_SHIFT, 0x00000000},
549                 {AUD_DCOC_1_SRC, 0x00000003},
550                 {AUD_DCOC1_SHIFT, 0x00000000},
551                 {AUD_DCOC_PASS_IN, 0x00000000},
552                 {AUD_IIR1_2_SEL, 0x00000023},
553                 {AUD_IIR1_2_SHIFT, 0x00000000},
554                 {AUD_IIR1_3_SEL, 0x00000004},
555                 {AUD_IIR1_3_SHIFT, 0x00000007},
556                 {AUD_IIR1_4_SEL, 0x00000005},
557                 {AUD_IIR1_4_SHIFT, 0x00000007},
558                 {AUD_IIR3_0_SEL, 0x00000007},
559                 {AUD_IIR3_0_SHIFT, 0x00000000},
560                 {AUD_DEEMPH0_SRC_SEL, 0x00000011},
561                 {AUD_DEEMPH0_SHIFT, 0x00000000},
562                 {AUD_DEEMPH0_G0, 0x00007000},
563                 {AUD_DEEMPH0_A0, 0x00000000},
564                 {AUD_DEEMPH0_B0, 0x00000000},
565                 {AUD_DEEMPH0_A1, 0x00000000},
566                 {AUD_DEEMPH0_B1, 0x00000000},
567                 {AUD_DEEMPH1_SRC_SEL, 0x00000011},
568                 {AUD_DEEMPH1_SHIFT, 0x00000000},
569                 {AUD_DEEMPH1_G0, 0x00007000},
570                 {AUD_DEEMPH1_A0, 0x00000000},
571                 {AUD_DEEMPH1_B0, 0x00000000},
572                 {AUD_DEEMPH1_A1, 0x00000000},
573                 {AUD_DEEMPH1_B1, 0x00000000},
574                 {AUD_OUT0_SEL, 0x0000003F},
575                 {AUD_OUT1_SEL, 0x0000003F},
576                 {AUD_DMD_RA_DDS, 0x00F5C285},
577                 {AUD_PLL_INT, 0x0000001E},
578                 {AUD_PLL_DDS, 0x00000000},
579                 {AUD_PLL_FRAC, 0x0000E542},
580                 {AUD_RATE_ADJ1, 0x00000100},
581                 {AUD_RATE_ADJ2, 0x00000200},
582                 {AUD_RATE_ADJ3, 0x00000300},
583                 {AUD_RATE_ADJ4, 0x00000400},
584                 {AUD_RATE_ADJ5, 0x00000500},
585                 {AUD_RATE_THRES_DMD, 0x000000C0},
586                 { /* end of list */ },
587         };
588
589         static const struct rlist a2_deemph50[] = {
590                 {AUD_DEEMPH0_G0, 0x00000380},
591                 {AUD_DEEMPH1_G0, 0x00000380},
592                 {AUD_DEEMPHGAIN_R, 0x000011e1},
593                 {AUD_DEEMPHNUMER1_R, 0x0002a7bc},
594                 {AUD_DEEMPHNUMER2_R, 0x0003023c},
595                 { /* end of list */ },
596         };
597
598         set_audio_start(core, SEL_A2);
599         switch (core->tvaudio) {
600         case WW_BG:
601                 dprintk("%s PAL-BG A1/2 (status: known-good)\n", __FUNCTION__);
602                 set_audio_registers(core, a2_bgdk_common);
603                 set_audio_registers(core, a2_bg);
604                 set_audio_registers(core, a2_deemph50);
605                 break;
606         case WW_DK:
607                 dprintk("%s PAL-DK A1/2 (status: known-good)\n", __FUNCTION__);
608                 set_audio_registers(core, a2_bgdk_common);
609                 set_audio_registers(core, a2_dk);
610                 set_audio_registers(core, a2_deemph50);
611                 break;
612         case WW_I:
613                 dprintk("%s PAL-I A1 (status: known-good)\n", __FUNCTION__);
614                 set_audio_registers(core, a1_i);
615                 set_audio_registers(core, a2_deemph50);
616                 break;
617         case WW_L:
618                 dprintk("%s AM-L (status: devel)\n", __FUNCTION__);
619                 set_audio_registers(core, am_l);
620                 break;
621         default:
622                 dprintk("%s Warning: wrong value\n", __FUNCTION__);
623                 return;
624                 break;
625         };
626
627         mode |= EN_FMRADIO_EN_RDS | EN_DMTRX_SUMDIFF;
628         set_audio_finish(core, mode);
629 }
630
631 static void set_audio_standard_EIAJ(struct cx88_core *core)
632 {
633         static const struct rlist eiaj[] = {
634                 /* TODO: eiaj register settings are not there yet ... */
635
636                 { /* end of list */ },
637         };
638         dprintk("%s (status: unknown)\n", __FUNCTION__);
639
640         set_audio_start(core, SEL_EIAJ);
641         set_audio_registers(core, eiaj);
642         set_audio_finish(core, EN_EIAJ_AUTO_STEREO);
643 }
644
645 static void set_audio_standard_FM(struct cx88_core *core,
646                                   enum cx88_deemph_type deemph)
647 {
648         static const struct rlist fm_deemph_50[] = {
649                 {AUD_DEEMPH0_G0, 0x0C45},
650                 {AUD_DEEMPH0_A0, 0x6262},
651                 {AUD_DEEMPH0_B0, 0x1C29},
652                 {AUD_DEEMPH0_A1, 0x3FC66},
653                 {AUD_DEEMPH0_B1, 0x399A},
654
655                 {AUD_DEEMPH1_G0, 0x0D80},
656                 {AUD_DEEMPH1_A0, 0x6262},
657                 {AUD_DEEMPH1_B0, 0x1C29},
658                 {AUD_DEEMPH1_A1, 0x3FC66},
659                 {AUD_DEEMPH1_B1, 0x399A},
660
661                 {AUD_POLYPH80SCALEFAC, 0x0003},
662                 { /* end of list */ },
663         };
664         static const struct rlist fm_deemph_75[] = {
665                 {AUD_DEEMPH0_G0, 0x091B},
666                 {AUD_DEEMPH0_A0, 0x6B68},
667                 {AUD_DEEMPH0_B0, 0x11EC},
668                 {AUD_DEEMPH0_A1, 0x3FC66},
669                 {AUD_DEEMPH0_B1, 0x399A},
670
671                 {AUD_DEEMPH1_G0, 0x0AA0},
672                 {AUD_DEEMPH1_A0, 0x6B68},
673                 {AUD_DEEMPH1_B0, 0x11EC},
674                 {AUD_DEEMPH1_A1, 0x3FC66},
675                 {AUD_DEEMPH1_B1, 0x399A},
676
677                 {AUD_POLYPH80SCALEFAC, 0x0003},
678                 { /* end of list */ },
679         };
680
681         /* It is enough to leave default values? */
682         static const struct rlist fm_no_deemph[] = {
683
684                 {AUD_POLYPH80SCALEFAC, 0x0003},
685                 { /* end of list */ },
686         };
687
688         dprintk("%s (status: unknown)\n", __FUNCTION__);
689         set_audio_start(core, SEL_FMRADIO);
690
691         switch (deemph) {
692         case FM_NO_DEEMPH:
693                 set_audio_registers(core, fm_no_deemph);
694                 break;
695
696         case FM_DEEMPH_50:
697                 set_audio_registers(core, fm_deemph_50);
698                 break;
699
700         case FM_DEEMPH_75:
701                 set_audio_registers(core, fm_deemph_75);
702                 break;
703         }
704
705         set_audio_finish(core, EN_FMRADIO_AUTO_STEREO);
706 }
707
708 /* ----------------------------------------------------------- */
709
710 static int cx88_detect_nicam(struct cx88_core *core)
711 {
712         int i, j = 0;
713
714         dprintk("start nicam autodetect.\n");
715
716         for (i = 0; i < 6; i++) {
717                 /* if bit1=1 then nicam is detected */
718                 j += ((cx_read(AUD_NICAM_STATUS2) & 0x02) >> 1);
719
720                 if (j == 1) {
721                         dprintk("nicam is detected.\n");
722                         return 1;
723                 }
724
725                 /* wait a little bit for next reading status */
726                 msleep(10);
727         }
728
729         dprintk("nicam is not detected.\n");
730         return 0;
731 }
732
733 void cx88_set_tvaudio(struct cx88_core *core)
734 {
735         switch (core->tvaudio) {
736         case WW_BTSC:
737                 set_audio_standard_BTSC(core, 0, EN_BTSC_AUTO_STEREO);
738                 break;
739         case WW_BG:
740         case WW_DK:
741         case WW_I:
742         case WW_L:
743                 /* prepare all dsp registers */
744                 set_audio_standard_A2(core, EN_A2_FORCE_MONO1);
745
746                 /* set nicam mode - otherwise
747                    AUD_NICAM_STATUS2 contains wrong values */
748                 set_audio_standard_NICAM(core, EN_NICAM_AUTO_STEREO);
749                 if (0 == cx88_detect_nicam(core)) {
750                         /* fall back to fm / am mono */
751                         set_audio_standard_A2(core, EN_A2_FORCE_MONO1);
752                         core->use_nicam = 0;
753                 } else {
754                         core->use_nicam = 1;
755                 }
756                 break;
757         case WW_EIAJ:
758                 set_audio_standard_EIAJ(core);
759                 break;
760         case WW_FM:
761                 set_audio_standard_FM(core, FM_NO_DEEMPH);
762                 break;
763         case WW_NONE:
764         default:
765                 printk("%s/0: unknown tv audio mode [%d]\n",
766                        core->name, core->tvaudio);
767                 break;
768         }
769         return;
770 }
771
772 void cx88_newstation(struct cx88_core *core)
773 {
774         core->audiomode_manual = UNSET;
775 }
776
777 void cx88_get_stereo(struct cx88_core *core, struct v4l2_tuner *t)
778 {
779         static char *m[] = { "stereo", "dual mono", "mono", "sap" };
780         static char *p[] = { "no pilot", "pilot c1", "pilot c2", "?" };
781         u32 reg, mode, pilot;
782
783         reg = cx_read(AUD_STATUS);
784         mode = reg & 0x03;
785         pilot = (reg >> 2) & 0x03;
786
787         if (core->astat != reg)
788                 dprintk("AUD_STATUS: 0x%x [%s/%s] ctl=%s\n",
789                         reg, m[mode], p[pilot],
790                         aud_ctl_names[cx_read(AUD_CTL) & 63]);
791         core->astat = reg;
792
793 /* TODO
794        Reading from AUD_STATUS is not enough
795        for auto-detecting sap/dual-fm/nicam.
796        Add some code here later.
797 */
798
799         return;
800 }
801
802 void cx88_set_stereo(struct cx88_core *core, u32 mode, int manual)
803 {
804         u32 ctl = UNSET;
805         u32 mask = UNSET;
806
807         if (manual) {
808                 core->audiomode_manual = mode;
809         } else {
810                 if (UNSET != core->audiomode_manual)
811                         return;
812         }
813         core->audiomode_current = mode;
814
815         switch (core->tvaudio) {
816         case WW_BTSC:
817                 switch (mode) {
818                 case V4L2_TUNER_MODE_MONO:
819                         set_audio_standard_BTSC(core, 0, EN_BTSC_FORCE_MONO);
820                         break;
821                 case V4L2_TUNER_MODE_LANG1:
822                         set_audio_standard_BTSC(core, 0, EN_BTSC_AUTO_STEREO);
823                         break;
824                 case V4L2_TUNER_MODE_LANG2:
825                         set_audio_standard_BTSC(core, 1, EN_BTSC_FORCE_SAP);
826                         break;
827                 case V4L2_TUNER_MODE_STEREO:
828                 case V4L2_TUNER_MODE_LANG1_LANG2:
829                         set_audio_standard_BTSC(core, 0, EN_BTSC_FORCE_STEREO);
830                         break;
831                 }
832                 break;
833         case WW_BG:
834         case WW_DK:
835         case WW_I:
836         case WW_L:
837                 if (1 == core->use_nicam) {
838                         switch (mode) {
839                         case V4L2_TUNER_MODE_MONO:
840                         case V4L2_TUNER_MODE_LANG1:
841                                 set_audio_standard_NICAM(core,
842                                                          EN_NICAM_FORCE_MONO1);
843                                 break;
844                         case V4L2_TUNER_MODE_LANG2:
845                                 set_audio_standard_NICAM(core,
846                                                          EN_NICAM_FORCE_MONO2);
847                                 break;
848                         case V4L2_TUNER_MODE_STEREO:
849                         case V4L2_TUNER_MODE_LANG1_LANG2:
850                                 set_audio_standard_NICAM(core,
851                                                          EN_NICAM_FORCE_STEREO);
852                                 break;
853                         }
854                 } else {
855                         if ((core->tvaudio == WW_I) || (core->tvaudio == WW_L)) {
856                                 /* fall back to fm / am mono */
857                                 set_audio_standard_A2(core, EN_A2_FORCE_MONO1);
858                         } else {
859                                 /* TODO: Add A2 autodection */
860                                 switch (mode) {
861                                 case V4L2_TUNER_MODE_MONO:
862                                 case V4L2_TUNER_MODE_LANG1:
863                                         set_audio_standard_A2(core,
864                                                               EN_A2_FORCE_MONO1);
865                                         break;
866                                 case V4L2_TUNER_MODE_LANG2:
867                                         set_audio_standard_A2(core,
868                                                               EN_A2_FORCE_MONO2);
869                                         break;
870                                 case V4L2_TUNER_MODE_STEREO:
871                                 case V4L2_TUNER_MODE_LANG1_LANG2:
872                                         set_audio_standard_A2(core,
873                                                               EN_A2_FORCE_STEREO);
874                                         break;
875                                 }
876                         }
877                 }
878                 break;
879         case WW_FM:
880                 switch (mode) {
881                 case V4L2_TUNER_MODE_MONO:
882                         ctl = EN_FMRADIO_FORCE_MONO;
883                         mask = 0x3f;
884                         break;
885                 case V4L2_TUNER_MODE_STEREO:
886                         ctl = EN_FMRADIO_AUTO_STEREO;
887                         mask = 0x3f;
888                         break;
889                 }
890                 break;
891         }
892
893         if (UNSET != ctl) {
894                 dprintk("cx88_set_stereo: mask 0x%x, ctl 0x%x "
895                         "[status=0x%x,ctl=0x%x,vol=0x%x]\n",
896                         mask, ctl, cx_read(AUD_STATUS),
897                         cx_read(AUD_CTL), cx_sread(SHADOW_AUD_VOL_CTL));
898                 cx_andor(AUD_CTL, mask, ctl);
899         }
900         return;
901 }
902
903 int cx88_audio_thread(void *data)
904 {
905         struct cx88_core *core = data;
906         struct v4l2_tuner t;
907         u32 mode = 0;
908
909         dprintk("cx88: tvaudio thread started\n");
910         for (;;) {
911                 msleep_interruptible(1000);
912                 if (kthread_should_stop())
913                         break;
914                 try_to_freeze();
915
916                 /* just monitor the audio status for now ... */
917                 memset(&t, 0, sizeof(t));
918                 cx88_get_stereo(core, &t);
919
920                 if (UNSET != core->audiomode_manual)
921                         /* manually set, don't do anything. */
922                         continue;
923
924                 /* monitor signal */
925                 if (t.rxsubchans & V4L2_TUNER_SUB_STEREO)
926                         mode = V4L2_TUNER_MODE_STEREO;
927                 else
928                         mode = V4L2_TUNER_MODE_MONO;
929                 if (mode == core->audiomode_current)
930                         continue;
931
932                 /* automatically switch to best available mode */
933                 cx88_set_stereo(core, mode, 0);
934         }
935
936         dprintk("cx88: tvaudio thread exiting\n");
937         return 0;
938 }
939
940 /* ----------------------------------------------------------- */
941
942 EXPORT_SYMBOL(cx88_set_tvaudio);
943 EXPORT_SYMBOL(cx88_newstation);
944 EXPORT_SYMBOL(cx88_set_stereo);
945 EXPORT_SYMBOL(cx88_get_stereo);
946 EXPORT_SYMBOL(cx88_audio_thread);
947
948 /*
949  * Local variables:
950  * c-basic-offset: 8
951  * End:
952  * kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off
953  */