V4L/DVB (10955): cx231xx: CodingStyle automatic fixes with Lindent
[linux-2.6.git] / drivers / media / video / cx231xx / cx231xx-avcore.c
1 /*
2    cx231xx_avcore.c - driver for Conexant Cx23100/101/102 USB video capture devices
3
4    Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
5
6    This program contains the specific code to control the avdecoder chip and
7    other related usb control functions for cx231xx based chipset.
8
9    This program is free software; you can redistribute it and/or modify
10    it under the terms of the GNU General Public License as published by
11    the Free Software Foundation; either version 2 of the License, or
12    (at your option) any later version.
13
14    This program is distributed in the hope that it will be useful,
15    but WITHOUT ANY WARRANTY; without even the implied warranty of
16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17    GNU General Public License for more details.
18
19    You should have received a copy of the GNU General Public License
20    along with this program; if not, write to the Free Software
21    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22  */
23
24 #include <linux/init.h>
25 #include <linux/list.h>
26 #include <linux/module.h>
27 #include <linux/kernel.h>
28 #include <linux/bitmap.h>
29 #include <linux/usb.h>
30 #include <linux/i2c.h>
31 #include <linux/version.h>
32 #include <linux/mm.h>
33 #include <linux/mutex.h>
34
35 #include <media/v4l2-common.h>
36 #include <media/v4l2-ioctl.h>
37 #include <media/v4l2-chip-ident.h>
38
39 #include "cx231xx.h"
40
41 /*************************************************************************************
42  *            C O L I B R I - B L O C K    C O N T R O L   functions                 *
43  *************************************************************************************/
44 int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count)
45 {
46         int status = 0;
47         u8 temp = 0;
48         u32 colibri_power_status = 0;
49         int i = 0;
50
51         /* super block initialize */
52         temp = (u8) (ref_count & 0xff);
53         status =
54             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE2,
55                                    2, temp, 1);
56
57         status =
58             cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE2, 2,
59                                   &colibri_power_status, 1);
60
61         temp = (u8) ((ref_count & 0x300) >> 8);
62         temp |= 0x40;
63         status =
64             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE1,
65                                    2, temp, 1);
66         status =
67             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PLL2, 2,
68                                    0x0f, 1);
69
70         /* enable pll     */
71         while (colibri_power_status != 0x18) {
72                 status =
73                     cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
74                                            SUP_BLK_PWRDN, 2, 0x18, 1);
75                 status =
76                     cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
77                                           SUP_BLK_PWRDN, 2,
78                                           &colibri_power_status, 1);
79                 colibri_power_status &= 0xff;
80                 if (status < 0) {
81                         cx231xx_info
82                             (": Init Super Block failed in sending/receiving cmds\n");
83                         break;
84                 }
85                 i++;
86                 if (i == 10) {
87                         cx231xx_info
88                             (": Init Super Block force break in loop !!!!\n");
89                         status = -1;
90                         break;
91                 }
92         }
93
94         if (status < 0)
95                 return status;
96
97         /* start tuning filter */
98         status =
99             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE3,
100                                    2, 0x40, 1);
101         msleep(5);
102
103         /* exit tuning */
104         status =
105             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE3,
106                                    2, 0x00, 1);
107
108         return status;
109 }
110
111 int cx231xx_colibri_init_channels(struct cx231xx *dev)
112 {
113         int status = 0;
114
115         /* power up all 3 channels, clear pd_buffer */
116         status =
117             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
118                                    ADC_PWRDN_CLAMP_CH1, 2, 0x00, 1);
119         status =
120             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
121                                    ADC_PWRDN_CLAMP_CH2, 2, 0x00, 1);
122         status =
123             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
124                                    ADC_PWRDN_CLAMP_CH3, 2, 0x00, 1);
125
126         /* Enable quantizer calibration */
127         status =
128             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_COM_QUANT,
129                                    2, 0x02, 1);
130
131         /* channel initialize, force modulator (fb) reset */
132         status =
133             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
134                                    ADC_FB_FRCRST_CH1, 2, 0x17, 1);
135         status =
136             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
137                                    ADC_FB_FRCRST_CH2, 2, 0x17, 1);
138         status =
139             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
140                                    ADC_FB_FRCRST_CH3, 2, 0x17, 1);
141
142         /* start quantilizer calibration  */
143         status =
144             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
145                                    ADC_CAL_ATEST_CH1, 2, 0x10, 1);
146         status =
147             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
148                                    ADC_CAL_ATEST_CH2, 2, 0x10, 1);
149         status =
150             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
151                                    ADC_CAL_ATEST_CH3, 2, 0x10, 1);
152         msleep(5);
153
154         /* exit modulator (fb) reset */
155         status =
156             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
157                                    ADC_FB_FRCRST_CH1, 2, 0x07, 1);
158         status =
159             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
160                                    ADC_FB_FRCRST_CH2, 2, 0x07, 1);
161         status =
162             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
163                                    ADC_FB_FRCRST_CH3, 2, 0x07, 1);
164
165         /* enable the pre_clamp in each channel for single-ended input */
166         status =
167             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
168                                    ADC_NTF_PRECLMP_EN_CH1, 2, 0xf0, 1);
169         status =
170             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
171                                    ADC_NTF_PRECLMP_EN_CH2, 2, 0xf0, 1);
172         status =
173             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
174                                    ADC_NTF_PRECLMP_EN_CH3, 2, 0xf0, 1);
175
176         /* use diode instead of resistor, so set term_en to 0, res_en to 0  */
177         status =
178             cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8,
179                                    ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00);
180         status =
181             cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8,
182                                    ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00);
183         status =
184             cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8,
185                                    ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00);
186
187         /* dynamic element matching off */
188         status =
189             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
190                                    ADC_DCSERVO_DEM_CH1, 2, 0x03, 1);
191         status =
192             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
193                                    ADC_DCSERVO_DEM_CH2, 2, 0x03, 1);
194         status =
195             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
196                                    ADC_DCSERVO_DEM_CH3, 2, 0x03, 1);
197
198         return status;
199 }
200
201 int cx231xx_colibri_setup_AFE_for_baseband(struct cx231xx *dev)
202 {
203         u32 c_value = 0;
204         int status = 0;
205
206         status =
207             cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
208                                   ADC_PWRDN_CLAMP_CH2, 2, &c_value, 1);
209         c_value &= (~(0x50));
210         status =
211             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
212                                    ADC_PWRDN_CLAMP_CH2, 2, c_value, 1);
213
214         return status;
215 }
216
217 /*
218         we have 3 channel
219         channel 1 ----- pin 1  to pin4(in reg is 1-4)
220         channel 2 ----- pin 5  to pin8(in reg is 5-8)
221         channel 3 ----- pin 9 to pin 12(in reg is 9-11)
222 */
223 int cx231xx_colibri_set_input_mux(struct cx231xx *dev, u32 input_mux)
224 {
225         u8 ch1_setting = (u8) input_mux;
226         u8 ch2_setting = (u8) (input_mux >> 8);
227         u8 ch3_setting = (u8) (input_mux >> 16);
228         int status = 0;
229         u32 value = 0;
230
231         if (ch1_setting != 0) {
232                 status =
233                     cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
234                                           ADC_INPUT_CH1, 2, &value, 1);
235                 value &= (!INPUT_SEL_MASK);
236                 value |= (ch1_setting - 1) << 4;
237                 value &= 0xff;
238                 status =
239                     cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
240                                            ADC_INPUT_CH1, 2, value, 1);
241         }
242
243         if (ch2_setting != 0) {
244                 status =
245                     cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
246                                           ADC_INPUT_CH2, 2, &value, 1);
247                 value &= (!INPUT_SEL_MASK);
248                 value |= (ch2_setting - 1) << 4;
249                 value &= 0xff;
250                 status =
251                     cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
252                                            ADC_INPUT_CH2, 2, value, 1);
253         }
254
255         /* For ch3_setting, the value to put in the register is 7 less than the input number */
256         if (ch3_setting != 0) {
257                 status =
258                     cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
259                                           ADC_INPUT_CH3, 2, &value, 1);
260                 value &= (!INPUT_SEL_MASK);
261                 value |= (ch3_setting - 1) << 4;
262                 value &= 0xff;
263                 status =
264                     cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
265                                            ADC_INPUT_CH3, 2, value, 1);
266         }
267
268         return status;
269 }
270
271 int cx231xx_colibri_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
272 {
273         int status = 0;
274
275         switch (mode) {
276         case AFE_MODE_LOW_IF:
277                 /* SetupAFEforLowIF();  */
278                 break;
279         case AFE_MODE_BASEBAND:
280                 status = cx231xx_colibri_setup_AFE_for_baseband(dev);
281                 break;
282         case AFE_MODE_EU_HI_IF:
283                 /* SetupAFEforEuHiIF(); */
284                 break;
285         case AFE_MODE_US_HI_IF:
286                 /* SetupAFEforUsHiIF(); */
287                 break;
288         case AFE_MODE_JAPAN_HI_IF:
289                 /* SetupAFEforJapanHiIF(); */
290                 break;
291         }
292
293         if ((mode != dev->colibri_mode)
294             && (dev->video_input == CX231XX_VMUX_TELEVISION)) {
295                 status =
296                     cx231xx_colibri_adjust_ref_count(dev,
297                                                      CX231XX_VMUX_TELEVISION);
298         }
299
300         dev->colibri_mode = mode;
301
302         return status;
303 }
304
305 /* For power saving in the EVK */
306 int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode)
307 {
308         u32 colibri_power_status = 0;
309         int status = 0;
310
311         switch (dev->model) {
312         case CX231XX_BOARD_CNXT_RDE_250:
313         case CX231XX_BOARD_CNXT_RDU_250:
314
315                 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
316                         while (colibri_power_status != 0x18) {
317                                 status =
318                                     cx231xx_write_i2c_data(dev,
319                                                            Colibri_DEVICE_ADDRESS,
320                                                            SUP_BLK_PWRDN, 2,
321                                                            0x18, 1);
322                                 status =
323                                     cx231xx_read_i2c_data(dev,
324                                                           Colibri_DEVICE_ADDRESS,
325                                                           SUP_BLK_PWRDN, 2,
326                                                           &colibri_power_status,
327                                                           1);
328                                 if (status < 0)
329                                         break;
330                         }
331
332                         status =
333                             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
334                                                    ADC_PWRDN_CLAMP_CH1, 2, 0x00,
335                                                    1);
336                         status =
337                             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
338                                                    ADC_PWRDN_CLAMP_CH2, 2, 0x00,
339                                                    1);
340                         status =
341                             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
342                                                    ADC_PWRDN_CLAMP_CH3, 2, 0x00,
343                                                    1);
344                 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
345                         status =
346                             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
347                                                    ADC_PWRDN_CLAMP_CH1, 2, 0x70,
348                                                    1);
349                         status =
350                             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
351                                                    ADC_PWRDN_CLAMP_CH2, 2, 0x70,
352                                                    1);
353                         status =
354                             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
355                                                    ADC_PWRDN_CLAMP_CH3, 2, 0x70,
356                                                    1);
357
358                         status =
359                             cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
360                                                   SUP_BLK_PWRDN, 2,
361                                                   &colibri_power_status, 1);
362                         colibri_power_status |= 0x07;
363                         status =
364                             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
365                                                    SUP_BLK_PWRDN, 2,
366                                                    colibri_power_status, 1);
367                 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
368
369                         while (colibri_power_status != 0x18) {
370                                 status =
371                                     cx231xx_write_i2c_data(dev,
372                                                            Colibri_DEVICE_ADDRESS,
373                                                            SUP_BLK_PWRDN, 2,
374                                                            0x18, 1);
375                                 status =
376                                     cx231xx_read_i2c_data(dev,
377                                                           Colibri_DEVICE_ADDRESS,
378                                                           SUP_BLK_PWRDN, 2,
379                                                           &colibri_power_status,
380                                                           1);
381                                 if (status < 0)
382                                         break;
383                         }
384
385                         status =
386                             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
387                                                    ADC_PWRDN_CLAMP_CH1, 2, 0x00,
388                                                    1);
389                         status =
390                             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
391                                                    ADC_PWRDN_CLAMP_CH2, 2, 0x00,
392                                                    1);
393                         status =
394                             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
395                                                    ADC_PWRDN_CLAMP_CH3, 2, 0x00,
396                                                    1);
397                 } else {
398                         cx231xx_info("Invalid AV mode input\n");
399                         status = -1;
400                 }
401                 break;
402         default:
403                 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
404                         while (colibri_power_status != 0x18) {
405                                 status =
406                                     cx231xx_write_i2c_data(dev,
407                                                            Colibri_DEVICE_ADDRESS,
408                                                            SUP_BLK_PWRDN, 2,
409                                                            0x18, 1);
410                                 status =
411                                     cx231xx_read_i2c_data(dev,
412                                                           Colibri_DEVICE_ADDRESS,
413                                                           SUP_BLK_PWRDN, 2,
414                                                           &colibri_power_status,
415                                                           1);
416                                 if (status < 0)
417                                         break;
418                         }
419
420                         status =
421                             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
422                                                    ADC_PWRDN_CLAMP_CH1, 2, 0x40,
423                                                    1);
424                         status =
425                             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
426                                                    ADC_PWRDN_CLAMP_CH2, 2, 0x40,
427                                                    1);
428                         status =
429                             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
430                                                    ADC_PWRDN_CLAMP_CH3, 2, 0x00,
431                                                    1);
432                 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
433                         status =
434                             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
435                                                    ADC_PWRDN_CLAMP_CH1, 2, 0x70,
436                                                    1);
437                         status =
438                             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
439                                                    ADC_PWRDN_CLAMP_CH2, 2, 0x70,
440                                                    1);
441                         status =
442                             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
443                                                    ADC_PWRDN_CLAMP_CH3, 2, 0x70,
444                                                    1);
445
446                         status =
447                             cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
448                                                   SUP_BLK_PWRDN, 2,
449                                                   &colibri_power_status, 1);
450                         colibri_power_status |= 0x07;
451                         status =
452                             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
453                                                    SUP_BLK_PWRDN, 2,
454                                                    colibri_power_status, 1);
455                 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
456                         while (colibri_power_status != 0x18) {
457                                 status =
458                                     cx231xx_write_i2c_data(dev,
459                                                            Colibri_DEVICE_ADDRESS,
460                                                            SUP_BLK_PWRDN, 2,
461                                                            0x18, 1);
462                                 status =
463                                     cx231xx_read_i2c_data(dev,
464                                                           Colibri_DEVICE_ADDRESS,
465                                                           SUP_BLK_PWRDN, 2,
466                                                           &colibri_power_status,
467                                                           1);
468                                 if (status < 0)
469                                         break;
470                         }
471
472                         status =
473                             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
474                                                    ADC_PWRDN_CLAMP_CH1, 2, 0x00,
475                                                    1);
476                         status =
477                             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
478                                                    ADC_PWRDN_CLAMP_CH2, 2, 0x00,
479                                                    1);
480                         status =
481                             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
482                                                    ADC_PWRDN_CLAMP_CH3, 2, 0x40,
483                                                    1);
484                 } else {
485                         cx231xx_info("Invalid AV mode input\n");
486                         status = -1;
487                 }
488         }                       /* switch  */
489
490         return status;
491 }
492
493 int cx231xx_colibri_adjust_ref_count(struct cx231xx *dev, u32 video_input)
494 {
495         u32 input_mode = 0;
496         u32 ntf_mode = 0;
497         int status = 0;
498
499         dev->video_input = video_input;
500
501         if (video_input == CX231XX_VMUX_TELEVISION) {
502                 status =
503                     cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
504                                           ADC_INPUT_CH3, 2, &input_mode, 1);
505                 status =
506                     cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
507                                           ADC_NTF_PRECLMP_EN_CH3, 2, &ntf_mode,
508                                           1);
509         } else {
510                 status =
511                     cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
512                                           ADC_INPUT_CH1, 2, &input_mode, 1);
513                 status =
514                     cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
515                                           ADC_NTF_PRECLMP_EN_CH1, 2, &ntf_mode,
516                                           1);
517         }
518
519         input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1);
520
521         switch (input_mode) {
522         case SINGLE_ENDED:
523                 dev->colibri_ref_count = 0x23C;
524                 break;
525         case LOW_IF:
526                 dev->colibri_ref_count = 0x24C;
527                 break;
528         case EU_IF:
529                 dev->colibri_ref_count = 0x258;
530                 break;
531         case US_IF:
532                 dev->colibri_ref_count = 0x260;
533                 break;
534         default:
535                 break;
536         }
537
538         status = cx231xx_colibri_init_super_block(dev, dev->colibri_ref_count);
539
540         return status;
541 }
542
543 /*************************************************************************************
544  *       V I D E O / A U D I O    D E C O D E R    C O N T R O L   functions         *
545  *************************************************************************************/
546 int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
547 {
548         int status = 0;
549
550         switch (INPUT(input)->type) {
551         case CX231XX_VMUX_COMPOSITE1:
552         case CX231XX_VMUX_SVIDEO:
553                 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
554                     (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) {
555                         status = cx231xx_set_power_mode(dev, POLARIS_AVMODE_ENXTERNAL_AV);      /* External AV */
556                         if (status < 0) {
557                                 cx231xx_errdev
558                                     ("%s: cx231xx_set_power_mode : Failed to set Power - errCode [%d]!\n",
559                                      __func__, status);
560                                 return status;
561                         }
562                 }
563                 status =
564                     cx231xx_set_decoder_video_input(dev, INPUT(input)->type,
565                                                     INPUT(input)->vmux);
566                 break;
567         case CX231XX_VMUX_TELEVISION:
568         case CX231XX_VMUX_CABLE:
569                 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
570                     (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) {
571                         status = cx231xx_set_power_mode(dev, POLARIS_AVMODE_ANALOGT_TV);        /* Tuner */
572                         if (status < 0) {
573                                 cx231xx_errdev
574                                     ("%s: cx231xx_set_power_mode : Failed to set Power - errCode [%d]!\n",
575                                      __func__, status);
576                                 return status;
577                         }
578                 }
579                 status =
580                     cx231xx_set_decoder_video_input(dev,
581                                                     CX231XX_VMUX_COMPOSITE1,
582                                                     INPUT(input)->vmux);
583                 break;
584         default:
585                 cx231xx_errdev
586                     ("%s: cx231xx_set_power_mode : Unknown Input %d !\n",
587                      __func__, INPUT(input)->type);
588                 break;
589         }
590
591         /* save the selection */
592         dev->video_input = input;
593
594         return status;
595 }
596
597 int cx231xx_set_decoder_video_input(struct cx231xx *dev, u8 pin_type, u8 input)
598 {
599         int status = 0;
600         u32 value = 0;
601
602         if (pin_type != dev->video_input) {
603                 status = cx231xx_colibri_adjust_ref_count(dev, pin_type);
604                 if (status < 0) {
605                         cx231xx_errdev
606                             ("%s: cx231xx_colibri_adjust_ref_count :Failed to set Colibri input mux - errCode [%d]!\n",
607                              __func__, status);
608                         return status;
609                 }
610         }
611
612         /* call colibri block to set video inputs */
613         status = cx231xx_colibri_set_input_mux(dev, input);
614         if (status < 0) {
615                 cx231xx_errdev
616                     ("%s: cx231xx_colibri_set_input_mux :Failed to set Colibri input mux - errCode [%d]!\n",
617                      __func__, status);
618                 return status;
619         }
620
621         switch (pin_type) {
622         case CX231XX_VMUX_COMPOSITE1:
623                 {
624                         status =
625                             cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
626                                                   AFE_CTRL, 2, &value, 4);
627                         value |= (0 << 13) | (1 << 4);
628                         value &= ~(1 << 5);
629
630                         value &= (~(0x1FF8000));        /* set [24:23] [22:15] to 0  */
631                         value |= 0x1000000;     /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0  */
632                         status =
633                             cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
634                                                    AFE_CTRL, 2, value, 4);
635
636                         status =
637                             cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
638                                                   OUT_CTRL1, 2, &value, 4);
639                         value |= (1 << 7);
640                         status =
641                             cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
642                                                    OUT_CTRL1, 2, value, 4);
643
644                         /* Set vip 1.1 output mode */
645                         status =
646                             cx231xx_read_modify_write_i2c_dword(dev,
647                                                                 HAMMERHEAD_I2C_ADDRESS,
648                                                                 OUT_CTRL1,
649                                                                 FLD_OUT_MODE,
650                                                                 OUT_MODE_VIP11);
651
652                         /* Tell DIF object to go to baseband mode  */
653                         status =
654                             cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
655                         if (status < 0) {
656                                 cx231xx_errdev
657                                     ("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n",
658                                      __func__, status);
659                                 return status;
660                         }
661
662                         /* Read the DFE_CTRL1 register */
663                         status =
664                             cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
665                                                   DFE_CTRL1, 2, &value, 4);
666
667                         /* enable the VBI_GATE_EN */
668                         value |= FLD_VBI_GATE_EN;
669
670                         /* Enable the auto-VGA enable */
671                         value |= FLD_VGA_AUTO_EN;
672
673                         /* Write it back */
674                         status =
675                             cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
676                                                    DFE_CTRL1, 2, value, 4);
677
678                         /* Disable auto config of registers */
679                         status =
680                             cx231xx_read_modify_write_i2c_dword(dev,
681                                                                 HAMMERHEAD_I2C_ADDRESS,
682                                                                 MODE_CTRL,
683                                                                 FLD_ACFG_DIS,
684                                                                 cx231xx_set_field
685                                                                 (FLD_ACFG_DIS,
686                                                                  1));
687
688                         /* Set CVBS input mode */
689                         status =
690                             cx231xx_read_modify_write_i2c_dword(dev,
691                                                                 HAMMERHEAD_I2C_ADDRESS,
692                                                                 MODE_CTRL,
693                                                                 FLD_INPUT_MODE,
694                                                                 cx231xx_set_field
695                                                                 (FLD_INPUT_MODE,
696                                                                  INPUT_MODE_CVBS_0));
697                 }
698                 break;
699         case CX231XX_VMUX_SVIDEO:
700                 {
701                         /* Disable the use of  DIF */
702
703                         status =
704                             cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
705                                                   AFE_CTRL, 2, &value, 4);
706
707                         value &= (~(0x1FF8000));        /* set [24:23] [22:15] to 0 */
708                         value |= 0x1000010;     /* set FUNC_MODE[24:23] = 2
709                                                    IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */
710                         status =
711                             cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
712                                                    AFE_CTRL, 2, value, 4);
713
714                         /* Tell DIF object to go to baseband mode */
715                         status =
716                             cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
717                         if (status < 0) {
718                                 cx231xx_errdev
719                                     ("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n",
720                                      __func__, status);
721                                 return status;
722                         }
723
724                         /* Read the DFE_CTRL1 register */
725                         status =
726                             cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
727                                                   DFE_CTRL1, 2, &value, 4);
728
729                         /* enable the VBI_GATE_EN */
730                         value |= FLD_VBI_GATE_EN;
731
732                         /* Enable the auto-VGA enable */
733                         value |= FLD_VGA_AUTO_EN;
734
735                         /* Write it back */
736                         status =
737                             cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
738                                                    DFE_CTRL1, 2, value, 4);
739
740                         /* Disable auto config of registers  */
741                         status =
742                             cx231xx_read_modify_write_i2c_dword(dev,
743                                                                 HAMMERHEAD_I2C_ADDRESS,
744                                                                 MODE_CTRL,
745                                                                 FLD_ACFG_DIS,
746                                                                 cx231xx_set_field
747                                                                 (FLD_ACFG_DIS,
748                                                                  1));
749
750                         /* Set YC input mode */
751                         status =
752                             cx231xx_read_modify_write_i2c_dword(dev,
753                                                                 HAMMERHEAD_I2C_ADDRESS,
754                                                                 MODE_CTRL,
755                                                                 FLD_INPUT_MODE,
756                                                                 cx231xx_set_field
757                                                                 (FLD_INPUT_MODE,
758                                                                  INPUT_MODE_YC_1));
759
760                         /* Chroma to ADC2 */
761                         status =
762                             cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
763                                                   AFE_CTRL, 2, &value, 4);
764                         value |= FLD_CHROMA_IN_SEL;     /* set the chroma in select */
765
766                         /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8)  This sets them to use video
767                            rather than audio.  Only one of the two will be in use. */
768                         value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3);
769
770                         status =
771                             cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
772                                                    AFE_CTRL, 2, value, 4);
773
774                         status =
775                             cx231xx_colibri_set_mode(dev, AFE_MODE_BASEBAND);
776                 }
777                 break;
778         case CX231XX_VMUX_TELEVISION:
779         case CX231XX_VMUX_CABLE:
780         default:
781                 {
782                         switch (dev->model) {
783                         case CX231XX_BOARD_CNXT_RDE_250:
784                         case CX231XX_BOARD_CNXT_RDU_250:
785                                 {
786                                         /* Disable the use of  DIF   */
787
788                                         status =
789                                             cx231xx_read_i2c_data(dev,
790                                                                   HAMMERHEAD_I2C_ADDRESS,
791                                                                   AFE_CTRL, 2,
792                                                                   &value, 4);
793                                         value |= (0 << 13) | (1 << 4);
794                                         value &= ~(1 << 5);
795
796                                         value &= (~(0x1FF8000));        /* set [24:23] [22:15] to 0 */
797                                         value |= 0x1000000;     /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
798                                         status =
799                                             cx231xx_write_i2c_data(dev,
800                                                                    HAMMERHEAD_I2C_ADDRESS,
801                                                                    AFE_CTRL, 2,
802                                                                    value, 4);
803
804                                         status =
805                                             cx231xx_read_i2c_data(dev,
806                                                                   HAMMERHEAD_I2C_ADDRESS,
807                                                                   OUT_CTRL1, 2,
808                                                                   &value, 4);
809                                         value |= (1 << 7);
810                                         status =
811                                             cx231xx_write_i2c_data(dev,
812                                                                    HAMMERHEAD_I2C_ADDRESS,
813                                                                    OUT_CTRL1, 2,
814                                                                    value, 4);
815
816                                         /* Set vip 1.1 output mode */
817                                         status =
818                                             cx231xx_read_modify_write_i2c_dword
819                                             (dev, HAMMERHEAD_I2C_ADDRESS,
820                                              OUT_CTRL1, FLD_OUT_MODE,
821                                              OUT_MODE_VIP11);
822
823                                         /* Tell DIF object to go to baseband mode */
824                                         status =
825                                             cx231xx_dif_set_standard(dev,
826                                                                      DIF_USE_BASEBAND);
827                                         if (status < 0) {
828                                                 cx231xx_errdev
829                                                     ("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n",
830                                                      __func__, status);
831                                                 return status;
832                                         }
833
834                                         /* Read the DFE_CTRL1 register */
835                                         status =
836                                             cx231xx_read_i2c_data(dev,
837                                                                   HAMMERHEAD_I2C_ADDRESS,
838                                                                   DFE_CTRL1, 2,
839                                                                   &value, 4);
840
841                                         /* enable the VBI_GATE_EN */
842                                         value |= FLD_VBI_GATE_EN;
843
844                                         /* Enable the auto-VGA enable */
845                                         value |= FLD_VGA_AUTO_EN;
846
847                                         /* Write it back */
848                                         status =
849                                             cx231xx_write_i2c_data(dev,
850                                                                    HAMMERHEAD_I2C_ADDRESS,
851                                                                    DFE_CTRL1, 2,
852                                                                    value, 4);
853
854                                         /* Disable auto config of registers */
855                                         status =
856                                             cx231xx_read_modify_write_i2c_dword
857                                             (dev, HAMMERHEAD_I2C_ADDRESS,
858                                              MODE_CTRL, FLD_ACFG_DIS,
859                                              cx231xx_set_field(FLD_ACFG_DIS,
860                                                                1));
861
862                                         /* Set CVBS input mode */
863                                         status =
864                                             cx231xx_read_modify_write_i2c_dword
865                                             (dev, HAMMERHEAD_I2C_ADDRESS,
866                                              MODE_CTRL, FLD_INPUT_MODE,
867                                              cx231xx_set_field(FLD_INPUT_MODE,
868                                                                INPUT_MODE_CVBS_0));
869                                 }
870                                 break;
871                         default:
872                                 {
873                                         /* Enable the DIF for the tuner */
874
875                                         /* Reinitialize the DIF */
876                                         status =
877                                             cx231xx_dif_set_standard(dev,
878                                                                      dev->norm);
879                                         if (status < 0) {
880                                                 cx231xx_errdev
881                                                     ("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n",
882                                                      __func__, status);
883                                                 return status;
884                                         }
885
886                                         /* Make sure bypass is cleared */
887                                         status =
888                                             cx231xx_read_i2c_data(dev,
889                                                                   HAMMERHEAD_I2C_ADDRESS,
890                                                                   DIF_MISC_CTRL,
891                                                                   2, &value, 4);
892
893                                         /* Clear the bypass bit */
894                                         value &= ~FLD_DIF_DIF_BYPASS;
895
896                                         /* Enable the use of the DIF block */
897                                         status =
898                                             cx231xx_write_i2c_data(dev,
899                                                                    HAMMERHEAD_I2C_ADDRESS,
900                                                                    DIF_MISC_CTRL,
901                                                                    2, value, 4);
902
903                                         /* Read the DFE_CTRL1 register */
904                                         status =
905                                             cx231xx_read_i2c_data(dev,
906                                                                   HAMMERHEAD_I2C_ADDRESS,
907                                                                   DFE_CTRL1, 2,
908                                                                   &value, 4);
909
910                                         /* Disable the VBI_GATE_EN */
911                                         value &= ~FLD_VBI_GATE_EN;
912
913                                         /* Enable the auto-VGA enable, AGC, and set the skip count to 2 */
914                                         value |=
915                                             FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN |
916                                             0x00200000;
917
918                                         /* Write it back */
919                                         status =
920                                             cx231xx_write_i2c_data(dev,
921                                                                    HAMMERHEAD_I2C_ADDRESS,
922                                                                    DFE_CTRL1, 2,
923                                                                    value, 4);
924
925                                         /* Wait 15 ms */
926                                         msleep(1);
927
928                                         /* Disable the auto-VGA enable AGC */
929                                         value &= ~(FLD_VGA_AUTO_EN);
930
931                                         /* Write it back */
932                                         status =
933                                             cx231xx_write_i2c_data(dev,
934                                                                    HAMMERHEAD_I2C_ADDRESS,
935                                                                    DFE_CTRL1, 2,
936                                                                    value, 4);
937
938                                         /* Enable Polaris B0 AGC output */
939                                         status =
940                                             cx231xx_read_i2c_data(dev,
941                                                                   HAMMERHEAD_I2C_ADDRESS,
942                                                                   PIN_CTRL, 2,
943                                                                   &value, 4);
944                                         value |=
945                                             (FLD_OEF_AGC_RF) |
946                                             (FLD_OEF_AGC_IFVGA) |
947                                             (FLD_OEF_AGC_IF);
948                                         status =
949                                             cx231xx_write_i2c_data(dev,
950                                                                    HAMMERHEAD_I2C_ADDRESS,
951                                                                    PIN_CTRL, 2,
952                                                                    value, 4);
953
954                                         /* Set vip 1.1 output mode */
955                                         status =
956                                             cx231xx_read_modify_write_i2c_dword
957                                             (dev, HAMMERHEAD_I2C_ADDRESS,
958                                              OUT_CTRL1, FLD_OUT_MODE,
959                                              OUT_MODE_VIP11);
960
961                                         /* Disable auto config of registers */
962                                         status =
963                                             cx231xx_read_modify_write_i2c_dword
964                                             (dev, HAMMERHEAD_I2C_ADDRESS,
965                                              MODE_CTRL, FLD_ACFG_DIS,
966                                              cx231xx_set_field(FLD_ACFG_DIS,
967                                                                1));
968
969                                         /* Set CVBS input mode */
970                                         status =
971                                             cx231xx_read_modify_write_i2c_dword
972                                             (dev, HAMMERHEAD_I2C_ADDRESS,
973                                              MODE_CTRL, FLD_INPUT_MODE,
974                                              cx231xx_set_field(FLD_INPUT_MODE,
975                                                                INPUT_MODE_CVBS_0));
976
977                                         /* Set some bits in AFE_CTRL so that channel 2 or 3 is ready to receive audio */
978                                         /* Clear clamp for channels 2 and 3      (bit 16-17) */
979                                         /* Clear droop comp                      (bit 19-20) */
980                                         /* Set VGA_SEL (for audio control)       (bit 7-8) */
981                                         status =
982                                             cx231xx_read_i2c_data(dev,
983                                                                   HAMMERHEAD_I2C_ADDRESS,
984                                                                   AFE_CTRL, 2,
985                                                                   &value, 4);
986
987                                         value |=
988                                             FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2;
989
990                                         status =
991                                             cx231xx_write_i2c_data(dev,
992                                                                    HAMMERHEAD_I2C_ADDRESS,
993                                                                    AFE_CTRL, 2,
994                                                                    value, 4);
995                                 }
996                                 break;
997
998                         }
999                 }
1000                 break;
1001         }
1002
1003         /* Set raw VBI mode */
1004         status =
1005             cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS,
1006                                                 OUT_CTRL1, FLD_VBIHACTRAW_EN,
1007                                                 cx231xx_set_field
1008                                                 (FLD_VBIHACTRAW_EN, 1));
1009
1010         status =
1011             cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, OUT_CTRL1, 2,
1012                                   &value, 4);
1013         if (value & 0x02) {
1014                 value |= (1 << 19);
1015                 status =
1016                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1017                                            OUT_CTRL1, 2, value, 4);
1018         }
1019
1020         return status;
1021 }
1022
1023 /*
1024  * Handle any video-mode specific overrides that are different on a per video standards
1025  * basis after touching the MODE_CTRL register which resets many values for autodetect
1026  */
1027 int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
1028 {
1029         int status = 0;
1030
1031         cx231xx_info("do_mode_ctrl_overrides : 0x%x\n",
1032                      (unsigned int)dev->norm);
1033
1034         /* Change the DFE_CTRL3 bp_percent to fix flagging */
1035         status =
1036             cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL3, 2,
1037                                    0xCD3F0280, 4);
1038
1039         if (dev->norm & (V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_PAL_M)) {
1040                 cx231xx_info("do_mode_ctrl_overrides NTSC\n");
1041
1042                 /* Move the close caption lines out of active video, adjust the active video start point */
1043                 status =
1044                     cx231xx_read_modify_write_i2c_dword(dev,
1045                                                         HAMMERHEAD_I2C_ADDRESS,
1046                                                         VERT_TIM_CTRL,
1047                                                         FLD_VBLANK_CNT, 0x18);
1048                 status =
1049                     cx231xx_read_modify_write_i2c_dword(dev,
1050                                                         HAMMERHEAD_I2C_ADDRESS,
1051                                                         VERT_TIM_CTRL,
1052                                                         FLD_VACTIVE_CNT,
1053                                                         0x1E6000);
1054                 status =
1055                     cx231xx_read_modify_write_i2c_dword(dev,
1056                                                         HAMMERHEAD_I2C_ADDRESS,
1057                                                         VERT_TIM_CTRL,
1058                                                         FLD_V656BLANK_CNT,
1059                                                         0x1E000000);
1060
1061                 status =
1062                     cx231xx_read_modify_write_i2c_dword(dev,
1063                                                         HAMMERHEAD_I2C_ADDRESS,
1064                                                         HORIZ_TIM_CTRL,
1065                                                         FLD_HBLANK_CNT,
1066                                                         cx231xx_set_field
1067                                                         (FLD_HBLANK_CNT, 0x79));
1068         } else if (dev->
1069                    norm & (V4L2_STD_PAL_B | V4L2_STD_PAL_G | V4L2_STD_PAL_D |
1070                            V4L2_STD_PAL_I | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
1071                 cx231xx_info("do_mode_ctrl_overrides PAL\n");
1072                 status =
1073                     cx231xx_read_modify_write_i2c_dword(dev,
1074                                                         HAMMERHEAD_I2C_ADDRESS,
1075                                                         VERT_TIM_CTRL,
1076                                                         FLD_VBLANK_CNT, 0x24);
1077                 /* Adjust the active video horizontal start point */
1078                 status =
1079                     cx231xx_read_modify_write_i2c_dword(dev,
1080                                                         HAMMERHEAD_I2C_ADDRESS,
1081                                                         HORIZ_TIM_CTRL,
1082                                                         FLD_HBLANK_CNT,
1083                                                         cx231xx_set_field
1084                                                         (FLD_HBLANK_CNT, 0x85));
1085         } else if (dev->
1086                    norm & (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D |
1087                            V4L2_STD_SECAM_G | V4L2_STD_SECAM_K |
1088                            V4L2_STD_SECAM_K1 | V4L2_STD_SECAM_L |
1089                            V4L2_STD_SECAM_LC)) {
1090                 cx231xx_info("do_mode_ctrl_overrides SECAM\n");
1091                 status =
1092                     cx231xx_read_modify_write_i2c_dword(dev,
1093                                                         HAMMERHEAD_I2C_ADDRESS,
1094                                                         VERT_TIM_CTRL,
1095                                                         FLD_VBLANK_CNT, 0x24);
1096                 /* Adjust the active video horizontal start point */
1097                 status =
1098                     cx231xx_read_modify_write_i2c_dword(dev,
1099                                                         HAMMERHEAD_I2C_ADDRESS,
1100                                                         HORIZ_TIM_CTRL,
1101                                                         FLD_HBLANK_CNT,
1102                                                         cx231xx_set_field
1103                                                         (FLD_HBLANK_CNT, 0x85));
1104         }
1105
1106         return status;
1107 }
1108
1109 int cx231xx_set_audio_input(struct cx231xx *dev, u8 input)
1110 {
1111         int status = 0;
1112         enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE;
1113
1114         switch (INPUT(input)->amux) {
1115         case CX231XX_AMUX_VIDEO:
1116                 ainput = AUDIO_INPUT_TUNER_TV;
1117                 break;
1118         case CX231XX_AMUX_LINE_IN:
1119                 status = cx231xx_flatiron_set_audio_input(dev, input);
1120                 ainput = AUDIO_INPUT_LINE;
1121                 break;
1122         default:
1123                 break;
1124         }
1125
1126         status = cx231xx_set_audio_decoder_input(dev, ainput);
1127
1128         return status;
1129 }
1130
1131 int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
1132                                     enum AUDIO_INPUT audio_input)
1133 {
1134         u32 dwval;
1135         int status;
1136         u32 gen_ctrl;
1137         u32 value = 0;
1138
1139         /* Put it in soft reset   */
1140         status =
1141             cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, GENERAL_CTL, 2,
1142                                   &gen_ctrl, 1);
1143         gen_ctrl |= 1;
1144         status =
1145             cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, GENERAL_CTL, 2,
1146                                    gen_ctrl, 1);
1147
1148         switch (audio_input) {
1149         case AUDIO_INPUT_LINE:
1150
1151                 /* setup AUD_IO control from Merlin paralle output */
1152                 value =
1153                     cx231xx_set_field(FLD_AUD_CHAN1_SRC, AUD_CHAN_SRC_PARALLEL);
1154                 status =
1155                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1156                                            AUD_IO_CTRL, 2, value, 4);
1157
1158                 /* setup input to Merlin, SRC2 connect to AC97
1159                    bypass upsample-by-2, slave mode, sony mode, left justify
1160                    adr 091c, dat 01000000 */
1161                 status =
1162                     cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AC97_CTL,
1163                                           2, &dwval, 4);
1164
1165                 status =
1166                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1167                                            AC97_CTL, 2,
1168                                            (dwval | FLD_AC97_UP2X_BYPASS), 4);
1169
1170                 /* select the parallel1 and SRC3 */
1171                 status =
1172                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1173                                            BAND_OUT_SEL, 2,
1174                                            cx231xx_set_field(FLD_SRC3_IN_SEL,
1175                                                              0x0) |
1176                                            cx231xx_set_field(FLD_SRC3_CLK_SEL,
1177                                                              0x0) |
1178                                            cx231xx_set_field
1179                                            (FLD_PARALLEL1_SRC_SEL, 0x0), 4);
1180
1181                 /* unmute all, AC97 in, independence mode
1182                    adr 08d0, data 0x00063073 */
1183                 status =
1184                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1185                                            PATH1_CTL1, 2, 0x00063073, 4);
1186
1187                 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */
1188                 status =
1189                     cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1190                                           PATH1_VOL_CTL, 2, &dwval, 4);
1191                 status =
1192                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1193                                            PATH1_VOL_CTL, 2,
1194                                            (dwval | FLD_PATH1_AVC_THRESHOLD),
1195                                            4);
1196
1197                 /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */
1198                 status =
1199                     cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1200                                           PATH1_SC_CTL, 2, &dwval, 4);
1201                 status =
1202                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1203                                            PATH1_SC_CTL, 2,
1204                                            (dwval | FLD_PATH1_SC_THRESHOLD), 4);
1205                 break;
1206
1207         case AUDIO_INPUT_TUNER_TV:
1208         default:
1209
1210                 /* Setup SRC sources and clocks */
1211                 status =
1212                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1213                                            BAND_OUT_SEL, 2,
1214                                            cx231xx_set_field(FLD_SRC6_IN_SEL,
1215                                                              0x00) |
1216                                            cx231xx_set_field(FLD_SRC6_CLK_SEL,
1217                                                              0x01) |
1218                                            cx231xx_set_field(FLD_SRC5_IN_SEL,
1219                                                              0x00) |
1220                                            cx231xx_set_field(FLD_SRC5_CLK_SEL,
1221                                                              0x02) |
1222                                            cx231xx_set_field(FLD_SRC4_IN_SEL,
1223                                                              0x02) |
1224                                            cx231xx_set_field(FLD_SRC4_CLK_SEL,
1225                                                              0x03) |
1226                                            cx231xx_set_field(FLD_SRC3_IN_SEL,
1227                                                              0x00) |
1228                                            cx231xx_set_field(FLD_SRC3_CLK_SEL,
1229                                                              0x00) |
1230                                            cx231xx_set_field
1231                                            (FLD_BASEBAND_BYPASS_CTL,
1232                                             0x00) |
1233                                            cx231xx_set_field(FLD_AC97_SRC_SEL,
1234                                                              0x03) |
1235                                            cx231xx_set_field(FLD_I2S_SRC_SEL,
1236                                                              0x00) |
1237                                            cx231xx_set_field
1238                                            (FLD_PARALLEL2_SRC_SEL,
1239                                             0x02) |
1240                                            cx231xx_set_field
1241                                            (FLD_PARALLEL1_SRC_SEL, 0x01), 4);
1242
1243                 /* Setup the AUD_IO control */
1244                 status =
1245                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1246                                            AUD_IO_CTRL, 2,
1247                                            cx231xx_set_field(FLD_I2S_PORT_DIR,
1248                                                              0x00) |
1249                                            cx231xx_set_field(FLD_I2S_OUT_SRC,
1250                                                              0x00) |
1251                                            cx231xx_set_field(FLD_AUD_CHAN3_SRC,
1252                                                              0x00) |
1253                                            cx231xx_set_field(FLD_AUD_CHAN2_SRC,
1254                                                              0x00) |
1255                                            cx231xx_set_field(FLD_AUD_CHAN1_SRC,
1256                                                              0x03), 4);
1257
1258                 status =
1259                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1260                                            PATH1_CTL1, 2, 0x1F063870, 4);
1261
1262                 /* setAudioStandard(_audio_standard); */
1263
1264                 status =
1265                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1266                                            PATH1_CTL1, 2, 0x00063870, 4);
1267                 switch (dev->model) {
1268                 case CX231XX_BOARD_CNXT_RDE_250:
1269                 case CX231XX_BOARD_CNXT_RDU_250:
1270                         status =
1271                             cx231xx_read_modify_write_i2c_dword(dev,
1272                                                                 HAMMERHEAD_I2C_ADDRESS,
1273                                                                 CHIP_CTRL,
1274                                                                 FLD_SIF_EN,
1275                                                                 cx231xx_set_field
1276                                                                 (FLD_SIF_EN,
1277                                                                  1));
1278                         break;
1279                 default:
1280                         break;
1281                 }
1282                 break;
1283
1284         case AUDIO_INPUT_TUNER_FM:
1285                 /*  use SIF for FM radio
1286                    setupFM();
1287                    setAudioStandard(_audio_standard);
1288                  */
1289                 break;
1290
1291         case AUDIO_INPUT_MUTE:
1292                 status =
1293                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1294                                            PATH1_CTL1, 2, 0x1F011012, 4);
1295                 break;
1296         }
1297
1298         /* Take it out of soft reset */
1299         status =
1300             cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, GENERAL_CTL, 2,
1301                                   &gen_ctrl, 1);
1302         gen_ctrl &= ~1;
1303         status =
1304             cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, GENERAL_CTL, 2,
1305                                    gen_ctrl, 1);
1306
1307         return status;
1308 }
1309
1310 /* Set resolution of the video */
1311 int cx231xx_resolution_set(struct cx231xx *dev)
1312 {
1313         int width, height;
1314         u32 hscale, vscale;
1315         int status = 0;
1316
1317         width = dev->width;
1318         height = dev->height;
1319
1320         get_scale(dev, width, height, &hscale, &vscale);
1321
1322         /* set horzontal scale */
1323         status =
1324             cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, HSCALE_CTRL, 2,
1325                                    hscale, 4);
1326
1327         /* set vertical scale */
1328         status =
1329             cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, VSCALE_CTRL, 2,
1330                                    vscale, 4);
1331
1332         return status;
1333 }
1334
1335 /*************************************************************************************
1336  *                        C H I P Specific  C O N T R O L   functions                *
1337  *************************************************************************************/
1338 int cx231xx_init_ctrl_pin_status(struct cx231xx *dev)
1339 {
1340         u32 value;
1341         int status = 0;
1342
1343         status =
1344             cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL, 2,
1345                                   &value, 4);
1346         value |= (~dev->board.ctl_pin_status_mask);
1347         status =
1348             cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL, 2,
1349                                    value, 4);
1350
1351         return status;
1352 }
1353
1354 int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev,
1355                                               u8 analog_or_digital)
1356 {
1357         int status = 0;
1358
1359         /* first set the direction to output */
1360         status =
1361             cx231xx_set_gpio_direction(dev,
1362                                        dev->board.
1363                                        agc_analog_digital_select_gpio, 1);
1364
1365         /* 0 - demod ; 1 - Analog mode */
1366         status =
1367             cx231xx_set_gpio_value(dev,
1368                                    dev->board.agc_analog_digital_select_gpio,
1369                                    analog_or_digital);
1370
1371         return status;
1372 }
1373
1374 int cx231xx_enable_i2c_for_tuner(struct cx231xx *dev, u8 I2CIndex)
1375 {
1376         u8 value[4] = { 0, 0, 0, 0 };
1377         int status = 0;
1378
1379         cx231xx_info("Changing the i2c port for tuner to %d\n", I2CIndex);
1380
1381         status =
1382             cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 4);
1383         if (status < 0)
1384                 return status;
1385
1386         if (I2CIndex == I2C_1) {
1387                 if (value[0] & I2C_DEMOD_EN) {
1388                         value[0] &= ~I2C_DEMOD_EN;
1389                         status =
1390                             cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1391                                                    PWR_CTL_EN, value, 4);
1392                 }
1393         } else {
1394                 if (!(value[0] & I2C_DEMOD_EN)) {
1395                         value[0] |= I2C_DEMOD_EN;
1396                         status =
1397                             cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1398                                                    PWR_CTL_EN, value, 4);
1399                 }
1400         }
1401
1402         return status;
1403
1404 }
1405
1406 /*************************************************************************************
1407  *                     D I F - B L O C K    C O N T R O L   functions                *
1408  *************************************************************************************/
1409 int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
1410                                           u32 function_mode, u32 standard)
1411 {
1412         int status = 0;
1413
1414         if (mode == V4L2_TUNER_RADIO) {
1415                 /* C2HH */
1416                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);  /* lo if big signal */
1417                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode);        /* FUNC_MODE = DIF */
1418                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF); /* IF_MODE */
1419                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);    /* no inv */
1420         } else {
1421                 switch (standard) {
1422                 case V4L2_STD_NTSC_M:   /* 75 IRE Setup */
1423                 case V4L2_STD_NTSC_M_JP:        /* Japan,  0 IRE Setup */
1424                 case V4L2_STD_PAL_M:
1425                 case V4L2_STD_PAL_N:
1426                 case V4L2_STD_PAL_Nc:
1427                         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);  /* lo if big signal */
1428                         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode);        /* FUNC_MODE = DIF */
1429                         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb);  /* IF_MODE */
1430                         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);    /* no inv */
1431                         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AUD_IO_CTRL, 0, 31, 0x00000003);       /* 0x124, AUD_CHAN1_SRC = 0x3 */
1432                         break;
1433
1434                 case V4L2_STD_PAL_B:
1435                 case V4L2_STD_PAL_G:
1436                         /* C2HH setup */
1437                         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);  /* lo if big signal */
1438                         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode);        /* FUNC_MODE = DIF */
1439                         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE);  /* IF_MODE */
1440                         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);    /* no inv */
1441                         break;
1442
1443                 case V4L2_STD_PAL_D:
1444                 case V4L2_STD_PAL_I:
1445                 case V4L2_STD_SECAM_L:
1446                 case V4L2_STD_SECAM_LC:
1447                 case V4L2_STD_SECAM_B:
1448                 case V4L2_STD_SECAM_D:
1449                 case V4L2_STD_SECAM_G:
1450                 case V4L2_STD_SECAM_K:
1451                 case V4L2_STD_SECAM_K1:
1452                         /* C2HH setup */
1453                         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);  /* lo if big signal */
1454                         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode);        /* FUNC_MODE = DIF */
1455                         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF);  /* IF_MODE */
1456                         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);    /* no inv */
1457                         break;
1458
1459                 case DIF_USE_BASEBAND:
1460                 default:
1461                         /* do nothing to config C2HH for baseband */
1462                         break;
1463                 }
1464         }
1465
1466         return status;
1467 }
1468
1469 int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1470 {
1471         int status = 0;
1472         u32 dif_misc_ctrl_value = 0;
1473         u32 func_mode = 0;
1474
1475         cx231xx_info("%s: setStandard to %x\n", __func__, standard);
1476
1477         status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1478                                        DIF_MISC_CTRL, 2, &dif_misc_ctrl_value,
1479                                        4);
1480         if (standard != DIF_USE_BASEBAND)
1481                 dev->norm = standard;
1482
1483         switch (dev->model) {
1484         case CX231XX_BOARD_CNXT_RDE_250:
1485         case CX231XX_BOARD_CNXT_RDU_250:
1486                 func_mode = 0x03;
1487                 break;
1488         default:
1489                 func_mode = 0x01;
1490         }
1491
1492         status =
1493             cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1494                                                   func_mode, standard);
1495
1496         if (standard == DIF_USE_BASEBAND) {     /* base band */
1497
1498                 /* There is a different SRC_PHASE_INC value for baseband vs. DIF */
1499                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1500                                                 DIF_SRC_PHASE_INC, 2, 0xDF7DF83,
1501                                                 4);
1502                 status =
1503                     cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1504                                           DIF_MISC_CTRL, 2,
1505                                           &dif_misc_ctrl_value, 4);
1506                 dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS;
1507                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1508                                                 DIF_MISC_CTRL, 2,
1509                                                 dif_misc_ctrl_value, 4);
1510
1511         } else if (standard & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) {
1512
1513                 status =
1514                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1515                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1516                 status =
1517                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1518                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1519                 status =
1520                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1521                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1522                 status =
1523                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1524                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
1525                 status =
1526                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1527                                            DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1528                 status =
1529                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1530                                            DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1531                 status =
1532                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1533                                            DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1534                 status =
1535                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1536                                            DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1537                 status =
1538                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1539                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
1540                                            0x26001700);
1541                 status =
1542                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1543                                            DIF_AGC_RF_CURRENT, 0, 31,
1544                                            0x00002660);
1545                 status =
1546                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1547                                            DIF_VIDEO_AGC_CTRL, 0, 31,
1548                                            0x72500800);
1549                 status =
1550                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1551                                            DIF_VID_AUD_OVERRIDE, 0, 31,
1552                                            0x27000100);
1553                 status =
1554                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1555                                            DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC);
1556                 status =
1557                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1558                                            DIF_COMP_FLT_CTRL, 0, 31,
1559                                            0x00A653A8);
1560                 status =
1561                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1562                                            DIF_SRC_PHASE_INC, 0, 31,
1563                                            0x1befbf06);
1564                 status =
1565                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1566                                            DIF_SRC_GAIN_CONTROL, 0, 31,
1567                                            0x000035e8);
1568                 status =
1569                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1570                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1571                 /* Save the Spec Inversion value */
1572                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1573                 dif_misc_ctrl_value |= 0x3a013F11;
1574
1575         } else if (standard & V4L2_STD_PAL_D) {
1576
1577                 status =
1578                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1579                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1580                 status =
1581                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1582                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1583                 status =
1584                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1585                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1586                 status =
1587                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1588                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
1589                 status =
1590                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1591                                            DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1592                 status =
1593                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1594                                            DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1595                 status =
1596                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1597                                            DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1598                 status =
1599                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1600                                            DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1601                 status =
1602                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1603                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
1604                                            0x26001700);
1605                 status =
1606                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1607                                            DIF_AGC_RF_CURRENT, 0, 31,
1608                                            0x00002660);
1609                 status =
1610                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1611                                            DIF_VIDEO_AGC_CTRL, 0, 31,
1612                                            0x72500800);
1613                 status =
1614                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1615                                            DIF_VID_AUD_OVERRIDE, 0, 31,
1616                                            0x27000100);
1617                 status =
1618                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1619                                            DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA);
1620                 status =
1621                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1622                                            DIF_COMP_FLT_CTRL, 0, 31,
1623                                            0x00000000);
1624                 status =
1625                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1626                                            DIF_SRC_PHASE_INC, 0, 31,
1627                                            0x1befbf06);
1628                 status =
1629                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1630                                            DIF_SRC_GAIN_CONTROL, 0, 31,
1631                                            0x000035e8);
1632                 status =
1633                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1634                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1635                 /* Save the Spec Inversion value */
1636                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1637                 dif_misc_ctrl_value |= 0x3a023F11;
1638
1639         } else if (standard & V4L2_STD_PAL_I) {
1640
1641                 status =
1642                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1643                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1644                 status =
1645                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1646                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1647                 status =
1648                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1649                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1650                 status =
1651                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1652                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
1653                 status =
1654                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1655                                            DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1656                 status =
1657                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1658                                            DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1659                 status =
1660                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1661                                            DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1662                 status =
1663                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1664                                            DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1665                 status =
1666                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1667                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
1668                                            0x26001700);
1669                 status =
1670                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1671                                            DIF_AGC_RF_CURRENT, 0, 31,
1672                                            0x00002660);
1673                 status =
1674                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1675                                            DIF_VIDEO_AGC_CTRL, 0, 31,
1676                                            0x72500800);
1677                 status =
1678                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1679                                            DIF_VID_AUD_OVERRIDE, 0, 31,
1680                                            0x27000100);
1681                 status =
1682                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1683                                            DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934);
1684                 status =
1685                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1686                                            DIF_COMP_FLT_CTRL, 0, 31,
1687                                            0x00000000);
1688                 status =
1689                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1690                                            DIF_SRC_PHASE_INC, 0, 31,
1691                                            0x1befbf06);
1692                 status =
1693                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1694                                            DIF_SRC_GAIN_CONTROL, 0, 31,
1695                                            0x000035e8);
1696                 status =
1697                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1698                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1699                 /* Save the Spec Inversion value */
1700                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1701                 dif_misc_ctrl_value |= 0x3a033F11;
1702
1703         } else if (standard & V4L2_STD_PAL_M) {
1704
1705                 /* improved Low Frequency Phase Noise */
1706                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1707                                                 DIF_PLL_CTRL, 2, 0xFF01FF0C, 4);
1708                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1709                                                 DIF_PLL_CTRL1, 2, 0xbd038c85,
1710                                                 4);
1711                 status =
1712                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1713                                            DIF_PLL_CTRL2, 2, 0x1db4640a, 4);
1714                 status =
1715                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1716                                            DIF_PLL_CTRL3, 2, 0x00008800, 4);
1717                 status =
1718                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1719                                            DIF_AGC_IF_REF, 2, 0x444C1380, 4);
1720                 status =
1721                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1722                                            DIF_AGC_IF_INT_CURRENT, 2,
1723                                            0x26001700, 4);
1724                 status =
1725                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1726                                            DIF_AGC_RF_CURRENT, 2, 0x00002660,
1727                                            4);
1728                 status =
1729                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1730                                            DIF_VIDEO_AGC_CTRL, 2, 0x72500800,
1731                                            4);
1732                 status =
1733                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1734                                            DIF_VID_AUD_OVERRIDE, 2, 0x27000100,
1735                                            4);
1736                 status =
1737                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1738                                            DIF_AV_SEP_CTRL, 2, 0x012c405d, 4);
1739                 status =
1740                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1741                                            DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4);
1742                 status =
1743                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1744                                            DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4);
1745                 status =
1746                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1747                                            DIF_SRC_GAIN_CONTROL, 2, 0x000035e8,
1748                                            4);
1749                 status =
1750                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1751                                            DIF_SOFT_RST_CTRL_REVB, 2,
1752                                            0x00000000, 4);
1753
1754                 /* Save the Spec Inversion value */
1755                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1756                 dif_misc_ctrl_value |= 0x3A0A3F10;
1757
1758         } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
1759
1760                 /* improved Low Frequency Phase Noise */
1761                 status =
1762                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1763                                            DIF_PLL_CTRL, 2, 0xFF01FF0C, 4);
1764                 status =
1765                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1766                                            DIF_PLL_CTRL1, 2, 0xbd038c85, 4);
1767                 status =
1768                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1769                                            DIF_PLL_CTRL2, 2, 0x1db4640a, 4);
1770                 status =
1771                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1772                                            DIF_PLL_CTRL3, 2, 0x00008800, 4);
1773                 status =
1774                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1775                                            DIF_AGC_IF_REF, 2, 0x444C1380, 4);
1776                 status =
1777                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1778                                            DIF_AGC_IF_INT_CURRENT, 2,
1779                                            0x26001700, 4);
1780                 status =
1781                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1782                                            DIF_AGC_RF_CURRENT, 2, 0x00002660,
1783                                            4);
1784                 status =
1785                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1786                                            DIF_VIDEO_AGC_CTRL, 2, 0x72500800,
1787                                            4);
1788                 status =
1789                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1790                                            DIF_VID_AUD_OVERRIDE, 2, 0x27000100,
1791                                            4);
1792                 status =
1793                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1794                                            DIF_AV_SEP_CTRL, 2, 0x012c405d, 4);
1795                 status =
1796                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1797                                            DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4);
1798                 status =
1799                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1800                                            DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4);
1801                 status =
1802                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1803                                            DIF_SRC_GAIN_CONTROL, 2, 0x000035e8,
1804                                            4);
1805                 status =
1806                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1807                                            DIF_SOFT_RST_CTRL_REVB, 2,
1808                                            0x00000000, 4);
1809
1810                 /* Save the Spec Inversion value */
1811                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1812                 dif_misc_ctrl_value = 0x3A093F10;
1813
1814         } else if (standard &
1815                    (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G |
1816                     V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) {
1817
1818                 status =
1819                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1820                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1821                 status =
1822                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1823                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1824                 status =
1825                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1826                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1827                 status =
1828                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1829                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
1830                 status =
1831                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1832                                            DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1833                 status =
1834                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1835                                            DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1836                 status =
1837                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1838                                            DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1839                 status =
1840                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1841                                            DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1842                 status =
1843                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1844                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
1845                                            0x26001700);
1846                 status =
1847                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1848                                            DIF_AGC_RF_CURRENT, 0, 31,
1849                                            0x00002660);
1850                 status =
1851                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1852                                            DIF_VID_AUD_OVERRIDE, 0, 31,
1853                                            0x27000100);
1854                 status =
1855                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1856                                            DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1857                 status =
1858                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1859                                            DIF_COMP_FLT_CTRL, 0, 31,
1860                                            0x00000000);
1861                 status =
1862                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1863                                            DIF_SRC_PHASE_INC, 0, 31,
1864                                            0x1befbf06);
1865                 status =
1866                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1867                                            DIF_SRC_GAIN_CONTROL, 0, 31,
1868                                            0x000035e8);
1869                 status =
1870                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1871                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1872                 status =
1873                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1874                                            DIF_VIDEO_AGC_CTRL, 0, 31,
1875                                            0xf4000000);
1876
1877                 /* Save the Spec Inversion value */
1878                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1879                 dif_misc_ctrl_value |= 0x3a023F11;
1880
1881         } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) {
1882
1883                 /* Is it SECAM_L1? */
1884                 status =
1885                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1886                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1887                 status =
1888                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1889                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1890                 status =
1891                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1892                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1893                 status =
1894                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1895                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
1896                 status =
1897                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1898                                            DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1899                 status =
1900                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1901                                            DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1902                 status =
1903                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1904                                            DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1905                 status =
1906                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1907                                            DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1908                 status =
1909                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1910                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
1911                                            0x26001700);
1912                 status =
1913                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1914                                            DIF_AGC_RF_CURRENT, 0, 31,
1915                                            0x00002660);
1916                 status =
1917                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1918                                            DIF_VID_AUD_OVERRIDE, 0, 31,
1919                                            0x27000100);
1920                 status =
1921                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1922                                            DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1923                 status =
1924                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1925                                            DIF_COMP_FLT_CTRL, 0, 31,
1926                                            0x00000000);
1927                 status =
1928                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1929                                            DIF_SRC_PHASE_INC, 0, 31,
1930                                            0x1befbf06);
1931                 status =
1932                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1933                                            DIF_SRC_GAIN_CONTROL, 0, 31,
1934                                            0x000035e8);
1935                 status =
1936                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1937                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1938                 status =
1939                     cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1940                                            DIF_VIDEO_AGC_CTRL, 0, 31,
1941                                            0xf2560000);
1942
1943                 /* Save the Spec Inversion value */
1944                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1945                 dif_misc_ctrl_value |= 0x3a023F11;
1946
1947         } else {                /* V4L2_STD_NTSC_M (75 IRE Setup) Or  V4L2_STD_NTSC_M_JP (Japan,  0 IRE Setup) */
1948
1949                 /* For NTSC the centre frequency of video coming out of sidewinder is
1950                    around 7.1MHz or 3.6MHz depending on the spectral inversion.
1951                    so for a non spectrally inverted channel the pll freq word is 0x03420c49
1952                  */
1953
1954                 status =
1955                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1956                                            DIF_PLL_CTRL, 2, 0x6503BC0C, 4);
1957                 status =
1958                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1959                                            DIF_PLL_CTRL1, 2, 0xBD038C85, 4);
1960                 status =
1961                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1962                                            DIF_PLL_CTRL2, 2, 0x1DB4640A, 4);
1963                 status =
1964                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1965                                            DIF_PLL_CTRL3, 2, 0x00008800, 4);
1966                 status =
1967                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1968                                            DIF_AGC_IF_REF, 2, 0x444C0380, 4);
1969                 status =
1970                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1971                                            DIF_AGC_IF_INT_CURRENT, 2,
1972                                            0x26001700, 4);
1973                 status =
1974                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1975                                            DIF_AGC_RF_CURRENT, 2, 0x00002660,
1976                                            4);
1977                 status =
1978                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1979                                            DIF_VIDEO_AGC_CTRL, 2, 0x04000800,
1980                                            4);
1981                 status =
1982                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1983                                            DIF_VID_AUD_OVERRIDE, 2, 0x27000100,
1984                                            4);
1985                 status =
1986                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1987                                            DIF_AV_SEP_CTRL, 2, 0x01296e1f, 4);
1988
1989                 status =
1990                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1991                                            DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4);
1992                 status =
1993                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1994                                            DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4);
1995                 status =
1996                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1997                                            DIF_SRC_GAIN_CONTROL, 2, 0x000035e8,
1998                                            4);
1999
2000                 status =
2001                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
2002                                            DIF_AGC_CTRL_IF, 2, 0xC2262600, 4);
2003                 status =
2004                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
2005                                            DIF_AGC_CTRL_INT, 2, 0xC2262600, 4);
2006                 status =
2007                     cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
2008                                            DIF_AGC_CTRL_RF, 2, 0xC2262600, 4);
2009
2010                 /* Save the Spec Inversion value */
2011                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2012                 dif_misc_ctrl_value |= 0x3a003F10;
2013
2014         }
2015
2016         /* The AGC values should be the same for all standards,
2017            AUD_SRC_SEL[19] should always be disabled    */
2018         dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL;
2019
2020         /* It is still possible to get Set Standard calls even when we are in FM mode
2021            This is done to override the value for FM. */
2022         if (dev->active_mode == V4L2_TUNER_RADIO)
2023                 dif_misc_ctrl_value = 0x7a080000;
2024
2025         /* Write the calculated value for misc ontrol register      */
2026         status =
2027             cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_MISC_CTRL,
2028                                    2, dif_misc_ctrl_value, 4);
2029
2030         return status;
2031 }
2032
2033 int cx231xx_tuner_pre_channel_change(struct cx231xx *dev)
2034 {
2035         int status = 0;
2036         u32 dwval;
2037
2038         /* Set the RF and IF k_agc values to 3 */
2039         status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
2040                                        DIF_AGC_IF_REF, 2, &dwval, 4);
2041         dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
2042         dwval |= 0x33000000;
2043
2044         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
2045                                         DIF_AGC_IF_REF, 2, dwval, 4);
2046
2047         return status;
2048 }
2049
2050 int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
2051 {
2052         int status = 0;
2053         u32 dwval;
2054
2055         /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for SECAM */
2056         status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
2057                                        DIF_AGC_IF_REF, 2, &dwval, 4);
2058         dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
2059
2060         if (dev->
2061             norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B | V4L2_STD_SECAM_D)) {
2062                 dwval |= 0x88000000;
2063         } else {
2064                 dwval |= 0x44000000;
2065         }
2066
2067         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
2068                                         DIF_AGC_IF_REF, 2, dwval, 4);
2069
2070         return status;
2071 }
2072
2073 /*************************************************************************************
2074  *            F L A T I R O N - B L O C K    C O N T R O L   functions               *
2075  *************************************************************************************/
2076 int cx231xx_flatiron_initialize(struct cx231xx *dev)
2077 {
2078         int status = 0;
2079         u32 value;
2080
2081         status =
2082             cx231xx_read_i2c_data(dev, Flatrion_DEVICE_ADDRESS, CH_PWR_CTRL1, 1,
2083                                   &value, 1);
2084         /* enables clock to delta-sigma and decimation filter */
2085         value |= 0x80;
2086         status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS,
2087                                         CH_PWR_CTRL1, 1, value, 1);
2088         /* power up all channel */
2089         status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS,
2090                                         CH_PWR_CTRL2, 1, 0x00, 1);
2091
2092         return status;
2093 }
2094
2095 int cx231xx_flatiron_update_power_control(struct cx231xx *dev, AV_MODE avmode)
2096 {
2097         int status = 0;
2098         u32 value = 0;
2099
2100         if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) {
2101                 status =
2102                     cx231xx_read_i2c_data(dev, Flatrion_DEVICE_ADDRESS,
2103                                           CH_PWR_CTRL2, 1, &value, 1);
2104                 value |= 0xfe;
2105                 status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS,
2106                                                 CH_PWR_CTRL2, 1, value, 1);
2107         } else {
2108                 status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS,
2109                                                 CH_PWR_CTRL2, 1, 0x00, 1);
2110         }
2111
2112         return status;
2113 }
2114
2115 /* set flatiron for audio input types */
2116 int cx231xx_flatiron_set_audio_input(struct cx231xx *dev, u8 audio_input)
2117 {
2118         int status = 0;
2119
2120         switch (audio_input) {
2121         case CX231XX_AMUX_LINE_IN:
2122
2123                 status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS,
2124                                                 CH_PWR_CTRL2, 1, 0x00, 1);
2125                 status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS,
2126                                                 CH_PWR_CTRL1, 1, 0x80, 1);
2127                 break;
2128         case CX231XX_AMUX_VIDEO:
2129         default:
2130                 break;
2131         }
2132
2133         dev->ctl_ainput = audio_input;
2134
2135         return status;
2136 }
2137
2138 /*************************************************************************************
2139  *                      P O W E R      C O N T R O L   functions                     *
2140  *************************************************************************************/
2141 int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode)
2142 {
2143         u8 value[4] = { 0, 0, 0, 0 };
2144         u32 tmp = 0;
2145         int status = 0;
2146
2147         if (dev->power_mode != mode)
2148                 dev->power_mode = mode;
2149         else {
2150                 cx231xx_info(" setPowerMode::mode = %d, No Change req.\n",
2151                              mode);
2152                 return 0;
2153         }
2154
2155         cx231xx_info(" setPowerMode::mode = %d\n", mode);
2156
2157         status =
2158             cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 4);
2159         if (status < 0)
2160                 return status;
2161
2162         tmp = *((u32 *) value);
2163
2164         switch (mode) {
2165         case POLARIS_AVMODE_ENXTERNAL_AV:
2166
2167                 tmp &= (~PWR_MODE_MASK);
2168
2169                 tmp |= PWR_AV_EN;
2170                 value[0] = (u8) tmp;
2171                 value[1] = (u8) (tmp >> 8);
2172                 value[2] = (u8) (tmp >> 16);
2173                 value[3] = (u8) (tmp >> 24);
2174                 status =
2175                     cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2176                                            value, 4);
2177                 msleep(PWR_SLEEP_INTERVAL);
2178
2179                 tmp |= PWR_ISO_EN;
2180                 value[0] = (u8) tmp;
2181                 value[1] = (u8) (tmp >> 8);
2182                 value[2] = (u8) (tmp >> 16);
2183                 value[3] = (u8) (tmp >> 24);
2184                 status =
2185                     cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2186                                            value, 4);
2187                 msleep(PWR_SLEEP_INTERVAL);
2188
2189                 tmp |= POLARIS_AVMODE_ENXTERNAL_AV;
2190                 value[0] = (u8) tmp;
2191                 value[1] = (u8) (tmp >> 8);
2192                 value[2] = (u8) (tmp >> 16);
2193                 value[3] = (u8) (tmp >> 24);
2194                 status =
2195                     cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2196                                            value, 4);
2197
2198                 dev->xc_fw_load_done = 0;       /* reset state of xceive tuner */
2199                 break;
2200
2201         case POLARIS_AVMODE_ANALOGT_TV:
2202
2203                 tmp &= (~PWR_DEMOD_EN);
2204                 tmp |= (I2C_DEMOD_EN);
2205                 value[0] = (u8) tmp;
2206                 value[1] = (u8) (tmp >> 8);
2207                 value[2] = (u8) (tmp >> 16);
2208                 value[3] = (u8) (tmp >> 24);
2209                 status =
2210                     cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2211                                            value, 4);
2212                 msleep(PWR_SLEEP_INTERVAL);
2213
2214                 if (!(tmp & PWR_TUNER_EN)) {
2215                         tmp |= (PWR_TUNER_EN);
2216                         value[0] = (u8) tmp;
2217                         value[1] = (u8) (tmp >> 8);
2218                         value[2] = (u8) (tmp >> 16);
2219                         value[3] = (u8) (tmp >> 24);
2220                         status =
2221                             cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2222                                                    PWR_CTL_EN, value, 4);
2223                         msleep(PWR_SLEEP_INTERVAL);
2224                 }
2225
2226                 if (!(tmp & PWR_AV_EN)) {
2227                         tmp |= PWR_AV_EN;
2228                         value[0] = (u8) tmp;
2229                         value[1] = (u8) (tmp >> 8);
2230                         value[2] = (u8) (tmp >> 16);
2231                         value[3] = (u8) (tmp >> 24);
2232                         status =
2233                             cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2234                                                    PWR_CTL_EN, value, 4);
2235                         msleep(PWR_SLEEP_INTERVAL);
2236                 }
2237                 if (!(tmp & PWR_ISO_EN)) {
2238                         tmp |= PWR_ISO_EN;
2239                         value[0] = (u8) tmp;
2240                         value[1] = (u8) (tmp >> 8);
2241                         value[2] = (u8) (tmp >> 16);
2242                         value[3] = (u8) (tmp >> 24);
2243                         status =
2244                             cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2245                                                    PWR_CTL_EN, value, 4);
2246                         msleep(PWR_SLEEP_INTERVAL);
2247                 }
2248
2249                 if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) {
2250                         tmp |= POLARIS_AVMODE_ANALOGT_TV;
2251                         value[0] = (u8) tmp;
2252                         value[1] = (u8) (tmp >> 8);
2253                         value[2] = (u8) (tmp >> 16);
2254                         value[3] = (u8) (tmp >> 24);
2255                         status =
2256                             cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2257                                                    PWR_CTL_EN, value, 4);
2258                         msleep(PWR_SLEEP_INTERVAL);
2259                 }
2260
2261                 if ((dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
2262                     (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
2263
2264                         /* tuner path to channel 1 from port 3 */
2265                         cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2266
2267                         if (dev->cx231xx_reset_analog_tuner)
2268                                 dev->cx231xx_reset_analog_tuner(dev);
2269                 }
2270                 break;
2271
2272         case POLARIS_AVMODE_DIGITAL:
2273
2274                 if (!(tmp & PWR_TUNER_EN)) {
2275                         tmp |= (PWR_TUNER_EN);
2276                         value[0] = (u8) tmp;
2277                         value[1] = (u8) (tmp >> 8);
2278                         value[2] = (u8) (tmp >> 16);
2279                         value[3] = (u8) (tmp >> 24);
2280                         status =
2281                             cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2282                                                    PWR_CTL_EN, value, 4);
2283                         msleep(PWR_SLEEP_INTERVAL);
2284                 }
2285                 if (!(tmp & PWR_AV_EN)) {
2286                         tmp |= PWR_AV_EN;
2287                         value[0] = (u8) tmp;
2288                         value[1] = (u8) (tmp >> 8);
2289                         value[2] = (u8) (tmp >> 16);
2290                         value[3] = (u8) (tmp >> 24);
2291                         status =
2292                             cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2293                                                    PWR_CTL_EN, value, 4);
2294                         msleep(PWR_SLEEP_INTERVAL);
2295                 }
2296                 if (!(tmp & PWR_ISO_EN)) {
2297                         tmp |= PWR_ISO_EN;
2298                         value[0] = (u8) tmp;
2299                         value[1] = (u8) (tmp >> 8);
2300                         value[2] = (u8) (tmp >> 16);
2301                         value[3] = (u8) (tmp >> 24);
2302                         status =
2303                             cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2304                                                    PWR_CTL_EN, value, 4);
2305                         msleep(PWR_SLEEP_INTERVAL);
2306                 }
2307
2308                 tmp |= POLARIS_AVMODE_DIGITAL | I2C_DEMOD_EN;
2309                 value[0] = (u8) tmp;
2310                 value[1] = (u8) (tmp >> 8);
2311                 value[2] = (u8) (tmp >> 16);
2312                 value[3] = (u8) (tmp >> 24);
2313                 status =
2314                     cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2315                                            value, 4);
2316                 msleep(PWR_SLEEP_INTERVAL);
2317
2318                 if (!(tmp & PWR_DEMOD_EN)) {
2319                         tmp |= PWR_DEMOD_EN;
2320                         value[0] = (u8) tmp;
2321                         value[1] = (u8) (tmp >> 8);
2322                         value[2] = (u8) (tmp >> 16);
2323                         value[3] = (u8) (tmp >> 24);
2324                         status =
2325                             cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2326                                                    PWR_CTL_EN, value, 4);
2327                         msleep(PWR_SLEEP_INTERVAL);
2328                 }
2329
2330                 if ((dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
2331                     (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
2332
2333                         /* tuner path to channel 1 from port 3 */
2334                         cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2335
2336                         if (dev->cx231xx_reset_analog_tuner)
2337                                 dev->cx231xx_reset_analog_tuner(dev);
2338                 }
2339                 break;
2340
2341         default:
2342                 break;
2343         }
2344
2345         msleep(PWR_SLEEP_INTERVAL);
2346
2347         /* For power saving, only enable Pwr_resetout_n when digital TV is selected. */
2348         if (mode == POLARIS_AVMODE_DIGITAL) {
2349                 tmp |= PWR_RESETOUT_EN;
2350                 value[0] = (u8) tmp;
2351                 value[1] = (u8) (tmp >> 8);
2352                 value[2] = (u8) (tmp >> 16);
2353                 value[3] = (u8) (tmp >> 24);
2354                 status =
2355                     cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2356                                            value, 4);
2357                 msleep(PWR_SLEEP_INTERVAL);
2358         }
2359
2360         /* update power control for colibri */
2361         status = cx231xx_colibri_update_power_control(dev, mode);
2362
2363         /* update power control for flatiron */
2364         status = cx231xx_flatiron_update_power_control(dev, mode);
2365
2366         status =
2367             cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 4);
2368         cx231xx_info
2369             (" The data of PWR_CTL_EN register 0x74=0x%0x,0x%0x,0x%0x,0x%0x\n",
2370              value[0], value[1], value[2], value[3]);
2371
2372         return status;
2373 }
2374
2375 int cx231xx_power_suspend(struct cx231xx *dev)
2376 {
2377         u8 value[4] = { 0, 0, 0, 0 };
2378         u32 tmp = 0;
2379         int status = 0;
2380
2381         status =
2382             cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 4);
2383         if (status > 0)
2384                 return status;
2385
2386         tmp = *((u32 *) value);
2387         tmp &= (~PWR_MODE_MASK);
2388
2389         value[0] = (u8) tmp;
2390         value[1] = (u8) (tmp >> 8);
2391         value[2] = (u8) (tmp >> 16);
2392         value[3] = (u8) (tmp >> 24);
2393         status =
2394             cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, value, 4);
2395
2396         return status;
2397 }
2398
2399 /*************************************************************************************
2400  *                      S T R E A M    C O N T R O L   functions                     *
2401  *************************************************************************************/
2402 int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask)
2403 {
2404         u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
2405         u32 tmp = 0;
2406         int status = 0;
2407
2408         cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask);
2409         status =
2410             cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4);
2411         if (status < 0)
2412                 return status;
2413
2414         tmp = *((u32 *) value);
2415         tmp |= ep_mask;
2416         value[0] = (u8) tmp;
2417         value[1] = (u8) (tmp >> 8);
2418         value[2] = (u8) (tmp >> 16);
2419         value[3] = (u8) (tmp >> 24);
2420
2421         status =
2422             cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, value,
2423                                    4);
2424
2425         return status;
2426 }
2427
2428 int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask)
2429 {
2430         u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
2431         u32 tmp = 0;
2432         int status = 0;
2433
2434         cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask);
2435         status =
2436             cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4);
2437         if (status < 0)
2438                 return status;
2439
2440         tmp = *((u32 *) value);
2441         tmp &= (~ep_mask);
2442         value[0] = (u8) tmp;
2443         value[1] = (u8) (tmp >> 8);
2444         value[2] = (u8) (tmp >> 16);
2445         value[3] = (u8) (tmp >> 24);
2446
2447         status =
2448             cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, value,
2449                                    4);
2450
2451         return status;
2452 }
2453
2454 int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type)
2455 {
2456         int status = 0;
2457
2458         if (dev->udev->speed == USB_SPEED_HIGH) {
2459                 switch (media_type) {
2460                 case 81:        /* audio */
2461                         cx231xx_info("%s: Audio enter HANC\n", __func__);
2462                         status =
2463                             cx231xx_mode_register(dev, TS_MODE_REG, 0x9300);
2464                         break;
2465
2466                 case 2: /* vbi */
2467                         cx231xx_info("%s: set vanc registers\n", __func__);
2468                         status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300);
2469                         break;
2470
2471                 case 3: /* sliced cc */
2472                         cx231xx_info("%s: set hanc registers\n", __func__);
2473                         status =
2474                             cx231xx_mode_register(dev, TS_MODE_REG, 0x1300);
2475                         break;
2476
2477                 case 0: /* video */
2478                         cx231xx_info("%s: set video registers\n", __func__);
2479                         status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2480                         break;
2481
2482                 case 4: /* ts1 */
2483                         cx231xx_info("%s: set ts1 registers\n", __func__);
2484                         status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2485                         status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2486                         break;
2487                 case 6: /* ts1 parallel mode */
2488                         cx231xx_info("%s: set ts1 parrallel mode registers\n",
2489                                      __func__);
2490                         status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2491                         status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2492                         break;
2493                 }
2494         } else {
2495                 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2496         }
2497
2498         return status;
2499 }
2500
2501 int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type)
2502 {
2503         int rc;
2504         u32 ep_mask = -1;
2505         PPCB_CONFIG pcb_config;
2506
2507         /* get EP for media type */
2508         pcb_config = &dev->current_pcb_config;
2509
2510         if (pcb_config->config_num == 1) {
2511                 switch (media_type) {
2512                 case 0: /* Video */
2513                         ep_mask = ENABLE_EP4;   /* ep4  [00:1000] */
2514                         break;
2515                 case 1: /* Audio */
2516                         ep_mask = ENABLE_EP3;   /* ep3  [00:0100] */
2517                         break;
2518                 case 2: /* Vbi */
2519                         ep_mask = ENABLE_EP5;   /* ep5 [01:0000] */
2520                         break;
2521                 case 3: /* Sliced_cc */
2522                         ep_mask = ENABLE_EP6;   /* ep6 [10:0000] */
2523                         break;
2524                 case 4: /* ts1 */
2525                 case 6: /* ts1 parallel mode */
2526                         ep_mask = ENABLE_EP1;   /* ep1 [00:0001] */
2527                         break;
2528                 case 5: /* ts2 */
2529                         ep_mask = ENABLE_EP2;   /* ep2 [00:0010] */
2530                         break;
2531                 }
2532
2533         } else if (pcb_config->config_num > 1) {
2534                 switch (media_type) {
2535                 case 0: /* Video */
2536                         ep_mask = ENABLE_EP4;   /* ep4  [00:1000] */
2537                         break;
2538                 case 1: /* Audio */
2539                         ep_mask = ENABLE_EP3;   /* ep3  [00:0100] */
2540                         break;
2541                 case 2: /* Vbi */
2542                         ep_mask = ENABLE_EP5;   /* ep5 [01:0000] */
2543                         break;
2544                 case 3: /* Sliced_cc */
2545                         ep_mask = ENABLE_EP6;   /* ep6 [10:0000] */
2546                         break;
2547                 case 4: /* ts1 */
2548                 case 6: /* ts1 parallel mode */
2549                         ep_mask = ENABLE_EP1;   /* ep1 [00:0001] */
2550                         break;
2551                 case 5: /* ts2 */
2552                         ep_mask = ENABLE_EP2;   /* ep2 [00:0010] */
2553                         break;
2554                 }
2555
2556         }
2557
2558         if (start) {
2559                 rc = cx231xx_initialize_stream_xfer(dev, media_type);
2560
2561                 if (rc < 0) {
2562                         return rc;
2563                 }
2564
2565                 /* enable video capture */
2566                 if (ep_mask > 0)
2567                         rc = cx231xx_start_stream(dev, ep_mask);
2568         } else {
2569                 /* disable video capture */
2570                 if (ep_mask > 0)
2571                         rc = cx231xx_stop_stream(dev, ep_mask);
2572         }
2573
2574         if (dev->mode == CX231XX_ANALOG_MODE) {
2575                 /* do any in Analog mode */
2576         } else {
2577                 /* do any in digital mode */
2578         }
2579
2580         return rc;
2581 }
2582
2583 EXPORT_SYMBOL_GPL(cx231xx_capture_start);
2584
2585 /************************************************************************************
2586 *                       G P I O   B I T control functions                           *
2587 *************************************************************************************/
2588 int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 * gpio_val)
2589 {
2590         int status = 0;
2591
2592         status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 0);
2593
2594         return status;
2595 }
2596
2597 int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 * gpio_val)
2598 {
2599         int status = 0;
2600
2601         status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 1);
2602
2603         return status;
2604 }
2605
2606 /*
2607 * cx231xx_set_gpio_direction
2608 *      Sets the direction of the GPIO pin to input or output
2609 *
2610 * Parameters :
2611 *      pin_number : The GPIO Pin number to program the direction for
2612 *                   from 0 to 31
2613 *      pin_value : The Direction of the GPIO Pin under reference.
2614 *                      0 = Input direction
2615 *                      1 = Output direction
2616 */
2617 int cx231xx_set_gpio_direction(struct cx231xx *dev,
2618                                int pin_number, int pin_value)
2619 {
2620         int status = 0;
2621         u32 value = 0;
2622
2623         /* Check for valid pin_number - if 32 , bail out */
2624         if (pin_number >= 32) {
2625                 return -EINVAL;
2626         }
2627
2628         if (pin_value == 0) {   /* input */
2629                 value = dev->gpio_dir & (~(1 << pin_number));   /* clear */
2630         } else {
2631                 value = dev->gpio_dir | (1 << pin_number);
2632         }
2633
2634         status = cx231xx_set_gpio_bit(dev, value, (u8 *) & dev->gpio_val);
2635
2636         /* cache the value for future */
2637         dev->gpio_dir = value;
2638
2639         return status;
2640 }
2641
2642 /*
2643 * SetGpioPinLogicValue
2644 *      Sets the value of the GPIO pin to Logic high or low. The Pin under
2645 *      reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!!
2646 *
2647 * Parameters :
2648 *      pin_number : The GPIO Pin number to program the direction for
2649 *      pin_value : The value of the GPIO Pin under reference.
2650 *                      0 = set it to 0
2651 *                      1 = set it to 1
2652 */
2653 int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value)
2654 {
2655         int status = 0;
2656         u32 value = 0;
2657
2658         /* Check for valid pin_number - if 0xFF , bail out */
2659         if (pin_number >= 32)
2660                 return -EINVAL;
2661
2662         /* first do a sanity check - if the Pin is not output, make it output */
2663         if ((dev->gpio_dir & (1 << pin_number)) == 0x00) {
2664                 /* It was in input mode */
2665                 value = dev->gpio_dir | (1 << pin_number);
2666                 dev->gpio_dir = value;
2667                 status =
2668                     cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2669                                          (u8 *) & dev->gpio_val);
2670                 value = 0;
2671         }
2672
2673         if (pin_value == 0) {
2674                 value = dev->gpio_val & (~(1 << pin_number));
2675         } else {
2676                 value = dev->gpio_val | (1 << pin_number);
2677         }
2678
2679         /* store the value */
2680         dev->gpio_val = value;
2681
2682         /* toggle bit0 of GP_IO */
2683         status =
2684             cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2685
2686         return status;
2687 }
2688
2689 /************************************************************************************
2690 *                          G P I O I2C related functions                            *
2691 *************************************************************************************/
2692 int cx231xx_gpio_i2c_start(struct cx231xx *dev)
2693 {
2694         int status = 0;
2695
2696         /* set SCL to output 1 ; set SDA to output 1 */
2697         dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2698         dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2699         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2700         dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2701
2702         status =
2703             cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2704         if (status < 0) {
2705                 return -EINVAL;
2706         }
2707
2708         /* set SCL to output 1; set SDA to output 0 */
2709         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2710         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2711
2712         status =
2713             cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2714         if (status < 0) {
2715                 return -EINVAL;
2716         }
2717
2718         /* set SCL to output 0; set SDA to output 0      */
2719         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2720         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2721
2722         status =
2723             cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2724         if (status < 0) {
2725                 return -EINVAL;
2726         }
2727
2728         return status;
2729 }
2730
2731 int cx231xx_gpio_i2c_end(struct cx231xx *dev)
2732 {
2733         int status = 0;
2734
2735         /* set SCL to output 0; set SDA to output 0      */
2736         dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2737         dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2738
2739         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2740         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2741
2742         status =
2743             cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2744         if (status < 0) {
2745                 return -EINVAL;
2746         }
2747
2748         /* set SCL to output 1; set SDA to output 0      */
2749         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2750         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2751
2752         status =
2753             cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2754         if (status < 0) {
2755                 return -EINVAL;
2756         }
2757
2758         /* set SCL to input ,release SCL cable control
2759            set SDA to input ,release SDA cable control */
2760         dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2761         dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2762
2763         status =
2764             cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2765         if (status < 0) {
2766                 return -EINVAL;
2767         }
2768         return status;
2769 }
2770
2771 int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data)
2772 {
2773         int status = 0;
2774         u8 i;
2775
2776         /* set SCL to output ; set SDA to output */
2777         dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2778         dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2779
2780         for (i = 0; i < 8; i++) {
2781                 if (((data << i) & 0x80) == 0) {
2782                         /* set SCL to output 0; set SDA to output 0     */
2783                         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2784                         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2785                         status =
2786                             cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2787                                                  (u8 *) & dev->gpio_val);
2788
2789                         /* set SCL to output 1; set SDA to output 0     */
2790                         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2791                         status =
2792                             cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2793                                                  (u8 *) & dev->gpio_val);
2794
2795                         /* set SCL to output 0; set SDA to output 0     */
2796                         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2797                         status =
2798                             cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2799                                                  (u8 *) & dev->gpio_val);
2800                 } else {
2801                         /* set SCL to output 0; set SDA to output 1     */
2802                         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2803                         dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2804                         status =
2805                             cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2806                                                  (u8 *) & dev->gpio_val);
2807
2808                         /* set SCL to output 1; set SDA to output 1     */
2809                         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2810                         status =
2811                             cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2812                                                  (u8 *) & dev->gpio_val);
2813
2814                         /* set SCL to output 0; set SDA to output 1     */
2815                         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2816                         status =
2817                             cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2818                                                  (u8 *) & dev->gpio_val);
2819                 }
2820         }
2821         return status;
2822 }
2823
2824 int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 * buf)
2825 {
2826         u8 value = 0;
2827         int status = 0;
2828         u32 gpio_logic_value = 0;
2829         u8 i;
2830
2831         /* read byte */
2832         for (i = 0; i < 8; i++) {       /* send write I2c addr */
2833
2834                 /* set SCL to output 0; set SDA to input */
2835                 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2836                 status =
2837                     cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2838                                          (u8 *) & dev->gpio_val);
2839
2840                 /* set SCL to output 1; set SDA to input */
2841                 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2842                 status =
2843                     cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2844                                          (u8 *) & dev->gpio_val);
2845
2846                 /* get SDA data bit */
2847                 gpio_logic_value = dev->gpio_val;
2848                 status =
2849                     cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2850                                          (u8 *) & dev->gpio_val);
2851                 if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0) {
2852                         value |= (1 << (8 - i - 1));
2853                 }
2854
2855                 dev->gpio_val = gpio_logic_value;
2856         }
2857
2858         /* set SCL to output 0,finish the read latest SCL signal.
2859            !!!set SDA to input,never to modify SDA direction at the same times */
2860         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2861         status =
2862             cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2863
2864         /* store the value */
2865         *buf = value & 0xff;
2866
2867         return status;
2868 }
2869
2870 int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev)
2871 {
2872         int status = 0;
2873         u32 gpio_logic_value = 0;
2874         int nCnt = 10;
2875         int nInit = nCnt;
2876
2877         /* clock stretch; set SCL to input; set SDA to input; get SCL value till SCL = 1 */
2878         dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2879         dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2880
2881         gpio_logic_value = dev->gpio_val;
2882         status =
2883             cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2884
2885         do {
2886                 msleep(2);
2887                 status =
2888                     cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2889                                          (u8 *) & dev->gpio_val);
2890                 nCnt--;
2891         } while (((dev->gpio_val & (1 << dev->board.tuner_scl_gpio)) == 0)
2892                  && (nCnt > 0));
2893
2894         if (nCnt == 0) {
2895                 cx231xx_info
2896                     ("No ACK after %d msec for clock stretch. GPIO I2C operation failed!",
2897                      nInit * 10);
2898         }
2899
2900         /* readAck
2901            throuth clock stretch ,slave has given a SCL signal,so the SDA data can be directly read.  */
2902         status =
2903             cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2904
2905         if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) {
2906                 dev->gpio_val = gpio_logic_value;
2907                 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2908                 status = 0;
2909         } else {
2910                 dev->gpio_val = gpio_logic_value;
2911                 dev->gpio_val |= (1 << dev->board.tuner_sda_gpio);
2912         }
2913
2914         /* read SDA end, set the SCL to output 0, after this operation, SDA direction can be changed. */
2915         dev->gpio_val = gpio_logic_value;
2916         dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio);
2917         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2918         status =
2919             cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2920
2921         return status;
2922 }
2923
2924 int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev)
2925 {
2926         int status = 0;
2927
2928         /* set SDA to ouput */
2929         dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2930         status =
2931             cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2932
2933         /* set SCL = 0 (output); set SDA = 0 (output) */
2934         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2935         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2936         status =
2937             cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2938
2939         /* set SCL = 1 (output); set SDA = 0 (output) */
2940         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2941         status =
2942             cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2943
2944         /* set SCL = 0 (output); set SDA = 0 (output) */
2945         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2946         status =
2947             cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2948
2949         /* set SDA to input,and then the slave will read data from SDA. */
2950         dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2951         status =
2952             cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2953
2954         return status;
2955 }
2956
2957 int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev)
2958 {
2959         int status = 0;
2960
2961         /* set scl to output ; set sda to input */
2962         dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2963         dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2964         status =
2965             cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2966
2967         /* set scl to output 0; set sda to input */
2968         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2969         status =
2970             cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2971
2972         /* set scl to output 1; set sda to input */
2973         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2974         status =
2975             cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2976
2977         return status;
2978 }
2979
2980 /************************************************************************************
2981 *                          G P I O I2C related functions                            *
2982 *************************************************************************************/
2983 /* cx231xx_gpio_i2c_read
2984  * Function to read data from gpio based I2C interface
2985  */
2986 int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 * buf, u8 len)
2987 {
2988         int status = 0;
2989         int i = 0;
2990
2991         /* get the lock */
2992         mutex_lock(&dev->gpio_i2c_lock);
2993
2994         /* start */
2995         status = cx231xx_gpio_i2c_start(dev);
2996
2997         /* write dev_addr */
2998         status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1);
2999
3000         /* readAck */
3001         status = cx231xx_gpio_i2c_read_ack(dev);
3002
3003         /* read data */
3004         for (i = 0; i < len; i++) {
3005                 /* read data */
3006                 buf[i] = 0;
3007                 status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]);
3008
3009                 if ((i + 1) != len) {
3010                         /* only do write ack if we more length */
3011                         status = cx231xx_gpio_i2c_write_ack(dev);
3012                 }
3013         }
3014
3015         /* write NAK - inform reads are complete */
3016         status = cx231xx_gpio_i2c_write_nak(dev);
3017
3018         /* write end */
3019         status = cx231xx_gpio_i2c_end(dev);
3020
3021         /* release the lock */
3022         mutex_unlock(&dev->gpio_i2c_lock);
3023
3024         return status;
3025 }
3026
3027 /* cx231xx_gpio_i2c_write
3028  * Function to write data to gpio based I2C interface
3029  */
3030 int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 * buf, u8 len)
3031 {
3032         int status = 0;
3033         int i = 0;
3034
3035         /* get the lock */
3036         mutex_lock(&dev->gpio_i2c_lock);
3037
3038         /* start */
3039         status = cx231xx_gpio_i2c_start(dev);
3040
3041         /* write dev_addr */
3042         status = cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1);
3043
3044         /* read Ack */
3045         status = cx231xx_gpio_i2c_read_ack(dev);
3046
3047         for (i = 0; i < len; i++) {
3048                 /* Write data */
3049                 status = cx231xx_gpio_i2c_write_byte(dev, buf[i]);
3050
3051                 /* read Ack */
3052                 status = cx231xx_gpio_i2c_read_ack(dev);
3053         }
3054
3055         /* write End */
3056         status = cx231xx_gpio_i2c_end(dev);
3057
3058         /* release the lock */
3059         mutex_unlock(&dev->gpio_i2c_lock);
3060
3061         return 0;
3062 }