2 * ngene.c: nGene PCIe bridge driver
4 * Copyright (C) 2005-2007 Micronas
6 * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de>
7 * Modifications for new nGene firmware,
8 * support for EEPROM-copying,
9 * support for new dual DVB-S2 card prototype
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * version 2 only, as published by the Free Software Foundation.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
27 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
30 #include <linux/module.h>
31 #include <linux/init.h>
32 #include <linux/delay.h>
33 #include <linux/slab.h>
34 #include <linux/poll.h>
36 #include <asm/div64.h>
37 #include <linux/pci.h>
38 #include <linux/pci_ids.h>
39 #include <linux/smp_lock.h>
40 #include <linux/timer.h>
41 #include <linux/version.h>
42 #include <linux/byteorder/generic.h>
43 #include <linux/firmware.h>
47 #ifdef NGENE_COMMAND_API
48 #include "ngene-ioctls.h"
51 static int copy_eeprom;
52 module_param(copy_eeprom, int, 0444);
53 MODULE_PARM_DESC(copy_eeprom, "Copy eeprom.");
55 static int ngene_fw_debug;
56 module_param(ngene_fw_debug, int, 0444);
57 MODULE_PARM_DESC(ngene_fw_debug, "Debug firmware.");
60 module_param(debug, int, 0444);
61 MODULE_PARM_DESC(debug, "Print debugging information.");
63 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
65 #define dprintk if (debug) printk
67 #define DEVICE_NAME "ngene"
69 #define ngwriteb(dat, adr) writeb((dat), (char *)(dev->iomem + (adr)))
70 #define ngwritel(dat, adr) writel((dat), (char *)(dev->iomem + (adr)))
71 #define ngwriteb(dat, adr) writeb((dat), (char *)(dev->iomem + (adr)))
72 #define ngreadl(adr) readl(dev->iomem + (adr))
73 #define ngreadb(adr) readb(dev->iomem + (adr))
74 #define ngcpyto(adr, src, count) memcpy_toio((char *) \
75 (dev->iomem + (adr)), (src), (count))
76 #define ngcpyfrom(dst, adr, count) memcpy_fromio((dst), (char *) \
77 (dev->iomem + (adr)), (count))
79 /****************************************************************************/
80 /* Functions with missing kernel exports ************************************/
81 /****************************************************************************/
83 /* yeah, let's throw out all exports which are not used in kernel ... */
85 void my_dvb_ringbuffer_flush(struct dvb_ringbuffer *rbuf)
87 rbuf->pread = rbuf->pwrite;
91 /****************************************************************************/
92 /* nGene interrupt handler **************************************************/
93 /****************************************************************************/
95 static void event_tasklet(unsigned long data)
97 struct ngene *dev = (struct ngene *)data;
99 while (dev->EventQueueReadIndex != dev->EventQueueWriteIndex) {
100 struct EVENT_BUFFER Event =
101 dev->EventQueue[dev->EventQueueReadIndex];
102 dev->EventQueueReadIndex =
103 (dev->EventQueueReadIndex + 1) & (EVENT_QUEUE_SIZE - 1);
105 if ((Event.UARTStatus & 0x01) && (dev->TxEventNotify))
106 dev->TxEventNotify(dev, Event.TimeStamp);
107 if ((Event.UARTStatus & 0x02) && (dev->RxEventNotify))
108 dev->RxEventNotify(dev, Event.TimeStamp,
113 static void demux_tasklet(unsigned long data)
115 struct ngene_channel *chan = (struct ngene_channel *)data;
116 struct SBufferHeader *Cur = chan->nextBuffer;
118 spin_lock_irq(&chan->state_lock);
120 while (Cur->ngeneBuffer.SR.Flags & 0x80) {
121 if (chan->mode & NGENE_IO_TSOUT) {
122 u32 Flags = chan->DataFormatFlags;
123 if (Cur->ngeneBuffer.SR.Flags & 0x20)
124 Flags |= BEF_OVERFLOW;
125 if (chan->pBufferExchange) {
126 if (!chan->pBufferExchange(chan,
128 chan->Capture1Length,
133 Clear in service flag to make sure we
134 get called on next interrupt again.
135 leave fill/empty (0x80) flag alone
136 to avoid hardware running out of
137 buffers during startup, we hold only
138 in run state ( the source may be late
142 if (chan->HWState == HWSTATE_RUN) {
143 Cur->ngeneBuffer.SR.Flags &=
146 /* Stop proccessing stream */
149 /* We got a valid buffer,
150 so switch to run state */
151 chan->HWState = HWSTATE_RUN;
154 printk(KERN_ERR DEVICE_NAME ": OOPS\n");
155 if (chan->HWState == HWSTATE_RUN) {
156 Cur->ngeneBuffer.SR.Flags &= ~0x40;
157 break; /* Stop proccessing stream */
160 if (chan->AudioDTOUpdated) {
161 printk(KERN_INFO DEVICE_NAME
162 ": Update AudioDTO = %d\n",
163 chan->AudioDTOValue);
164 Cur->ngeneBuffer.SR.DTOUpdate =
166 chan->AudioDTOUpdated = 0;
169 if (chan->HWState == HWSTATE_RUN) {
171 if (Cur->ngeneBuffer.SR.Flags & 0x01)
172 Flags |= BEF_EVEN_FIELD;
173 if (Cur->ngeneBuffer.SR.Flags & 0x20)
174 Flags |= BEF_OVERFLOW;
175 if (chan->pBufferExchange)
176 chan->pBufferExchange(chan,
182 if (chan->pBufferExchange2)
183 chan->pBufferExchange2(chan,
189 } else if (chan->HWState != HWSTATE_STOP)
190 chan->HWState = HWSTATE_RUN;
192 Cur->ngeneBuffer.SR.Flags = 0x00;
195 chan->nextBuffer = Cur;
197 spin_unlock_irq(&chan->state_lock);
200 static irqreturn_t irq_handler(int irq, void *dev_id)
202 struct ngene *dev = (struct ngene *)dev_id;
204 irqreturn_t rc = IRQ_NONE;
208 if (dev->BootFirmware) {
209 icounts = ngreadl(NGENE_INT_COUNTS);
210 if (icounts != dev->icounts) {
211 ngwritel(0, FORCE_NMI);
213 wake_up(&dev->cmd_wq);
214 dev->icounts = icounts;
220 ngwritel(0, FORCE_NMI);
222 spin_lock(&dev->cmd_lock);
223 tmpCmdDoneByte = dev->CmdDoneByte;
224 if (tmpCmdDoneByte &&
226 (dev->ngenetohost[0] == 1 && dev->ngenetohost[1] != 0))) {
227 dev->CmdDoneByte = NULL;
229 wake_up(&dev->cmd_wq);
232 spin_unlock(&dev->cmd_lock);
234 if (dev->EventBuffer->EventStatus & 0x80) {
236 (dev->EventQueueWriteIndex + 1) &
237 (EVENT_QUEUE_SIZE - 1);
238 if (nextWriteIndex != dev->EventQueueReadIndex) {
239 dev->EventQueue[dev->EventQueueWriteIndex] =
241 dev->EventQueueWriteIndex = nextWriteIndex;
243 printk(KERN_ERR DEVICE_NAME ": event overflow\n");
244 dev->EventQueueOverflowCount += 1;
245 dev->EventQueueOverflowFlag = 1;
247 dev->EventBuffer->EventStatus &= ~0x80;
248 tasklet_schedule(&dev->event_tasklet);
254 spin_lock(&dev->channel[i].state_lock);
255 /* if (dev->channel[i].State>=KSSTATE_RUN) { */
256 if (dev->channel[i].nextBuffer) {
257 if ((dev->channel[i].nextBuffer->
258 ngeneBuffer.SR.Flags & 0xC0) == 0x80) {
259 dev->channel[i].nextBuffer->
260 ngeneBuffer.SR.Flags |= 0x40;
262 &dev->channel[i].demux_tasklet);
266 spin_unlock(&dev->channel[i].state_lock);
272 /****************************************************************************/
273 /* nGene command interface **************************************************/
274 /****************************************************************************/
276 static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com)
283 if (com->cmd.hdr.Opcode == CMD_FWLOAD_PREPARE) {
284 dev->BootFirmware = 1;
285 dev->icounts = ngreadl(NGENE_INT_COUNTS);
286 ngwritel(0, NGENE_COMMAND);
287 ngwritel(0, NGENE_COMMAND_HI);
288 ngwritel(0, NGENE_STATUS);
289 ngwritel(0, NGENE_STATUS_HI);
290 ngwritel(0, NGENE_EVENT);
291 ngwritel(0, NGENE_EVENT_HI);
292 } else if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) {
293 u64 fwio = dev->PAFWInterfaceBuffer;
295 ngwritel(fwio & 0xffffffff, NGENE_COMMAND);
296 ngwritel(fwio >> 32, NGENE_COMMAND_HI);
297 ngwritel((fwio + 256) & 0xffffffff, NGENE_STATUS);
298 ngwritel((fwio + 256) >> 32, NGENE_STATUS_HI);
299 ngwritel((fwio + 512) & 0xffffffff, NGENE_EVENT);
300 ngwritel((fwio + 512) >> 32, NGENE_EVENT_HI);
303 memcpy(dev->FWInterfaceBuffer, com->cmd.raw8, com->in_len + 2);
305 if (dev->BootFirmware)
306 ngcpyto(HOST_TO_NGENE, com->cmd.raw8, com->in_len + 2);
308 spin_lock_irq(&dev->cmd_lock);
309 tmpCmdDoneByte = dev->ngenetohost + com->out_len;
313 dev->ngenetohost[0] = 0;
314 dev->ngenetohost[1] = 0;
315 dev->CmdDoneByte = tmpCmdDoneByte;
316 spin_unlock_irq(&dev->cmd_lock);
319 ngwritel(1, FORCE_INT);
321 ret = wait_event_timeout(dev->cmd_wq, dev->cmd_done == 1, 2 * HZ);
323 /*ngwritel(0, FORCE_NMI);*/
325 printk(KERN_ERR DEVICE_NAME
326 ": Command timeout cmd=%02x prev=%02x\n",
327 com->cmd.hdr.Opcode, dev->prev_cmd);
330 if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH)
331 dev->BootFirmware = 0;
333 dev->prev_cmd = com->cmd.hdr.Opcode;
339 memcpy(com->cmd.raw8, dev->ngenetohost, com->out_len);
344 static int ngene_command(struct ngene *dev, struct ngene_command *com)
348 down(&dev->cmd_mutex);
349 result = ngene_command_mutex(dev, com);
354 int ngene_command_nop(struct ngene *dev)
356 struct ngene_command com;
358 com.cmd.hdr.Opcode = CMD_NOP;
359 com.cmd.hdr.Length = 0;
363 return ngene_command(dev, &com);
366 int ngene_command_i2c_read(struct ngene *dev, u8 adr,
367 u8 *out, u8 outlen, u8 *in, u8 inlen, int flag)
369 struct ngene_command com;
371 com.cmd.hdr.Opcode = CMD_I2C_READ;
372 com.cmd.hdr.Length = outlen + 3;
373 com.cmd.I2CRead.Device = adr << 1;
374 memcpy(com.cmd.I2CRead.Data, out, outlen);
375 com.cmd.I2CRead.Data[outlen] = inlen;
376 com.cmd.I2CRead.Data[outlen + 1] = 0;
377 com.in_len = outlen + 3;
378 com.out_len = inlen + 1;
380 if (ngene_command(dev, &com) < 0)
383 if ((com.cmd.raw8[0] >> 1) != adr)
387 memcpy(in, com.cmd.raw8, inlen + 1);
389 memcpy(in, com.cmd.raw8 + 1, inlen);
393 int ngene_command_i2c_write(struct ngene *dev, u8 adr, u8 *out, u8 outlen)
395 struct ngene_command com;
398 com.cmd.hdr.Opcode = CMD_I2C_WRITE;
399 com.cmd.hdr.Length = outlen + 1;
400 com.cmd.I2CRead.Device = adr << 1;
401 memcpy(com.cmd.I2CRead.Data, out, outlen);
402 com.in_len = outlen + 1;
405 if (ngene_command(dev, &com) < 0)
408 if (com.cmd.raw8[0] == 1)
414 static int ngene_command_load_firmware(struct ngene *dev,
415 u8 *ngene_fw, u32 size)
417 #define FIRSTCHUNK (1024)
419 struct ngene_command com;
421 com.cmd.hdr.Opcode = CMD_FWLOAD_PREPARE;
422 com.cmd.hdr.Length = 0;
426 ngene_command(dev, &com);
428 cleft = (size + 3) & ~3;
429 if (cleft > FIRSTCHUNK) {
430 ngcpyto(PROGRAM_SRAM + FIRSTCHUNK, ngene_fw + FIRSTCHUNK,
434 ngene_fw[FW_DEBUG_DEFAULT - PROGRAM_SRAM] = ngene_fw_debug;
435 ngcpyto(DATA_FIFO_AREA, ngene_fw, cleft);
437 memset(&com, 0, sizeof(struct ngene_command));
438 com.cmd.hdr.Opcode = CMD_FWLOAD_FINISH;
439 com.cmd.hdr.Length = 4;
440 com.cmd.FWLoadFinish.Address = DATA_FIFO_AREA;
441 com.cmd.FWLoadFinish.Length = (unsigned short)cleft;
445 return ngene_command(dev, &com);
448 int ngene_command_imem_read(struct ngene *dev, u8 adr, u8 *data, int type)
450 struct ngene_command com;
452 com.cmd.hdr.Opcode = type ? CMD_SFR_READ : CMD_IRAM_READ;
453 com.cmd.hdr.Length = 1;
454 com.cmd.SfrIramRead.address = adr;
458 if (ngene_command(dev, &com) < 0)
461 *data = com.cmd.raw8[1];
465 int ngene_command_imem_write(struct ngene *dev, u8 adr, u8 data, int type)
467 struct ngene_command com;
469 com.cmd.hdr.Opcode = type ? CMD_SFR_WRITE : CMD_IRAM_WRITE;
470 com.cmd.hdr.Length = 2;
471 com.cmd.SfrIramWrite.address = adr;
472 com.cmd.SfrIramWrite.data = data;
476 if (ngene_command(dev, &com) < 0)
482 static int ngene_command_config_uart(struct ngene *dev, u8 config,
483 tx_cb_t *tx_cb, rx_cb_t *rx_cb)
485 struct ngene_command com;
487 com.cmd.hdr.Opcode = CMD_CONFIGURE_UART;
488 com.cmd.hdr.Length = sizeof(struct FW_CONFIGURE_UART) - 2;
489 com.cmd.ConfigureUart.UartControl = config;
490 com.in_len = sizeof(struct FW_CONFIGURE_UART);
493 if (ngene_command(dev, &com) < 0)
496 dev->TxEventNotify = tx_cb;
497 dev->RxEventNotify = rx_cb;
499 dprintk(KERN_DEBUG DEVICE_NAME ": Set UART config %02x.\n", config);
504 static void tx_cb(struct ngene *dev, u32 ts)
507 wake_up_interruptible(&dev->tx_wq);
510 static void rx_cb(struct ngene *dev, u32 ts, u8 c)
512 int rp = dev->uart_rp;
513 int nwp, wp = dev->uart_wp;
515 /* dprintk(KERN_DEBUG DEVICE_NAME ": %c\n", c); */
516 nwp = (wp + 1) % (UART_RBUF_LEN);
519 dev->uart_rbuf[wp] = c;
521 wake_up_interruptible(&dev->rx_wq);
524 static int ngene_command_config_buf(struct ngene *dev, u8 config)
526 struct ngene_command com;
528 com.cmd.hdr.Opcode = CMD_CONFIGURE_BUFFER;
529 com.cmd.hdr.Length = 1;
530 com.cmd.ConfigureBuffers.config = config;
534 if (ngene_command(dev, &com) < 0)
539 static int ngene_command_config_free_buf(struct ngene *dev, u8 *config)
541 struct ngene_command com;
543 com.cmd.hdr.Opcode = CMD_CONFIGURE_FREE_BUFFER;
544 com.cmd.hdr.Length = 6;
545 memcpy(&com.cmd.ConfigureBuffers.config, config, 6);
549 if (ngene_command(dev, &com) < 0)
555 static int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level)
557 struct ngene_command com;
559 com.cmd.hdr.Opcode = CMD_SET_GPIO_PIN;
560 com.cmd.hdr.Length = 1;
561 com.cmd.SetGpioPin.select = select | (level << 7);
565 return ngene_command(dev, &com);
568 /* The reset is only wired to GPIO4 on MicRacer Revision 1.10 !
569 Also better set bootdelay to 1 in nvram or less. */
570 static void ngene_reset_decypher(struct ngene *dev)
572 printk(KERN_INFO DEVICE_NAME ": Resetting Decypher.\n");
573 ngene_command_gpio_set(dev, 4, 0);
575 ngene_command_gpio_set(dev, 4, 1);
580 02000640 is sample on rising edge.
581 02000740 is sample on falling edge.
582 02000040 is ignore "valid" signal
584 0: FD_CTL1 Bit 7,6 must be 0,1
585 7 disable(fw controlled)
590 1,0 0-no sync, 1-use ext. start, 2-use 0x47, 3-both
591 1: FD_CTL2 has 3-valid must be hi, 2-use valid, 1-edge
592 2: FD_STA is read-only. 0-sync
593 3: FD_INSYNC is number of 47s to trigger "in sync".
594 4: FD_OUTSYNC is number of 47s to trigger "out of sync".
595 5: FD_MAXBYTE1 is low-order of bytes per packet.
596 6: FD_MAXBYTE2 is high-order of bytes per packet.
597 7: Top byte is unused.
600 /****************************************************************************/
602 static u8 TSFeatureDecoderSetup[8 * 4] = {
603 0x42, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00,
604 0x40, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXH */
605 0x71, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXHser */
606 0x72, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* S2ser */
609 /* Set NGENE I2S Config to 16 bit packed */
610 static u8 I2SConfiguration[] = {
611 0x00, 0x10, 0x00, 0x00,
612 0x80, 0x10, 0x00, 0x00,
615 static u8 SPDIFConfiguration[10] = {
616 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
619 /* Set NGENE I2S Config to transport stream compatible mode */
621 static u8 TS_I2SConfiguration[4] = { 0x3E, 0x1A, 0x00, 0x00 }; /*3e 18 00 00 ?*/
623 static u8 TS_I2SOutConfiguration[4] = { 0x80, 0x20, 0x00, 0x00 };
625 static u8 ITUDecoderSetup[4][16] = {
626 {0x1c, 0x13, 0x01, 0x68, 0x3d, 0x90, 0x14, 0x20, /* SDTV */
627 0x00, 0x00, 0x01, 0xb0, 0x9c, 0x00, 0x00, 0x00},
628 {0x9c, 0x03, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,
629 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
630 {0x9f, 0x00, 0x23, 0xC0, 0x60, 0x0F, 0x13, 0x00, /* HDTV 1080i50 */
631 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
632 {0x9c, 0x01, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00, /* HDTV 1080i60 */
633 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
638 * 27p50 9f 00 22 80 42 69 18 ...
639 * 27p60 93 00 22 80 82 69 1c ...
642 /* Maxbyte to 1144 (for raw data) */
643 static u8 ITUFeatureDecoderSetup[8] = {
644 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x04, 0x00
647 static void FillTSBuffer(void *Buffer, int Length, u32 Flags)
651 memset(Buffer, Length, 0xff);
653 if (Flags & DF_SWAP32)
663 static void flush_buffers(struct ngene_channel *chan)
669 spin_lock_irq(&chan->state_lock);
670 val = chan->nextBuffer->ngeneBuffer.SR.Flags & 0x80;
671 spin_unlock_irq(&chan->state_lock);
675 static void clear_buffers(struct ngene_channel *chan)
677 struct SBufferHeader *Cur = chan->nextBuffer;
680 memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR));
681 if (chan->mode & NGENE_IO_TSOUT)
682 FillTSBuffer(Cur->Buffer1,
683 chan->Capture1Length,
684 chan->DataFormatFlags);
686 } while (Cur != chan->nextBuffer);
688 if (chan->mode & NGENE_IO_TSOUT) {
689 chan->nextBuffer->ngeneBuffer.SR.DTOUpdate =
691 chan->AudioDTOUpdated = 0;
693 Cur = chan->TSIdleBuffer.Head;
696 memset(&Cur->ngeneBuffer.SR, 0,
697 sizeof(Cur->ngeneBuffer.SR));
698 FillTSBuffer(Cur->Buffer1,
699 chan->Capture1Length,
700 chan->DataFormatFlags);
702 } while (Cur != chan->TSIdleBuffer.Head);
706 int ngene_command_stream_control(struct ngene *dev, u8 stream, u8 control,
709 struct ngene_channel *chan = &dev->channel[stream];
710 struct ngene_command com;
711 u16 BsUVI = ((stream & 1) ? 0x9400 : 0x9300);
712 u16 BsSDI = ((stream & 1) ? 0x9600 : 0x9500);
713 u16 BsSPI = ((stream & 1) ? 0x9800 : 0x9700);
716 /* down(&dev->stream_mutex); */
717 while (down_trylock(&dev->stream_mutex)) {
718 printk(KERN_INFO DEVICE_NAME ": SC locked\n");
721 memset(&com, 0, sizeof(com));
722 com.cmd.hdr.Opcode = CMD_CONTROL;
723 com.cmd.hdr.Length = sizeof(struct FW_STREAM_CONTROL) - 2;
724 com.cmd.StreamControl.Stream = stream | (control ? 8 : 0);
725 if (chan->mode & NGENE_IO_TSOUT)
726 com.cmd.StreamControl.Stream |= 0x07;
727 com.cmd.StreamControl.Control = control |
728 (flags & SFLAG_ORDER_LUMA_CHROMA);
729 com.cmd.StreamControl.Mode = mode;
730 com.in_len = sizeof(struct FW_STREAM_CONTROL);
733 printk(KERN_INFO DEVICE_NAME ": Stream=%02x, Control=%02x, Mode=%02x\n",
734 com.cmd.StreamControl.Stream, com.cmd.StreamControl.Control,
735 com.cmd.StreamControl.Mode);
738 if (!(control & 0x80)) {
739 spin_lock_irq(&chan->state_lock);
740 if (chan->State == KSSTATE_RUN) {
741 chan->State = KSSTATE_ACQUIRE;
742 chan->HWState = HWSTATE_STOP;
743 spin_unlock_irq(&chan->state_lock);
744 if (ngene_command(dev, &com) < 0) {
745 up(&dev->stream_mutex);
748 /* clear_buffers(chan); */
750 up(&dev->stream_mutex);
753 spin_unlock_irq(&chan->state_lock);
754 up(&dev->stream_mutex);
758 if (mode & SMODE_AUDIO_CAPTURE) {
759 com.cmd.StreamControl.CaptureBlockCount =
760 chan->Capture1Length / AUDIO_BLOCK_SIZE;
761 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
762 } else if (mode & SMODE_TRANSPORT_STREAM) {
763 com.cmd.StreamControl.CaptureBlockCount =
764 chan->Capture1Length / TS_BLOCK_SIZE;
765 com.cmd.StreamControl.MaxLinesPerField =
766 chan->Capture1Length / TS_BLOCK_SIZE;
767 com.cmd.StreamControl.Buffer_Address =
768 chan->TSRingBuffer.PAHead;
769 if (chan->mode & NGENE_IO_TSOUT) {
770 com.cmd.StreamControl.BytesPerVBILine =
771 chan->Capture1Length / TS_BLOCK_SIZE;
772 com.cmd.StreamControl.Stream |= 0x07;
775 com.cmd.StreamControl.BytesPerVideoLine = chan->nBytesPerLine;
776 com.cmd.StreamControl.MaxLinesPerField = chan->nLines;
777 com.cmd.StreamControl.MinLinesPerField = 100;
778 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
780 if (mode & SMODE_VBI_CAPTURE) {
781 com.cmd.StreamControl.MaxVBILinesPerField =
783 com.cmd.StreamControl.MinVBILinesPerField = 0;
784 com.cmd.StreamControl.BytesPerVBILine =
785 chan->nBytesPerVBILine;
787 if (flags & SFLAG_COLORBAR)
788 com.cmd.StreamControl.Stream |= 0x04;
791 spin_lock_irq(&chan->state_lock);
792 if (mode & SMODE_AUDIO_CAPTURE) {
793 chan->nextBuffer = chan->RingBuffer.Head;
794 if (mode & SMODE_AUDIO_SPDIF) {
795 com.cmd.StreamControl.SetupDataLen =
796 sizeof(SPDIFConfiguration);
797 com.cmd.StreamControl.SetupDataAddr = BsSPI;
798 memcpy(com.cmd.StreamControl.SetupData,
799 SPDIFConfiguration, sizeof(SPDIFConfiguration));
801 com.cmd.StreamControl.SetupDataLen = 4;
802 com.cmd.StreamControl.SetupDataAddr = BsSDI;
803 memcpy(com.cmd.StreamControl.SetupData,
805 4 * dev->card_info->i2s[stream], 4);
807 } else if (mode & SMODE_TRANSPORT_STREAM) {
808 chan->nextBuffer = chan->TSRingBuffer.Head;
809 if (stream >= STREAM_AUDIOIN1) {
810 if (chan->mode & NGENE_IO_TSOUT) {
811 com.cmd.StreamControl.SetupDataLen =
812 sizeof(TS_I2SOutConfiguration);
813 com.cmd.StreamControl.SetupDataAddr = BsSDO;
814 memcpy(com.cmd.StreamControl.SetupData,
815 TS_I2SOutConfiguration,
816 sizeof(TS_I2SOutConfiguration));
818 com.cmd.StreamControl.SetupDataLen =
819 sizeof(TS_I2SConfiguration);
820 com.cmd.StreamControl.SetupDataAddr = BsSDI;
821 memcpy(com.cmd.StreamControl.SetupData,
823 sizeof(TS_I2SConfiguration));
826 com.cmd.StreamControl.SetupDataLen = 8;
827 com.cmd.StreamControl.SetupDataAddr = BsUVI + 0x10;
828 memcpy(com.cmd.StreamControl.SetupData,
829 TSFeatureDecoderSetup +
830 8 * dev->card_info->tsf[stream], 8);
833 chan->nextBuffer = chan->RingBuffer.Head;
834 com.cmd.StreamControl.SetupDataLen =
835 16 + sizeof(ITUFeatureDecoderSetup);
836 com.cmd.StreamControl.SetupDataAddr = BsUVI;
837 memcpy(com.cmd.StreamControl.SetupData,
838 ITUDecoderSetup[chan->itumode], 16);
839 memcpy(com.cmd.StreamControl.SetupData + 16,
840 ITUFeatureDecoderSetup, sizeof(ITUFeatureDecoderSetup));
843 chan->State = KSSTATE_RUN;
844 if (mode & SMODE_TRANSPORT_STREAM)
845 chan->HWState = HWSTATE_RUN;
847 chan->HWState = HWSTATE_STARTUP;
848 spin_unlock_irq(&chan->state_lock);
850 if (ngene_command(dev, &com) < 0) {
851 up(&dev->stream_mutex);
854 up(&dev->stream_mutex);
858 int ngene_stream_control(struct ngene *dev, u8 stream, u8 control, u8 mode,
859 u16 lines, u16 bpl, u16 vblines, u16 vbibpl)
861 if (!(mode & SMODE_TRANSPORT_STREAM))
864 if (lines * bpl > MAX_VIDEO_BUFFER_SIZE)
867 if ((mode & SMODE_TRANSPORT_STREAM) && (((bpl * lines) & 0xff) != 0))
870 if ((mode & SMODE_VIDEO_CAPTURE) && (bpl & 7) != 0)
873 return ngene_command_stream_control(dev, stream, control, mode, 0);
876 /****************************************************************************/
877 /* I2C **********************************************************************/
878 /****************************************************************************/
880 static void ngene_i2c_set_bus(struct ngene *dev, int bus)
882 if (!(dev->card_info->i2c_access & 2))
884 if (dev->i2c_current_bus == bus)
889 ngene_command_gpio_set(dev, 3, 0);
890 ngene_command_gpio_set(dev, 2, 1);
894 ngene_command_gpio_set(dev, 2, 0);
895 ngene_command_gpio_set(dev, 3, 1);
898 dev->i2c_current_bus = bus;
901 static int ngene_i2c_master_xfer(struct i2c_adapter *adapter,
902 struct i2c_msg msg[], int num)
904 struct ngene_channel *chan =
905 (struct ngene_channel *)i2c_get_adapdata(adapter);
906 struct ngene *dev = chan->dev;
908 down(&dev->i2c_switch_mutex);
909 ngene_i2c_set_bus(dev, chan->number);
911 if (num == 2 && msg[1].flags & I2C_M_RD && !(msg[0].flags & I2C_M_RD))
912 if (!ngene_command_i2c_read(dev, msg[0].addr,
913 msg[0].buf, msg[0].len,
914 msg[1].buf, msg[1].len, 0))
917 if (num == 1 && !(msg[0].flags & I2C_M_RD))
918 if (!ngene_command_i2c_write(dev, msg[0].addr,
919 msg[0].buf, msg[0].len))
921 if (num == 1 && (msg[0].flags & I2C_M_RD))
922 if (!ngene_command_i2c_read(dev, msg[0].addr, 0, 0,
923 msg[0].buf, msg[0].len, 0))
926 up(&dev->i2c_switch_mutex);
930 up(&dev->i2c_switch_mutex);
936 static u32 ngene_i2c_functionality(struct i2c_adapter *adap)
938 return I2C_FUNC_SMBUS_EMUL;
941 struct i2c_algorithm ngene_i2c_algo = {
942 .master_xfer = ngene_i2c_master_xfer,
943 .functionality = ngene_i2c_functionality,
946 static int ngene_i2c_init(struct ngene *dev, int dev_nr)
948 struct i2c_adapter *adap = &(dev->channel[dev_nr].i2c_adapter);
950 i2c_set_adapdata(adap, &(dev->channel[dev_nr]));
951 #ifdef I2C_ADAP_CLASS_TV_DIGITAL
952 adap->class = I2C_ADAP_CLASS_TV_DIGITAL | I2C_CLASS_TV_ANALOG;
954 adap->class = I2C_CLASS_TV_ANALOG;
957 strcpy(adap->name, "nGene");
959 adap->id = I2C_HW_SAA7146;
960 adap->algo = &ngene_i2c_algo;
961 adap->algo_data = (void *)&(dev->channel[dev_nr]);
963 mutex_init(&adap->bus_lock);
964 return i2c_add_adapter(adap);
967 int i2c_write(struct i2c_adapter *adapter, u8 adr, u8 data)
970 struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, .len = 1};
972 if (i2c_transfer(adapter, &msg, 1) != 1) {
973 printk(KERN_ERR DEVICE_NAME
974 ": Failed to write to I2C adr %02x!\n", adr);
981 static int i2c_write_read(struct i2c_adapter *adapter,
982 u8 adr, u8 *w, u8 wlen, u8 *r, u8 rlen)
984 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
985 .buf = w, .len = wlen},
986 {.addr = adr, .flags = I2C_M_RD,
987 .buf = r, .len = rlen} };
989 if (i2c_transfer(adapter, msgs, 2) != 2) {
990 printk(KERN_ERR DEVICE_NAME ": error in i2c_write_read\n");
996 static int test_dec_i2c(struct i2c_adapter *adapter, int reg)
998 u8 data[256] = { reg, 0x00, 0x93, 0x78, 0x43, 0x45 };
1002 memset(data2, 0, 256);
1003 i2c_write_read(adapter, 0x66, data, 2, data2, 4);
1004 for (i = 0; i < 4; i++)
1005 printk("%02x ", data2[i]);
1012 /****************************************************************************/
1013 /* EEPROM TAGS **************************************************************/
1014 /****************************************************************************/
1016 #define MICNG_EE_START 0x0100
1017 #define MICNG_EE_END 0x0FF0
1019 #define MICNG_EETAG_END0 0x0000
1020 #define MICNG_EETAG_END1 0xFFFF
1022 /* 0x0001 - 0x000F reserved for housekeeping */
1023 /* 0xFFFF - 0xFFFE reserved for housekeeping */
1025 /* Micronas assigned tags
1026 EEProm tags for hardware support */
1028 #define MICNG_EETAG_DRXD1_OSCDEVIATION 0x1000 /* 2 Bytes data */
1029 #define MICNG_EETAG_DRXD2_OSCDEVIATION 0x1001 /* 2 Bytes data */
1031 #define MICNG_EETAG_MT2060_1_1STIF 0x1100 /* 2 Bytes data */
1032 #define MICNG_EETAG_MT2060_2_1STIF 0x1101 /* 2 Bytes data */
1034 /* Tag range for OEMs */
1036 #define MICNG_EETAG_OEM_FIRST 0xC000
1037 #define MICNG_EETAG_OEM_LAST 0xFFEF
1039 static int i2c_write_eeprom(struct i2c_adapter *adapter,
1040 u8 adr, u16 reg, u8 data)
1042 u8 m[3] = {(reg >> 8), (reg & 0xff), data};
1043 struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m,
1046 if (i2c_transfer(adapter, &msg, 1) != 1) {
1047 dprintk(KERN_DEBUG DEVICE_NAME ": Error writing EEPROM!\n");
1053 static int i2c_read_eeprom(struct i2c_adapter *adapter,
1054 u8 adr, u16 reg, u8 *data, int len)
1056 u8 msg[2] = {(reg >> 8), (reg & 0xff)};
1057 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
1058 .buf = msg, .len = 2 },
1059 {.addr = adr, .flags = I2C_M_RD,
1060 .buf = data, .len = len} };
1062 if (i2c_transfer(adapter, msgs, 2) != 2) {
1063 dprintk(KERN_DEBUG DEVICE_NAME ": Error reading EEPROM\n");
1070 static int i2c_dump_eeprom(struct i2c_adapter *adapter, u8 adr)
1075 if (i2c_read_eeprom(adapter, adr, 0x0000, buf, sizeof(buf))) {
1076 printk(KERN_ERR DEVICE_NAME ": No EEPROM?\n");
1079 for (i = 0; i < sizeof(buf); i++) {
1082 printk("%02x ", buf[i]);
1089 static int i2c_copy_eeprom(struct i2c_adapter *adapter, u8 adr, u8 adr2)
1094 if (i2c_read_eeprom(adapter, adr, 0x0000, buf, sizeof(buf))) {
1095 printk(KERN_ERR DEVICE_NAME ": No EEPROM?\n");
1100 for (i = 0; i < sizeof(buf); i++) {
1101 i2c_write_eeprom(adapter, adr2, i, buf[i]);
1108 /****************************************************************************/
1109 /* COMMAND API interface ****************************************************/
1110 /****************************************************************************/
1112 #ifdef NGENE_COMMAND_API
1114 static int command_do_ioctl(struct inode *inode, struct file *file,
1115 unsigned int cmd, void *parg)
1117 struct dvb_device *dvbdev = file->private_data;
1118 struct ngene_channel *chan = dvbdev->priv;
1119 struct ngene *dev = chan->dev;
1123 case IOCTL_MIC_NO_OP:
1124 err = ngene_command_nop(dev);
1127 case IOCTL_MIC_DOWNLOAD_FIRMWARE:
1130 case IOCTL_MIC_I2C_READ:
1132 MIC_I2C_READ *msg = parg;
1134 err = ngene_command_i2c_read(dev, msg->I2CAddress >> 1,
1135 msg->OutData, msg->OutLength,
1136 msg->OutData, msg->InLength, 1);
1140 case IOCTL_MIC_I2C_WRITE:
1142 MIC_I2C_WRITE *msg = parg;
1144 err = ngene_command_i2c_write(dev, msg->I2CAddress >> 1,
1145 msg->Data, msg->Length);
1149 case IOCTL_MIC_TEST_GETMEM:
1153 if (m->Length > 64 * 1024 || m->Start + m->Length > 64 * 1024)
1156 /* WARNING, only use this on x86,
1157 other archs may not swallow this */
1158 err = copy_to_user(m->Data, dev->iomem + m->Start, m->Length);
1162 case IOCTL_MIC_TEST_SETMEM:
1166 if (m->Length > 64 * 1024 || m->Start + m->Length > 64 * 1024)
1169 err = copy_from_user(dev->iomem + m->Start, m->Data, m->Length);
1173 case IOCTL_MIC_SFR_READ:
1177 err = ngene_command_imem_read(dev, m->Address, &m->Data, 1);
1181 case IOCTL_MIC_SFR_WRITE:
1185 err = ngene_command_imem_write(dev, m->Address, m->Data, 1);
1189 case IOCTL_MIC_IRAM_READ:
1193 err = ngene_command_imem_read(dev, m->Address, &m->Data, 0);
1197 case IOCTL_MIC_IRAM_WRITE:
1201 err = ngene_command_imem_write(dev, m->Address, m->Data, 0);
1205 case IOCTL_MIC_STREAM_CONTROL:
1207 MIC_STREAM_CONTROL *m = parg;
1209 err = ngene_stream_control(dev, m->Stream, m->Control, m->Mode,
1210 m->nLines, m->nBytesPerLine,
1211 m->nVBILines, m->nBytesPerVBILine);
1222 static int command_ioctl(struct inode *inode, struct file *file,
1223 unsigned int cmd, unsigned long arg)
1225 void *parg = (void *)arg, *pbuf = NULL;
1229 if (_IOC_DIR(cmd) & _IOC_WRITE) {
1231 if (_IOC_SIZE(cmd) > sizeof(buf)) {
1232 pbuf = kmalloc(_IOC_SIZE(cmd), GFP_KERNEL);
1237 if (copy_from_user(parg, (void __user *)arg, _IOC_SIZE(cmd)))
1240 res = command_do_ioctl(inode, file, cmd, parg);
1243 if (_IOC_DIR(cmd) & _IOC_READ)
1244 if (copy_to_user((void __user *)arg, parg, _IOC_SIZE(cmd)))
1251 struct page *ngene_nopage(struct vm_area_struct *vma,
1252 unsigned long address, int *type)
1257 static int ngene_mmap(struct file *file, struct vm_area_struct *vma)
1259 struct dvb_device *dvbdev = file->private_data;
1260 struct ngene_channel *chan = dvbdev->priv;
1261 struct ngene *dev = chan->dev;
1263 unsigned long size = vma->vm_end - vma->vm_start;
1264 unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
1265 unsigned long padr = pci_resource_start(dev->pci_dev, 0) + off;
1266 unsigned long psize = pci_resource_len(dev->pci_dev, 0) - off;
1271 if (io_remap_pfn_range(vma, vma->vm_start, padr >> PAGE_SHIFT, size,
1277 static int write_uart(struct ngene *dev, u8 *data, int len)
1279 struct ngene_command com;
1281 com.cmd.hdr.Opcode = CMD_WRITE_UART;
1282 com.cmd.hdr.Length = len;
1283 memcpy(com.cmd.WriteUart.Data, data, len);
1284 com.cmd.WriteUart.Data[len] = 0;
1285 com.cmd.WriteUart.Data[len + 1] = 0;
1289 if (ngene_command(dev, &com) < 0)
1295 static int send_cli(struct ngene *dev, char *cmd)
1297 /* printk(KERN_INFO DEVICE_NAME ": %s", cmd); */
1298 return write_uart(dev, cmd, strlen(cmd));
1301 static int send_cli_val(struct ngene *dev, char *cmd, u32 val)
1305 snprintf(s, 32, "%s %d\n", cmd, val);
1306 /* printk(KERN_INFO DEVICE_NAME ": %s", s); */
1307 return write_uart(dev, s, strlen(s));
1310 static int ngene_command_write_uart_user(struct ngene *dev,
1311 const u8 *data, int len)
1313 struct ngene_command com;
1316 com.cmd.hdr.Opcode = CMD_WRITE_UART;
1317 com.cmd.hdr.Length = len;
1319 if (copy_from_user(com.cmd.WriteUart.Data, data, len))
1324 if (ngene_command(dev, &com) < 0)
1330 static ssize_t uart_write(struct file *file, const char *buf,
1331 size_t count, loff_t *ppos)
1333 struct dvb_device *dvbdev = file->private_data;
1334 struct ngene_channel *chan = dvbdev->priv;
1335 struct ngene *dev = chan->dev;
1337 size_t left = count;
1343 ret = wait_event_interruptible(dev->tx_wq, dev->tx_busy == 0);
1346 ngene_command_write_uart_user(dev, buf, len);
1353 static ssize_t ts_write(struct file *file, const char *buf,
1354 size_t count, loff_t *ppos)
1356 struct dvb_device *dvbdev = file->private_data;
1357 struct ngene_channel *chan = dvbdev->priv;
1358 struct ngene *dev = chan->dev;
1360 if (wait_event_interruptible(dev->tsout_rbuf.queue,
1362 (&dev->tsout_rbuf) >= count) < 0)
1365 dvb_ringbuffer_write(&dev->tsout_rbuf, buf, count);
1370 static ssize_t uart_read(struct file *file, char *buf,
1371 size_t count, loff_t *ppos)
1373 struct dvb_device *dvbdev = file->private_data;
1374 struct ngene_channel *chan = dvbdev->priv;
1375 struct ngene *dev = chan->dev;
1377 int wp, rp, avail, len;
1379 if (!dev->uart_rbuf)
1385 if (wait_event_interruptible(dev->rx_wq,
1386 dev->uart_wp != dev->uart_rp) < 0)
1393 avail += UART_RBUF_LEN;
1397 len = UART_RBUF_LEN - rp;
1400 if (copy_to_user(buf, dev->uart_rbuf + rp, len))
1403 if (copy_to_user(buf + len, dev->uart_rbuf,
1407 if (copy_to_user(buf, dev->uart_rbuf + rp, avail))
1410 dev->uart_rp = (rp + avail) % UART_RBUF_LEN;
1417 static const struct file_operations command_fops = {
1418 .owner = THIS_MODULE,
1421 .ioctl = command_ioctl,
1422 .open = dvb_generic_open,
1423 .release = dvb_generic_release,
1428 static struct dvb_device dvbdev_command = {
1433 .fops = &command_fops,
1438 /****************************************************************************/
1439 /* DVB functions and API interface ******************************************/
1440 /****************************************************************************/
1442 static void swap_buffer(u32 *p, u32 len)
1452 static void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags)
1454 struct ngene_channel *chan = priv;
1457 dvb_dmx_swfilter(&chan->demux, buf, len);
1461 u8 fill_ts[188] = { 0x47, 0x1f, 0xff, 0x10 };
1463 static void *tsout_exchange(void *priv, void *buf, u32 len,
1464 u32 clock, u32 flags)
1466 struct ngene_channel *chan = priv;
1467 struct ngene *dev = chan->dev;
1470 alen = dvb_ringbuffer_avail(&dev->tsout_rbuf);
1474 FillTSBuffer(buf + alen, len - alen, flags);
1477 dvb_ringbuffer_read(&dev->tsout_rbuf, buf, alen);
1478 if (flags & DF_SWAP32)
1479 swap_buffer((u32 *)buf, alen);
1480 wake_up_interruptible(&dev->tsout_rbuf.queue);
1485 static void set_transfer(struct ngene_channel *chan, int state)
1487 u8 control = 0, mode = 0, flags = 0;
1488 struct ngene *dev = chan->dev;
1497 printk(KERN_INFO DEVICE_NAME ": st %d\n", state);
1502 if (chan->running) {
1503 printk(KERN_INFO DEVICE_NAME ": already running\n");
1507 if (!chan->running) {
1508 printk(KERN_INFO DEVICE_NAME ": already stopped\n");
1513 if (dev->card_info->switch_ctrl)
1514 dev->card_info->switch_ctrl(chan, 1, state ^ 1);
1517 spin_lock_irq(&chan->state_lock);
1519 /* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
1520 ngreadl(0x9310)); */
1521 my_dvb_ringbuffer_flush(&dev->tsout_rbuf);
1523 if (chan->mode & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1524 chan->Capture1Length = 512 * 188;
1525 mode = SMODE_TRANSPORT_STREAM;
1527 if (chan->mode & NGENE_IO_TSOUT) {
1528 chan->pBufferExchange = tsout_exchange;
1529 /* 0x66666666 = 50MHz *2^33 /250MHz */
1530 chan->AudioDTOValue = 0x66666666;
1531 /* set_dto(chan, 38810700+1000); */
1532 /* set_dto(chan, 19392658); */
1534 if (chan->mode & NGENE_IO_TSIN)
1535 chan->pBufferExchange = tsin_exchange;
1536 /* ngwritel(0, 0x9310); */
1537 spin_unlock_irq(&chan->state_lock);
1539 ;/* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
1540 ngreadl(0x9310)); */
1542 ret = ngene_command_stream_control(dev, chan->number,
1543 control, mode, flags);
1545 chan->running = state;
1547 printk(KERN_ERR DEVICE_NAME ": set_transfer %d failed\n",
1550 spin_lock_irq(&chan->state_lock);
1551 chan->pBufferExchange = 0;
1552 my_dvb_ringbuffer_flush(&dev->tsout_rbuf);
1553 spin_unlock_irq(&chan->state_lock);
1557 static int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed)
1559 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
1560 struct ngene_channel *chan = dvbdmx->priv;
1561 #ifdef NGENE_COMMAND_API
1562 struct ngene *dev = chan->dev;
1564 if (dev->card_info->io_type[chan->number] & NGENE_IO_TSOUT) {
1565 switch (dvbdmxfeed->pes_type) {
1566 case DMX_TS_PES_VIDEO:
1567 send_cli_val(dev, "vpid", dvbdmxfeed->pid);
1568 send_cli(dev, "res 1080i50\n");
1569 /* send_cli(dev, "vdec mpeg2\n"); */
1572 case DMX_TS_PES_AUDIO:
1573 send_cli_val(dev, "apid", dvbdmxfeed->pid);
1574 send_cli(dev, "start\n");
1577 case DMX_TS_PES_PCR:
1578 send_cli_val(dev, "pcrpid", dvbdmxfeed->pid);
1588 if (chan->users == 0) {
1589 set_transfer(chan, 1);
1593 return ++chan->users;
1596 static int ngene_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
1598 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
1599 struct ngene_channel *chan = dvbdmx->priv;
1600 #ifdef NGENE_COMMAND_API
1601 struct ngene *dev = chan->dev;
1603 if (dev->card_info->io_type[chan->number] & NGENE_IO_TSOUT) {
1604 switch (dvbdmxfeed->pes_type) {
1605 case DMX_TS_PES_VIDEO:
1606 send_cli(dev, "stop\n");
1609 case DMX_TS_PES_AUDIO:
1612 case DMX_TS_PES_PCR:
1625 set_transfer(chan, 0);
1632 static int write_to_decoder(struct dvb_demux_feed *feed,
1633 const u8 *buf, size_t len)
1635 struct dvb_demux *dvbdmx = feed->demux;
1636 struct ngene_channel *chan = dvbdmx->priv;
1637 struct ngene *dev = chan->dev;
1639 if (wait_event_interruptible(dev->tsout_rbuf.queue,
1641 (&dev->tsout_rbuf) >= len) < 0)
1644 dvb_ringbuffer_write(&dev->tsout_rbuf, buf, len);
1649 static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
1650 int (*start_feed)(struct dvb_demux_feed *),
1651 int (*stop_feed)(struct dvb_demux_feed *),
1654 dvbdemux->priv = priv;
1656 dvbdemux->filternum = 256;
1657 dvbdemux->feednum = 256;
1658 dvbdemux->start_feed = start_feed;
1659 dvbdemux->stop_feed = stop_feed;
1660 dvbdemux->write_to_decoder = 0;
1661 dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
1662 DMX_SECTION_FILTERING |
1663 DMX_MEMORY_BASED_FILTERING);
1664 return dvb_dmx_init(dvbdemux);
1667 static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
1668 struct dvb_demux *dvbdemux,
1669 struct dmx_frontend *hw_frontend,
1670 struct dmx_frontend *mem_frontend,
1671 struct dvb_adapter *dvb_adapter)
1675 dmxdev->filternum = 256;
1676 dmxdev->demux = &dvbdemux->dmx;
1677 dmxdev->capabilities = 0;
1678 ret = dvb_dmxdev_init(dmxdev, dvb_adapter);
1682 hw_frontend->source = DMX_FRONTEND_0;
1683 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend);
1684 mem_frontend->source = DMX_MEMORY_FE;
1685 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend);
1686 return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend);
1689 /****************************************************************************/
1690 /* Decypher firmware loading ************************************************/
1691 /****************************************************************************/
1693 #define DECYPHER_FW "decypher.fw"
1695 static int dec_ts_send(struct ngene *dev, u8 *buf, u32 len)
1697 while (dvb_ringbuffer_free(&dev->tsout_rbuf) < len)
1701 dvb_ringbuffer_write(&dev->tsout_rbuf, buf, len);
1706 u8 dec_fw_fill_ts[188] = { 0x47, 0x09, 0x0e, 0x10, 0xff, 0xff, 0x00, 0x00 };
1708 int dec_fw_send(struct ngene *dev, u8 *fw, u32 size)
1710 struct ngene_channel *chan = &dev->channel[4];
1711 u32 len = 180, cc = 0;
1712 u8 buf[8] = { 0x47, 0x09, 0x0e, 0x10, 0x00, 0x00, 0x00, 0x00 };
1714 set_transfer(chan, 1);
1720 buf[3] = 0x10 | (cc & 0x0f);
1725 dec_ts_send(dev, buf, 8);
1726 dec_ts_send(dev, fw, len);
1728 dec_ts_send(dev, dec_fw_fill_ts + len + 8, 180 - len);
1733 for (len = 0; len < 512; len++)
1734 dec_ts_send(dev, dec_fw_fill_ts, 188);
1735 while (dvb_ringbuffer_avail(&dev->tsout_rbuf))
1738 set_transfer(chan, 0);
1742 int dec_fw_boot(struct ngene *dev)
1745 const struct firmware *fw = NULL;
1748 if (request_firmware(&fw, DECYPHER_FW, &dev->pci_dev->dev) < 0) {
1749 printk(KERN_ERR DEVICE_NAME
1750 ": %s not found. Check hotplug directory.\n",
1754 printk(KERN_INFO DEVICE_NAME ": Booting decypher firmware file %s\n",
1758 dec_fw = (u8 *)fw->data;
1759 dec_fw_send(dev, dec_fw, size);
1760 release_firmware(fw);
1764 /****************************************************************************/
1765 /* nGene hardware init and release functions ********************************/
1766 /****************************************************************************/
1768 void free_ringbuffer(struct ngene *dev, struct SRingBufferDescriptor *rb)
1770 struct SBufferHeader *Cur = rb->Head;
1776 for (j = 0; j < rb->NumBuffers; j++, Cur = Cur->Next) {
1778 pci_free_consistent(dev->pci_dev,
1781 Cur->scList1->Address);
1784 pci_free_consistent(dev->pci_dev,
1787 Cur->scList2->Address);
1791 pci_free_consistent(dev->pci_dev, rb->SCListMemSize,
1792 rb->SCListMem, rb->PASCListMem);
1794 pci_free_consistent(dev->pci_dev, rb->MemSize, rb->Head, rb->PAHead);
1797 void free_idlebuffer(struct ngene *dev,
1798 struct SRingBufferDescriptor *rb,
1799 struct SRingBufferDescriptor *tb)
1802 struct SBufferHeader *Cur = tb->Head;
1806 free_ringbuffer(dev, rb);
1807 for (j = 0; j < tb->NumBuffers; j++, Cur = Cur->Next) {
1810 Cur->ngeneBuffer.Address_of_first_entry_2 = 0;
1811 Cur->ngeneBuffer.Number_of_entries_2 = 0;
1815 void free_common_buffers(struct ngene *dev)
1818 struct ngene_channel *chan;
1820 for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
1821 chan = &dev->channel[i];
1822 free_idlebuffer(dev, &chan->TSIdleBuffer, &chan->TSRingBuffer);
1823 free_ringbuffer(dev, &chan->RingBuffer);
1824 free_ringbuffer(dev, &chan->TSRingBuffer);
1827 if (dev->OverflowBuffer)
1828 pci_free_consistent(dev->pci_dev,
1829 OVERFLOW_BUFFER_SIZE,
1830 dev->OverflowBuffer, dev->PAOverflowBuffer);
1832 if (dev->FWInterfaceBuffer)
1833 pci_free_consistent(dev->pci_dev,
1835 dev->FWInterfaceBuffer,
1836 dev->PAFWInterfaceBuffer);
1839 /****************************************************************************/
1840 /* Ring buffer handling *****************************************************/
1841 /****************************************************************************/
1843 int create_ring_buffer(struct pci_dev *pci_dev,
1844 struct SRingBufferDescriptor *descr, u32 NumBuffers)
1847 struct SBufferHeader *Head;
1849 u32 MemSize = SIZEOF_SBufferHeader * NumBuffers;
1850 u64 PARingBufferHead;
1851 u64 PARingBufferCur;
1852 u64 PARingBufferNext;
1853 struct SBufferHeader *Cur, *Next;
1858 descr->NumBuffers = 0;
1863 Head = pci_alloc_consistent(pci_dev, MemSize, &tmp);
1864 PARingBufferHead = tmp;
1869 memset(Head, 0, MemSize);
1871 PARingBufferCur = PARingBufferHead;
1874 for (i = 0; i < NumBuffers - 1; i++) {
1875 Next = (struct SBufferHeader *)
1876 (((u8 *) Cur) + SIZEOF_SBufferHeader);
1877 PARingBufferNext = PARingBufferCur + SIZEOF_SBufferHeader;
1879 Cur->ngeneBuffer.Next = PARingBufferNext;
1881 PARingBufferCur = PARingBufferNext;
1883 /* Last Buffer points back to first one */
1885 Cur->ngeneBuffer.Next = PARingBufferHead;
1888 descr->MemSize = MemSize;
1889 descr->PAHead = PARingBufferHead;
1890 descr->NumBuffers = NumBuffers;
1895 static int AllocateRingBuffers(struct pci_dev *pci_dev,
1897 struct SRingBufferDescriptor *pRingBuffer,
1898 u32 Buffer1Length, u32 Buffer2Length)
1903 u32 SCListMemSize = pRingBuffer->NumBuffers
1904 * ((Buffer2Length != 0) ? (NUM_SCATTER_GATHER_ENTRIES * 2) :
1905 NUM_SCATTER_GATHER_ENTRIES)
1906 * sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1909 PHW_SCATTER_GATHER_ELEMENT SCListEntry;
1911 struct SBufferHeader *Cur;
1914 if (SCListMemSize < 4096)
1915 SCListMemSize = 4096;
1917 SCListMem = pci_alloc_consistent(pci_dev, SCListMemSize, &tmp);
1920 if (SCListMem == NULL)
1923 memset(SCListMem, 0, SCListMemSize);
1925 pRingBuffer->SCListMem = SCListMem;
1926 pRingBuffer->PASCListMem = PASCListMem;
1927 pRingBuffer->SCListMemSize = SCListMemSize;
1928 pRingBuffer->Buffer1Length = Buffer1Length;
1929 pRingBuffer->Buffer2Length = Buffer2Length;
1931 SCListEntry = (PHW_SCATTER_GATHER_ELEMENT) SCListMem;
1932 PASCListEntry = PASCListMem;
1933 Cur = pRingBuffer->Head;
1935 for (i = 0; i < pRingBuffer->NumBuffers; i += 1, Cur = Cur->Next) {
1938 void *Buffer = pci_alloc_consistent(pci_dev, Buffer1Length,
1945 Cur->Buffer1 = Buffer;
1947 SCListEntry->Address = PABuffer;
1948 SCListEntry->Length = Buffer1Length;
1950 Cur->scList1 = SCListEntry;
1951 Cur->ngeneBuffer.Address_of_first_entry_1 = PASCListEntry;
1952 Cur->ngeneBuffer.Number_of_entries_1 =
1953 NUM_SCATTER_GATHER_ENTRIES;
1956 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1958 #if NUM_SCATTER_GATHER_ENTRIES > 1
1959 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j += 1) {
1960 SCListEntry->Address = of;
1961 SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
1964 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1971 Buffer = pci_alloc_consistent(pci_dev, Buffer2Length, &tmp);
1977 Cur->Buffer2 = Buffer;
1979 SCListEntry->Address = PABuffer;
1980 SCListEntry->Length = Buffer2Length;
1982 Cur->scList2 = SCListEntry;
1983 Cur->ngeneBuffer.Address_of_first_entry_2 = PASCListEntry;
1984 Cur->ngeneBuffer.Number_of_entries_2 =
1985 NUM_SCATTER_GATHER_ENTRIES;
1988 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1990 #if NUM_SCATTER_GATHER_ENTRIES > 1
1991 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j++) {
1992 SCListEntry->Address = of;
1993 SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
1996 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
2005 static int FillTSIdleBuffer(struct SRingBufferDescriptor *pIdleBuffer,
2006 struct SRingBufferDescriptor *pRingBuffer)
2010 /* Copy pointer to scatter gather list in TSRingbuffer
2011 structure for buffer 2
2012 Load number of buffer
2014 u32 n = pRingBuffer->NumBuffers;
2016 /* Point to first buffer entry */
2017 struct SBufferHeader *Cur = pRingBuffer->Head;
2019 /* Loop thru all buffer and set Buffer 2 pointers to TSIdlebuffer */
2020 for (i = 0; i < n; i++) {
2021 Cur->Buffer2 = pIdleBuffer->Head->Buffer1;
2022 Cur->scList2 = pIdleBuffer->Head->scList1;
2023 Cur->ngeneBuffer.Address_of_first_entry_2 =
2024 pIdleBuffer->Head->ngeneBuffer.
2025 Address_of_first_entry_1;
2026 Cur->ngeneBuffer.Number_of_entries_2 =
2027 pIdleBuffer->Head->ngeneBuffer.Number_of_entries_1;
2033 static u32 RingBufferSizes[MAX_STREAM] = {
2041 static u32 Buffer1Sizes[MAX_STREAM] = {
2042 MAX_VIDEO_BUFFER_SIZE,
2043 MAX_VIDEO_BUFFER_SIZE,
2044 MAX_AUDIO_BUFFER_SIZE,
2045 MAX_AUDIO_BUFFER_SIZE,
2046 MAX_AUDIO_BUFFER_SIZE
2049 static u32 Buffer2Sizes[MAX_STREAM] = {
2050 MAX_VBI_BUFFER_SIZE,
2051 MAX_VBI_BUFFER_SIZE,
2058 static int AllocCommonBuffers(struct ngene *dev)
2062 dev->FWInterfaceBuffer = pci_alloc_consistent(dev->pci_dev, 4096,
2063 &dev->PAFWInterfaceBuffer);
2064 if (!dev->FWInterfaceBuffer)
2066 dev->hosttongene = dev->FWInterfaceBuffer;
2067 dev->ngenetohost = dev->FWInterfaceBuffer + 256;
2068 dev->EventBuffer = dev->FWInterfaceBuffer + 512;
2070 dev->OverflowBuffer = pci_alloc_consistent(dev->pci_dev,
2071 OVERFLOW_BUFFER_SIZE,
2072 &dev->PAOverflowBuffer);
2073 if (!dev->OverflowBuffer)
2075 memset(dev->OverflowBuffer, 0, OVERFLOW_BUFFER_SIZE);
2077 for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
2078 int type = dev->card_info->io_type[i];
2080 dev->channel[i].State = KSSTATE_STOP;
2082 if (type & (NGENE_IO_TV | NGENE_IO_HDTV | NGENE_IO_AIN)) {
2083 status = create_ring_buffer(dev->pci_dev,
2084 &dev->channel[i].RingBuffer,
2085 RingBufferSizes[i]);
2089 if (type & (NGENE_IO_TV | NGENE_IO_AIN)) {
2090 status = AllocateRingBuffers(dev->pci_dev,
2099 } else if (type & NGENE_IO_HDTV) {
2100 status = AllocateRingBuffers(dev->pci_dev,
2105 MAX_HDTV_BUFFER_SIZE,
2112 if (type & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
2114 status = create_ring_buffer(dev->pci_dev,
2116 TSRingBuffer, RING_SIZE_TS);
2120 status = AllocateRingBuffers(dev->pci_dev,
2121 dev->PAOverflowBuffer,
2124 MAX_TS_BUFFER_SIZE, 0);
2129 if (type & NGENE_IO_TSOUT) {
2130 status = create_ring_buffer(dev->pci_dev,
2135 status = AllocateRingBuffers(dev->pci_dev,
2136 dev->PAOverflowBuffer,
2139 MAX_TS_BUFFER_SIZE, 0);
2142 FillTSIdleBuffer(&dev->channel[i].TSIdleBuffer,
2143 &dev->channel[i].TSRingBuffer);
2149 static void ngene_release_buffers(struct ngene *dev)
2152 iounmap(dev->iomem);
2153 free_common_buffers(dev);
2154 vfree(dev->tsout_buf);
2155 vfree(dev->ain_buf);
2156 vfree(dev->vin_buf);
2160 static int ngene_get_buffers(struct ngene *dev)
2162 if (AllocCommonBuffers(dev))
2164 if (dev->card_info->io_type[4] & NGENE_IO_TSOUT) {
2165 dev->tsout_buf = vmalloc(TSOUT_BUF_SIZE);
2166 if (!dev->tsout_buf)
2168 dvb_ringbuffer_init(&dev->tsout_rbuf,
2169 dev->tsout_buf, TSOUT_BUF_SIZE);
2171 if (dev->card_info->io_type[2] & NGENE_IO_AIN) {
2172 dev->ain_buf = vmalloc(AIN_BUF_SIZE);
2175 dvb_ringbuffer_init(&dev->ain_rbuf, dev->ain_buf, AIN_BUF_SIZE);
2177 if (dev->card_info->io_type[0] & NGENE_IO_HDTV) {
2178 dev->vin_buf = vmalloc(VIN_BUF_SIZE);
2181 dvb_ringbuffer_init(&dev->vin_rbuf, dev->vin_buf, VIN_BUF_SIZE);
2183 dev->iomem = ioremap(pci_resource_start(dev->pci_dev, 0),
2184 pci_resource_len(dev->pci_dev, 0));
2191 static void ngene_init(struct ngene *dev)
2195 tasklet_init(&dev->event_tasklet, event_tasklet, (unsigned long)dev);
2197 memset_io(dev->iomem + 0xc000, 0x00, 0x220);
2198 memset_io(dev->iomem + 0xc400, 0x00, 0x100);
2200 for (i = 0; i < MAX_STREAM; i++) {
2201 dev->channel[i].dev = dev;
2202 dev->channel[i].number = i;
2205 dev->fw_interface_version = 0;
2207 ngwritel(0, NGENE_INT_ENABLE);
2209 dev->icounts = ngreadl(NGENE_INT_COUNTS);
2211 dev->device_version = ngreadl(DEV_VER) & 0x0f;
2212 printk(KERN_INFO DEVICE_NAME ": Device version %d\n",
2213 dev->device_version);
2216 static int ngene_load_firm(struct ngene *dev)
2219 const struct firmware *fw = NULL;
2224 version = dev->card_info->fw_version;
2231 fw_name = "ngene_15.fw";
2235 fw_name = "ngene_16.fw";
2239 fw_name = "ngene_17.fw";
2243 if (request_firmware(&fw, fw_name, &dev->pci_dev->dev) < 0) {
2244 printk(KERN_ERR DEVICE_NAME
2245 ": Could not load firmware file %s.\n", fw_name);
2246 printk(KERN_INFO DEVICE_NAME
2247 ": Copy %s to your hotplug directory!\n", fw_name);
2250 if (size != fw->size) {
2251 printk(KERN_ERR DEVICE_NAME
2252 ": Firmware %s has invalid size!", fw_name);
2255 printk(KERN_INFO DEVICE_NAME
2256 ": Loading firmware file %s.\n", fw_name);
2257 ngene_fw = (u8 *) fw->data;
2258 err = ngene_command_load_firmware(dev, ngene_fw, size);
2261 release_firmware(fw);
2266 static void ngene_stop(struct ngene *dev)
2268 down(&dev->cmd_mutex);
2269 i2c_del_adapter(&(dev->channel[0].i2c_adapter));
2270 i2c_del_adapter(&(dev->channel[1].i2c_adapter));
2271 ngwritel(0, NGENE_INT_ENABLE);
2272 ngwritel(0, NGENE_COMMAND);
2273 ngwritel(0, NGENE_COMMAND_HI);
2274 ngwritel(0, NGENE_STATUS);
2275 ngwritel(0, NGENE_STATUS_HI);
2276 ngwritel(0, NGENE_EVENT);
2277 ngwritel(0, NGENE_EVENT_HI);
2278 free_irq(dev->pci_dev->irq, dev);
2281 static int ngene_start(struct ngene *dev)
2286 pci_set_master(dev->pci_dev);
2289 stat = request_irq(dev->pci_dev->irq, irq_handler,
2290 IRQF_SHARED, "nGene",
2295 init_waitqueue_head(&dev->cmd_wq);
2296 init_waitqueue_head(&dev->tx_wq);
2297 init_waitqueue_head(&dev->rx_wq);
2298 sema_init(&dev->cmd_mutex, 1);
2299 sema_init(&dev->stream_mutex, 1);
2300 sema_init(&dev->pll_mutex, 1);
2301 sema_init(&dev->i2c_switch_mutex, 1);
2302 spin_lock_init(&dev->cmd_lock);
2303 for (i = 0; i < MAX_STREAM; i++)
2304 spin_lock_init(&dev->channel[i].state_lock);
2305 ngwritel(1, TIMESTAMPS);
2307 ngwritel(1, NGENE_INT_ENABLE);
2309 stat = ngene_load_firm(dev);
2313 stat = ngene_i2c_init(dev, 0);
2317 stat = ngene_i2c_init(dev, 1);
2321 if (dev->card_info->fw_version == 17) {
2323 {6144 / 64, 0, 0, 2048 / 64, 2048 / 64, 2048 / 64};
2324 u8 tsin4_config[6] =
2325 {3072 / 64, 3072 / 64, 0, 3072 / 64, 3072 / 64, 0};
2326 u8 default_config[6] =
2327 {4096 / 64, 4096 / 64, 0, 2048 / 64, 2048 / 64, 0};
2328 u8 *bconf = default_config;
2330 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
2331 bconf = tsin4_config;
2332 if (dev->card_info->io_type[0] == NGENE_IO_HDTV) {
2333 bconf = hdtv_config;
2334 ngene_reset_decypher(dev);
2336 printk(KERN_INFO DEVICE_NAME ": FW 17 buffer config\n");
2337 stat = ngene_command_config_free_buf(dev, bconf);
2339 int bconf = BUFFER_CONFIG_4422;
2341 if (dev->card_info->io_type[0] == NGENE_IO_HDTV) {
2342 bconf = BUFFER_CONFIG_8022;
2343 ngene_reset_decypher(dev);
2345 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
2346 bconf = BUFFER_CONFIG_3333;
2347 stat = ngene_command_config_buf(dev, bconf);
2350 if (dev->card_info->io_type[0] == NGENE_IO_HDTV) {
2351 ngene_command_config_uart(dev, 0xc1, tx_cb, rx_cb);
2352 test_dec_i2c(&dev->channel[0].i2c_adapter, 0);
2353 test_dec_i2c(&dev->channel[0].i2c_adapter, 1);
2358 ngwritel(0, NGENE_INT_ENABLE);
2359 free_irq(dev->pci_dev->irq, dev);
2365 /****************************************************************************/
2366 /* Switch control (I2C gates, etc.) *****************************************/
2367 /****************************************************************************/
2370 /****************************************************************************/
2371 /* Demod/tuner attachment ***************************************************/
2372 /****************************************************************************/
2375 /****************************************************************************/
2376 /****************************************************************************/
2377 /****************************************************************************/
2379 static void release_channel(struct ngene_channel *chan)
2381 struct dvb_demux *dvbdemux = &chan->demux;
2382 struct ngene *dev = chan->dev;
2383 struct ngene_info *ni = dev->card_info;
2384 int io = ni->io_type[chan->number];
2386 tasklet_kill(&chan->demux_tasklet);
2388 if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
2389 #ifdef NGENE_COMMAND_API
2390 if (chan->command_dev)
2391 dvb_unregister_device(chan->command_dev);
2394 dvb_unregister_frontend(chan->fe);
2395 /*dvb_frontend_detach(chan->fe); */
2398 dvbdemux->dmx.close(&dvbdemux->dmx);
2399 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
2400 &chan->hw_frontend);
2401 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
2402 &chan->mem_frontend);
2403 dvb_dmxdev_release(&chan->dmxdev);
2404 dvb_dmx_release(&chan->demux);
2406 dvb_unregister_adapter(&chan->dvb_adapter);
2412 static int init_channel(struct ngene_channel *chan)
2414 int ret = 0, nr = chan->number;
2415 struct dvb_adapter *adapter = 0;
2416 struct dvb_demux *dvbdemux = &chan->demux;
2417 struct ngene *dev = chan->dev;
2418 struct ngene_info *ni = dev->card_info;
2419 int io = ni->io_type[nr];
2421 tasklet_init(&chan->demux_tasklet, demux_tasklet, (unsigned long)chan);
2424 chan->mode = chan->type; /* for now only one mode */
2426 if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
2427 if (nr >= STREAM_AUDIOIN1)
2428 chan->DataFormatFlags = DF_SWAP32;
2430 if (io & NGENE_IO_TSOUT)
2434 adapter = &chan->dev->dvb_adapter;
2436 ret = dvb_register_adapter(&chan->dvb_adapter, "nGene",
2438 &chan->dev->pci_dev->dev);
2441 adapter = &chan->dvb_adapter;
2443 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
2445 ngene_stop_feed, chan);
2446 ret = my_dvb_dmxdev_ts_card_init(&chan->dmxdev, &chan->demux,
2448 &chan->mem_frontend, adapter);
2449 if (io & NGENE_IO_TSOUT) {
2450 dvbdemux->write_to_decoder = write_to_decoder;
2452 #ifdef NGENE_COMMAND_API
2453 dvb_register_device(adapter, &chan->command_dev,
2454 &dvbdev_command, (void *)chan,
2459 if (io & NGENE_IO_TSIN) {
2461 if (ni->demod_attach[nr])
2462 ni->demod_attach[nr](chan);
2464 if (dvb_register_frontend(adapter, chan->fe) < 0) {
2465 if (chan->fe->ops.release)
2466 chan->fe->ops.release(chan->fe);
2470 if (chan->fe && ni->tuner_attach[nr])
2471 if (ni->tuner_attach[nr] (chan) < 0) {
2472 printk(KERN_ERR DEVICE_NAME
2473 ": Tuner attach failed on channel %d!\n",
2481 static int init_channels(struct ngene *dev)
2485 for (i = 0; i < MAX_STREAM; i++) {
2486 if (init_channel(&dev->channel[i]) < 0) {
2487 for (j = 0; j < i; j++)
2488 release_channel(&dev->channel[j]);
2495 /****************************************************************************/
2496 /* device probe/remove calls ************************************************/
2497 /****************************************************************************/
2499 static void __devexit ngene_remove(struct pci_dev *pdev)
2501 struct ngene *dev = (struct ngene *)pci_get_drvdata(pdev);
2504 tasklet_kill(&dev->event_tasklet);
2505 for (i = 0; i < MAX_STREAM; i++)
2506 release_channel(&dev->channel[i]);
2508 dvb_unregister_adapter(&dev->dvb_adapter);
2511 ngene_release_buffers(dev);
2512 pci_set_drvdata(pdev, 0);
2513 pci_disable_device(pdev);
2516 static int __devinit ngene_probe(struct pci_dev *pci_dev,
2517 const struct pci_device_id *id)
2522 if (pci_enable_device(pci_dev) < 0)
2525 dev = vmalloc(sizeof(struct ngene));
2528 memset(dev, 0, sizeof(struct ngene));
2530 dev->pci_dev = pci_dev;
2531 dev->card_info = (struct ngene_info *)id->driver_data;
2532 printk(KERN_INFO DEVICE_NAME ": Found %s\n", dev->card_info->name);
2534 pci_set_drvdata(pci_dev, dev);
2536 /* Alloc buffers and start nGene */
2537 stat = ngene_get_buffers(dev);
2540 stat = ngene_start(dev);
2544 dev->i2c_current_bus = -1;
2545 /* Disable analog TV decoder chips if present */
2547 i2c_copy_eeprom(&dev->channel[0].i2c_adapter, 0x50, 0x52);
2548 i2c_dump_eeprom(&dev->channel[0].i2c_adapter, 0x52);
2550 /*i2c_check_eeprom(&dev->i2c_adapter);*/
2552 /* Register DVB adapters and devices for both channels */
2554 if (dvb_register_adapter(&dev->dvb_adapter, "nGene", THIS_MODULE,
2555 &dev->pci_dev->dev, adapter_nr) < 0)
2558 if (init_channels(dev) < 0)
2566 ngene_release_buffers(dev);
2567 pci_set_drvdata(pci_dev, 0);
2571 /****************************************************************************/
2572 /* Card configs *************************************************************/
2573 /****************************************************************************/
2577 /****************************************************************************/
2578 /****************************************************************************/
2579 /****************************************************************************/
2581 #define NGENE_ID(_subvend, _subdev, _driverdata) { \
2582 .vendor = NGENE_VID, .device = NGENE_PID, \
2583 .subvendor = _subvend, .subdevice = _subdev, \
2584 .driver_data = (unsigned long) &_driverdata }
2586 /****************************************************************************/
2588 static const struct pci_device_id ngene_id_tbl[] __devinitdata = {
2592 /****************************************************************************/
2593 /* Init/Exit ****************************************************************/
2594 /****************************************************************************/
2596 static pci_ers_result_t ngene_error_detected(struct pci_dev *dev,
2597 enum pci_channel_state state)
2599 printk(KERN_ERR DEVICE_NAME ": PCI error\n");
2600 if (state == pci_channel_io_perm_failure)
2601 return PCI_ERS_RESULT_DISCONNECT;
2602 if (state == pci_channel_io_frozen)
2603 return PCI_ERS_RESULT_NEED_RESET;
2604 return PCI_ERS_RESULT_CAN_RECOVER;
2607 static pci_ers_result_t ngene_link_reset(struct pci_dev *dev)
2609 printk(KERN_INFO DEVICE_NAME ": link reset\n");
2613 static pci_ers_result_t ngene_slot_reset(struct pci_dev *dev)
2615 printk(KERN_INFO DEVICE_NAME ": slot reset\n");
2619 static void ngene_resume(struct pci_dev *dev)
2621 printk(KERN_INFO DEVICE_NAME ": resume\n");
2624 static struct pci_error_handlers ngene_errors = {
2625 .error_detected = ngene_error_detected,
2626 .link_reset = ngene_link_reset,
2627 .slot_reset = ngene_slot_reset,
2628 .resume = ngene_resume,
2631 static struct pci_driver ngene_pci_driver = {
2633 .id_table = ngene_id_tbl,
2634 .probe = ngene_probe,
2635 .remove = ngene_remove,
2636 .err_handler = &ngene_errors,
2639 static __init int module_init_ngene(void)
2642 "nGene PCIE bridge driver, Copyright (C) 2005-2007 Micronas\n");
2643 return pci_register_driver(&ngene_pci_driver);
2646 static __exit void module_exit_ngene(void)
2648 pci_unregister_driver(&ngene_pci_driver);
2651 module_init(module_init_ngene);
2652 module_exit(module_exit_ngene);
2654 MODULE_DESCRIPTION("nGene");
2655 MODULE_AUTHOR("Micronas, Ralph Metzler, Manfred Voelkel");
2656 MODULE_LICENSE("GPL");