Merge branch 'v4l_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab...
[linux-2.6.git] / drivers / media / dvb / frontends / it913x-fe.h
1 /*
2  *  Driver for it913x Frontend
3  *
4  *
5  *  This program is free software; you can redistribute it and/or modify
6  *  it under the terms of the GNU General Public License as published by
7  *  the Free Software Foundation; either version 2 of the License, or
8  *  (at your option) any later version.
9  *
10  *  This program is distributed in the hope that it will be useful,
11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  *
14  *  GNU General Public License for more details.
15  *
16  *  You should have received a copy of the GNU General Public License
17  *  along with this program; if not, write to the Free Software
18  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
19  */
20
21 #ifndef IT913X_FE_H
22 #define IT913X_FE_H
23
24 #include <linux/dvb/frontend.h>
25 #include "dvb_frontend.h"
26
27 struct ite_config {
28         u8 chip_ver;
29         u16 chip_type;
30         u32 firmware;
31         u8 firmware_ver;
32         u8 adc_x2;
33         u8 tuner_id_0;
34         u8 tuner_id_1;
35         u8 dual_mode;
36         u8 adf;
37 };
38
39 #if defined(CONFIG_DVB_IT913X_FE) || (defined(CONFIG_DVB_IT913X_FE_MODULE) && \
40 defined(MODULE))
41 extern struct dvb_frontend *it913x_fe_attach(struct i2c_adapter *i2c_adap,
42                         u8 i2c_addr, struct ite_config *config);
43 #else
44 static inline struct dvb_frontend *it913x_fe_attach(
45                 struct i2c_adapter *i2c_adap,
46                         u8 i2c_addr, struct ite_config *config)
47 {
48         printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
49         return NULL;
50 }
51 #endif /* CONFIG_IT913X_FE */
52 #define I2C_BASE_ADDR           0x10
53 #define DEV_0                   0x0
54 #define DEV_1                   0x10
55 #define PRO_LINK                0x0
56 #define PRO_DMOD                0x1
57 #define DEV_0_DMOD              (PRO_DMOD << 0x7)
58 #define DEV_1_DMOD              (DEV_0_DMOD | DEV_1)
59 #define CHIP2_I2C_ADDR          0x3a
60
61 #define AFE_MEM0                0xfb24
62
63 #define MP2_SW_RST              0xf99d
64 #define MP2IF2_SW_RST           0xf9a4
65
66 #define PADODPU                 0xd827
67 #define THIRDODPU               0xd828
68 #define AGC_O_D                 0xd829
69
70 #define EP0_TX_EN               0xdd11
71 #define EP0_TX_NAK              0xdd13
72 #define EP4_TX_LEN_LSB          0xdd88
73 #define EP4_TX_LEN_MSB          0xdd89
74 #define EP4_MAX_PKT             0xdd0c
75 #define EP5_TX_LEN_LSB          0xdd8a
76 #define EP5_TX_LEN_MSB          0xdd8b
77 #define EP5_MAX_PKT             0xdd0d
78
79 #define IO_MUX_POWER_CLK        0xd800
80 #define CLK_O_EN                0xd81a
81 #define I2C_CLK                 0xf103
82 #define I2C_CLK_100             0x7
83 #define I2C_CLK_400             0x1a
84
85 #define D_TPSD_LOCK             0xf5a9
86 #define MP2IF2_EN               0xf9a3
87 #define MP2IF_SERIAL            0xf985
88 #define TSIS_ENABLE             0xf9cd
89 #define MP2IF2_HALF_PSB         0xf9a5
90 #define MP2IF_STOP_EN           0xf9b5
91 #define MPEG_FULL_SPEED         0xf990
92 #define TOP_HOSTB_SER_MODE      0xd91c
93
94 #define PID_RST                 0xf992
95 #define PID_EN                  0xf993
96 #define PID_INX_EN              0xf994
97 #define PID_INX                 0xf995
98 #define PID_LSB                 0xf996
99 #define PID_MSB                 0xf997
100
101 #define MP2IF_MPEG_PAR_MODE     0xf986
102 #define DCA_UPPER_CHIP          0xf731
103 #define DCA_LOWER_CHIP          0xf732
104 #define DCA_PLATCH              0xf730
105 #define DCA_FPGA_LATCH          0xf778
106 #define DCA_STAND_ALONE         0xf73c
107 #define DCA_ENABLE              0xf776
108
109 #define DVBT_INTEN              0xf41f
110 #define DVBT_ENABLE             0xf41a
111 #define HOSTB_DCA_LOWER         0xd91f
112 #define HOSTB_MPEG_PAR_MODE     0xd91b
113 #define HOSTB_MPEG_SER_MODE     0xd91c
114 #define HOSTB_MPEG_SER_DO7      0xd91d
115 #define HOSTB_DCA_UPPER         0xd91e
116 #define PADMISCDR2              0xd830
117 #define PADMISCDR4              0xd831
118 #define PADMISCDR8              0xd832
119 #define PADMISCDRSR             0xd833
120 #define LOCK3_OUT               0xd8fd
121
122 #define GPIOH1_O                0xd8af
123 #define GPIOH1_EN               0xd8b0
124 #define GPIOH1_ON               0xd8b1
125 #define GPIOH3_O                0xd8b3
126 #define GPIOH3_EN               0xd8b4
127 #define GPIOH3_ON               0xd8b5
128 #define GPIOH5_O                0xd8bb
129 #define GPIOH5_EN               0xd8bc
130 #define GPIOH5_ON               0xd8bd
131
132 #define AFE_MEM0                0xfb24
133
134 #define REG_TPSD_TX_MODE        0xf900
135 #define REG_TPSD_GI             0xf901
136 #define REG_TPSD_HIER           0xf902
137 #define REG_TPSD_CONST          0xf903
138 #define REG_BW                  0xf904
139 #define REG_PRIV                0xf905
140 #define REG_TPSD_HP_CODE        0xf906
141 #define REG_TPSD_LP_CODE        0xf907
142
143 #define MP2IF_SYNC_LK           0xf999
144 #define ADC_FREQ                0xf1cd
145
146 #define TRIGGER_OFSM            0x0000
147 /* COEFF Registers start at 0x0001 to 0x0020 */
148 #define COEFF_1_2048            0x0001
149 #define XTAL_CLK                0x0025
150 #define BFS_FCW                 0x0029
151
152 /* Error Regs */
153 #define RSD_ABORT_PKT_LSB       0x0032
154 #define RSD_ABORT_PKT_MSB       0x0033
155 #define RSD_BIT_ERR_0_7         0x0034
156 #define RSD_BIT_ERR_8_15        0x0035
157 #define RSD_BIT_ERR_23_16       0x0036
158 #define RSD_BIT_COUNT_LSB       0x0037
159 #define RSD_BIT_COUNT_MSB       0x0038
160
161 #define TPSD_LOCK               0x003c
162 #define TRAINING_MODE           0x0040
163 #define ADC_X_2                 0x0045
164 #define TUNER_ID                0x0046
165 #define EMPTY_CHANNEL_STATUS    0x0047
166 #define SIGNAL_LEVEL            0x0048
167 #define SIGNAL_QUALITY          0x0049
168 #define EST_SIGNAL_LEVEL        0x004a
169 #define FREE_BAND               0x004b
170 #define SUSPEND_FLAG            0x004c
171 /* Build in tuner types */
172 #define IT9137 0x38
173 #define IT9135_38 0x38
174 #define IT9135_51 0x51
175 #define IT9135_52 0x52
176 #define IT9135_60 0x60
177 #define IT9135_61 0x61
178 #define IT9135_62 0x62
179
180 enum {
181         CMD_DEMOD_READ = 0,
182         CMD_DEMOD_WRITE,
183         CMD_TUNER_READ,
184         CMD_TUNER_WRITE,
185         CMD_REG_EEPROM_READ,
186         CMD_REG_EEPROM_WRITE,
187         CMD_DATA_READ,
188         CMD_VAR_READ = 8,
189         CMD_VAR_WRITE,
190         CMD_PLATFORM_GET,
191         CMD_PLATFORM_SET,
192         CMD_IP_CACHE,
193         CMD_IP_ADD,
194         CMD_IP_REMOVE,
195         CMD_PID_ADD,
196         CMD_PID_REMOVE,
197         CMD_SIPSI_GET,
198         CMD_SIPSI_MPE_RESET,
199         CMD_H_PID_ADD = 0x15,
200         CMD_H_PID_REMOVE,
201         CMD_ABORT,
202         CMD_IR_GET,
203         CMD_IR_SET,
204         CMD_FW_DOWNLOAD = 0x21,
205         CMD_QUERYINFO,
206         CMD_BOOT,
207         CMD_FW_DOWNLOAD_BEGIN,
208         CMD_FW_DOWNLOAD_END,
209         CMD_RUN_CODE,
210         CMD_SCATTER_READ = 0x28,
211         CMD_SCATTER_WRITE,
212         CMD_GENERIC_READ,
213         CMD_GENERIC_WRITE
214 };
215
216 enum {
217         READ_LONG,
218         WRITE_LONG,
219         READ_SHORT,
220         WRITE_SHORT,
221         READ_DATA,
222         WRITE_DATA,
223         WRITE_CMD,
224 };
225
226 enum {
227         IT9135_AUTO = 0,
228         IT9137_FW,
229         IT9135_V1_FW,
230         IT9135_V2_FW,
231 };
232
233 #endif /* IT913X_FE_H */