[PATCH] fix missing includes
[linux-2.6.git] / drivers / media / dvb / frontends / dib3000mc.c
1 /*
2  * Frontend driver for mobile DVB-T demodulator DiBcom 3000P/M-C
3  * DiBcom (http://www.dibcom.fr/)
4  *
5  * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@desy.de)
6  *
7  * based on GPL code from DiBCom, which has
8  *
9  * Copyright (C) 2004 Amaury Demol for DiBcom (ademol@dibcom.fr)
10  *
11  *      This program is free software; you can redistribute it and/or
12  *      modify it under the terms of the GNU General Public License as
13  *      published by the Free Software Foundation, version 2.
14  *
15  * Acknowledgements
16  *
17  *  Amaury Demol (ademol@dibcom.fr) from DiBcom for providing specs and driver
18  *  sources, on which this driver (and the dvb-dibusb) are based.
19  *
20  * see Documentation/dvb/README.dibusb for more information
21  *
22  */
23 #include <linux/config.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
29 #include <linux/string.h>
30 #include <linux/slab.h>
31
32 #include "dib3000-common.h"
33 #include "dib3000mc_priv.h"
34 #include "dib3000.h"
35
36 /* Version information */
37 #define DRIVER_VERSION "0.1"
38 #define DRIVER_DESC "DiBcom 3000M-C DVB-T demodulator"
39 #define DRIVER_AUTHOR "Patrick Boettcher, patrick.boettcher@desy.de"
40
41 #ifdef CONFIG_DVB_DIBCOM_DEBUG
42 static int debug;
43 module_param(debug, int, 0644);
44 MODULE_PARM_DESC(debug, "set debugging level (1=info,2=xfer,4=setfe,8=getfe,16=stat (|-able)).");
45 #endif
46 #define deb_info(args...) dprintk(0x01,args)
47 #define deb_xfer(args...) dprintk(0x02,args)
48 #define deb_setf(args...) dprintk(0x04,args)
49 #define deb_getf(args...) dprintk(0x08,args)
50 #define deb_stat(args...) dprintk(0x10,args)
51
52 static int dib3000mc_set_impulse_noise(struct dib3000_state * state, int mode,
53         fe_transmit_mode_t transmission_mode, fe_bandwidth_t bandwidth)
54 {
55         switch (transmission_mode) {
56                 case TRANSMISSION_MODE_2K:
57                         wr_foreach(dib3000mc_reg_fft,dib3000mc_fft_modes[0]);
58                         break;
59                 case TRANSMISSION_MODE_8K:
60                         wr_foreach(dib3000mc_reg_fft,dib3000mc_fft_modes[1]);
61                         break;
62                 default:
63                         break;
64         }
65
66         switch (bandwidth) {
67 /*              case BANDWIDTH_5_MHZ:
68                         wr_foreach(dib3000mc_reg_impulse_noise,dib3000mc_impluse_noise[0]);
69                         break; */
70                 case BANDWIDTH_6_MHZ:
71                         wr_foreach(dib3000mc_reg_impulse_noise,dib3000mc_impluse_noise[1]);
72                         break;
73                 case BANDWIDTH_7_MHZ:
74                         wr_foreach(dib3000mc_reg_impulse_noise,dib3000mc_impluse_noise[2]);
75                         break;
76                 case BANDWIDTH_8_MHZ:
77                         wr_foreach(dib3000mc_reg_impulse_noise,dib3000mc_impluse_noise[3]);
78                         break;
79                 default:
80                         break;
81         }
82
83         switch (mode) {
84                 case 0: /* no impulse */ /* fall through */
85                         wr_foreach(dib3000mc_reg_imp_noise_ctl,dib3000mc_imp_noise_ctl[0]);
86                         break;
87                 case 1: /* new algo */
88                         wr_foreach(dib3000mc_reg_imp_noise_ctl,dib3000mc_imp_noise_ctl[1]);
89                         set_or(DIB3000MC_REG_IMP_NOISE_55,DIB3000MC_IMP_NEW_ALGO(0)); /* gives 1<<10 */
90                         break;
91                 default: /* old algo */
92                         wr_foreach(dib3000mc_reg_imp_noise_ctl,dib3000mc_imp_noise_ctl[3]);
93                         break;
94         }
95         return 0;
96 }
97
98 static int dib3000mc_set_timing(struct dib3000_state *state, int upd_offset,
99                 fe_transmit_mode_t fft, fe_bandwidth_t bw)
100 {
101         u16 timf_msb,timf_lsb;
102         s32 tim_offset,tim_sgn;
103         u64 comp1,comp2,comp=0;
104
105         switch (bw) {
106                 case BANDWIDTH_8_MHZ: comp = DIB3000MC_CLOCK_REF*8; break;
107                 case BANDWIDTH_7_MHZ: comp = DIB3000MC_CLOCK_REF*7; break;
108                 case BANDWIDTH_6_MHZ: comp = DIB3000MC_CLOCK_REF*6; break;
109                 default: err("unknown bandwidth (%d)",bw); break;
110         }
111         timf_msb = (comp >> 16) & 0xff;
112         timf_lsb = (comp & 0xffff);
113
114         // Update the timing offset ;
115         if (upd_offset > 0) {
116                 if (!state->timing_offset_comp_done) {
117                         msleep(200);
118                         state->timing_offset_comp_done = 1;
119                 }
120                 tim_offset = rd(DIB3000MC_REG_TIMING_OFFS_MSB);
121                 if ((tim_offset & 0x2000) == 0x2000)
122                         tim_offset |= 0xC000;
123                 if (fft == TRANSMISSION_MODE_2K)
124                         tim_offset <<= 2;
125                 state->timing_offset += tim_offset;
126         }
127
128         tim_offset = state->timing_offset;
129         if (tim_offset < 0) {
130                 tim_sgn = 1;
131                 tim_offset = -tim_offset;
132         } else
133                 tim_sgn = 0;
134
135         comp1 =  (u32)tim_offset * (u32)timf_lsb ;
136         comp2 =  (u32)tim_offset * (u32)timf_msb ;
137         comp  = ((comp1 >> 16) + comp2) >> 7;
138
139         if (tim_sgn == 0)
140                 comp = (u32)(timf_msb << 16) + (u32) timf_lsb + comp;
141         else
142                 comp = (u32)(timf_msb << 16) + (u32) timf_lsb - comp ;
143
144         timf_msb = (comp >> 16) & 0xff;
145         timf_lsb = comp & 0xffff;
146
147         wr(DIB3000MC_REG_TIMING_FREQ_MSB,timf_msb);
148         wr(DIB3000MC_REG_TIMING_FREQ_LSB,timf_lsb);
149         return 0;
150 }
151
152 static int dib3000mc_init_auto_scan(struct dib3000_state *state, fe_bandwidth_t bw, int boost)
153 {
154         if (boost) {
155                 wr(DIB3000MC_REG_SCAN_BOOST,DIB3000MC_SCAN_BOOST_ON);
156         } else {
157                 wr(DIB3000MC_REG_SCAN_BOOST,DIB3000MC_SCAN_BOOST_OFF);
158         }
159         switch (bw) {
160                 case BANDWIDTH_8_MHZ:
161                         wr_foreach(dib3000mc_reg_bandwidth,dib3000mc_bandwidth_8mhz);
162                         break;
163                 case BANDWIDTH_7_MHZ:
164                         wr_foreach(dib3000mc_reg_bandwidth,dib3000mc_bandwidth_7mhz);
165                         break;
166                 case BANDWIDTH_6_MHZ:
167                         wr_foreach(dib3000mc_reg_bandwidth,dib3000mc_bandwidth_6mhz);
168                         break;
169 /*              case BANDWIDTH_5_MHZ:
170                         wr_foreach(dib3000mc_reg_bandwidth,dib3000mc_bandwidth_5mhz);
171                         break;*/
172                 case BANDWIDTH_AUTO:
173                         return -EOPNOTSUPP;
174                 default:
175                         err("unknown bandwidth value (%d).",bw);
176                         return -EINVAL;
177         }
178         if (boost) {
179                 u32 timeout = (rd(DIB3000MC_REG_BW_TIMOUT_MSB) << 16) +
180                         rd(DIB3000MC_REG_BW_TIMOUT_LSB);
181                 timeout *= 85; timeout >>= 7;
182                 wr(DIB3000MC_REG_BW_TIMOUT_MSB,(timeout >> 16) & 0xffff);
183                 wr(DIB3000MC_REG_BW_TIMOUT_LSB,timeout & 0xffff);
184         }
185         return 0;
186 }
187
188 static int dib3000mc_set_adp_cfg(struct dib3000_state *state, fe_modulation_t con)
189 {
190         switch (con) {
191                 case QAM_64:
192                         wr_foreach(dib3000mc_reg_adp_cfg,dib3000mc_adp_cfg[2]);
193                         break;
194                 case QAM_16:
195                         wr_foreach(dib3000mc_reg_adp_cfg,dib3000mc_adp_cfg[1]);
196                         break;
197                 case QPSK:
198                         wr_foreach(dib3000mc_reg_adp_cfg,dib3000mc_adp_cfg[0]);
199                         break;
200                 case QAM_AUTO:
201                         break;
202                 default:
203                         warn("unkown constellation.");
204                         break;
205         }
206         return 0;
207 }
208
209 static int dib3000mc_set_general_cfg(struct dib3000_state *state, struct dvb_frontend_parameters *fep, int *auto_val)
210 {
211         struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
212         fe_code_rate_t fe_cr = FEC_NONE;
213         u8 fft=0, guard=0, qam=0, alpha=0, sel_hp=0, cr=0, hrch=0;
214         int seq;
215
216         switch (ofdm->transmission_mode) {
217                 case TRANSMISSION_MODE_2K: fft = DIB3000_TRANSMISSION_MODE_2K; break;
218                 case TRANSMISSION_MODE_8K: fft = DIB3000_TRANSMISSION_MODE_8K; break;
219                 case TRANSMISSION_MODE_AUTO: break;
220                 default: return -EINVAL;
221         }
222         switch (ofdm->guard_interval) {
223                 case GUARD_INTERVAL_1_32: guard = DIB3000_GUARD_TIME_1_32; break;
224                 case GUARD_INTERVAL_1_16: guard = DIB3000_GUARD_TIME_1_16; break;
225                 case GUARD_INTERVAL_1_8:  guard = DIB3000_GUARD_TIME_1_8; break;
226                 case GUARD_INTERVAL_1_4:  guard = DIB3000_GUARD_TIME_1_4; break;
227                 case GUARD_INTERVAL_AUTO: break;
228                 default: return -EINVAL;
229         }
230         switch (ofdm->constellation) {
231                 case QPSK:   qam = DIB3000_CONSTELLATION_QPSK; break;
232                 case QAM_16: qam = DIB3000_CONSTELLATION_16QAM; break;
233                 case QAM_64: qam = DIB3000_CONSTELLATION_64QAM; break;
234                 case QAM_AUTO: break;
235                 default: return -EINVAL;
236         }
237         switch (ofdm->hierarchy_information) {
238                 case HIERARCHY_NONE: /* fall through */
239                 case HIERARCHY_1: alpha = DIB3000_ALPHA_1; break;
240                 case HIERARCHY_2: alpha = DIB3000_ALPHA_2; break;
241                 case HIERARCHY_4: alpha = DIB3000_ALPHA_4; break;
242                 case HIERARCHY_AUTO: break;
243                 default: return -EINVAL;
244         }
245         if (ofdm->hierarchy_information == HIERARCHY_NONE) {
246                 hrch   = DIB3000_HRCH_OFF;
247                 sel_hp = DIB3000_SELECT_HP;
248                 fe_cr  = ofdm->code_rate_HP;
249         } else if (ofdm->hierarchy_information != HIERARCHY_AUTO) {
250                 hrch   = DIB3000_HRCH_ON;
251                 sel_hp = DIB3000_SELECT_LP;
252                 fe_cr  = ofdm->code_rate_LP;
253         }
254         switch (fe_cr) {
255                 case FEC_1_2: cr = DIB3000_FEC_1_2; break;
256                 case FEC_2_3: cr = DIB3000_FEC_2_3; break;
257                 case FEC_3_4: cr = DIB3000_FEC_3_4; break;
258                 case FEC_5_6: cr = DIB3000_FEC_5_6; break;
259                 case FEC_7_8: cr = DIB3000_FEC_7_8; break;
260                 case FEC_NONE: break;
261                 case FEC_AUTO: break;
262                 default: return -EINVAL;
263         }
264
265         wr(DIB3000MC_REG_DEMOD_PARM,DIB3000MC_DEMOD_PARM(alpha,qam,guard,fft));
266         wr(DIB3000MC_REG_HRCH_PARM,DIB3000MC_HRCH_PARM(sel_hp,cr,hrch));
267
268         switch (fep->inversion) {
269                 case INVERSION_OFF:
270                         wr(DIB3000MC_REG_SET_DDS_FREQ_MSB,DIB3000MC_DDS_FREQ_MSB_INV_OFF);
271                         break;
272                 case INVERSION_AUTO: /* fall through */
273                 case INVERSION_ON:
274                         wr(DIB3000MC_REG_SET_DDS_FREQ_MSB,DIB3000MC_DDS_FREQ_MSB_INV_ON);
275                         break;
276                 default:
277                         return -EINVAL;
278         }
279
280         seq = dib3000_seq
281                 [ofdm->transmission_mode == TRANSMISSION_MODE_AUTO]
282                 [ofdm->guard_interval == GUARD_INTERVAL_AUTO]
283                 [fep->inversion == INVERSION_AUTO];
284
285         deb_setf("seq? %d\n", seq);
286         wr(DIB3000MC_REG_SEQ_TPS,DIB3000MC_SEQ_TPS(seq,1));
287         *auto_val = ofdm->constellation == QAM_AUTO ||
288                         ofdm->hierarchy_information == HIERARCHY_AUTO ||
289                         ofdm->guard_interval == GUARD_INTERVAL_AUTO ||
290                         ofdm->transmission_mode == TRANSMISSION_MODE_AUTO ||
291                         fe_cr == FEC_AUTO ||
292                         fep->inversion == INVERSION_AUTO;
293         return 0;
294 }
295
296 static int dib3000mc_get_frontend(struct dvb_frontend* fe,
297                                   struct dvb_frontend_parameters *fep)
298 {
299         struct dib3000_state* state = fe->demodulator_priv;
300         struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
301         fe_code_rate_t *cr;
302         u16 tps_val,cr_val;
303         int inv_test1,inv_test2;
304         u32 dds_val, threshold = 0x1000000;
305
306         if (!(rd(DIB3000MC_REG_LOCK_507) & DIB3000MC_LOCK_507))
307                 return 0;
308
309         dds_val = (rd(DIB3000MC_REG_DDS_FREQ_MSB) << 16) + rd(DIB3000MC_REG_DDS_FREQ_LSB);
310         deb_getf("DDS_FREQ: %6x\n",dds_val);
311         if (dds_val < threshold)
312                 inv_test1 = 0;
313         else if (dds_val == threshold)
314                 inv_test1 = 1;
315         else
316                 inv_test1 = 2;
317
318         dds_val = (rd(DIB3000MC_REG_SET_DDS_FREQ_MSB) << 16) + rd(DIB3000MC_REG_SET_DDS_FREQ_LSB);
319         deb_getf("DDS_SET_FREQ: %6x\n",dds_val);
320         if (dds_val < threshold)
321                 inv_test2 = 0;
322         else if (dds_val == threshold)
323                 inv_test2 = 1;
324         else
325                 inv_test2 = 2;
326
327         fep->inversion =
328                 ((inv_test2 == 2) && (inv_test1==1 || inv_test1==0)) ||
329                 ((inv_test2 == 0) && (inv_test1==1 || inv_test1==2)) ?
330                 INVERSION_ON : INVERSION_OFF;
331
332         deb_getf("inversion %d %d, %d\n", inv_test2, inv_test1, fep->inversion);
333
334         fep->frequency = state->last_tuned_freq;
335         fep->u.ofdm.bandwidth= state->last_tuned_bw;
336
337         tps_val = rd(DIB3000MC_REG_TUNING_PARM);
338
339         switch (DIB3000MC_TP_QAM(tps_val)) {
340                 case DIB3000_CONSTELLATION_QPSK:
341                         deb_getf("QPSK ");
342                         ofdm->constellation = QPSK;
343                         break;
344                 case DIB3000_CONSTELLATION_16QAM:
345                         deb_getf("QAM16 ");
346                         ofdm->constellation = QAM_16;
347                         break;
348                 case DIB3000_CONSTELLATION_64QAM:
349                         deb_getf("QAM64 ");
350                         ofdm->constellation = QAM_64;
351                         break;
352                 default:
353                         err("Unexpected constellation returned by TPS (%d)", tps_val);
354                         break;
355         }
356
357         if (DIB3000MC_TP_HRCH(tps_val)) {
358                 deb_getf("HRCH ON ");
359                 cr = &ofdm->code_rate_LP;
360                 ofdm->code_rate_HP = FEC_NONE;
361                 switch (DIB3000MC_TP_ALPHA(tps_val)) {
362                         case DIB3000_ALPHA_0:
363                                 deb_getf("HIERARCHY_NONE ");
364                                 ofdm->hierarchy_information = HIERARCHY_NONE;
365                                 break;
366                         case DIB3000_ALPHA_1:
367                                 deb_getf("HIERARCHY_1 ");
368                                 ofdm->hierarchy_information = HIERARCHY_1;
369                                 break;
370                         case DIB3000_ALPHA_2:
371                                 deb_getf("HIERARCHY_2 ");
372                                 ofdm->hierarchy_information = HIERARCHY_2;
373                                 break;
374                         case DIB3000_ALPHA_4:
375                                 deb_getf("HIERARCHY_4 ");
376                                 ofdm->hierarchy_information = HIERARCHY_4;
377                                 break;
378                         default:
379                                 err("Unexpected ALPHA value returned by TPS (%d)", tps_val);
380                                 break;
381                 }
382                 cr_val = DIB3000MC_TP_FEC_CR_LP(tps_val);
383         } else {
384                 deb_getf("HRCH OFF ");
385                 cr = &ofdm->code_rate_HP;
386                 ofdm->code_rate_LP = FEC_NONE;
387                 ofdm->hierarchy_information = HIERARCHY_NONE;
388                 cr_val = DIB3000MC_TP_FEC_CR_HP(tps_val);
389         }
390
391         switch (cr_val) {
392                 case DIB3000_FEC_1_2:
393                         deb_getf("FEC_1_2 ");
394                         *cr = FEC_1_2;
395                         break;
396                 case DIB3000_FEC_2_3:
397                         deb_getf("FEC_2_3 ");
398                         *cr = FEC_2_3;
399                         break;
400                 case DIB3000_FEC_3_4:
401                         deb_getf("FEC_3_4 ");
402                         *cr = FEC_3_4;
403                         break;
404                 case DIB3000_FEC_5_6:
405                         deb_getf("FEC_5_6 ");
406                         *cr = FEC_4_5;
407                         break;
408                 case DIB3000_FEC_7_8:
409                         deb_getf("FEC_7_8 ");
410                         *cr = FEC_7_8;
411                         break;
412                 default:
413                         err("Unexpected FEC returned by TPS (%d)", tps_val);
414                         break;
415         }
416
417         switch (DIB3000MC_TP_GUARD(tps_val)) {
418                 case DIB3000_GUARD_TIME_1_32:
419                         deb_getf("GUARD_INTERVAL_1_32 ");
420                         ofdm->guard_interval = GUARD_INTERVAL_1_32;
421                         break;
422                 case DIB3000_GUARD_TIME_1_16:
423                         deb_getf("GUARD_INTERVAL_1_16 ");
424                         ofdm->guard_interval = GUARD_INTERVAL_1_16;
425                         break;
426                 case DIB3000_GUARD_TIME_1_8:
427                         deb_getf("GUARD_INTERVAL_1_8 ");
428                         ofdm->guard_interval = GUARD_INTERVAL_1_8;
429                         break;
430                 case DIB3000_GUARD_TIME_1_4:
431                         deb_getf("GUARD_INTERVAL_1_4 ");
432                         ofdm->guard_interval = GUARD_INTERVAL_1_4;
433                         break;
434                 default:
435                         err("Unexpected Guard Time returned by TPS (%d)", tps_val);
436                         break;
437         }
438
439         switch (DIB3000MC_TP_FFT(tps_val)) {
440                 case DIB3000_TRANSMISSION_MODE_2K:
441                         deb_getf("TRANSMISSION_MODE_2K ");
442                         ofdm->transmission_mode = TRANSMISSION_MODE_2K;
443                         break;
444                 case DIB3000_TRANSMISSION_MODE_8K:
445                         deb_getf("TRANSMISSION_MODE_8K ");
446                         ofdm->transmission_mode = TRANSMISSION_MODE_8K;
447                         break;
448                 default:
449                         err("unexpected transmission mode return by TPS (%d)", tps_val);
450                         break;
451         }
452         deb_getf("\n");
453
454         return 0;
455 }
456
457 static int dib3000mc_set_frontend(struct dvb_frontend* fe,
458                                   struct dvb_frontend_parameters *fep, int tuner)
459 {
460         struct dib3000_state* state = fe->demodulator_priv;
461         struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
462         int search_state,auto_val;
463         u16 val;
464
465         if (tuner && state->config.pll_set) { /* initial call from dvb */
466                 state->config.pll_set(fe,fep);
467
468                 state->last_tuned_freq = fep->frequency;
469         //      if (!scanboost) {
470                         dib3000mc_set_timing(state,0,ofdm->transmission_mode,ofdm->bandwidth);
471                         dib3000mc_init_auto_scan(state, ofdm->bandwidth, 0);
472                         state->last_tuned_bw = ofdm->bandwidth;
473
474                         wr_foreach(dib3000mc_reg_agc_bandwidth,dib3000mc_agc_bandwidth);
475                         wr(DIB3000MC_REG_RESTART,DIB3000MC_RESTART_AGC);
476                         wr(DIB3000MC_REG_RESTART,DIB3000MC_RESTART_OFF);
477
478                         /* Default cfg isi offset adp */
479                         wr_foreach(dib3000mc_reg_offset,dib3000mc_offset[0]);
480
481                         wr(DIB3000MC_REG_ISI,DIB3000MC_ISI_DEFAULT | DIB3000MC_ISI_INHIBIT);
482                         dib3000mc_set_adp_cfg(state,ofdm->constellation);
483                         wr(DIB3000MC_REG_UNK_133,DIB3000MC_UNK_133);
484
485                         wr_foreach(dib3000mc_reg_bandwidth_general,dib3000mc_bandwidth_general);
486                         /* power smoothing */
487                         if (ofdm->bandwidth != BANDWIDTH_8_MHZ) {
488                                 wr_foreach(dib3000mc_reg_bw,dib3000mc_bw[0]);
489                         } else {
490                                 wr_foreach(dib3000mc_reg_bw,dib3000mc_bw[3]);
491                         }
492                         auto_val = 0;
493                         dib3000mc_set_general_cfg(state,fep,&auto_val);
494                         dib3000mc_set_impulse_noise(state,0,ofdm->constellation,ofdm->bandwidth);
495
496                         val = rd(DIB3000MC_REG_DEMOD_PARM);
497                         wr(DIB3000MC_REG_DEMOD_PARM,val|DIB3000MC_DEMOD_RST_DEMOD_ON);
498                         wr(DIB3000MC_REG_DEMOD_PARM,val);
499         //      }
500                 msleep(70);
501
502                 /* something has to be auto searched */
503                 if (auto_val) {
504                         int as_count=0;
505
506                         deb_setf("autosearch enabled.\n");
507
508                         val = rd(DIB3000MC_REG_DEMOD_PARM);
509                         wr(DIB3000MC_REG_DEMOD_PARM,val | DIB3000MC_DEMOD_RST_AUTO_SRCH_ON);
510                         wr(DIB3000MC_REG_DEMOD_PARM,val);
511
512                         while ((search_state = dib3000_search_status(
513                                                 rd(DIB3000MC_REG_AS_IRQ),1)) < 0 && as_count++ < 100)
514                                 msleep(10);
515
516                         deb_info("search_state after autosearch %d after %d checks\n",search_state,as_count);
517
518                         if (search_state == 1) {
519                                 struct dvb_frontend_parameters feps;
520                                 if (dib3000mc_get_frontend(fe, &feps) == 0) {
521                                         deb_setf("reading tuning data from frontend succeeded.\n");
522                                         return dib3000mc_set_frontend(fe, &feps, 0);
523                                 }
524                         }
525                 } else {
526                         dib3000mc_set_impulse_noise(state,0,ofdm->transmission_mode,ofdm->bandwidth);
527                         wr(DIB3000MC_REG_ISI,DIB3000MC_ISI_DEFAULT|DIB3000MC_ISI_ACTIVATE);
528                         dib3000mc_set_adp_cfg(state,ofdm->constellation);
529
530                         /* set_offset_cfg */
531                         wr_foreach(dib3000mc_reg_offset,
532                                         dib3000mc_offset[(ofdm->transmission_mode == TRANSMISSION_MODE_8K)+1]);
533                 }
534         } else { /* second call, after autosearch (fka: set_WithKnownParams) */
535 //              dib3000mc_set_timing(state,1,ofdm->transmission_mode,ofdm->bandwidth);
536
537                 auto_val = 0;
538                 dib3000mc_set_general_cfg(state,fep,&auto_val);
539                 if (auto_val)
540                         deb_info("auto_val is true, even though an auto search was already performed.\n");
541
542                 dib3000mc_set_impulse_noise(state,0,ofdm->constellation,ofdm->bandwidth);
543
544                 val = rd(DIB3000MC_REG_DEMOD_PARM);
545                 wr(DIB3000MC_REG_DEMOD_PARM,val | DIB3000MC_DEMOD_RST_AUTO_SRCH_ON);
546                 wr(DIB3000MC_REG_DEMOD_PARM,val);
547
548                 msleep(30);
549
550                 wr(DIB3000MC_REG_ISI,DIB3000MC_ISI_DEFAULT|DIB3000MC_ISI_ACTIVATE);
551                         dib3000mc_set_adp_cfg(state,ofdm->constellation);
552                 wr_foreach(dib3000mc_reg_offset,
553                                 dib3000mc_offset[(ofdm->transmission_mode == TRANSMISSION_MODE_8K)+1]);
554         }
555         return 0;
556 }
557
558 static int dib3000mc_fe_init(struct dvb_frontend* fe, int mobile_mode)
559 {
560         struct dib3000_state *state = fe->demodulator_priv;
561         deb_info("init start\n");
562
563         state->timing_offset = 0;
564         state->timing_offset_comp_done = 0;
565
566         wr(DIB3000MC_REG_RESTART,DIB3000MC_RESTART_CONFIG);
567         wr(DIB3000MC_REG_RESTART,DIB3000MC_RESTART_OFF);
568         wr(DIB3000MC_REG_CLK_CFG_1,DIB3000MC_CLK_CFG_1_POWER_UP);
569         wr(DIB3000MC_REG_CLK_CFG_2,DIB3000MC_CLK_CFG_2_PUP_MOBILE);
570         wr(DIB3000MC_REG_CLK_CFG_3,DIB3000MC_CLK_CFG_3_POWER_UP);
571         wr(DIB3000MC_REG_CLK_CFG_7,DIB3000MC_CLK_CFG_7_INIT);
572
573         wr(DIB3000MC_REG_RST_UNC,DIB3000MC_RST_UNC_OFF);
574         wr(DIB3000MC_REG_UNK_19,DIB3000MC_UNK_19);
575
576         wr(33,5);
577         wr(36,81);
578         wr(DIB3000MC_REG_UNK_88,DIB3000MC_UNK_88);
579
580         wr(DIB3000MC_REG_UNK_99,DIB3000MC_UNK_99);
581         wr(DIB3000MC_REG_UNK_111,DIB3000MC_UNK_111_PH_N_MODE_0); /* phase noise algo off */
582
583         /* mobile mode - portable reception */
584         wr_foreach(dib3000mc_reg_mobile_mode,dib3000mc_mobile_mode[1]);
585
586 /* TUNER_PANASONIC_ENV57H12D5: */
587         wr_foreach(dib3000mc_reg_agc_bandwidth,dib3000mc_agc_bandwidth);
588         wr_foreach(dib3000mc_reg_agc_bandwidth_general,dib3000mc_agc_bandwidth_general);
589         wr_foreach(dib3000mc_reg_agc,dib3000mc_agc_tuner[1]);
590
591         wr(DIB3000MC_REG_UNK_110,DIB3000MC_UNK_110);
592         wr(26,0x6680);
593         wr(DIB3000MC_REG_UNK_1,DIB3000MC_UNK_1);
594         wr(DIB3000MC_REG_UNK_2,DIB3000MC_UNK_2);
595         wr(DIB3000MC_REG_UNK_3,DIB3000MC_UNK_3);
596         wr(DIB3000MC_REG_SEQ_TPS,DIB3000MC_SEQ_TPS_DEFAULT);
597
598         wr_foreach(dib3000mc_reg_bandwidth,dib3000mc_bandwidth_8mhz);
599         wr_foreach(dib3000mc_reg_bandwidth_general,dib3000mc_bandwidth_general);
600
601         wr(DIB3000MC_REG_UNK_4,DIB3000MC_UNK_4);
602
603         wr(DIB3000MC_REG_SET_DDS_FREQ_MSB,DIB3000MC_DDS_FREQ_MSB_INV_OFF);
604         wr(DIB3000MC_REG_SET_DDS_FREQ_LSB,DIB3000MC_DDS_FREQ_LSB);
605
606         dib3000mc_set_timing(state,0,TRANSMISSION_MODE_8K,BANDWIDTH_8_MHZ);
607 //      wr_foreach(dib3000mc_reg_timing_freq,dib3000mc_timing_freq[3]);
608
609         wr(DIB3000MC_REG_UNK_120,DIB3000MC_UNK_120);
610         wr(DIB3000MC_REG_UNK_134,DIB3000MC_UNK_134);
611         wr(DIB3000MC_REG_FEC_CFG,DIB3000MC_FEC_CFG);
612
613         wr(DIB3000MC_REG_DIVERSITY3,DIB3000MC_DIVERSITY3_IN_OFF);
614
615         dib3000mc_set_impulse_noise(state,0,TRANSMISSION_MODE_8K,BANDWIDTH_8_MHZ);
616
617 /* output mode control, just the MPEG2_SLAVE */
618 //      set_or(DIB3000MC_REG_OUTMODE,DIB3000MC_OM_SLAVE);
619         wr(DIB3000MC_REG_OUTMODE,DIB3000MC_OM_SLAVE);
620         wr(DIB3000MC_REG_SMO_MODE,DIB3000MC_SMO_MODE_SLAVE);
621         wr(DIB3000MC_REG_FIFO_THRESHOLD,DIB3000MC_FIFO_THRESHOLD_SLAVE);
622         wr(DIB3000MC_REG_ELEC_OUT,DIB3000MC_ELEC_OUT_SLAVE);
623
624 /* MPEG2_PARALLEL_CONTINUOUS_CLOCK
625         wr(DIB3000MC_REG_OUTMODE,
626                 DIB3000MC_SET_OUTMODE(DIB3000MC_OM_PAR_CONT_CLK,
627                         rd(DIB3000MC_REG_OUTMODE)));
628
629         wr(DIB3000MC_REG_SMO_MODE,
630                         DIB3000MC_SMO_MODE_DEFAULT |
631                         DIB3000MC_SMO_MODE_188);
632
633         wr(DIB3000MC_REG_FIFO_THRESHOLD,DIB3000MC_FIFO_THRESHOLD_DEFAULT);
634         wr(DIB3000MC_REG_ELEC_OUT,DIB3000MC_ELEC_OUT_DIV_OUT_ON);
635 */
636
637 /* diversity */
638         wr(DIB3000MC_REG_DIVERSITY1,DIB3000MC_DIVERSITY1_DEFAULT);
639         wr(DIB3000MC_REG_DIVERSITY2,DIB3000MC_DIVERSITY2_DEFAULT);
640
641         set_and(DIB3000MC_REG_DIVERSITY3,DIB3000MC_DIVERSITY3_IN_OFF);
642
643         set_or(DIB3000MC_REG_CLK_CFG_7,DIB3000MC_CLK_CFG_7_DIV_IN_OFF);
644
645         if (state->config.pll_init)
646                 state->config.pll_init(fe);
647
648         deb_info("init end\n");
649         return 0;
650 }
651 static int dib3000mc_read_status(struct dvb_frontend* fe, fe_status_t *stat)
652 {
653         struct dib3000_state* state = fe->demodulator_priv;
654         u16 lock = rd(DIB3000MC_REG_LOCKING);
655
656         *stat = 0;
657         if (DIB3000MC_AGC_LOCK(lock))
658                 *stat |= FE_HAS_SIGNAL;
659         if (DIB3000MC_CARRIER_LOCK(lock))
660                 *stat |= FE_HAS_CARRIER;
661         if (DIB3000MC_TPS_LOCK(lock))
662                 *stat |= FE_HAS_VITERBI;
663         if (DIB3000MC_MPEG_SYNC_LOCK(lock))
664                 *stat |= (FE_HAS_SYNC | FE_HAS_LOCK);
665
666         deb_stat("actual status is %2x fifo_level: %x,244: %x, 206: %x, 207: %x, 1040: %x\n",*stat,rd(510),rd(244),rd(206),rd(207),rd(1040));
667
668         return 0;
669 }
670
671 static int dib3000mc_read_ber(struct dvb_frontend* fe, u32 *ber)
672 {
673         struct dib3000_state* state = fe->demodulator_priv;
674         *ber = ((rd(DIB3000MC_REG_BER_MSB) << 16) | rd(DIB3000MC_REG_BER_LSB));
675         return 0;
676 }
677
678 static int dib3000mc_read_unc_blocks(struct dvb_frontend* fe, u32 *unc)
679 {
680         struct dib3000_state* state = fe->demodulator_priv;
681
682         *unc = rd(DIB3000MC_REG_PACKET_ERRORS);
683         return 0;
684 }
685
686 /* see dib3000mb.c for calculation comments */
687 static int dib3000mc_read_signal_strength(struct dvb_frontend* fe, u16 *strength)
688 {
689         struct dib3000_state* state = fe->demodulator_priv;
690         u16 val = rd(DIB3000MC_REG_SIGNAL_NOISE_LSB);
691         *strength = (((val >> 6) & 0xff) << 8) + (val & 0x3f);
692
693         deb_stat("signal: mantisse = %d, exponent = %d\n",(*strength >> 8) & 0xff, *strength & 0xff);
694         return 0;
695 }
696
697 /* see dib3000mb.c for calculation comments */
698 static int dib3000mc_read_snr(struct dvb_frontend* fe, u16 *snr)
699 {
700         struct dib3000_state* state = fe->demodulator_priv;
701         u16 val = rd(DIB3000MC_REG_SIGNAL_NOISE_LSB),
702                 val2 = rd(DIB3000MC_REG_SIGNAL_NOISE_MSB);
703         u16 sig,noise;
704
705         sig =   (((val >> 6) & 0xff) << 8) + (val & 0x3f);
706         noise = (((val >> 4) & 0xff) << 8) + ((val & 0xf) << 2) + ((val2 >> 14) & 0x3);
707         if (noise == 0)
708                 *snr = 0xffff;
709         else
710                 *snr = (u16) sig/noise;
711
712         deb_stat("signal: mantisse = %d, exponent = %d\n",(sig >> 8) & 0xff, sig & 0xff);
713         deb_stat("noise:  mantisse = %d, exponent = %d\n",(noise >> 8) & 0xff, noise & 0xff);
714         deb_stat("snr: %d\n",*snr);
715         return 0;
716 }
717
718 static int dib3000mc_sleep(struct dvb_frontend* fe)
719 {
720         struct dib3000_state* state = fe->demodulator_priv;
721
722         set_or(DIB3000MC_REG_CLK_CFG_7,DIB3000MC_CLK_CFG_7_PWR_DOWN);
723         wr(DIB3000MC_REG_CLK_CFG_1,DIB3000MC_CLK_CFG_1_POWER_DOWN);
724         wr(DIB3000MC_REG_CLK_CFG_2,DIB3000MC_CLK_CFG_2_POWER_DOWN);
725         wr(DIB3000MC_REG_CLK_CFG_3,DIB3000MC_CLK_CFG_3_POWER_DOWN);
726         return 0;
727 }
728
729 static int dib3000mc_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
730 {
731         tune->min_delay_ms = 1000;
732         return 0;
733 }
734
735 static int dib3000mc_fe_init_nonmobile(struct dvb_frontend* fe)
736 {
737         return dib3000mc_fe_init(fe, 0);
738 }
739
740 static int dib3000mc_set_frontend_and_tuner(struct dvb_frontend* fe, struct dvb_frontend_parameters *fep)
741 {
742         return dib3000mc_set_frontend(fe, fep, 1);
743 }
744
745 static void dib3000mc_release(struct dvb_frontend* fe)
746 {
747         struct dib3000_state *state = fe->demodulator_priv;
748         kfree(state);
749 }
750
751 /* pid filter and transfer stuff */
752 static int dib3000mc_pid_control(struct dvb_frontend *fe,int index, int pid,int onoff)
753 {
754         struct dib3000_state *state = fe->demodulator_priv;
755         pid = (onoff ? pid | DIB3000_ACTIVATE_PID_FILTERING : 0);
756         wr(index+DIB3000MC_REG_FIRST_PID,pid);
757         return 0;
758 }
759
760 static int dib3000mc_fifo_control(struct dvb_frontend *fe, int onoff)
761 {
762         struct dib3000_state *state = fe->demodulator_priv;
763         u16 tmp = rd(DIB3000MC_REG_SMO_MODE);
764
765         deb_xfer("%s fifo\n",onoff ? "enabling" : "disabling");
766
767         if (onoff) {
768                 deb_xfer("%d %x\n",tmp & DIB3000MC_SMO_MODE_FIFO_UNFLUSH,tmp & DIB3000MC_SMO_MODE_FIFO_UNFLUSH);
769                 wr(DIB3000MC_REG_SMO_MODE,tmp & DIB3000MC_SMO_MODE_FIFO_UNFLUSH);
770         } else {
771                 deb_xfer("%d %x\n",tmp | DIB3000MC_SMO_MODE_FIFO_FLUSH,tmp | DIB3000MC_SMO_MODE_FIFO_FLUSH);
772                 wr(DIB3000MC_REG_SMO_MODE,tmp | DIB3000MC_SMO_MODE_FIFO_FLUSH);
773         }
774         return 0;
775 }
776
777 static int dib3000mc_pid_parse(struct dvb_frontend *fe, int onoff)
778 {
779         struct dib3000_state *state = fe->demodulator_priv;
780         u16 tmp = rd(DIB3000MC_REG_SMO_MODE);
781
782         deb_xfer("%s pid parsing\n",onoff ? "enabling" : "disabling");
783
784         if (onoff) {
785                 wr(DIB3000MC_REG_SMO_MODE,tmp | DIB3000MC_SMO_MODE_PID_PARSE);
786         } else {
787                 wr(DIB3000MC_REG_SMO_MODE,tmp & DIB3000MC_SMO_MODE_NO_PID_PARSE);
788         }
789         return 0;
790 }
791
792 static int dib3000mc_tuner_pass_ctrl(struct dvb_frontend *fe, int onoff, u8 pll_addr)
793 {
794         struct dib3000_state *state = fe->demodulator_priv;
795         if (onoff) {
796                 wr(DIB3000MC_REG_TUNER, DIB3000_TUNER_WRITE_ENABLE(pll_addr));
797         } else {
798                 wr(DIB3000MC_REG_TUNER, DIB3000_TUNER_WRITE_DISABLE(pll_addr));
799         }
800         return 0;
801 }
802
803 static int dib3000mc_demod_init(struct dib3000_state *state)
804 {
805         u16 default_addr = 0x0a;
806         /* first init */
807         if (state->config.demod_address != default_addr) {
808                 deb_info("initializing the demod the first time. Setting demod addr to 0x%x\n",default_addr);
809                 wr(DIB3000MC_REG_ELEC_OUT,DIB3000MC_ELEC_OUT_DIV_OUT_ON);
810                 wr(DIB3000MC_REG_OUTMODE,DIB3000MC_OM_PAR_CONT_CLK);
811
812                 wr(DIB3000MC_REG_RST_I2C_ADDR,
813                         DIB3000MC_DEMOD_ADDR(default_addr) |
814                         DIB3000MC_DEMOD_ADDR_ON);
815
816                 state->config.demod_address = default_addr;
817
818                 wr(DIB3000MC_REG_RST_I2C_ADDR,
819                         DIB3000MC_DEMOD_ADDR(default_addr));
820         } else
821                 deb_info("demod is already initialized. Demod addr: 0x%x\n",state->config.demod_address);
822         return 0;
823 }
824
825
826 static struct dvb_frontend_ops dib3000mc_ops;
827
828 struct dvb_frontend* dib3000mc_attach(const struct dib3000_config* config,
829                                       struct i2c_adapter* i2c, struct dib_fe_xfer_ops *xfer_ops)
830 {
831         struct dib3000_state* state = NULL;
832         u16 devid;
833
834         /* allocate memory for the internal state */
835         state = kmalloc(sizeof(struct dib3000_state), GFP_KERNEL);
836         if (state == NULL)
837                 goto error;
838         memset(state,0,sizeof(struct dib3000_state));
839
840         /* setup the state */
841         state->i2c = i2c;
842         memcpy(&state->config,config,sizeof(struct dib3000_config));
843         memcpy(&state->ops, &dib3000mc_ops, sizeof(struct dvb_frontend_ops));
844
845         /* check for the correct demod */
846         if (rd(DIB3000_REG_MANUFACTOR_ID) != DIB3000_I2C_ID_DIBCOM)
847                 goto error;
848
849         devid = rd(DIB3000_REG_DEVICE_ID);
850         if (devid != DIB3000MC_DEVICE_ID && devid != DIB3000P_DEVICE_ID)
851                 goto error;
852
853         switch (devid) {
854                 case DIB3000MC_DEVICE_ID:
855                         info("Found a DiBcom 3000M-C, interesting...");
856                         break;
857                 case DIB3000P_DEVICE_ID:
858                         info("Found a DiBcom 3000P.");
859                         break;
860         }
861
862         /* create dvb_frontend */
863         state->frontend.ops = &state->ops;
864         state->frontend.demodulator_priv = state;
865
866         /* set the xfer operations */
867         xfer_ops->pid_parse = dib3000mc_pid_parse;
868         xfer_ops->fifo_ctrl = dib3000mc_fifo_control;
869         xfer_ops->pid_ctrl = dib3000mc_pid_control;
870         xfer_ops->tuner_pass_ctrl = dib3000mc_tuner_pass_ctrl;
871
872         dib3000mc_demod_init(state);
873
874         return &state->frontend;
875
876 error:
877         kfree(state);
878         return NULL;
879 }
880
881 static struct dvb_frontend_ops dib3000mc_ops = {
882
883         .info = {
884                 .name                   = "DiBcom 3000P/M-C DVB-T",
885                 .type                   = FE_OFDM,
886                 .frequency_min          = 44250000,
887                 .frequency_max          = 867250000,
888                 .frequency_stepsize     = 62500,
889                 .caps = FE_CAN_INVERSION_AUTO |
890                                 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
891                                 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
892                                 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
893                                 FE_CAN_TRANSMISSION_MODE_AUTO |
894                                 FE_CAN_GUARD_INTERVAL_AUTO |
895                                 FE_CAN_RECOVER |
896                                 FE_CAN_HIERARCHY_AUTO,
897         },
898
899         .release = dib3000mc_release,
900
901         .init = dib3000mc_fe_init_nonmobile,
902         .sleep = dib3000mc_sleep,
903
904         .set_frontend = dib3000mc_set_frontend_and_tuner,
905         .get_frontend = dib3000mc_get_frontend,
906         .get_tune_settings = dib3000mc_fe_get_tune_settings,
907
908         .read_status = dib3000mc_read_status,
909         .read_ber = dib3000mc_read_ber,
910         .read_signal_strength = dib3000mc_read_signal_strength,
911         .read_snr = dib3000mc_read_snr,
912         .read_ucblocks = dib3000mc_read_unc_blocks,
913 };
914
915 MODULE_AUTHOR(DRIVER_AUTHOR);
916 MODULE_DESCRIPTION(DRIVER_DESC);
917 MODULE_LICENSE("GPL");
918
919 EXPORT_SYMBOL(dib3000mc_attach);