[PATCH] dvb: Add generalized dvb-usb driver
[linux-2.6.git] / drivers / media / dvb / frontends / dib3000mb.c
1 /*
2  * Frontend driver for mobile DVB-T demodulator DiBcom 3000M-B
3  * DiBcom (http://www.dibcom.fr/)
4  *
5  * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@desy.de)
6  *
7  * based on GPL code from DibCom, which has
8  *
9  * Copyright (C) 2004 Amaury Demol for DiBcom (ademol@dibcom.fr)
10  *
11  *      This program is free software; you can redistribute it and/or
12  *      modify it under the terms of the GNU General Public License as
13  *      published by the Free Software Foundation, version 2.
14  *
15  * Acknowledgements
16  *
17  *  Amaury Demol (ademol@dibcom.fr) from DiBcom for providing specs and driver
18  *  sources, on which this driver (and the dvb-dibusb) are based.
19  *
20  * see Documentation/dvb/README.dibusb for more information
21  *
22  */
23
24 #include <linux/config.h>
25 #include <linux/kernel.h>
26 #include <linux/version.h>
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/init.h>
30 #include <linux/delay.h>
31
32 #include "dib3000-common.h"
33 #include "dib3000mb_priv.h"
34 #include "dib3000.h"
35
36 /* Version information */
37 #define DRIVER_VERSION "0.1"
38 #define DRIVER_DESC "DiBcom 3000M-B DVB-T demodulator"
39 #define DRIVER_AUTHOR "Patrick Boettcher, patrick.boettcher@desy.de"
40
41 #ifdef CONFIG_DVB_DIBCOM_DEBUG
42 static int debug;
43 module_param(debug, int, 0644);
44 MODULE_PARM_DESC(debug, "set debugging level (1=info,2=xfer,4=setfe,8=getfe (|-able)).");
45 #endif
46 #define deb_info(args...) dprintk(0x01,args)
47 #define deb_xfer(args...) dprintk(0x02,args)
48 #define deb_setf(args...) dprintk(0x04,args)
49 #define deb_getf(args...) dprintk(0x08,args)
50
51 static int dib3000mb_get_frontend(struct dvb_frontend* fe,
52                                   struct dvb_frontend_parameters *fep);
53
54 static int dib3000mb_set_frontend(struct dvb_frontend* fe,
55                                   struct dvb_frontend_parameters *fep, int tuner)
56 {
57         struct dib3000_state* state = fe->demodulator_priv;
58         struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
59         fe_code_rate_t fe_cr = FEC_NONE;
60         int search_state, seq;
61
62         if (tuner && state->config.pll_set) {
63                 state->config.pll_set(fe, fep);
64
65                 deb_setf("bandwidth: ");
66                 switch (ofdm->bandwidth) {
67                         case BANDWIDTH_8_MHZ:
68                                 deb_setf("8 MHz\n");
69                                 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]);
70                                 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz);
71                                 break;
72                         case BANDWIDTH_7_MHZ:
73                                 deb_setf("7 MHz\n");
74                                 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[1]);
75                                 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_7mhz);
76                                 break;
77                         case BANDWIDTH_6_MHZ:
78                                 deb_setf("6 MHz\n");
79                                 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[0]);
80                                 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_6mhz);
81                                 break;
82                         case BANDWIDTH_AUTO:
83                                 return -EOPNOTSUPP;
84                         default:
85                                 err("unkown bandwidth value.");
86                                 return -EINVAL;
87                 }
88         }
89         wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4);
90
91         deb_setf("transmission mode: ");
92         switch (ofdm->transmission_mode) {
93                 case TRANSMISSION_MODE_2K:
94                         deb_setf("2k\n");
95                         wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_2K);
96                         break;
97                 case TRANSMISSION_MODE_8K:
98                         deb_setf("8k\n");
99                         wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_8K);
100                         break;
101                 case TRANSMISSION_MODE_AUTO:
102                         deb_setf("auto\n");
103                         break;
104                 default:
105                         return -EINVAL;
106         }
107
108         deb_setf("guard: ");
109         switch (ofdm->guard_interval) {
110                 case GUARD_INTERVAL_1_32:
111                         deb_setf("1_32\n");
112                         wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_32);
113                         break;
114                 case GUARD_INTERVAL_1_16:
115                         deb_setf("1_16\n");
116                         wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_16);
117                         break;
118                 case GUARD_INTERVAL_1_8:
119                         deb_setf("1_8\n");
120                         wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_8);
121                         break;
122                 case GUARD_INTERVAL_1_4:
123                         deb_setf("1_4\n");
124                         wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_4);
125                         break;
126                 case GUARD_INTERVAL_AUTO:
127                         deb_setf("auto\n");
128                         break;
129                 default:
130                         return -EINVAL;
131         }
132
133         deb_setf("inversion: ");
134         switch (fep->inversion) {
135                 case INVERSION_OFF:
136                         deb_setf("off\n");
137                         wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_OFF);
138                         break;
139                 case INVERSION_AUTO:
140                         deb_setf("auto ");
141                         break;
142                 case INVERSION_ON:
143                         deb_setf("on\n");
144                         wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_ON);
145                         break;
146                 default:
147                         return -EINVAL;
148         }
149
150         deb_setf("constellation: ");
151         switch (ofdm->constellation) {
152                 case QPSK:
153                         deb_setf("qpsk\n");
154                         wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_QPSK);
155                         break;
156                 case QAM_16:
157                         deb_setf("qam16\n");
158                         wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_16QAM);
159                         break;
160                 case QAM_64:
161                         deb_setf("qam64\n");
162                         wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_64QAM);
163                         break;
164                 case QAM_AUTO:
165                         break;
166                 default:
167                         return -EINVAL;
168         }
169         deb_setf("hierachy: ");
170         switch (ofdm->hierarchy_information) {
171                 case HIERARCHY_NONE:
172                         deb_setf("none ");
173                         /* fall through */
174                 case HIERARCHY_1:
175                         deb_setf("alpha=1\n");
176                         wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_1);
177                         break;
178                 case HIERARCHY_2:
179                         deb_setf("alpha=2\n");
180                         wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_2);
181                         break;
182                 case HIERARCHY_4:
183                         deb_setf("alpha=4\n");
184                         wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_4);
185                         break;
186                 case HIERARCHY_AUTO:
187                         deb_setf("alpha=auto\n");
188                         break;
189                 default:
190                         return -EINVAL;
191         }
192
193         deb_setf("hierarchy: ");
194         if (ofdm->hierarchy_information == HIERARCHY_NONE) {
195                 deb_setf("none\n");
196                 wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_OFF);
197                 wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_HP);
198                 fe_cr = ofdm->code_rate_HP;
199         } else if (ofdm->hierarchy_information != HIERARCHY_AUTO) {
200                 deb_setf("on\n");
201                 wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_ON);
202                 wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_LP);
203                 fe_cr = ofdm->code_rate_LP;
204         }
205         deb_setf("fec: ");
206         switch (fe_cr) {
207                 case FEC_1_2:
208                         deb_setf("1_2\n");
209                         wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_1_2);
210                         break;
211                 case FEC_2_3:
212                         deb_setf("2_3\n");
213                         wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_2_3);
214                         break;
215                 case FEC_3_4:
216                         deb_setf("3_4\n");
217                         wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_3_4);
218                         break;
219                 case FEC_5_6:
220                         deb_setf("5_6\n");
221                         wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_5_6);
222                         break;
223                 case FEC_7_8:
224                         deb_setf("7_8\n");
225                         wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_7_8);
226                         break;
227                 case FEC_NONE:
228                         deb_setf("none ");
229                         break;
230                 case FEC_AUTO:
231                         deb_setf("auto\n");
232                         break;
233                 default:
234                         return -EINVAL;
235         }
236
237         seq = dib3000_seq
238                 [ofdm->transmission_mode == TRANSMISSION_MODE_AUTO]
239                 [ofdm->guard_interval == GUARD_INTERVAL_AUTO]
240                 [fep->inversion == INVERSION_AUTO];
241
242         deb_setf("seq? %d\n", seq);
243
244         wr(DIB3000MB_REG_SEQ, seq);
245
246         wr(DIB3000MB_REG_ISI, seq ? DIB3000MB_ISI_INHIBIT : DIB3000MB_ISI_ACTIVATE);
247
248         if (ofdm->transmission_mode == TRANSMISSION_MODE_2K) {
249                 if (ofdm->guard_interval == GUARD_INTERVAL_1_8) {
250                         wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_2K_1_8);
251                 } else {
252                         wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_DEFAULT);
253                 }
254
255                 wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_2K);
256         } else {
257                 wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_DEFAULT);
258         }
259
260         wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_OFF);
261         wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF);
262         wr(DIB3000MB_REG_MOBILE_MODE, DIB3000MB_MOBILE_MODE_OFF);
263
264         wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_high);
265
266         wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_ACTIVATE);
267
268         wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC + DIB3000MB_RESTART_CTRL);
269         wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
270
271         /* wait for AGC lock */
272         msleep(70);
273
274         wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low);
275
276         /* something has to be auto searched */
277         if (ofdm->constellation == QAM_AUTO ||
278                 ofdm->hierarchy_information == HIERARCHY_AUTO ||
279                 fe_cr == FEC_AUTO ||
280                 fep->inversion == INVERSION_AUTO) {
281                 int as_count=0;
282
283                 deb_setf("autosearch enabled.\n");
284
285                 wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT);
286
287                 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AUTO_SEARCH);
288                 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
289
290                 while ((search_state =
291                                 dib3000_search_status(
292                                         rd(DIB3000MB_REG_AS_IRQ_PENDING),
293                                         rd(DIB3000MB_REG_LOCK2_VALUE))) < 0 && as_count++ < 100)
294                         msleep(1);
295
296                 deb_setf("search_state after autosearch %d after %d checks\n",search_state,as_count);
297
298                 if (search_state == 1) {
299                         struct dvb_frontend_parameters feps;
300                         if (dib3000mb_get_frontend(fe, &feps) == 0) {
301                                 deb_setf("reading tuning data from frontend succeeded.\n");
302                                 return dib3000mb_set_frontend(fe, &feps, 0);
303                         }
304                 }
305
306         } else {
307                 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_CTRL);
308                 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
309         }
310
311         return 0;
312 }
313
314 static int dib3000mb_fe_init(struct dvb_frontend* fe, int mobile_mode)
315 {
316         struct dib3000_state* state = fe->demodulator_priv;
317
318         deb_info("dib3000mb is getting up.\n");
319         wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_UP);
320
321         wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC);
322
323         wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE);
324         wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE_RST);
325
326         wr(DIB3000MB_REG_CLOCK, DIB3000MB_CLOCK_DEFAULT);
327
328         wr(DIB3000MB_REG_ELECT_OUT_MODE, DIB3000MB_ELECT_OUT_MODE_ON);
329
330         wr(DIB3000MB_REG_DDS_FREQ_MSB, DIB3000MB_DDS_FREQ_MSB);
331         wr(DIB3000MB_REG_DDS_FREQ_LSB, DIB3000MB_DDS_FREQ_LSB);
332
333         wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]);
334
335         wr_foreach(dib3000mb_reg_impulse_noise,
336                         dib3000mb_impulse_noise_values[DIB3000MB_IMPNOISE_OFF]);
337
338         wr_foreach(dib3000mb_reg_agc_gain, dib3000mb_default_agc_gain);
339
340         wr(DIB3000MB_REG_PHASE_NOISE, DIB3000MB_PHASE_NOISE_DEFAULT);
341
342         wr_foreach(dib3000mb_reg_phase_noise, dib3000mb_default_noise_phase);
343
344         wr_foreach(dib3000mb_reg_lock_duration, dib3000mb_default_lock_duration);
345
346         wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low);
347
348         wr(DIB3000MB_REG_LOCK0_MASK, DIB3000MB_LOCK0_DEFAULT);
349         wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4);
350         wr(DIB3000MB_REG_LOCK2_MASK, DIB3000MB_LOCK2_DEFAULT);
351         wr(DIB3000MB_REG_SEQ, dib3000_seq[1][1][1]);
352
353         wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz);
354
355         wr(DIB3000MB_REG_UNK_68, DIB3000MB_UNK_68);
356         wr(DIB3000MB_REG_UNK_69, DIB3000MB_UNK_69);
357         wr(DIB3000MB_REG_UNK_71, DIB3000MB_UNK_71);
358         wr(DIB3000MB_REG_UNK_77, DIB3000MB_UNK_77);
359         wr(DIB3000MB_REG_UNK_78, DIB3000MB_UNK_78);
360         wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT);
361         wr(DIB3000MB_REG_UNK_92, DIB3000MB_UNK_92);
362         wr(DIB3000MB_REG_UNK_96, DIB3000MB_UNK_96);
363         wr(DIB3000MB_REG_UNK_97, DIB3000MB_UNK_97);
364         wr(DIB3000MB_REG_UNK_106, DIB3000MB_UNK_106);
365         wr(DIB3000MB_REG_UNK_107, DIB3000MB_UNK_107);
366         wr(DIB3000MB_REG_UNK_108, DIB3000MB_UNK_108);
367         wr(DIB3000MB_REG_UNK_122, DIB3000MB_UNK_122);
368         wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF);
369         wr(DIB3000MB_REG_BERLEN, DIB3000MB_BERLEN_DEFAULT);
370
371         wr_foreach(dib3000mb_reg_filter_coeffs, dib3000mb_filter_coeffs);
372
373         wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_ON);
374         wr(DIB3000MB_REG_MULTI_DEMOD_MSB, DIB3000MB_MULTI_DEMOD_MSB);
375         wr(DIB3000MB_REG_MULTI_DEMOD_LSB, DIB3000MB_MULTI_DEMOD_LSB);
376
377         wr(DIB3000MB_REG_OUTPUT_MODE, DIB3000MB_OUTPUT_MODE_SLAVE);
378
379         wr(DIB3000MB_REG_FIFO_142, DIB3000MB_FIFO_142);
380         wr(DIB3000MB_REG_MPEG2_OUT_MODE, DIB3000MB_MPEG2_OUT_MODE_188);
381         wr(DIB3000MB_REG_PID_PARSE, DIB3000MB_PID_PARSE_ACTIVATE);
382         wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT);
383         wr(DIB3000MB_REG_FIFO_146, DIB3000MB_FIFO_146);
384         wr(DIB3000MB_REG_FIFO_147, DIB3000MB_FIFO_147);
385
386         wr(DIB3000MB_REG_DATA_IN_DIVERSITY, DIB3000MB_DATA_DIVERSITY_IN_OFF);
387
388         if (state->config.pll_init)
389                 state->config.pll_init(fe);
390
391         return 0;
392 }
393
394 static int dib3000mb_get_frontend(struct dvb_frontend* fe,
395                                   struct dvb_frontend_parameters *fep)
396 {
397         struct dib3000_state* state = fe->demodulator_priv;
398         struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
399         fe_code_rate_t *cr;
400         u16 tps_val;
401         int inv_test1,inv_test2;
402         u32 dds_val, threshold = 0x800000;
403
404         if (!rd(DIB3000MB_REG_TPS_LOCK))
405                 return 0;
406
407         dds_val = ((rd(DIB3000MB_REG_DDS_VALUE_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_VALUE_LSB);
408         deb_getf("DDS_VAL: %x %x %x",dds_val, rd(DIB3000MB_REG_DDS_VALUE_MSB), rd(DIB3000MB_REG_DDS_VALUE_LSB));
409         if (dds_val < threshold)
410                 inv_test1 = 0;
411         else if (dds_val == threshold)
412                 inv_test1 = 1;
413         else
414                 inv_test1 = 2;
415
416         dds_val = ((rd(DIB3000MB_REG_DDS_FREQ_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_FREQ_LSB);
417         deb_getf("DDS_FREQ: %x %x %x",dds_val, rd(DIB3000MB_REG_DDS_FREQ_MSB), rd(DIB3000MB_REG_DDS_FREQ_LSB));
418         if (dds_val < threshold)
419                 inv_test2 = 0;
420         else if (dds_val == threshold)
421                 inv_test2 = 1;
422         else
423                 inv_test2 = 2;
424
425         fep->inversion =
426                 ((inv_test2 == 2) && (inv_test1==1 || inv_test1==0)) ||
427                 ((inv_test2 == 0) && (inv_test1==1 || inv_test1==2)) ?
428                 INVERSION_ON : INVERSION_OFF;
429
430         deb_getf("inversion %d %d, %d\n", inv_test2, inv_test1, fep->inversion);
431
432         switch ((tps_val = rd(DIB3000MB_REG_TPS_QAM))) {
433                 case DIB3000_CONSTELLATION_QPSK:
434                         deb_getf("QPSK ");
435                         ofdm->constellation = QPSK;
436                         break;
437                 case DIB3000_CONSTELLATION_16QAM:
438                         deb_getf("QAM16 ");
439                         ofdm->constellation = QAM_16;
440                         break;
441                 case DIB3000_CONSTELLATION_64QAM:
442                         deb_getf("QAM64 ");
443                         ofdm->constellation = QAM_64;
444                         break;
445                 default:
446                         err("Unexpected constellation returned by TPS (%d)", tps_val);
447                         break;
448         }
449         deb_getf("TPS: %d\n", tps_val);
450
451         if (rd(DIB3000MB_REG_TPS_HRCH)) {
452                 deb_getf("HRCH ON\n");
453                 cr = &ofdm->code_rate_LP;
454                 ofdm->code_rate_HP = FEC_NONE;
455                 switch ((tps_val = rd(DIB3000MB_REG_TPS_VIT_ALPHA))) {
456                         case DIB3000_ALPHA_0:
457                                 deb_getf("HIERARCHY_NONE ");
458                                 ofdm->hierarchy_information = HIERARCHY_NONE;
459                                 break;
460                         case DIB3000_ALPHA_1:
461                                 deb_getf("HIERARCHY_1 ");
462                                 ofdm->hierarchy_information = HIERARCHY_1;
463                                 break;
464                         case DIB3000_ALPHA_2:
465                                 deb_getf("HIERARCHY_2 ");
466                                 ofdm->hierarchy_information = HIERARCHY_2;
467                                 break;
468                         case DIB3000_ALPHA_4:
469                                 deb_getf("HIERARCHY_4 ");
470                                 ofdm->hierarchy_information = HIERARCHY_4;
471                                 break;
472                         default:
473                                 err("Unexpected ALPHA value returned by TPS (%d)", tps_val);
474                                 break;
475                 }
476                 deb_getf("TPS: %d\n", tps_val);
477
478                 tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_LP);
479         } else {
480                 deb_getf("HRCH OFF\n");
481                 cr = &ofdm->code_rate_HP;
482                 ofdm->code_rate_LP = FEC_NONE;
483                 ofdm->hierarchy_information = HIERARCHY_NONE;
484
485                 tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_HP);
486         }
487
488         switch (tps_val) {
489                 case DIB3000_FEC_1_2:
490                         deb_getf("FEC_1_2 ");
491                         *cr = FEC_1_2;
492                         break;
493                 case DIB3000_FEC_2_3:
494                         deb_getf("FEC_2_3 ");
495                         *cr = FEC_2_3;
496                         break;
497                 case DIB3000_FEC_3_4:
498                         deb_getf("FEC_3_4 ");
499                         *cr = FEC_3_4;
500                         break;
501                 case DIB3000_FEC_5_6:
502                         deb_getf("FEC_5_6 ");
503                         *cr = FEC_4_5;
504                         break;
505                 case DIB3000_FEC_7_8:
506                         deb_getf("FEC_7_8 ");
507                         *cr = FEC_7_8;
508                         break;
509                 default:
510                         err("Unexpected FEC returned by TPS (%d)", tps_val);
511                         break;
512         }
513         deb_getf("TPS: %d\n",tps_val);
514
515         switch ((tps_val = rd(DIB3000MB_REG_TPS_GUARD_TIME))) {
516                 case DIB3000_GUARD_TIME_1_32:
517                         deb_getf("GUARD_INTERVAL_1_32 ");
518                         ofdm->guard_interval = GUARD_INTERVAL_1_32;
519                         break;
520                 case DIB3000_GUARD_TIME_1_16:
521                         deb_getf("GUARD_INTERVAL_1_16 ");
522                         ofdm->guard_interval = GUARD_INTERVAL_1_16;
523                         break;
524                 case DIB3000_GUARD_TIME_1_8:
525                         deb_getf("GUARD_INTERVAL_1_8 ");
526                         ofdm->guard_interval = GUARD_INTERVAL_1_8;
527                         break;
528                 case DIB3000_GUARD_TIME_1_4:
529                         deb_getf("GUARD_INTERVAL_1_4 ");
530                         ofdm->guard_interval = GUARD_INTERVAL_1_4;
531                         break;
532                 default:
533                         err("Unexpected Guard Time returned by TPS (%d)", tps_val);
534                         break;
535         }
536         deb_getf("TPS: %d\n", tps_val);
537
538         switch ((tps_val = rd(DIB3000MB_REG_TPS_FFT))) {
539                 case DIB3000_TRANSMISSION_MODE_2K:
540                         deb_getf("TRANSMISSION_MODE_2K ");
541                         ofdm->transmission_mode = TRANSMISSION_MODE_2K;
542                         break;
543                 case DIB3000_TRANSMISSION_MODE_8K:
544                         deb_getf("TRANSMISSION_MODE_8K ");
545                         ofdm->transmission_mode = TRANSMISSION_MODE_8K;
546                         break;
547                 default:
548                         err("unexpected transmission mode return by TPS (%d)", tps_val);
549                         break;
550         }
551         deb_getf("TPS: %d\n", tps_val);
552
553         return 0;
554 }
555
556 static int dib3000mb_read_status(struct dvb_frontend* fe, fe_status_t *stat)
557 {
558         struct dib3000_state* state = fe->demodulator_priv;
559
560         *stat = 0;
561
562         if (rd(DIB3000MB_REG_AGC_LOCK))
563                 *stat |= FE_HAS_SIGNAL;
564         if (rd(DIB3000MB_REG_CARRIER_LOCK))
565                 *stat |= FE_HAS_CARRIER;
566         if (rd(DIB3000MB_REG_VIT_LCK))
567                 *stat |= FE_HAS_VITERBI;
568         if (rd(DIB3000MB_REG_TS_SYNC_LOCK))
569                 *stat |= (FE_HAS_SYNC | FE_HAS_LOCK);
570
571         deb_getf("actual status is %2x\n",*stat);
572
573         deb_getf("autoval: tps: %d, qam: %d, hrch: %d, alpha: %d, hp: %d, lp: %d, guard: %d, fft: %d cell: %d\n",
574                         rd(DIB3000MB_REG_TPS_LOCK),
575                         rd(DIB3000MB_REG_TPS_QAM),
576                         rd(DIB3000MB_REG_TPS_HRCH),
577                         rd(DIB3000MB_REG_TPS_VIT_ALPHA),
578                         rd(DIB3000MB_REG_TPS_CODE_RATE_HP),
579                         rd(DIB3000MB_REG_TPS_CODE_RATE_LP),
580                         rd(DIB3000MB_REG_TPS_GUARD_TIME),
581                         rd(DIB3000MB_REG_TPS_FFT),
582                         rd(DIB3000MB_REG_TPS_CELL_ID));
583
584         //*stat = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
585         return 0;
586 }
587
588 static int dib3000mb_read_ber(struct dvb_frontend* fe, u32 *ber)
589 {
590         struct dib3000_state* state = fe->demodulator_priv;
591
592         *ber = ((rd(DIB3000MB_REG_BER_MSB) << 16) | rd(DIB3000MB_REG_BER_LSB));
593         return 0;
594 }
595
596 /* see dib3000-watch dvb-apps for exact calcuations of signal_strength and snr */
597 static int dib3000mb_read_signal_strength(struct dvb_frontend* fe, u16 *strength)
598 {
599         struct dib3000_state* state = fe->demodulator_priv;
600
601         *strength = rd(DIB3000MB_REG_SIGNAL_POWER) * 0xffff / 0x170;
602         return 0;
603 }
604
605 static int dib3000mb_read_snr(struct dvb_frontend* fe, u16 *snr)
606 {
607         struct dib3000_state* state = fe->demodulator_priv;
608         short sigpow = rd(DIB3000MB_REG_SIGNAL_POWER);
609         int icipow = ((rd(DIB3000MB_REG_NOISE_POWER_MSB) & 0xff) << 16) |
610                 rd(DIB3000MB_REG_NOISE_POWER_LSB);
611         *snr = (sigpow << 8) / ((icipow > 0) ? icipow : 1);
612         return 0;
613 }
614
615 static int dib3000mb_read_unc_blocks(struct dvb_frontend* fe, u32 *unc)
616 {
617         struct dib3000_state* state = fe->demodulator_priv;
618
619         *unc = rd(DIB3000MB_REG_PACKET_ERROR_RATE);
620         return 0;
621 }
622
623 static int dib3000mb_sleep(struct dvb_frontend* fe)
624 {
625         struct dib3000_state* state = fe->demodulator_priv;
626         deb_info("dib3000mb is going to bed.\n");
627         wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_DOWN);
628         return 0;
629 }
630
631 static int dib3000mb_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
632 {
633         tune->min_delay_ms = 800;
634         return 0;
635 }
636
637 static int dib3000mb_fe_init_nonmobile(struct dvb_frontend* fe)
638 {
639         return dib3000mb_fe_init(fe, 0);
640 }
641
642 static int dib3000mb_set_frontend_and_tuner(struct dvb_frontend* fe, struct dvb_frontend_parameters *fep)
643 {
644         return dib3000mb_set_frontend(fe, fep, 1);
645 }
646
647 static void dib3000mb_release(struct dvb_frontend* fe)
648 {
649         struct dib3000_state *state = fe->demodulator_priv;
650         kfree(state);
651 }
652
653 /* pid filter and transfer stuff */
654 static int dib3000mb_pid_control(struct dvb_frontend *fe,int index, int pid,int onoff)
655 {
656         struct dib3000_state *state = fe->demodulator_priv;
657         pid = (onoff ? pid | DIB3000_ACTIVATE_PID_FILTERING : 0);
658         wr(index+DIB3000MB_REG_FIRST_PID,pid);
659         return 0;
660 }
661
662 static int dib3000mb_fifo_control(struct dvb_frontend *fe, int onoff)
663 {
664         struct dib3000_state *state = fe->demodulator_priv;
665
666         deb_xfer("%s fifo\n",onoff ? "enabling" : "disabling");
667         if (onoff) {
668                 wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_ACTIVATE);
669         } else {
670                 wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT);
671         }
672         return 0;
673 }
674
675 static int dib3000mb_pid_parse(struct dvb_frontend *fe, int onoff)
676 {
677         struct dib3000_state *state = fe->demodulator_priv;
678         deb_xfer("%s pid parsing\n",onoff ? "enabling" : "disabling");
679         wr(DIB3000MB_REG_PID_PARSE,onoff);
680         return 0;
681 }
682
683 static int dib3000mb_tuner_pass_ctrl(struct dvb_frontend *fe, int onoff, u8 pll_addr)
684 {
685         struct dib3000_state *state = fe->demodulator_priv;
686         if (onoff) {
687                 wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_ENABLE(pll_addr));
688         } else {
689                 wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_DISABLE(pll_addr));
690         }
691         return 0;
692 }
693
694 static struct dvb_frontend_ops dib3000mb_ops;
695
696 struct dvb_frontend* dib3000mb_attach(const struct dib3000_config* config,
697                                       struct i2c_adapter* i2c, struct dib_fe_xfer_ops *xfer_ops)
698 {
699         struct dib3000_state* state = NULL;
700
701         /* allocate memory for the internal state */
702         state = kmalloc(sizeof(struct dib3000_state), GFP_KERNEL);
703         if (state == NULL)
704                 goto error;
705         memset(state,0,sizeof(struct dib3000_state));
706
707         /* setup the state */
708         state->i2c = i2c;
709         memcpy(&state->config,config,sizeof(struct dib3000_config));
710         memcpy(&state->ops, &dib3000mb_ops, sizeof(struct dvb_frontend_ops));
711
712         /* check for the correct demod */
713         if (rd(DIB3000_REG_MANUFACTOR_ID) != DIB3000_I2C_ID_DIBCOM)
714                 goto error;
715
716         if (rd(DIB3000_REG_DEVICE_ID) != DIB3000MB_DEVICE_ID)
717                 goto error;
718
719         /* create dvb_frontend */
720         state->frontend.ops = &state->ops;
721         state->frontend.demodulator_priv = state;
722
723         /* set the xfer operations */
724         xfer_ops->pid_parse = dib3000mb_pid_parse;
725         xfer_ops->fifo_ctrl = dib3000mb_fifo_control;
726         xfer_ops->pid_ctrl = dib3000mb_pid_control;
727         xfer_ops->tuner_pass_ctrl = dib3000mb_tuner_pass_ctrl;
728
729         return &state->frontend;
730
731 error:
732         kfree(state);
733         return NULL;
734 }
735
736 static struct dvb_frontend_ops dib3000mb_ops = {
737
738         .info = {
739                 .name                   = "DiBcom 3000M-B DVB-T",
740                 .type                   = FE_OFDM,
741                 .frequency_min          = 44250000,
742                 .frequency_max          = 867250000,
743                 .frequency_stepsize     = 62500,
744                 .caps = FE_CAN_INVERSION_AUTO |
745                                 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
746                                 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
747                                 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
748                                 FE_CAN_TRANSMISSION_MODE_AUTO |
749                                 FE_CAN_GUARD_INTERVAL_AUTO |
750                                 FE_CAN_RECOVER |
751                                 FE_CAN_HIERARCHY_AUTO,
752         },
753
754         .release = dib3000mb_release,
755
756         .init = dib3000mb_fe_init_nonmobile,
757         .sleep = dib3000mb_sleep,
758
759         .set_frontend = dib3000mb_set_frontend_and_tuner,
760         .get_frontend = dib3000mb_get_frontend,
761         .get_tune_settings = dib3000mb_fe_get_tune_settings,
762
763         .read_status = dib3000mb_read_status,
764         .read_ber = dib3000mb_read_ber,
765         .read_signal_strength = dib3000mb_read_signal_strength,
766         .read_snr = dib3000mb_read_snr,
767         .read_ucblocks = dib3000mb_read_unc_blocks,
768 };
769
770 MODULE_AUTHOR(DRIVER_AUTHOR);
771 MODULE_DESCRIPTION(DRIVER_DESC);
772 MODULE_LICENSE("GPL");
773
774 EXPORT_SYMBOL(dib3000mb_attach);