[PATCH] KVM: Handle p5 mce msrs
[linux-2.6.git] / drivers / kvm / vmx.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * This module enables machines with Intel VT-x extensions to run virtual
5  * machines without emulation or binary translation.
6  *
7  * Copyright (C) 2006 Qumranet, Inc.
8  *
9  * Authors:
10  *   Avi Kivity   <avi@qumranet.com>
11  *   Yaniv Kamay  <yaniv@qumranet.com>
12  *
13  * This work is licensed under the terms of the GNU GPL, version 2.  See
14  * the COPYING file in the top-level directory.
15  *
16  */
17
18 #include "kvm.h"
19 #include "vmx.h"
20 #include "kvm_vmx.h"
21 #include <linux/module.h>
22 #include <linux/mm.h>
23 #include <linux/highmem.h>
24 #include <asm/io.h>
25 #include <asm/desc.h>
26
27 #include "segment_descriptor.h"
28
29 #define MSR_IA32_FEATURE_CONTROL                0x03a
30
31 MODULE_AUTHOR("Qumranet");
32 MODULE_LICENSE("GPL");
33
34 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
35 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
36
37 #ifdef CONFIG_X86_64
38 #define HOST_IS_64 1
39 #else
40 #define HOST_IS_64 0
41 #endif
42
43 static struct vmcs_descriptor {
44         int size;
45         int order;
46         u32 revision_id;
47 } vmcs_descriptor;
48
49 #define VMX_SEGMENT_FIELD(seg)                                  \
50         [VCPU_SREG_##seg] = {                                   \
51                 .selector = GUEST_##seg##_SELECTOR,             \
52                 .base = GUEST_##seg##_BASE,                     \
53                 .limit = GUEST_##seg##_LIMIT,                   \
54                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
55         }
56
57 static struct kvm_vmx_segment_field {
58         unsigned selector;
59         unsigned base;
60         unsigned limit;
61         unsigned ar_bytes;
62 } kvm_vmx_segment_fields[] = {
63         VMX_SEGMENT_FIELD(CS),
64         VMX_SEGMENT_FIELD(DS),
65         VMX_SEGMENT_FIELD(ES),
66         VMX_SEGMENT_FIELD(FS),
67         VMX_SEGMENT_FIELD(GS),
68         VMX_SEGMENT_FIELD(SS),
69         VMX_SEGMENT_FIELD(TR),
70         VMX_SEGMENT_FIELD(LDTR),
71 };
72
73 static const u32 vmx_msr_index[] = {
74 #ifdef CONFIG_X86_64
75         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
76 #endif
77         MSR_EFER, MSR_K6_STAR,
78 };
79 #define NR_VMX_MSR (sizeof(vmx_msr_index) / sizeof(*vmx_msr_index))
80
81 static inline int is_page_fault(u32 intr_info)
82 {
83         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
84                              INTR_INFO_VALID_MASK)) ==
85                 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
86 }
87
88 static inline int is_external_interrupt(u32 intr_info)
89 {
90         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
91                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
92 }
93
94 static struct vmx_msr_entry *find_msr_entry(struct kvm_vcpu *vcpu, u32 msr)
95 {
96         int i;
97
98         for (i = 0; i < vcpu->nmsrs; ++i)
99                 if (vcpu->guest_msrs[i].index == msr)
100                         return &vcpu->guest_msrs[i];
101         return 0;
102 }
103
104 static void vmcs_clear(struct vmcs *vmcs)
105 {
106         u64 phys_addr = __pa(vmcs);
107         u8 error;
108
109         asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
110                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
111                       : "cc", "memory");
112         if (error)
113                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
114                        vmcs, phys_addr);
115 }
116
117 static void __vcpu_clear(void *arg)
118 {
119         struct kvm_vcpu *vcpu = arg;
120         int cpu = smp_processor_id();
121
122         if (vcpu->cpu == cpu)
123                 vmcs_clear(vcpu->vmcs);
124         if (per_cpu(current_vmcs, cpu) == vcpu->vmcs)
125                 per_cpu(current_vmcs, cpu) = NULL;
126 }
127
128 static unsigned long vmcs_readl(unsigned long field)
129 {
130         unsigned long value;
131
132         asm volatile (ASM_VMX_VMREAD_RDX_RAX
133                       : "=a"(value) : "d"(field) : "cc");
134         return value;
135 }
136
137 static u16 vmcs_read16(unsigned long field)
138 {
139         return vmcs_readl(field);
140 }
141
142 static u32 vmcs_read32(unsigned long field)
143 {
144         return vmcs_readl(field);
145 }
146
147 static u64 vmcs_read64(unsigned long field)
148 {
149 #ifdef CONFIG_X86_64
150         return vmcs_readl(field);
151 #else
152         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
153 #endif
154 }
155
156 static void vmcs_writel(unsigned long field, unsigned long value)
157 {
158         u8 error;
159
160         asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
161                        : "=q"(error) : "a"(value), "d"(field) : "cc" );
162         if (error)
163                 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
164                        field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
165 }
166
167 static void vmcs_write16(unsigned long field, u16 value)
168 {
169         vmcs_writel(field, value);
170 }
171
172 static void vmcs_write32(unsigned long field, u32 value)
173 {
174         vmcs_writel(field, value);
175 }
176
177 static void vmcs_write64(unsigned long field, u64 value)
178 {
179 #ifdef CONFIG_X86_64
180         vmcs_writel(field, value);
181 #else
182         vmcs_writel(field, value);
183         asm volatile ("");
184         vmcs_writel(field+1, value >> 32);
185 #endif
186 }
187
188 /*
189  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
190  * vcpu mutex is already taken.
191  */
192 static struct kvm_vcpu *vmx_vcpu_load(struct kvm_vcpu *vcpu)
193 {
194         u64 phys_addr = __pa(vcpu->vmcs);
195         int cpu;
196
197         cpu = get_cpu();
198
199         if (vcpu->cpu != cpu) {
200                 smp_call_function(__vcpu_clear, vcpu, 0, 1);
201                 vcpu->launched = 0;
202         }
203
204         if (per_cpu(current_vmcs, cpu) != vcpu->vmcs) {
205                 u8 error;
206
207                 per_cpu(current_vmcs, cpu) = vcpu->vmcs;
208                 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
209                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
210                               : "cc");
211                 if (error)
212                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
213                                vcpu->vmcs, phys_addr);
214         }
215
216         if (vcpu->cpu != cpu) {
217                 struct descriptor_table dt;
218                 unsigned long sysenter_esp;
219
220                 vcpu->cpu = cpu;
221                 /*
222                  * Linux uses per-cpu TSS and GDT, so set these when switching
223                  * processors.
224                  */
225                 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
226                 get_gdt(&dt);
227                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
228
229                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
230                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
231         }
232         return vcpu;
233 }
234
235 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
236 {
237         put_cpu();
238 }
239
240 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
241 {
242         return vmcs_readl(GUEST_RFLAGS);
243 }
244
245 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
246 {
247         vmcs_writel(GUEST_RFLAGS, rflags);
248 }
249
250 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
251 {
252         unsigned long rip;
253         u32 interruptibility;
254
255         rip = vmcs_readl(GUEST_RIP);
256         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
257         vmcs_writel(GUEST_RIP, rip);
258
259         /*
260          * We emulated an instruction, so temporary interrupt blocking
261          * should be removed, if set.
262          */
263         interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
264         if (interruptibility & 3)
265                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
266                              interruptibility & ~3);
267 }
268
269 static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
270 {
271         printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
272                vmcs_readl(GUEST_RIP));
273         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
274         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
275                      GP_VECTOR |
276                      INTR_TYPE_EXCEPTION |
277                      INTR_INFO_DELIEVER_CODE_MASK |
278                      INTR_INFO_VALID_MASK);
279 }
280
281 /*
282  * reads and returns guest's timestamp counter "register"
283  * guest_tsc = host_tsc + tsc_offset    -- 21.3
284  */
285 static u64 guest_read_tsc(void)
286 {
287         u64 host_tsc, tsc_offset;
288
289         rdtscll(host_tsc);
290         tsc_offset = vmcs_read64(TSC_OFFSET);
291         return host_tsc + tsc_offset;
292 }
293
294 /*
295  * writes 'guest_tsc' into guest's timestamp counter "register"
296  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
297  */
298 static void guest_write_tsc(u64 guest_tsc)
299 {
300         u64 host_tsc;
301
302         rdtscll(host_tsc);
303         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
304 }
305
306 static void reload_tss(void)
307 {
308 #ifndef CONFIG_X86_64
309
310         /*
311          * VT restores TR but not its size.  Useless.
312          */
313         struct descriptor_table gdt;
314         struct segment_descriptor *descs;
315
316         get_gdt(&gdt);
317         descs = (void *)gdt.base;
318         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
319         load_TR_desc();
320 #endif
321 }
322
323 /*
324  * Reads an msr value (of 'msr_index') into 'pdata'.
325  * Returns 0 on success, non-0 otherwise.
326  * Assumes vcpu_load() was already called.
327  */
328 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
329 {
330         u64 data;
331         struct vmx_msr_entry *msr;
332
333         if (!pdata) {
334                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
335                 return -EINVAL;
336         }
337
338         switch (msr_index) {
339 #ifdef CONFIG_X86_64
340         case MSR_FS_BASE:
341                 data = vmcs_readl(GUEST_FS_BASE);
342                 break;
343         case MSR_GS_BASE:
344                 data = vmcs_readl(GUEST_GS_BASE);
345                 break;
346         case MSR_EFER:
347                 data = vcpu->shadow_efer;
348                 break;
349 #endif
350         case MSR_IA32_TIME_STAMP_COUNTER:
351                 data = guest_read_tsc();
352                 break;
353         case MSR_IA32_SYSENTER_CS:
354                 data = vmcs_read32(GUEST_SYSENTER_CS);
355                 break;
356         case MSR_IA32_SYSENTER_EIP:
357                 data = vmcs_read32(GUEST_SYSENTER_EIP);
358                 break;
359         case MSR_IA32_SYSENTER_ESP:
360                 data = vmcs_read32(GUEST_SYSENTER_ESP);
361                 break;
362         case MSR_IA32_P5_MC_ADDR:
363         case MSR_IA32_P5_MC_TYPE:
364         case MSR_IA32_MC0_CTL:
365         case MSR_IA32_MCG_STATUS:
366         case MSR_IA32_MCG_CAP:
367         case MSR_IA32_MC0_MISC:
368         case MSR_IA32_MC0_MISC+4:
369         case MSR_IA32_MC0_MISC+8:
370         case MSR_IA32_MC0_MISC+12:
371         case MSR_IA32_MC0_MISC+16:
372         case MSR_IA32_UCODE_REV:
373                 /* MTRR registers */
374         case 0xfe:
375         case 0x200 ... 0x2ff:
376                 data = 0;
377                 break;
378         case MSR_IA32_APICBASE:
379                 data = vcpu->apic_base;
380                 break;
381         default:
382                 msr = find_msr_entry(vcpu, msr_index);
383                 if (!msr) {
384                         printk(KERN_ERR "kvm: unhandled rdmsr: %x\n", msr_index);
385                         return 1;
386                 }
387                 data = msr->data;
388                 break;
389         }
390
391         *pdata = data;
392         return 0;
393 }
394
395 /*
396  * Writes msr value into into the appropriate "register".
397  * Returns 0 on success, non-0 otherwise.
398  * Assumes vcpu_load() was already called.
399  */
400 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
401 {
402         struct vmx_msr_entry *msr;
403         switch (msr_index) {
404 #ifdef CONFIG_X86_64
405         case MSR_FS_BASE:
406                 vmcs_writel(GUEST_FS_BASE, data);
407                 break;
408         case MSR_GS_BASE:
409                 vmcs_writel(GUEST_GS_BASE, data);
410                 break;
411 #endif
412         case MSR_IA32_SYSENTER_CS:
413                 vmcs_write32(GUEST_SYSENTER_CS, data);
414                 break;
415         case MSR_IA32_SYSENTER_EIP:
416                 vmcs_write32(GUEST_SYSENTER_EIP, data);
417                 break;
418         case MSR_IA32_SYSENTER_ESP:
419                 vmcs_write32(GUEST_SYSENTER_ESP, data);
420                 break;
421 #ifdef __x86_64
422         case MSR_EFER:
423                 set_efer(vcpu, data);
424                 break;
425         case MSR_IA32_MC0_STATUS:
426                 printk(KERN_WARNING "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n"
427                             , __FUNCTION__, data);
428                 break;
429 #endif
430         case MSR_IA32_TIME_STAMP_COUNTER: {
431                 guest_write_tsc(data);
432                 break;
433         }
434         case MSR_IA32_UCODE_REV:
435         case MSR_IA32_UCODE_WRITE:
436         case 0x200 ... 0x2ff: /* MTRRs */
437                 break;
438         case MSR_IA32_APICBASE:
439                 vcpu->apic_base = data;
440                 break;
441         default:
442                 msr = find_msr_entry(vcpu, msr_index);
443                 if (!msr) {
444                         printk(KERN_ERR "kvm: unhandled wrmsr: 0x%x\n", msr_index);
445                         return 1;
446                 }
447                 msr->data = data;
448                 break;
449         }
450
451         return 0;
452 }
453
454 /*
455  * Sync the rsp and rip registers into the vcpu structure.  This allows
456  * registers to be accessed by indexing vcpu->regs.
457  */
458 static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
459 {
460         vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
461         vcpu->rip = vmcs_readl(GUEST_RIP);
462 }
463
464 /*
465  * Syncs rsp and rip back into the vmcs.  Should be called after possible
466  * modification.
467  */
468 static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
469 {
470         vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
471         vmcs_writel(GUEST_RIP, vcpu->rip);
472 }
473
474 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
475 {
476         unsigned long dr7 = 0x400;
477         u32 exception_bitmap;
478         int old_singlestep;
479
480         exception_bitmap = vmcs_read32(EXCEPTION_BITMAP);
481         old_singlestep = vcpu->guest_debug.singlestep;
482
483         vcpu->guest_debug.enabled = dbg->enabled;
484         if (vcpu->guest_debug.enabled) {
485                 int i;
486
487                 dr7 |= 0x200;  /* exact */
488                 for (i = 0; i < 4; ++i) {
489                         if (!dbg->breakpoints[i].enabled)
490                                 continue;
491                         vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
492                         dr7 |= 2 << (i*2);    /* global enable */
493                         dr7 |= 0 << (i*4+16); /* execution breakpoint */
494                 }
495
496                 exception_bitmap |= (1u << 1);  /* Trap debug exceptions */
497
498                 vcpu->guest_debug.singlestep = dbg->singlestep;
499         } else {
500                 exception_bitmap &= ~(1u << 1); /* Ignore debug exceptions */
501                 vcpu->guest_debug.singlestep = 0;
502         }
503
504         if (old_singlestep && !vcpu->guest_debug.singlestep) {
505                 unsigned long flags;
506
507                 flags = vmcs_readl(GUEST_RFLAGS);
508                 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
509                 vmcs_writel(GUEST_RFLAGS, flags);
510         }
511
512         vmcs_write32(EXCEPTION_BITMAP, exception_bitmap);
513         vmcs_writel(GUEST_DR7, dr7);
514
515         return 0;
516 }
517
518 static __init int cpu_has_kvm_support(void)
519 {
520         unsigned long ecx = cpuid_ecx(1);
521         return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
522 }
523
524 static __init int vmx_disabled_by_bios(void)
525 {
526         u64 msr;
527
528         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
529         return (msr & 5) == 1; /* locked but not enabled */
530 }
531
532 static __init void hardware_enable(void *garbage)
533 {
534         int cpu = raw_smp_processor_id();
535         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
536         u64 old;
537
538         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
539         if ((old & 5) != 5)
540                 /* enable and lock */
541                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | 5);
542         write_cr4(read_cr4() | CR4_VMXE); /* FIXME: not cpu hotplug safe */
543         asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
544                       : "memory", "cc");
545 }
546
547 static void hardware_disable(void *garbage)
548 {
549         asm volatile (ASM_VMX_VMXOFF : : : "cc");
550 }
551
552 static __init void setup_vmcs_descriptor(void)
553 {
554         u32 vmx_msr_low, vmx_msr_high;
555
556         rdmsr(MSR_IA32_VMX_BASIC_MSR, vmx_msr_low, vmx_msr_high);
557         vmcs_descriptor.size = vmx_msr_high & 0x1fff;
558         vmcs_descriptor.order = get_order(vmcs_descriptor.size);
559         vmcs_descriptor.revision_id = vmx_msr_low;
560 };
561
562 static struct vmcs *alloc_vmcs_cpu(int cpu)
563 {
564         int node = cpu_to_node(cpu);
565         struct page *pages;
566         struct vmcs *vmcs;
567
568         pages = alloc_pages_node(node, GFP_KERNEL, vmcs_descriptor.order);
569         if (!pages)
570                 return NULL;
571         vmcs = page_address(pages);
572         memset(vmcs, 0, vmcs_descriptor.size);
573         vmcs->revision_id = vmcs_descriptor.revision_id; /* vmcs revision id */
574         return vmcs;
575 }
576
577 static struct vmcs *alloc_vmcs(void)
578 {
579         return alloc_vmcs_cpu(smp_processor_id());
580 }
581
582 static void free_vmcs(struct vmcs *vmcs)
583 {
584         free_pages((unsigned long)vmcs, vmcs_descriptor.order);
585 }
586
587 static __exit void free_kvm_area(void)
588 {
589         int cpu;
590
591         for_each_online_cpu(cpu)
592                 free_vmcs(per_cpu(vmxarea, cpu));
593 }
594
595 extern struct vmcs *alloc_vmcs_cpu(int cpu);
596
597 static __init int alloc_kvm_area(void)
598 {
599         int cpu;
600
601         for_each_online_cpu(cpu) {
602                 struct vmcs *vmcs;
603
604                 vmcs = alloc_vmcs_cpu(cpu);
605                 if (!vmcs) {
606                         free_kvm_area();
607                         return -ENOMEM;
608                 }
609
610                 per_cpu(vmxarea, cpu) = vmcs;
611         }
612         return 0;
613 }
614
615 static __init int hardware_setup(void)
616 {
617         setup_vmcs_descriptor();
618         return alloc_kvm_area();
619 }
620
621 static __exit void hardware_unsetup(void)
622 {
623         free_kvm_area();
624 }
625
626 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
627 {
628         if (vcpu->rmode.active)
629                 vmcs_write32(EXCEPTION_BITMAP, ~0);
630         else
631                 vmcs_write32(EXCEPTION_BITMAP, 1 << PF_VECTOR);
632 }
633
634 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
635 {
636         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
637
638         if (vmcs_readl(sf->base) == save->base) {
639                 vmcs_write16(sf->selector, save->selector);
640                 vmcs_writel(sf->base, save->base);
641                 vmcs_write32(sf->limit, save->limit);
642                 vmcs_write32(sf->ar_bytes, save->ar);
643         } else {
644                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
645                         << AR_DPL_SHIFT;
646                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
647         }
648 }
649
650 static void enter_pmode(struct kvm_vcpu *vcpu)
651 {
652         unsigned long flags;
653
654         vcpu->rmode.active = 0;
655
656         vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
657         vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
658         vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
659
660         flags = vmcs_readl(GUEST_RFLAGS);
661         flags &= ~(IOPL_MASK | X86_EFLAGS_VM);
662         flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
663         vmcs_writel(GUEST_RFLAGS, flags);
664
665         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~CR4_VME_MASK) |
666                         (vmcs_readl(CR4_READ_SHADOW) & CR4_VME_MASK));
667
668         update_exception_bitmap(vcpu);
669
670         fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
671         fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
672         fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
673         fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
674
675         vmcs_write16(GUEST_SS_SELECTOR, 0);
676         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
677
678         vmcs_write16(GUEST_CS_SELECTOR,
679                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
680         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
681 }
682
683 static int rmode_tss_base(struct kvm* kvm)
684 {
685         gfn_t base_gfn = kvm->memslots[0].base_gfn + kvm->memslots[0].npages - 3;
686         return base_gfn << PAGE_SHIFT;
687 }
688
689 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
690 {
691         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
692
693         save->selector = vmcs_read16(sf->selector);
694         save->base = vmcs_readl(sf->base);
695         save->limit = vmcs_read32(sf->limit);
696         save->ar = vmcs_read32(sf->ar_bytes);
697         vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
698         vmcs_write32(sf->limit, 0xffff);
699         vmcs_write32(sf->ar_bytes, 0xf3);
700 }
701
702 static void enter_rmode(struct kvm_vcpu *vcpu)
703 {
704         unsigned long flags;
705
706         vcpu->rmode.active = 1;
707
708         vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
709         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
710
711         vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
712         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
713
714         vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
715         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
716
717         flags = vmcs_readl(GUEST_RFLAGS);
718         vcpu->rmode.save_iopl = (flags & IOPL_MASK) >> IOPL_SHIFT;
719
720         flags |= IOPL_MASK | X86_EFLAGS_VM;
721
722         vmcs_writel(GUEST_RFLAGS, flags);
723         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | CR4_VME_MASK);
724         update_exception_bitmap(vcpu);
725
726         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
727         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
728         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
729
730         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
731         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
732         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
733
734         fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
735         fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
736         fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
737         fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
738 }
739
740 #ifdef CONFIG_X86_64
741
742 static void enter_lmode(struct kvm_vcpu *vcpu)
743 {
744         u32 guest_tr_ar;
745
746         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
747         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
748                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
749                        __FUNCTION__);
750                 vmcs_write32(GUEST_TR_AR_BYTES,
751                              (guest_tr_ar & ~AR_TYPE_MASK)
752                              | AR_TYPE_BUSY_64_TSS);
753         }
754
755         vcpu->shadow_efer |= EFER_LMA;
756
757         find_msr_entry(vcpu, MSR_EFER)->data |= EFER_LMA | EFER_LME;
758         vmcs_write32(VM_ENTRY_CONTROLS,
759                      vmcs_read32(VM_ENTRY_CONTROLS)
760                      | VM_ENTRY_CONTROLS_IA32E_MASK);
761 }
762
763 static void exit_lmode(struct kvm_vcpu *vcpu)
764 {
765         vcpu->shadow_efer &= ~EFER_LMA;
766
767         vmcs_write32(VM_ENTRY_CONTROLS,
768                      vmcs_read32(VM_ENTRY_CONTROLS)
769                      & ~VM_ENTRY_CONTROLS_IA32E_MASK);
770 }
771
772 #endif
773
774 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
775 {
776         if (vcpu->rmode.active && (cr0 & CR0_PE_MASK))
777                 enter_pmode(vcpu);
778
779         if (!vcpu->rmode.active && !(cr0 & CR0_PE_MASK))
780                 enter_rmode(vcpu);
781
782 #ifdef CONFIG_X86_64
783         if (vcpu->shadow_efer & EFER_LME) {
784                 if (!is_paging(vcpu) && (cr0 & CR0_PG_MASK))
785                         enter_lmode(vcpu);
786                 if (is_paging(vcpu) && !(cr0 & CR0_PG_MASK))
787                         exit_lmode(vcpu);
788         }
789 #endif
790
791         vmcs_writel(CR0_READ_SHADOW, cr0);
792         vmcs_writel(GUEST_CR0,
793                     (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
794         vcpu->cr0 = cr0;
795 }
796
797 /*
798  * Used when restoring the VM to avoid corrupting segment registers
799  */
800 static void vmx_set_cr0_no_modeswitch(struct kvm_vcpu *vcpu, unsigned long cr0)
801 {
802         vcpu->rmode.active = ((cr0 & CR0_PE_MASK) == 0);
803         update_exception_bitmap(vcpu);
804         vmcs_writel(CR0_READ_SHADOW, cr0);
805         vmcs_writel(GUEST_CR0,
806                     (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
807         vcpu->cr0 = cr0;
808 }
809
810 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
811 {
812         vmcs_writel(GUEST_CR3, cr3);
813 }
814
815 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
816 {
817         vmcs_writel(CR4_READ_SHADOW, cr4);
818         vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
819                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
820         vcpu->cr4 = cr4;
821 }
822
823 #ifdef CONFIG_X86_64
824
825 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
826 {
827         struct vmx_msr_entry *msr = find_msr_entry(vcpu, MSR_EFER);
828
829         vcpu->shadow_efer = efer;
830         if (efer & EFER_LMA) {
831                 vmcs_write32(VM_ENTRY_CONTROLS,
832                                      vmcs_read32(VM_ENTRY_CONTROLS) |
833                                      VM_ENTRY_CONTROLS_IA32E_MASK);
834                 msr->data = efer;
835
836         } else {
837                 vmcs_write32(VM_ENTRY_CONTROLS,
838                                      vmcs_read32(VM_ENTRY_CONTROLS) &
839                                      ~VM_ENTRY_CONTROLS_IA32E_MASK);
840
841                 msr->data = efer & ~EFER_LME;
842         }
843 }
844
845 #endif
846
847 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
848 {
849         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
850
851         return vmcs_readl(sf->base);
852 }
853
854 static void vmx_get_segment(struct kvm_vcpu *vcpu,
855                             struct kvm_segment *var, int seg)
856 {
857         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
858         u32 ar;
859
860         var->base = vmcs_readl(sf->base);
861         var->limit = vmcs_read32(sf->limit);
862         var->selector = vmcs_read16(sf->selector);
863         ar = vmcs_read32(sf->ar_bytes);
864         if (ar & AR_UNUSABLE_MASK)
865                 ar = 0;
866         var->type = ar & 15;
867         var->s = (ar >> 4) & 1;
868         var->dpl = (ar >> 5) & 3;
869         var->present = (ar >> 7) & 1;
870         var->avl = (ar >> 12) & 1;
871         var->l = (ar >> 13) & 1;
872         var->db = (ar >> 14) & 1;
873         var->g = (ar >> 15) & 1;
874         var->unusable = (ar >> 16) & 1;
875 }
876
877 static void vmx_set_segment(struct kvm_vcpu *vcpu,
878                             struct kvm_segment *var, int seg)
879 {
880         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
881         u32 ar;
882
883         vmcs_writel(sf->base, var->base);
884         vmcs_write32(sf->limit, var->limit);
885         vmcs_write16(sf->selector, var->selector);
886         if (var->unusable)
887                 ar = 1 << 16;
888         else {
889                 ar = var->type & 15;
890                 ar |= (var->s & 1) << 4;
891                 ar |= (var->dpl & 3) << 5;
892                 ar |= (var->present & 1) << 7;
893                 ar |= (var->avl & 1) << 12;
894                 ar |= (var->l & 1) << 13;
895                 ar |= (var->db & 1) << 14;
896                 ar |= (var->g & 1) << 15;
897         }
898         if (ar == 0) /* a 0 value means unusable */
899                 ar = AR_UNUSABLE_MASK;
900         vmcs_write32(sf->ar_bytes, ar);
901 }
902
903 static int vmx_is_long_mode(struct kvm_vcpu *vcpu)
904 {
905         return vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_CONTROLS_IA32E_MASK;
906 }
907
908 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
909 {
910         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
911
912         *db = (ar >> 14) & 1;
913         *l = (ar >> 13) & 1;
914 }
915
916 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
917 {
918         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
919         dt->base = vmcs_readl(GUEST_IDTR_BASE);
920 }
921
922 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
923 {
924         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
925         vmcs_writel(GUEST_IDTR_BASE, dt->base);
926 }
927
928 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
929 {
930         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
931         dt->base = vmcs_readl(GUEST_GDTR_BASE);
932 }
933
934 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
935 {
936         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
937         vmcs_writel(GUEST_GDTR_BASE, dt->base);
938 }
939
940 static int init_rmode_tss(struct kvm* kvm)
941 {
942         struct page *p1, *p2, *p3;
943         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
944         char *page;
945
946         p1 = _gfn_to_page(kvm, fn++);
947         p2 = _gfn_to_page(kvm, fn++);
948         p3 = _gfn_to_page(kvm, fn);
949
950         if (!p1 || !p2 || !p3) {
951                 kvm_printf(kvm,"%s: gfn_to_page failed\n", __FUNCTION__);
952                 return 0;
953         }
954
955         page = kmap_atomic(p1, KM_USER0);
956         memset(page, 0, PAGE_SIZE);
957         *(u16*)(page + 0x66) = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
958         kunmap_atomic(page, KM_USER0);
959
960         page = kmap_atomic(p2, KM_USER0);
961         memset(page, 0, PAGE_SIZE);
962         kunmap_atomic(page, KM_USER0);
963
964         page = kmap_atomic(p3, KM_USER0);
965         memset(page, 0, PAGE_SIZE);
966         *(page + RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1) = ~0;
967         kunmap_atomic(page, KM_USER0);
968
969         return 1;
970 }
971
972 static void vmcs_write32_fixedbits(u32 msr, u32 vmcs_field, u32 val)
973 {
974         u32 msr_high, msr_low;
975
976         rdmsr(msr, msr_low, msr_high);
977
978         val &= msr_high;
979         val |= msr_low;
980         vmcs_write32(vmcs_field, val);
981 }
982
983 static void seg_setup(int seg)
984 {
985         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
986
987         vmcs_write16(sf->selector, 0);
988         vmcs_writel(sf->base, 0);
989         vmcs_write32(sf->limit, 0xffff);
990         vmcs_write32(sf->ar_bytes, 0x93);
991 }
992
993 /*
994  * Sets up the vmcs for emulated real mode.
995  */
996 static int vmx_vcpu_setup(struct kvm_vcpu *vcpu)
997 {
998         u32 host_sysenter_cs;
999         u32 junk;
1000         unsigned long a;
1001         struct descriptor_table dt;
1002         int i;
1003         int ret = 0;
1004         int nr_good_msrs;
1005         extern asmlinkage void kvm_vmx_return(void);
1006
1007         if (!init_rmode_tss(vcpu->kvm)) {
1008                 ret = -ENOMEM;
1009                 goto out;
1010         }
1011
1012         memset(vcpu->regs, 0, sizeof(vcpu->regs));
1013         vcpu->regs[VCPU_REGS_RDX] = get_rdx_init_val();
1014         vcpu->cr8 = 0;
1015         vcpu->apic_base = 0xfee00000 |
1016                         /*for vcpu 0*/ MSR_IA32_APICBASE_BSP |
1017                         MSR_IA32_APICBASE_ENABLE;
1018
1019         fx_init(vcpu);
1020
1021         /*
1022          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1023          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
1024          */
1025         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1026         vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1027         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1028         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1029
1030         seg_setup(VCPU_SREG_DS);
1031         seg_setup(VCPU_SREG_ES);
1032         seg_setup(VCPU_SREG_FS);
1033         seg_setup(VCPU_SREG_GS);
1034         seg_setup(VCPU_SREG_SS);
1035
1036         vmcs_write16(GUEST_TR_SELECTOR, 0);
1037         vmcs_writel(GUEST_TR_BASE, 0);
1038         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1039         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1040
1041         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1042         vmcs_writel(GUEST_LDTR_BASE, 0);
1043         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1044         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1045
1046         vmcs_write32(GUEST_SYSENTER_CS, 0);
1047         vmcs_writel(GUEST_SYSENTER_ESP, 0);
1048         vmcs_writel(GUEST_SYSENTER_EIP, 0);
1049
1050         vmcs_writel(GUEST_RFLAGS, 0x02);
1051         vmcs_writel(GUEST_RIP, 0xfff0);
1052         vmcs_writel(GUEST_RSP, 0);
1053
1054         vmcs_writel(GUEST_CR3, 0);
1055
1056         //todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0
1057         vmcs_writel(GUEST_DR7, 0x400);
1058
1059         vmcs_writel(GUEST_GDTR_BASE, 0);
1060         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1061
1062         vmcs_writel(GUEST_IDTR_BASE, 0);
1063         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1064
1065         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1066         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1067         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1068
1069         /* I/O */
1070         vmcs_write64(IO_BITMAP_A, 0);
1071         vmcs_write64(IO_BITMAP_B, 0);
1072
1073         guest_write_tsc(0);
1074
1075         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1076
1077         /* Special registers */
1078         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1079
1080         /* Control */
1081         vmcs_write32_fixedbits(MSR_IA32_VMX_PINBASED_CTLS_MSR,
1082                                PIN_BASED_VM_EXEC_CONTROL,
1083                                PIN_BASED_EXT_INTR_MASK   /* 20.6.1 */
1084                                | PIN_BASED_NMI_EXITING   /* 20.6.1 */
1085                         );
1086         vmcs_write32_fixedbits(MSR_IA32_VMX_PROCBASED_CTLS_MSR,
1087                                CPU_BASED_VM_EXEC_CONTROL,
1088                                CPU_BASED_HLT_EXITING         /* 20.6.2 */
1089                                | CPU_BASED_CR8_LOAD_EXITING    /* 20.6.2 */
1090                                | CPU_BASED_CR8_STORE_EXITING   /* 20.6.2 */
1091                                | CPU_BASED_UNCOND_IO_EXITING   /* 20.6.2 */
1092                                | CPU_BASED_INVDPG_EXITING
1093                                | CPU_BASED_MOV_DR_EXITING
1094                                | CPU_BASED_USE_TSC_OFFSETING   /* 21.3 */
1095                         );
1096
1097         vmcs_write32(EXCEPTION_BITMAP, 1 << PF_VECTOR);
1098         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
1099         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
1100         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
1101
1102         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
1103         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
1104         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
1105
1106         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
1107         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1108         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1109         vmcs_write16(HOST_FS_SELECTOR, read_fs());    /* 22.2.4 */
1110         vmcs_write16(HOST_GS_SELECTOR, read_gs());    /* 22.2.4 */
1111         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1112 #ifdef CONFIG_X86_64
1113         rdmsrl(MSR_FS_BASE, a);
1114         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1115         rdmsrl(MSR_GS_BASE, a);
1116         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1117 #else
1118         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1119         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1120 #endif
1121
1122         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
1123
1124         get_idt(&dt);
1125         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
1126
1127
1128         vmcs_writel(HOST_RIP, (unsigned long)kvm_vmx_return); /* 22.2.5 */
1129
1130         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1131         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1132         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1133         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
1134         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1135         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
1136
1137         ret = -ENOMEM;
1138         vcpu->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
1139         if (!vcpu->guest_msrs)
1140                 goto out;
1141         vcpu->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
1142         if (!vcpu->host_msrs)
1143                 goto out_free_guest_msrs;
1144
1145         for (i = 0; i < NR_VMX_MSR; ++i) {
1146                 u32 index = vmx_msr_index[i];
1147                 u32 data_low, data_high;
1148                 u64 data;
1149                 int j = vcpu->nmsrs;
1150
1151                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1152                         continue;
1153                 data = data_low | ((u64)data_high << 32);
1154                 vcpu->host_msrs[j].index = index;
1155                 vcpu->host_msrs[j].reserved = 0;
1156                 vcpu->host_msrs[j].data = data;
1157                 vcpu->guest_msrs[j] = vcpu->host_msrs[j];
1158                 ++vcpu->nmsrs;
1159         }
1160         printk(KERN_DEBUG "kvm: msrs: %d\n", vcpu->nmsrs);
1161
1162         nr_good_msrs = vcpu->nmsrs - NR_BAD_MSRS;
1163         vmcs_writel(VM_ENTRY_MSR_LOAD_ADDR,
1164                     virt_to_phys(vcpu->guest_msrs + NR_BAD_MSRS));
1165         vmcs_writel(VM_EXIT_MSR_STORE_ADDR,
1166                     virt_to_phys(vcpu->guest_msrs + NR_BAD_MSRS));
1167         vmcs_writel(VM_EXIT_MSR_LOAD_ADDR,
1168                     virt_to_phys(vcpu->host_msrs + NR_BAD_MSRS));
1169         vmcs_write32_fixedbits(MSR_IA32_VMX_EXIT_CTLS_MSR, VM_EXIT_CONTROLS,
1170                                (HOST_IS_64 << 9));  /* 22.2,1, 20.7.1 */
1171         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, nr_good_msrs); /* 22.2.2 */
1172         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, nr_good_msrs);  /* 22.2.2 */
1173         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, nr_good_msrs); /* 22.2.2 */
1174
1175
1176         /* 22.2.1, 20.8.1 */
1177         vmcs_write32_fixedbits(MSR_IA32_VMX_ENTRY_CTLS_MSR,
1178                                VM_ENTRY_CONTROLS, 0);
1179         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
1180
1181 #ifdef CONFIG_X86_64
1182         vmcs_writel(VIRTUAL_APIC_PAGE_ADDR, 0);
1183         vmcs_writel(TPR_THRESHOLD, 0);
1184 #endif
1185
1186         vmcs_writel(CR0_GUEST_HOST_MASK, KVM_GUEST_CR0_MASK);
1187         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1188
1189         vcpu->cr0 = 0x60000010;
1190         vmx_set_cr0(vcpu, vcpu->cr0); // enter rmode
1191         vmx_set_cr4(vcpu, 0);
1192 #ifdef CONFIG_X86_64
1193         vmx_set_efer(vcpu, 0);
1194 #endif
1195
1196         return 0;
1197
1198 out_free_guest_msrs:
1199         kfree(vcpu->guest_msrs);
1200 out:
1201         return ret;
1202 }
1203
1204 static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq)
1205 {
1206         u16 ent[2];
1207         u16 cs;
1208         u16 ip;
1209         unsigned long flags;
1210         unsigned long ss_base = vmcs_readl(GUEST_SS_BASE);
1211         u16 sp =  vmcs_readl(GUEST_RSP);
1212         u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT);
1213
1214         if (sp > ss_limit || sp - 6 > sp) {
1215                 vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n",
1216                             __FUNCTION__,
1217                             vmcs_readl(GUEST_RSP),
1218                             vmcs_readl(GUEST_SS_BASE),
1219                             vmcs_read32(GUEST_SS_LIMIT));
1220                 return;
1221         }
1222
1223         if (kvm_read_guest(vcpu, irq * sizeof(ent), sizeof(ent), &ent) !=
1224                                                                 sizeof(ent)) {
1225                 vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__);
1226                 return;
1227         }
1228
1229         flags =  vmcs_readl(GUEST_RFLAGS);
1230         cs =  vmcs_readl(GUEST_CS_BASE) >> 4;
1231         ip =  vmcs_readl(GUEST_RIP);
1232
1233
1234         if (kvm_write_guest(vcpu, ss_base + sp - 2, 2, &flags) != 2 ||
1235             kvm_write_guest(vcpu, ss_base + sp - 4, 2, &cs) != 2 ||
1236             kvm_write_guest(vcpu, ss_base + sp - 6, 2, &ip) != 2) {
1237                 vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__);
1238                 return;
1239         }
1240
1241         vmcs_writel(GUEST_RFLAGS, flags &
1242                     ~( X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF));
1243         vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ;
1244         vmcs_writel(GUEST_CS_BASE, ent[1] << 4);
1245         vmcs_writel(GUEST_RIP, ent[0]);
1246         vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6));
1247 }
1248
1249 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1250 {
1251         int word_index = __ffs(vcpu->irq_summary);
1252         int bit_index = __ffs(vcpu->irq_pending[word_index]);
1253         int irq = word_index * BITS_PER_LONG + bit_index;
1254
1255         clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1256         if (!vcpu->irq_pending[word_index])
1257                 clear_bit(word_index, &vcpu->irq_summary);
1258
1259         if (vcpu->rmode.active) {
1260                 inject_rmode_irq(vcpu, irq);
1261                 return;
1262         }
1263         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1264                         irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1265 }
1266
1267 static void kvm_try_inject_irq(struct kvm_vcpu *vcpu)
1268 {
1269         if ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF)
1270             && (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0)
1271                 /*
1272                  * Interrupts enabled, and not blocked by sti or mov ss. Good.
1273                  */
1274                 kvm_do_inject_irq(vcpu);
1275         else
1276                 /*
1277                  * Interrupts blocked.  Wait for unblock.
1278                  */
1279                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1280                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL)
1281                              | CPU_BASED_VIRTUAL_INTR_PENDING);
1282 }
1283
1284 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1285 {
1286         struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1287
1288         set_debugreg(dbg->bp[0], 0);
1289         set_debugreg(dbg->bp[1], 1);
1290         set_debugreg(dbg->bp[2], 2);
1291         set_debugreg(dbg->bp[3], 3);
1292
1293         if (dbg->singlestep) {
1294                 unsigned long flags;
1295
1296                 flags = vmcs_readl(GUEST_RFLAGS);
1297                 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1298                 vmcs_writel(GUEST_RFLAGS, flags);
1299         }
1300 }
1301
1302 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1303                                   int vec, u32 err_code)
1304 {
1305         if (!vcpu->rmode.active)
1306                 return 0;
1307
1308         if (vec == GP_VECTOR && err_code == 0)
1309                 if (emulate_instruction(vcpu, NULL, 0, 0) == EMULATE_DONE)
1310                         return 1;
1311         return 0;
1312 }
1313
1314 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1315 {
1316         u32 intr_info, error_code;
1317         unsigned long cr2, rip;
1318         u32 vect_info;
1319         enum emulation_result er;
1320
1321         vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1322         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1323
1324         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1325                                                 !is_page_fault(intr_info)) {
1326                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1327                        "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1328         }
1329
1330         if (is_external_interrupt(vect_info)) {
1331                 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1332                 set_bit(irq, vcpu->irq_pending);
1333                 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1334         }
1335
1336         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */
1337                 asm ("int $2");
1338                 return 1;
1339         }
1340         error_code = 0;
1341         rip = vmcs_readl(GUEST_RIP);
1342         if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1343                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1344         if (is_page_fault(intr_info)) {
1345                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1346
1347                 spin_lock(&vcpu->kvm->lock);
1348                 if (!vcpu->mmu.page_fault(vcpu, cr2, error_code)) {
1349                         spin_unlock(&vcpu->kvm->lock);
1350                         return 1;
1351                 }
1352
1353                 er = emulate_instruction(vcpu, kvm_run, cr2, error_code);
1354                 spin_unlock(&vcpu->kvm->lock);
1355
1356                 switch (er) {
1357                 case EMULATE_DONE:
1358                         return 1;
1359                 case EMULATE_DO_MMIO:
1360                         ++kvm_stat.mmio_exits;
1361                         kvm_run->exit_reason = KVM_EXIT_MMIO;
1362                         return 0;
1363                  case EMULATE_FAIL:
1364                         vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__);
1365                         break;
1366                 default:
1367                         BUG();
1368                 }
1369         }
1370
1371         if (vcpu->rmode.active &&
1372             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1373                                                                 error_code))
1374                 return 1;
1375
1376         if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == (INTR_TYPE_EXCEPTION | 1)) {
1377                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1378                 return 0;
1379         }
1380         kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1381         kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1382         kvm_run->ex.error_code = error_code;
1383         return 0;
1384 }
1385
1386 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1387                                      struct kvm_run *kvm_run)
1388 {
1389         ++kvm_stat.irq_exits;
1390         return 1;
1391 }
1392
1393
1394 static int get_io_count(struct kvm_vcpu *vcpu, u64 *count)
1395 {
1396         u64 inst;
1397         gva_t rip;
1398         int countr_size;
1399         int i, n;
1400
1401         if ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_VM)) {
1402                 countr_size = 2;
1403         } else {
1404                 u32 cs_ar = vmcs_read32(GUEST_CS_AR_BYTES);
1405
1406                 countr_size = (cs_ar & AR_L_MASK) ? 8:
1407                               (cs_ar & AR_DB_MASK) ? 4: 2;
1408         }
1409
1410         rip =  vmcs_readl(GUEST_RIP);
1411         if (countr_size != 8)
1412                 rip += vmcs_readl(GUEST_CS_BASE);
1413
1414         n = kvm_read_guest(vcpu, rip, sizeof(inst), &inst);
1415
1416         for (i = 0; i < n; i++) {
1417                 switch (((u8*)&inst)[i]) {
1418                 case 0xf0:
1419                 case 0xf2:
1420                 case 0xf3:
1421                 case 0x2e:
1422                 case 0x36:
1423                 case 0x3e:
1424                 case 0x26:
1425                 case 0x64:
1426                 case 0x65:
1427                 case 0x66:
1428                         break;
1429                 case 0x67:
1430                         countr_size = (countr_size == 2) ? 4: (countr_size >> 1);
1431                 default:
1432                         goto done;
1433                 }
1434         }
1435         return 0;
1436 done:
1437         countr_size *= 8;
1438         *count = vcpu->regs[VCPU_REGS_RCX] & (~0ULL >> (64 - countr_size));
1439         return 1;
1440 }
1441
1442 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1443 {
1444         u64 exit_qualification;
1445
1446         ++kvm_stat.io_exits;
1447         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1448         kvm_run->exit_reason = KVM_EXIT_IO;
1449         if (exit_qualification & 8)
1450                 kvm_run->io.direction = KVM_EXIT_IO_IN;
1451         else
1452                 kvm_run->io.direction = KVM_EXIT_IO_OUT;
1453         kvm_run->io.size = (exit_qualification & 7) + 1;
1454         kvm_run->io.string = (exit_qualification & 16) != 0;
1455         kvm_run->io.string_down
1456                 = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1457         kvm_run->io.rep = (exit_qualification & 32) != 0;
1458         kvm_run->io.port = exit_qualification >> 16;
1459         if (kvm_run->io.string) {
1460                 if (!get_io_count(vcpu, &kvm_run->io.count))
1461                         return 1;
1462                 kvm_run->io.address = vmcs_readl(GUEST_LINEAR_ADDRESS);
1463         } else
1464                 kvm_run->io.value = vcpu->regs[VCPU_REGS_RAX]; /* rax */
1465         return 0;
1466 }
1467
1468 static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1469 {
1470         u64 address = vmcs_read64(EXIT_QUALIFICATION);
1471         int instruction_length = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1472         spin_lock(&vcpu->kvm->lock);
1473         vcpu->mmu.inval_page(vcpu, address);
1474         spin_unlock(&vcpu->kvm->lock);
1475         vmcs_writel(GUEST_RIP, vmcs_readl(GUEST_RIP) + instruction_length);
1476         return 1;
1477 }
1478
1479 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1480 {
1481         u64 exit_qualification;
1482         int cr;
1483         int reg;
1484
1485         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1486         cr = exit_qualification & 15;
1487         reg = (exit_qualification >> 8) & 15;
1488         switch ((exit_qualification >> 4) & 3) {
1489         case 0: /* mov to cr */
1490                 switch (cr) {
1491                 case 0:
1492                         vcpu_load_rsp_rip(vcpu);
1493                         set_cr0(vcpu, vcpu->regs[reg]);
1494                         skip_emulated_instruction(vcpu);
1495                         return 1;
1496                 case 3:
1497                         vcpu_load_rsp_rip(vcpu);
1498                         set_cr3(vcpu, vcpu->regs[reg]);
1499                         skip_emulated_instruction(vcpu);
1500                         return 1;
1501                 case 4:
1502                         vcpu_load_rsp_rip(vcpu);
1503                         set_cr4(vcpu, vcpu->regs[reg]);
1504                         skip_emulated_instruction(vcpu);
1505                         return 1;
1506                 case 8:
1507                         vcpu_load_rsp_rip(vcpu);
1508                         set_cr8(vcpu, vcpu->regs[reg]);
1509                         skip_emulated_instruction(vcpu);
1510                         return 1;
1511                 };
1512                 break;
1513         case 1: /*mov from cr*/
1514                 switch (cr) {
1515                 case 3:
1516                         vcpu_load_rsp_rip(vcpu);
1517                         vcpu->regs[reg] = vcpu->cr3;
1518                         vcpu_put_rsp_rip(vcpu);
1519                         skip_emulated_instruction(vcpu);
1520                         return 1;
1521                 case 8:
1522                         printk(KERN_DEBUG "handle_cr: read CR8 "
1523                                "cpu erratum AA15\n");
1524                         vcpu_load_rsp_rip(vcpu);
1525                         vcpu->regs[reg] = vcpu->cr8;
1526                         vcpu_put_rsp_rip(vcpu);
1527                         skip_emulated_instruction(vcpu);
1528                         return 1;
1529                 }
1530                 break;
1531         case 3: /* lmsw */
1532                 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
1533
1534                 skip_emulated_instruction(vcpu);
1535                 return 1;
1536         default:
1537                 break;
1538         }
1539         kvm_run->exit_reason = 0;
1540         printk(KERN_ERR "kvm: unhandled control register: op %d cr %d\n",
1541                (int)(exit_qualification >> 4) & 3, cr);
1542         return 0;
1543 }
1544
1545 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1546 {
1547         u64 exit_qualification;
1548         unsigned long val;
1549         int dr, reg;
1550
1551         /*
1552          * FIXME: this code assumes the host is debugging the guest.
1553          *        need to deal with guest debugging itself too.
1554          */
1555         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1556         dr = exit_qualification & 7;
1557         reg = (exit_qualification >> 8) & 15;
1558         vcpu_load_rsp_rip(vcpu);
1559         if (exit_qualification & 16) {
1560                 /* mov from dr */
1561                 switch (dr) {
1562                 case 6:
1563                         val = 0xffff0ff0;
1564                         break;
1565                 case 7:
1566                         val = 0x400;
1567                         break;
1568                 default:
1569                         val = 0;
1570                 }
1571                 vcpu->regs[reg] = val;
1572         } else {
1573                 /* mov to dr */
1574         }
1575         vcpu_put_rsp_rip(vcpu);
1576         skip_emulated_instruction(vcpu);
1577         return 1;
1578 }
1579
1580 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1581 {
1582         kvm_run->exit_reason = KVM_EXIT_CPUID;
1583         return 0;
1584 }
1585
1586 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1587 {
1588         u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1589         u64 data;
1590
1591         if (vmx_get_msr(vcpu, ecx, &data)) {
1592                 vmx_inject_gp(vcpu, 0);
1593                 return 1;
1594         }
1595
1596         /* FIXME: handling of bits 32:63 of rax, rdx */
1597         vcpu->regs[VCPU_REGS_RAX] = data & -1u;
1598         vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
1599         skip_emulated_instruction(vcpu);
1600         return 1;
1601 }
1602
1603 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1604 {
1605         u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1606         u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
1607                 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
1608
1609         if (vmx_set_msr(vcpu, ecx, data) != 0) {
1610                 vmx_inject_gp(vcpu, 0);
1611                 return 1;
1612         }
1613
1614         skip_emulated_instruction(vcpu);
1615         return 1;
1616 }
1617
1618 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
1619                                    struct kvm_run *kvm_run)
1620 {
1621         /* Turn off interrupt window reporting. */
1622         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1623                      vmcs_read32(CPU_BASED_VM_EXEC_CONTROL)
1624                      & ~CPU_BASED_VIRTUAL_INTR_PENDING);
1625         return 1;
1626 }
1627
1628 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1629 {
1630         skip_emulated_instruction(vcpu);
1631         if (vcpu->irq_summary && (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF))
1632                 return 1;
1633
1634         kvm_run->exit_reason = KVM_EXIT_HLT;
1635         return 0;
1636 }
1637
1638 /*
1639  * The exit handlers return 1 if the exit was handled fully and guest execution
1640  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
1641  * to be done to userspace and return 0.
1642  */
1643 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
1644                                       struct kvm_run *kvm_run) = {
1645         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
1646         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
1647         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
1648         [EXIT_REASON_INVLPG]                  = handle_invlpg,
1649         [EXIT_REASON_CR_ACCESS]               = handle_cr,
1650         [EXIT_REASON_DR_ACCESS]               = handle_dr,
1651         [EXIT_REASON_CPUID]                   = handle_cpuid,
1652         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
1653         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
1654         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
1655         [EXIT_REASON_HLT]                     = handle_halt,
1656 };
1657
1658 static const int kvm_vmx_max_exit_handlers =
1659         sizeof(kvm_vmx_exit_handlers) / sizeof(*kvm_vmx_exit_handlers);
1660
1661 /*
1662  * The guest has exited.  See if we can fix it or if we need userspace
1663  * assistance.
1664  */
1665 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1666 {
1667         u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1668         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
1669
1670         if ( (vectoring_info & VECTORING_INFO_VALID_MASK) &&
1671                                 exit_reason != EXIT_REASON_EXCEPTION_NMI )
1672                 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
1673                        "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
1674         kvm_run->instruction_length = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1675         if (exit_reason < kvm_vmx_max_exit_handlers
1676             && kvm_vmx_exit_handlers[exit_reason])
1677                 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
1678         else {
1679                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1680                 kvm_run->hw.hardware_exit_reason = exit_reason;
1681         }
1682         return 0;
1683 }
1684
1685 static int vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1686 {
1687         u8 fail;
1688         u16 fs_sel, gs_sel, ldt_sel;
1689         int fs_gs_ldt_reload_needed;
1690
1691 again:
1692         /*
1693          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1694          * allow segment selectors with cpl > 0 or ti == 1.
1695          */
1696         fs_sel = read_fs();
1697         gs_sel = read_gs();
1698         ldt_sel = read_ldt();
1699         fs_gs_ldt_reload_needed = (fs_sel & 7) | (gs_sel & 7) | ldt_sel;
1700         if (!fs_gs_ldt_reload_needed) {
1701                 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1702                 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1703         } else {
1704                 vmcs_write16(HOST_FS_SELECTOR, 0);
1705                 vmcs_write16(HOST_GS_SELECTOR, 0);
1706         }
1707
1708 #ifdef CONFIG_X86_64
1709         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1710         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1711 #else
1712         vmcs_writel(HOST_FS_BASE, segment_base(fs_sel));
1713         vmcs_writel(HOST_GS_BASE, segment_base(gs_sel));
1714 #endif
1715
1716         if (vcpu->irq_summary &&
1717             !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
1718                 kvm_try_inject_irq(vcpu);
1719
1720         if (vcpu->guest_debug.enabled)
1721                 kvm_guest_debug_pre(vcpu);
1722
1723         fx_save(vcpu->host_fx_image);
1724         fx_restore(vcpu->guest_fx_image);
1725
1726         save_msrs(vcpu->host_msrs, vcpu->nmsrs);
1727         load_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
1728
1729         asm (
1730                 /* Store host registers */
1731                 "pushf \n\t"
1732 #ifdef CONFIG_X86_64
1733                 "push %%rax; push %%rbx; push %%rdx;"
1734                 "push %%rsi; push %%rdi; push %%rbp;"
1735                 "push %%r8;  push %%r9;  push %%r10; push %%r11;"
1736                 "push %%r12; push %%r13; push %%r14; push %%r15;"
1737                 "push %%rcx \n\t"
1738                 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
1739 #else
1740                 "pusha; push %%ecx \n\t"
1741                 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
1742 #endif
1743                 /* Check if vmlaunch of vmresume is needed */
1744                 "cmp $0, %1 \n\t"
1745                 /* Load guest registers.  Don't clobber flags. */
1746 #ifdef CONFIG_X86_64
1747                 "mov %c[cr2](%3), %%rax \n\t"
1748                 "mov %%rax, %%cr2 \n\t"
1749                 "mov %c[rax](%3), %%rax \n\t"
1750                 "mov %c[rbx](%3), %%rbx \n\t"
1751                 "mov %c[rdx](%3), %%rdx \n\t"
1752                 "mov %c[rsi](%3), %%rsi \n\t"
1753                 "mov %c[rdi](%3), %%rdi \n\t"
1754                 "mov %c[rbp](%3), %%rbp \n\t"
1755                 "mov %c[r8](%3),  %%r8  \n\t"
1756                 "mov %c[r9](%3),  %%r9  \n\t"
1757                 "mov %c[r10](%3), %%r10 \n\t"
1758                 "mov %c[r11](%3), %%r11 \n\t"
1759                 "mov %c[r12](%3), %%r12 \n\t"
1760                 "mov %c[r13](%3), %%r13 \n\t"
1761                 "mov %c[r14](%3), %%r14 \n\t"
1762                 "mov %c[r15](%3), %%r15 \n\t"
1763                 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
1764 #else
1765                 "mov %c[cr2](%3), %%eax \n\t"
1766                 "mov %%eax,   %%cr2 \n\t"
1767                 "mov %c[rax](%3), %%eax \n\t"
1768                 "mov %c[rbx](%3), %%ebx \n\t"
1769                 "mov %c[rdx](%3), %%edx \n\t"
1770                 "mov %c[rsi](%3), %%esi \n\t"
1771                 "mov %c[rdi](%3), %%edi \n\t"
1772                 "mov %c[rbp](%3), %%ebp \n\t"
1773                 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
1774 #endif
1775                 /* Enter guest mode */
1776                 "jne launched \n\t"
1777                 ASM_VMX_VMLAUNCH "\n\t"
1778                 "jmp kvm_vmx_return \n\t"
1779                 "launched: " ASM_VMX_VMRESUME "\n\t"
1780                 ".globl kvm_vmx_return \n\t"
1781                 "kvm_vmx_return: "
1782                 /* Save guest registers, load host registers, keep flags */
1783 #ifdef CONFIG_X86_64
1784                 "xchg %3,     0(%%rsp) \n\t"
1785                 "mov %%rax, %c[rax](%3) \n\t"
1786                 "mov %%rbx, %c[rbx](%3) \n\t"
1787                 "pushq 0(%%rsp); popq %c[rcx](%3) \n\t"
1788                 "mov %%rdx, %c[rdx](%3) \n\t"
1789                 "mov %%rsi, %c[rsi](%3) \n\t"
1790                 "mov %%rdi, %c[rdi](%3) \n\t"
1791                 "mov %%rbp, %c[rbp](%3) \n\t"
1792                 "mov %%r8,  %c[r8](%3) \n\t"
1793                 "mov %%r9,  %c[r9](%3) \n\t"
1794                 "mov %%r10, %c[r10](%3) \n\t"
1795                 "mov %%r11, %c[r11](%3) \n\t"
1796                 "mov %%r12, %c[r12](%3) \n\t"
1797                 "mov %%r13, %c[r13](%3) \n\t"
1798                 "mov %%r14, %c[r14](%3) \n\t"
1799                 "mov %%r15, %c[r15](%3) \n\t"
1800                 "mov %%cr2, %%rax   \n\t"
1801                 "mov %%rax, %c[cr2](%3) \n\t"
1802                 "mov 0(%%rsp), %3 \n\t"
1803
1804                 "pop  %%rcx; pop  %%r15; pop  %%r14; pop  %%r13; pop  %%r12;"
1805                 "pop  %%r11; pop  %%r10; pop  %%r9;  pop  %%r8;"
1806                 "pop  %%rbp; pop  %%rdi; pop  %%rsi;"
1807                 "pop  %%rdx; pop  %%rbx; pop  %%rax \n\t"
1808 #else
1809                 "xchg %3, 0(%%esp) \n\t"
1810                 "mov %%eax, %c[rax](%3) \n\t"
1811                 "mov %%ebx, %c[rbx](%3) \n\t"
1812                 "pushl 0(%%esp); popl %c[rcx](%3) \n\t"
1813                 "mov %%edx, %c[rdx](%3) \n\t"
1814                 "mov %%esi, %c[rsi](%3) \n\t"
1815                 "mov %%edi, %c[rdi](%3) \n\t"
1816                 "mov %%ebp, %c[rbp](%3) \n\t"
1817                 "mov %%cr2, %%eax  \n\t"
1818                 "mov %%eax, %c[cr2](%3) \n\t"
1819                 "mov 0(%%esp), %3 \n\t"
1820
1821                 "pop %%ecx; popa \n\t"
1822 #endif
1823                 "setbe %0 \n\t"
1824                 "popf \n\t"
1825               : "=g" (fail)
1826               : "r"(vcpu->launched), "d"((unsigned long)HOST_RSP),
1827                 "c"(vcpu),
1828                 [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])),
1829                 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
1830                 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
1831                 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
1832                 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
1833                 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
1834                 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])),
1835 #ifdef CONFIG_X86_64
1836                 [r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
1837                 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
1838                 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
1839                 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
1840                 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
1841                 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
1842                 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
1843                 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])),
1844 #endif
1845                 [cr2]"i"(offsetof(struct kvm_vcpu, cr2))
1846               : "cc", "memory" );
1847
1848         ++kvm_stat.exits;
1849
1850         save_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
1851         load_msrs(vcpu->host_msrs, NR_BAD_MSRS);
1852
1853         fx_save(vcpu->guest_fx_image);
1854         fx_restore(vcpu->host_fx_image);
1855
1856 #ifndef CONFIG_X86_64
1857         asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
1858 #endif
1859
1860         kvm_run->exit_type = 0;
1861         if (fail) {
1862                 kvm_run->exit_type = KVM_EXIT_TYPE_FAIL_ENTRY;
1863                 kvm_run->exit_reason = vmcs_read32(VM_INSTRUCTION_ERROR);
1864         } else {
1865                 if (fs_gs_ldt_reload_needed) {
1866                         load_ldt(ldt_sel);
1867                         load_fs(fs_sel);
1868                         /*
1869                          * If we have to reload gs, we must take care to
1870                          * preserve our gs base.
1871                          */
1872                         local_irq_disable();
1873                         load_gs(gs_sel);
1874 #ifdef CONFIG_X86_64
1875                         wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
1876 #endif
1877                         local_irq_enable();
1878
1879                         reload_tss();
1880                 }
1881                 vcpu->launched = 1;
1882                 kvm_run->exit_type = KVM_EXIT_TYPE_VM_EXIT;
1883                 if (kvm_handle_exit(kvm_run, vcpu)) {
1884                         /* Give scheduler a change to reschedule. */
1885                         if (signal_pending(current)) {
1886                                 ++kvm_stat.signal_exits;
1887                                 return -EINTR;
1888                         }
1889                         kvm_resched(vcpu);
1890                         goto again;
1891                 }
1892         }
1893         return 0;
1894 }
1895
1896 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1897 {
1898         vmcs_writel(GUEST_CR3, vmcs_readl(GUEST_CR3));
1899 }
1900
1901 static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
1902                                   unsigned long addr,
1903                                   u32 err_code)
1904 {
1905         u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1906
1907         ++kvm_stat.pf_guest;
1908
1909         if (is_page_fault(vect_info)) {
1910                 printk(KERN_DEBUG "inject_page_fault: "
1911                        "double fault 0x%lx @ 0x%lx\n",
1912                        addr, vmcs_readl(GUEST_RIP));
1913                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
1914                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1915                              DF_VECTOR |
1916                              INTR_TYPE_EXCEPTION |
1917                              INTR_INFO_DELIEVER_CODE_MASK |
1918                              INTR_INFO_VALID_MASK);
1919                 return;
1920         }
1921         vcpu->cr2 = addr;
1922         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
1923         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1924                      PF_VECTOR |
1925                      INTR_TYPE_EXCEPTION |
1926                      INTR_INFO_DELIEVER_CODE_MASK |
1927                      INTR_INFO_VALID_MASK);
1928
1929 }
1930
1931 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
1932 {
1933         if (vcpu->vmcs) {
1934                 on_each_cpu(__vcpu_clear, vcpu, 0, 1);
1935                 free_vmcs(vcpu->vmcs);
1936                 vcpu->vmcs = NULL;
1937         }
1938 }
1939
1940 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
1941 {
1942         vmx_free_vmcs(vcpu);
1943 }
1944
1945 static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
1946 {
1947         struct vmcs *vmcs;
1948
1949         vmcs = alloc_vmcs();
1950         if (!vmcs)
1951                 return -ENOMEM;
1952         vmcs_clear(vmcs);
1953         vcpu->vmcs = vmcs;
1954         vcpu->launched = 0;
1955         return 0;
1956 }
1957
1958 static struct kvm_arch_ops vmx_arch_ops = {
1959         .cpu_has_kvm_support = cpu_has_kvm_support,
1960         .disabled_by_bios = vmx_disabled_by_bios,
1961         .hardware_setup = hardware_setup,
1962         .hardware_unsetup = hardware_unsetup,
1963         .hardware_enable = hardware_enable,
1964         .hardware_disable = hardware_disable,
1965
1966         .vcpu_create = vmx_create_vcpu,
1967         .vcpu_free = vmx_free_vcpu,
1968
1969         .vcpu_load = vmx_vcpu_load,
1970         .vcpu_put = vmx_vcpu_put,
1971
1972         .set_guest_debug = set_guest_debug,
1973         .get_msr = vmx_get_msr,
1974         .set_msr = vmx_set_msr,
1975         .get_segment_base = vmx_get_segment_base,
1976         .get_segment = vmx_get_segment,
1977         .set_segment = vmx_set_segment,
1978         .is_long_mode = vmx_is_long_mode,
1979         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
1980         .set_cr0 = vmx_set_cr0,
1981         .set_cr0_no_modeswitch = vmx_set_cr0_no_modeswitch,
1982         .set_cr3 = vmx_set_cr3,
1983         .set_cr4 = vmx_set_cr4,
1984 #ifdef CONFIG_X86_64
1985         .set_efer = vmx_set_efer,
1986 #endif
1987         .get_idt = vmx_get_idt,
1988         .set_idt = vmx_set_idt,
1989         .get_gdt = vmx_get_gdt,
1990         .set_gdt = vmx_set_gdt,
1991         .cache_regs = vcpu_load_rsp_rip,
1992         .decache_regs = vcpu_put_rsp_rip,
1993         .get_rflags = vmx_get_rflags,
1994         .set_rflags = vmx_set_rflags,
1995
1996         .tlb_flush = vmx_flush_tlb,
1997         .inject_page_fault = vmx_inject_page_fault,
1998
1999         .inject_gp = vmx_inject_gp,
2000
2001         .run = vmx_vcpu_run,
2002         .skip_emulated_instruction = skip_emulated_instruction,
2003         .vcpu_setup = vmx_vcpu_setup,
2004 };
2005
2006 static int __init vmx_init(void)
2007 {
2008         return kvm_init_arch(&vmx_arch_ops, THIS_MODULE);
2009 }
2010
2011 static void __exit vmx_exit(void)
2012 {
2013         kvm_exit_arch();
2014 }
2015
2016 module_init(vmx_init)
2017 module_exit(vmx_exit)