Revert "Merge commit 'main-jb-2012.08.03-B4' into t114-0806"
[linux-2.6.git] / drivers / iommu / tegra-smmu.c
1 /*
2  * IOMMU API for SMMU in Tegra30
3  *
4  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along with
16  * this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18  */
19
20 #define pr_fmt(fmt)     "%s(): " fmt, __func__
21
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/spinlock.h>
25 #include <linux/slab.h>
26 #include <linux/vmalloc.h>
27 #include <linux/mm.h>
28 #include <linux/pagemap.h>
29 #include <linux/device.h>
30 #include <linux/sched.h>
31 #include <linux/iommu.h>
32 #include <linux/io.h>
33 #include <linux/of.h>
34 #include <linux/of_iommu.h>
35 #include <linux/debugfs.h>
36 #include <linux/seq_file.h>
37
38 #include <asm/page.h>
39 #include <asm/cacheflush.h>
40
41 #include <mach/iomap.h>
42 #include <mach/smmu.h>
43 #include <mach/tegra_smmu.h>
44
45 /* REVISIT: With new configurations for t114/124/148 passed from DT */
46 #define SKIP_SWGRP_CHECK
47
48 /* bitmap of the page sizes currently supported */
49 #define SMMU_IOMMU_PGSIZES      (SZ_4K)
50
51 #define SMMU_CONFIG                             0x10
52 #define SMMU_CONFIG_DISABLE                     0
53 #define SMMU_CONFIG_ENABLE                      1
54
55 /* REVISIT: To support multiple MCs */
56 enum {
57         _MC = 0,
58 };
59
60 enum {
61         _TLB = 0,
62         _PTC,
63 };
64
65 #define SMMU_CACHE_CONFIG_BASE                  0x14
66 #define __SMMU_CACHE_CONFIG(mc, cache)          (SMMU_CACHE_CONFIG_BASE + 4 * cache)
67 #define SMMU_CACHE_CONFIG(cache)                __SMMU_CACHE_CONFIG(_MC, cache)
68
69 #define SMMU_CACHE_CONFIG_STATS_SHIFT           31
70 #define SMMU_CACHE_CONFIG_STATS_MASK            (1 << SMMU_CACHE_CONFIG_STATS_SHIFT)
71 #define SMMU_CACHE_CONFIG_STATS_ENABLE          (1 << SMMU_CACHE_CONFIG_STATS_SHIFT)
72 #define SMMU_CACHE_CONFIG_STATS_TEST_SHIFT      30
73 #define SMMU_CACHE_CONFIG_STATS_TEST_MASK       (1 << SMMU_CACHE_CONFIG_STATS_TEST_SHIFT)
74 #define SMMU_CACHE_CONFIG_STATS_TEST            (1 << SMMU_CACHE_CONFIG_STATS_TEST_SHIFT)
75
76 #define SMMU_TLB_CONFIG_HIT_UNDER_MISS__ENABLE  (1 << 29)
77 #define SMMU_TLB_CONFIG_ACTIVE_LINES__VALUE     0x10
78 #define SMMU_TLB_CONFIG_RESET_VAL               0x20000010
79
80 #define SMMU_PTC_CONFIG_CACHE__ENABLE           (1 << 29)
81 #define SMMU_PTC_CONFIG_INDEX_MAP__PATTERN      0x3f
82 #define SMMU_PTC_CONFIG_RESET_VAL               0x2000003f
83
84 #define SMMU_PTB_ASID                           0x1c
85 #define SMMU_PTB_ASID_CURRENT_SHIFT             0
86
87 #define SMMU_PTB_DATA                           0x20
88 #define SMMU_PTB_DATA_RESET_VAL                 0
89 #define SMMU_PTB_DATA_ASID_NONSECURE_SHIFT      29
90 #define SMMU_PTB_DATA_ASID_WRITABLE_SHIFT       30
91 #define SMMU_PTB_DATA_ASID_READABLE_SHIFT       31
92
93 #define SMMU_TLB_FLUSH                          0x30
94 #define SMMU_TLB_FLUSH_VA_MATCH_ALL             0
95 #define SMMU_TLB_FLUSH_VA_MATCH_SECTION         2
96 #define SMMU_TLB_FLUSH_VA_MATCH_GROUP           3
97 #define SMMU_TLB_FLUSH_ASID_SHIFT               29
98 #define SMMU_TLB_FLUSH_ASID_MATCH_DISABLE       0
99 #define SMMU_TLB_FLUSH_ASID_MATCH_ENABLE        1
100 #define SMMU_TLB_FLUSH_ASID_MATCH_SHIFT         31
101
102 #define SMMU_PTC_FLUSH                          0x34
103 #define SMMU_PTC_FLUSH_TYPE_ALL                 0
104 #define SMMU_PTC_FLUSH_TYPE_ADR                 1
105 #define SMMU_PTC_FLUSH_ADR_SHIFT                4
106
107 #define SMMU_ASID_SECURITY                      0x38
108
109 #define SMMU_STATS_CACHE_COUNT_BASE             0x1f0
110
111 #define SMMU_STATS_CACHE_COUNT(mc, cache, hitmiss)              \
112         (SMMU_STATS_CACHE_COUNT_BASE + 8 * cache + 4 * hitmiss)
113
114 #define SMMU_TRANSLATION_ENABLE_0               0x228
115 #define SMMU_TRANSLATION_ENABLE_1               0x22c
116 #define SMMU_TRANSLATION_ENABLE_2               0x230
117
118 #define SMMU_AFI_ASID   0x238   /* PCIE */
119 #define SMMU_AVPC_ASID  0x23c   /* AVP */
120 #define SMMU_DC_ASID    0x240   /* Display controller */
121 #define SMMU_DCB_ASID   0x244   /* Display controller B */
122 #define SMMU_EPP_ASID   0x248   /* Encoder pre-processor */
123 #define SMMU_G2_ASID    0x24c   /* 2D engine */
124 #define SMMU_HC_ASID    0x250   /* Host1x */
125 #define SMMU_HDA_ASID   0x254   /* High-def audio */
126 #define SMMU_ISP_ASID   0x258   /* Image signal processor */
127 #define SMMU_MPE_ASID   0x264   /* MPEG encoder */
128 #define SMMU_NV_ASID    0x268   /* (3D) */
129 #define SMMU_NV2_ASID   0x26c   /* (3D) */
130 #define SMMU_PPCS_ASID  0x270   /* AHB */
131 #define SMMU_SATA_ASID  0x278   /* SATA */
132 #define SMMU_VDE_ASID   0x27c   /* Video decoder */
133 #define SMMU_VI_ASID    0x280   /* Video input */
134
135 #define SMMU_PDE_NEXT_SHIFT             28
136
137 /* AHB Arbiter Registers */
138 #define AHB_XBAR_CTRL                           0xe0
139 #define AHB_XBAR_CTRL_SMMU_INIT_DONE_DONE       1
140 #define AHB_XBAR_CTRL_SMMU_INIT_DONE_SHIFT      17
141
142 #define SMMU_NUM_ASIDS                          4
143 #define SMMU_TLB_FLUSH_VA_SECTION__MASK         0xffc00000
144 #define SMMU_TLB_FLUSH_VA_SECTION__SHIFT        12 /* right shift */
145 #define SMMU_TLB_FLUSH_VA_GROUP__MASK           0xffffc000
146 #define SMMU_TLB_FLUSH_VA_GROUP__SHIFT          12 /* right shift */
147 #define SMMU_TLB_FLUSH_VA(iova, which)  \
148         ((((iova) & SMMU_TLB_FLUSH_VA_##which##__MASK) >> \
149                 SMMU_TLB_FLUSH_VA_##which##__SHIFT) |   \
150         SMMU_TLB_FLUSH_VA_MATCH_##which)
151 #define SMMU_PTB_ASID_CUR(n)    \
152                 ((n) << SMMU_PTB_ASID_CURRENT_SHIFT)
153 #define SMMU_TLB_FLUSH_ASID_MATCH_disable               \
154                 (SMMU_TLB_FLUSH_ASID_MATCH_DISABLE <<   \
155                         SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
156 #define SMMU_TLB_FLUSH_ASID_MATCH__ENABLE               \
157                 (SMMU_TLB_FLUSH_ASID_MATCH_ENABLE <<    \
158                         SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
159
160 #define SMMU_PAGE_SHIFT 12
161 #define SMMU_PAGE_SIZE  (1 << SMMU_PAGE_SHIFT)
162
163 #define SMMU_PDIR_COUNT 1024
164 #define SMMU_PDIR_SIZE  (sizeof(unsigned long) * SMMU_PDIR_COUNT)
165 #define SMMU_PTBL_COUNT 1024
166 #define SMMU_PTBL_SIZE  (sizeof(unsigned long) * SMMU_PTBL_COUNT)
167 #define SMMU_PDIR_SHIFT 12
168 #define SMMU_PDE_SHIFT  12
169 #define SMMU_PTE_SHIFT  12
170 #define SMMU_PFN_MASK   0x000fffff
171
172 #define SMMU_ADDR_TO_PFN(addr)  ((addr) >> 12)
173 #define SMMU_ADDR_TO_PDN(addr)  ((addr) >> 22)
174 #define SMMU_PDN_TO_ADDR(addr)  ((pdn) << 22)
175
176 #define _READABLE       (1 << SMMU_PTB_DATA_ASID_READABLE_SHIFT)
177 #define _WRITABLE       (1 << SMMU_PTB_DATA_ASID_WRITABLE_SHIFT)
178 #define _NONSECURE      (1 << SMMU_PTB_DATA_ASID_NONSECURE_SHIFT)
179 #define _PDE_NEXT       (1 << SMMU_PDE_NEXT_SHIFT)
180 #define _MASK_ATTR      (_READABLE | _WRITABLE | _NONSECURE)
181
182 #define _PDIR_ATTR      (_READABLE | _WRITABLE | _NONSECURE)
183
184 #define _PDE_ATTR       (_READABLE | _WRITABLE | _NONSECURE)
185 #define _PDE_ATTR_N     (_PDE_ATTR | _PDE_NEXT)
186 #define _PDE_VACANT(pdn)        (0)
187
188 #define _PTE_ATTR       (_READABLE | _WRITABLE | _NONSECURE)
189 #define _PTE_VACANT(addr)       (0)
190
191 #ifdef  CONFIG_TEGRA_IOMMU_SMMU_LINEAR
192 #undef  _PDE_VACANT(pdn)
193 #undef  _PTE_VACANT(addr)
194 #define _PDE_VACANT(pdn)        (((pdn) << 10) | _PDE_ATTR)
195 #define _PTE_VACANT(addr)       (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR)
196 #endif
197
198 #define SMMU_MK_PDIR(page, attr)        \
199                 ((page_to_phys(page) >> SMMU_PDIR_SHIFT) | (attr))
200 #define SMMU_MK_PDE(page, attr)         \
201                 (unsigned long)((page_to_phys(page) >> SMMU_PDE_SHIFT) | (attr))
202 #define SMMU_EX_PTBL_PAGE(pde)          \
203                 pfn_to_page((unsigned long)(pde) & SMMU_PFN_MASK)
204 #define SMMU_PFN_TO_PTE(pfn, attr)      (unsigned long)((pfn) | (attr))
205
206 #define SMMU_ASID_ENABLE(asid)  ((asid) | (1 << 31))
207 #define SMMU_ASID_DISABLE       0
208 #define SMMU_ASID_ASID(n)       ((n) & ~SMMU_ASID_ENABLE(0))
209
210 #define smmu_client_enable_hwgrp(c, m)  smmu_client_set_hwgrp(c, m, 1)
211 #define smmu_client_disable_hwgrp(c)    smmu_client_set_hwgrp(c, 0, 0)
212 #define __smmu_client_enable_hwgrp(c, m) __smmu_client_set_hwgrp(c, m, 1)
213 #define __smmu_client_disable_hwgrp(c)  __smmu_client_set_hwgrp(c, 0, 0)
214
215 #define HWGRP_INIT(client) [HWGRP_##client] = SMMU_##client##_ASID
216
217 static const u32 smmu_hwgrp_asid_reg[] = {
218         HWGRP_INIT(AFI),
219         HWGRP_INIT(AVPC),
220         HWGRP_INIT(DC),
221         HWGRP_INIT(DCB),
222         HWGRP_INIT(EPP),
223         HWGRP_INIT(G2),
224         HWGRP_INIT(HC),
225         HWGRP_INIT(HDA),
226         HWGRP_INIT(ISP),
227         HWGRP_INIT(MPE),
228         HWGRP_INIT(NV),
229         HWGRP_INIT(NV2),
230         HWGRP_INIT(PPCS),
231         HWGRP_INIT(SATA),
232         HWGRP_INIT(VDE),
233         HWGRP_INIT(VI),
234 };
235 #define HWGRP_ASID_REG(x) (smmu_hwgrp_asid_reg[x])
236
237 /*
238  * Per client for address space
239  */
240 struct smmu_client {
241         struct device           *dev;
242         struct list_head        list;
243         struct smmu_as          *as;
244         u32                     hwgrp;
245 };
246
247 /*
248  * Per address space
249  */
250 struct smmu_as {
251         struct smmu_device      *smmu;  /* back pointer to container */
252         unsigned int            asid;
253         spinlock_t              lock;   /* for pagetable */
254         struct page             *pdir_page;
255         unsigned long           pdir_attr;
256         unsigned long           pde_attr;
257         unsigned long           pte_attr;
258         unsigned int            *pte_count;
259
260         struct list_head        client;
261         spinlock_t              client_lock; /* for client list */
262 };
263
264 /*
265  * Per SMMU device - IOMMU device
266  */
267 struct smmu_device {
268         void __iomem    *regs, *regs_ahbarb;
269         unsigned long   iovmm_base;     /* remappable base address */
270         unsigned long   page_count;     /* total remappable size */
271         spinlock_t      lock;
272         char            *name;
273         struct device   *dev;
274         int             num_as;
275         struct smmu_as  *as;            /* Run-time allocated array */
276         struct page *avp_vector_page;   /* dummy page shared by all AS's */
277
278         /*
279          * Register image savers for suspend/resume
280          */
281         unsigned long translation_enable_0;
282         unsigned long translation_enable_1;
283         unsigned long translation_enable_2;
284         unsigned long asid_security;
285
286         struct dentry *debugfs_root;
287
288         struct device_node *ahb;
289
290         int             num_as;
291         struct smmu_as  as[0];          /* Run-time allocated array */
292 };
293
294 static struct smmu_device *smmu_handle; /* unique for a system */
295
296 /*
297  *      SMMU/AHB register accessors
298  */
299 static inline u32 smmu_read(struct smmu_device *smmu, size_t offs)
300 {
301         return readl(smmu->regs + offs);
302 }
303 static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs)
304 {
305         writel(val, smmu->regs + offs);
306 }
307
308 static inline u32 ahb_read(struct smmu_device *smmu, size_t offs)
309 {
310         return readl(smmu->regs_ahbarb + offs);
311 }
312 static inline void ahb_write(struct smmu_device *smmu, u32 val, size_t offs)
313 {
314         writel(val, smmu->regs_ahbarb + offs);
315 }
316
317 #define VA_PAGE_TO_PA(va, page) \
318         (page_to_phys(page) + ((unsigned long)(va) & ~PAGE_MASK))
319
320 #define FLUSH_CPU_DCACHE(va, page, size)        \
321         do {    \
322                 unsigned long _pa_ = VA_PAGE_TO_PA(va, page);           \
323                 __cpuc_flush_dcache_area((void *)(va), (size_t)(size)); \
324                 outer_flush_range(_pa_, _pa_+(size_t)(size));           \
325         } while (0)
326
327 /*
328  * Any interaction between any block on PPSB and a block on APB or AHB
329  * must have these read-back barriers to ensure the APB/AHB bus
330  * transaction is complete before initiating activity on the PPSB
331  * block.
332  */
333 #define FLUSH_SMMU_REGS(smmu)   smmu_read(smmu, SMMU_CONFIG)
334
335 #define smmu_client_hwgrp(c) (u32)((c)->dev->platform_data)
336
337 static int __smmu_client_set_hwgrp(struct smmu_client *c,
338                                    unsigned long map, int on)
339 {
340         int i;
341         struct smmu_as *as = c->as;
342         u32 val, offs, mask = SMMU_ASID_ENABLE(as->asid);
343         struct smmu_device *smmu = as->smmu;
344
345         WARN_ON(!on && map);
346         if (on && !map)
347                 return -EINVAL;
348         if (!on)
349                 map = smmu_client_hwgrp(c);
350
351         for_each_set_bit(i, &map, HWGRP_COUNT) {
352                 offs = HWGRP_ASID_REG(i);
353                 val = smmu_read(smmu, offs);
354                 if (on) {
355 #if !defined(SKIP_SWGRP_CHECK)
356                         if (WARN_ON(val & mask))
357                                 goto err_hw_busy;
358 #endif
359                         val |= mask;
360                 } else {
361 #if !defined(SKIP_SWGRP_CHECK)
362                         WARN_ON((val & mask) == mask);
363 #endif
364                         val &= ~mask;
365                 }
366                 smmu_write(smmu, val, offs);
367         }
368         FLUSH_SMMU_REGS(smmu);
369         c->hwgrp = map;
370         return 0;
371
372 err_hw_busy:
373         for_each_set_bit(i, &map, HWGRP_COUNT) {
374                 offs = HWGRP_ASID_REG(i);
375                 val = smmu_read(smmu, offs);
376                 val &= ~mask;
377                 smmu_write(smmu, val, offs);
378         }
379         return -EBUSY;
380 }
381
382 static int smmu_client_set_hwgrp(struct smmu_client *c, u32 map, int on)
383 {
384         u32 val;
385         unsigned long flags;
386         struct smmu_as *as = c->as;
387         struct smmu_device *smmu = as->smmu;
388
389         spin_lock_irqsave(&smmu->lock, flags);
390         val = __smmu_client_set_hwgrp(c, map, on);
391         spin_unlock_irqrestore(&smmu->lock, flags);
392         return val;
393 }
394
395 /*
396  * Flush all TLB entries and all PTC entries
397  * Caller must lock smmu
398  */
399 static void smmu_flush_regs(struct smmu_device *smmu, int enable)
400 {
401         u32 val;
402
403         smmu_write(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH);
404         FLUSH_SMMU_REGS(smmu);
405         val = SMMU_TLB_FLUSH_VA_MATCH_ALL |
406                 SMMU_TLB_FLUSH_ASID_MATCH_disable;
407         smmu_write(smmu, val, SMMU_TLB_FLUSH);
408
409         if (enable)
410                 smmu_write(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG);
411         FLUSH_SMMU_REGS(smmu);
412 }
413
414 static void smmu_setup_regs(struct smmu_device *smmu)
415 {
416         int i;
417         u32 val;
418
419         for (i = 0; i < smmu->num_as; i++) {
420                 struct smmu_as *as = &smmu->as[i];
421                 struct smmu_client *c;
422
423                 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
424                 val = as->pdir_page ?
425                         SMMU_MK_PDIR(as->pdir_page, as->pdir_attr) :
426                         SMMU_PTB_DATA_RESET_VAL;
427                 smmu_write(smmu, val, SMMU_PTB_DATA);
428
429                 list_for_each_entry(c, &as->client, list)
430                         __smmu_client_set_hwgrp(c, c->hwgrp, 1);
431         }
432
433         smmu_write(smmu, smmu->translation_enable_0, SMMU_TRANSLATION_ENABLE_0);
434         smmu_write(smmu, smmu->translation_enable_1, SMMU_TRANSLATION_ENABLE_1);
435         smmu_write(smmu, smmu->translation_enable_2, SMMU_TRANSLATION_ENABLE_2);
436         smmu_write(smmu, smmu->asid_security, SMMU_ASID_SECURITY);
437         smmu_write(smmu, SMMU_TLB_CONFIG_RESET_VAL, SMMU_CACHE_CONFIG(_TLB));
438         smmu_write(smmu, SMMU_PTC_CONFIG_RESET_VAL, SMMU_CACHE_CONFIG(_PTC));
439
440         smmu_flush_regs(smmu, 1);
441
442         val = ahb_read(smmu, AHB_XBAR_CTRL);
443         val |= AHB_XBAR_CTRL_SMMU_INIT_DONE_DONE <<
444                 AHB_XBAR_CTRL_SMMU_INIT_DONE_SHIFT;
445         ahb_write(smmu, val, AHB_XBAR_CTRL);
446 }
447
448 static void flush_ptc_and_tlb(struct smmu_device *smmu,
449                       struct smmu_as *as, dma_addr_t iova,
450                       unsigned long *pte, struct page *page, int is_pde)
451 {
452         u32 val;
453         unsigned long tlb_flush_va = is_pde
454                 ?  SMMU_TLB_FLUSH_VA(iova, SECTION)
455                 :  SMMU_TLB_FLUSH_VA(iova, GROUP);
456
457         val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pte, page);
458         smmu_write(smmu, val, SMMU_PTC_FLUSH);
459         FLUSH_SMMU_REGS(smmu);
460         val = tlb_flush_va |
461                 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE |
462                 (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT);
463         smmu_write(smmu, val, SMMU_TLB_FLUSH);
464         FLUSH_SMMU_REGS(smmu);
465 }
466
467 static void free_ptbl(struct smmu_as *as, dma_addr_t iova)
468 {
469         unsigned long pdn = SMMU_ADDR_TO_PDN(iova);
470         unsigned long *pdir = (unsigned long *)page_address(as->pdir_page);
471
472         if (pdir[pdn] != _PDE_VACANT(pdn)) {
473                 dev_dbg(as->smmu->dev, "pdn: %lx\n", pdn);
474
475                 ClearPageReserved(SMMU_EX_PTBL_PAGE(pdir[pdn]));
476                 __free_page(SMMU_EX_PTBL_PAGE(pdir[pdn]));
477                 pdir[pdn] = _PDE_VACANT(pdn);
478                 FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]);
479                 flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn],
480                                   as->pdir_page, 1);
481         }
482 }
483
484 static void free_pdir(struct smmu_as *as)
485 {
486         unsigned addr;
487         int count;
488         struct device *dev = as->smmu->dev;
489
490         if (!as->pdir_page)
491                 return;
492
493         addr = as->smmu->iovmm_base;
494         count = as->smmu->page_count;
495         while (count-- > 0) {
496                 free_ptbl(as, addr);
497                 addr += SMMU_PAGE_SIZE * SMMU_PTBL_COUNT;
498         }
499         ClearPageReserved(as->pdir_page);
500         __free_page(as->pdir_page);
501         as->pdir_page = NULL;
502         devm_kfree(dev, as->pte_count);
503         as->pte_count = NULL;
504 }
505
506 /*
507  * Maps PTBL for given iova and returns the PTE address
508  * Caller must unmap the mapped PTBL returned in *ptbl_page_p
509  */
510 static unsigned long *locate_pte(struct smmu_as *as,
511                                  dma_addr_t iova, bool allocate,
512                                  struct page **ptbl_page_p,
513                                  unsigned int **count)
514 {
515         unsigned long ptn = SMMU_ADDR_TO_PFN(iova);
516         unsigned long pdn = SMMU_ADDR_TO_PDN(iova);
517         unsigned long *pdir = page_address(as->pdir_page);
518         unsigned long *ptbl;
519
520         if (pdir[pdn] != _PDE_VACANT(pdn)) {
521                 /* Mapped entry table already exists */
522                 *ptbl_page_p = SMMU_EX_PTBL_PAGE(pdir[pdn]);
523                 ptbl = page_address(*ptbl_page_p);
524         } else if (!allocate) {
525                 return NULL;
526         } else {
527                 int pn;
528                 unsigned long addr = SMMU_PDN_TO_ADDR(pdn);
529
530                 /* Vacant - allocate a new page table */
531                 dev_dbg(as->smmu->dev, "New PTBL pdn: %lx\n", pdn);
532
533                 *ptbl_page_p = alloc_page(GFP_ATOMIC);
534                 if (!*ptbl_page_p) {
535                         dev_err(as->smmu->dev,
536                                 "failed to allocate smmu_device page table\n");
537                         return NULL;
538                 }
539                 SetPageReserved(*ptbl_page_p);
540                 ptbl = (unsigned long *)page_address(*ptbl_page_p);
541                 for (pn = 0; pn < SMMU_PTBL_COUNT;
542                      pn++, addr += SMMU_PAGE_SIZE) {
543                         ptbl[pn] = _PTE_VACANT(addr);
544                 }
545                 FLUSH_CPU_DCACHE(ptbl, *ptbl_page_p, SMMU_PTBL_SIZE);
546                 pdir[pdn] = SMMU_MK_PDE(*ptbl_page_p,
547                                         as->pde_attr | _PDE_NEXT);
548                 FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]);
549                 flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn],
550                                   as->pdir_page, 1);
551         }
552         *count = &as->pte_count[pdn];
553
554         return &ptbl[ptn % SMMU_PTBL_COUNT];
555 }
556
557 #ifdef CONFIG_SMMU_SIG_DEBUG
558 static void put_signature(struct smmu_as *as,
559                           dma_addr_t iova, unsigned long pfn)
560 {
561         struct page *page;
562         unsigned long *vaddr;
563
564         page = pfn_to_page(pfn);
565         vaddr = page_address(page);
566         if (!vaddr)
567                 return;
568
569         vaddr[0] = iova;
570         vaddr[1] = pfn << PAGE_SHIFT;
571         FLUSH_CPU_DCACHE(vaddr, page, sizeof(vaddr[0]) * 2);
572 }
573 #else
574 static inline void put_signature(struct smmu_as *as,
575                                  unsigned long addr, unsigned long pfn)
576 {
577 }
578 #endif
579
580 /*
581  * Caller must not hold as->lock
582  */
583 static int alloc_pdir(struct smmu_as *as)
584 {
585         unsigned long *pdir, flags;
586         int pdn, err = 0;
587         u32 val;
588         struct smmu_device *smmu = as->smmu;
589         struct page *page;
590         unsigned int *cnt;
591
592         /*
593          * do the allocation outside the as lock
594          */
595         cnt = devm_kzalloc(smmu->dev,
596                            sizeof(cnt[0]) * SMMU_PDIR_COUNT, GFP_KERNEL);
597         page = alloc_page(GFP_KERNEL | __GFP_DMA);
598
599         spin_lock_irqsave(&as->lock, flags);
600
601         if (as->pdir_page) {
602                 /* We raced, free the redundant */
603                 err = -EAGAIN;
604                 goto err_out;
605         }
606
607         if (!page || !cnt) {
608                 dev_err(smmu->dev, "failed to allocate at %s\n", __func__);
609                 err = -ENOMEM;
610                 goto err_out;
611         }
612
613         as->pdir_page = page;
614         as->pte_count = cnt;
615
616         SetPageReserved(as->pdir_page);
617         pdir = page_address(as->pdir_page);
618
619         for (pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++)
620                 pdir[pdn] = _PDE_VACANT(pdn);
621         FLUSH_CPU_DCACHE(pdir, as->pdir_page, SMMU_PDIR_SIZE);
622         val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pdir, as->pdir_page);
623         smmu_write(smmu, val, SMMU_PTC_FLUSH);
624         FLUSH_SMMU_REGS(as->smmu);
625         val = SMMU_TLB_FLUSH_VA_MATCH_ALL |
626                 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE |
627                 (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT);
628         smmu_write(smmu, val, SMMU_TLB_FLUSH);
629         FLUSH_SMMU_REGS(as->smmu);
630
631         spin_unlock_irqrestore(&as->lock, flags);
632
633         return 0;
634
635 err_out:
636         spin_unlock_irqrestore(&as->lock, flags);
637
638         devm_kfree(smmu->dev, cnt);
639         if (page)
640                 __free_page(page);
641         return err;
642 }
643
644 static void __smmu_iommu_unmap(struct smmu_as *as, dma_addr_t iova)
645 {
646         unsigned long *pte;
647         struct page *page;
648         unsigned int *count;
649
650         pte = locate_pte(as, iova, false, &page, &count);
651         if (WARN_ON(!pte))
652                 return;
653
654         if (WARN_ON(*pte == _PTE_VACANT(iova)))
655                 return;
656
657         *pte = _PTE_VACANT(iova);
658         FLUSH_CPU_DCACHE(pte, page, sizeof(*pte));
659         flush_ptc_and_tlb(as->smmu, as, iova, pte, page, 0);
660         if (!--(*count)) {
661                 free_ptbl(as, iova);
662                 smmu_flush_regs(as->smmu, 0);
663         }
664 }
665
666 static void __smmu_iommu_map_pfn(struct smmu_as *as, dma_addr_t iova,
667                                  unsigned long pfn)
668 {
669         struct smmu_device *smmu = as->smmu;
670         unsigned long *pte;
671         unsigned int *count;
672         struct page *page;
673
674         pte = locate_pte(as, iova, true, &page, &count);
675         if (WARN_ON(!pte))
676                 return;
677
678         if (*pte == _PTE_VACANT(iova))
679                 (*count)++;
680         *pte = SMMU_PFN_TO_PTE(pfn, as->pte_attr);
681         if (unlikely((*pte == _PTE_VACANT(iova))))
682                 (*count)--;
683         FLUSH_CPU_DCACHE(pte, page, sizeof(*pte));
684         flush_ptc_and_tlb(smmu, as, iova, pte, page, 0);
685         put_signature(as, iova, pfn);
686 }
687
688 static int smmu_iommu_map(struct iommu_domain *domain, unsigned long iova,
689                           phys_addr_t pa, size_t bytes, int prot)
690 {
691         struct smmu_as *as = domain->priv;
692         unsigned long pfn = __phys_to_pfn(pa);
693         unsigned long flags;
694
695         dev_dbg(as->smmu->dev, "[%d] %08lx:%08x\n", as->asid, iova, pa);
696
697         if (!pfn_valid(pfn))
698                 return -ENOMEM;
699
700         spin_lock_irqsave(&as->lock, flags);
701         __smmu_iommu_map_pfn(as, iova, pfn);
702         spin_unlock_irqrestore(&as->lock, flags);
703         return 0;
704 }
705
706 static size_t smmu_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
707                                size_t bytes)
708 {
709         struct smmu_as *as = domain->priv;
710         unsigned long flags;
711
712         dev_dbg(as->smmu->dev, "[%d] %08lx\n", as->asid, iova);
713
714         spin_lock_irqsave(&as->lock, flags);
715         __smmu_iommu_unmap(as, iova);
716         spin_unlock_irqrestore(&as->lock, flags);
717         return SMMU_PAGE_SIZE;
718 }
719
720 static phys_addr_t smmu_iommu_iova_to_phys(struct iommu_domain *domain,
721                                            unsigned long iova)
722 {
723         struct smmu_as *as = domain->priv;
724         unsigned long *pte;
725         unsigned int *count;
726         struct page *page;
727         unsigned long pfn;
728         unsigned long flags;
729
730         spin_lock_irqsave(&as->lock, flags);
731
732         pte = locate_pte(as, iova, true, &page, &count);
733         pfn = *pte & SMMU_PFN_MASK;
734         WARN_ON(!pfn_valid(pfn));
735         dev_dbg(as->smmu->dev,
736                 "iova:%08lx pfn:%08lx asid:%d\n", iova, pfn, as->asid);
737
738         spin_unlock_irqrestore(&as->lock, flags);
739         return PFN_PHYS(pfn);
740 }
741
742 static int smmu_iommu_domain_has_cap(struct iommu_domain *domain,
743                                      unsigned long cap)
744 {
745         return 0;
746 }
747
748 static int smmu_iommu_attach_dev(struct iommu_domain *domain,
749                                  struct device *dev)
750 {
751         struct smmu_as *as = domain->priv;
752         struct smmu_device *smmu = as->smmu;
753         struct smmu_client *client, *c;
754         u32 map;
755         int err;
756
757         client = devm_kzalloc(smmu->dev, sizeof(*c), GFP_KERNEL);
758         if (!client)
759                 return -ENOMEM;
760         client->dev = dev;
761         client->as = as;
762
763 #ifdef SKIP_SWGRP_CHECK
764         /* Enable all SWGRP blindly by default */
765         map = (1 << HWGRP_COUNT) - 1;
766 #else
767         map = (unsigned long)dev->platform_data;
768         if (!map)
769                 return -EINVAL;
770 #endif
771
772         err = smmu_client_enable_hwgrp(client, map);
773         if (err)
774                 goto err_hwgrp;
775
776         spin_lock(&as->client_lock);
777         list_for_each_entry(c, &as->client, list) {
778                 if (c->dev == dev) {
779                         dev_err(smmu->dev,
780                                 "%s is already attached\n", dev_name(c->dev));
781                         err = -EINVAL;
782                         goto err_client;
783                 }
784         }
785         list_add(&client->list, &as->client);
786         spin_unlock(&as->client_lock);
787
788         /*
789          * Reserve "page zero" for AVP vectors using a common dummy
790          * page.
791          */
792         if (map & HWG_AVPC) {
793                 struct page *page;
794
795                 page = as->smmu->avp_vector_page;
796                 __smmu_iommu_map_pfn(as, 0, page_to_pfn(page));
797
798                 pr_info("Reserve \"page zero\" for AVP vectors using a common dummy\n");
799         }
800
801         dev_dbg(smmu->dev, "%s is attached\n", dev_name(dev));
802         return 0;
803
804 err_client:
805         smmu_client_disable_hwgrp(client);
806         spin_unlock(&as->client_lock);
807 err_hwgrp:
808         devm_kfree(smmu->dev, client);
809         return err;
810 }
811
812 static void smmu_iommu_detach_dev(struct iommu_domain *domain,
813                                   struct device *dev)
814 {
815         struct smmu_as *as = domain->priv;
816         struct smmu_device *smmu = as->smmu;
817         struct smmu_client *c;
818
819         spin_lock(&as->client_lock);
820
821         list_for_each_entry(c, &as->client, list) {
822                 if (c->dev == dev) {
823                         smmu_client_disable_hwgrp(c);
824                         list_del(&c->list);
825                         devm_kfree(smmu->dev, c);
826                         c->as = NULL;
827                         dev_dbg(smmu->dev,
828                                 "%s is detached\n", dev_name(c->dev));
829                         goto out;
830                 }
831         }
832         dev_err(smmu->dev, "Couldn't find %s\n", dev_name(c->dev));
833 out:
834         spin_unlock(&as->client_lock);
835 }
836
837 #if !defined(CONFIG_TEGRA_IOMMU_SMMU_LINEAR)
838 static inline void __smmu_iommu_map_linear(struct smmu_as *as,
839                                            unsigned long start, size_t size)
840 {
841         int i;
842         unsigned long count = size >> PAGE_SHIFT;
843
844         for (i = 0; i < count; i++) {
845                 unsigned long addr;
846
847                 addr = start + i * PAGE_SIZE;
848                 __smmu_iommu_map_pfn(as, addr, __phys_to_pfn(addr));
849         }
850 }
851
852 void smmu_iommu_map_linear(unsigned long start, size_t size)
853 {
854         int i;
855         struct smmu_device *smmu = smmu_handle;
856
857         for  (i = 0; i < smmu->num_as; i++) {
858                 struct smmu_as *as;
859
860                 as = &smmu->as[i];
861                 if (!as->pdir_page)
862                         continue;
863
864                 __smmu_iommu_map_linear(as, start, size);
865
866                 dev_dbg(smmu->dev, "%s as[%d]: %08lx(%x)\n",
867                         __func__, i, start, size);
868         }
869 }
870 EXPORT_SYMBOL_GPL(smmu_iommu_map_linear);
871 #endif
872
873 static int smmu_iommu_domain_init(struct iommu_domain *domain)
874 {
875         int i, err = -EAGAIN;
876         unsigned long flags;
877         struct smmu_as *as;
878         struct smmu_device *smmu = smmu_handle;
879
880         /* Look for a free AS with lock held */
881         for  (i = 0; i < smmu->num_as; i++) {
882                 as = &smmu->as[i];
883
884                 if (as->pdir_page)
885                         continue;
886
887                 err = alloc_pdir(as);
888                 if (!err)
889                         goto found;
890
891                 if (err != -EAGAIN)
892                         break;
893         }
894         if (i == smmu->num_as)
895                 dev_err(smmu->dev,  "no free AS\n");
896         return err;
897
898 found:
899         spin_lock_irqsave(&smmu->lock, flags);
900
901         /* Update PDIR register */
902         smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
903         smmu_write(smmu,
904                    SMMU_MK_PDIR(as->pdir_page, as->pdir_attr), SMMU_PTB_DATA);
905         FLUSH_SMMU_REGS(smmu);
906
907         spin_unlock_irqrestore(&smmu->lock, flags);
908
909         domain->priv = as;
910
911         dev_dbg(smmu->dev, "smmu_as@%p\n", as);
912         return 0;
913 }
914
915 static void smmu_iommu_domain_destroy(struct iommu_domain *domain)
916 {
917         struct smmu_as *as = domain->priv;
918         struct smmu_device *smmu = as->smmu;
919         unsigned long flags;
920
921         spin_lock_irqsave(&as->lock, flags);
922
923         if (as->pdir_page) {
924                 spin_lock(&smmu->lock);
925                 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
926                 smmu_write(smmu, SMMU_PTB_DATA_RESET_VAL, SMMU_PTB_DATA);
927                 FLUSH_SMMU_REGS(smmu);
928                 spin_unlock(&smmu->lock);
929
930                 free_pdir(as);
931         }
932
933         if (!list_empty(&as->client)) {
934                 struct smmu_client *c;
935
936                 list_for_each_entry(c, &as->client, list)
937                         smmu_iommu_detach_dev(domain, c->dev);
938         }
939
940         spin_unlock_irqrestore(&as->lock, flags);
941
942         domain->priv = NULL;
943         dev_dbg(smmu->dev, "smmu_as@%p\n", as);
944 }
945
946 static struct iommu_ops smmu_iommu_ops = {
947         .domain_init    = smmu_iommu_domain_init,
948         .domain_destroy = smmu_iommu_domain_destroy,
949         .attach_dev     = smmu_iommu_attach_dev,
950         .detach_dev     = smmu_iommu_detach_dev,
951         .map            = smmu_iommu_map,
952         .unmap          = smmu_iommu_unmap,
953         .iova_to_phys   = smmu_iommu_iova_to_phys,
954         .domain_has_cap = smmu_iommu_domain_has_cap,
955         .pgsize_bitmap  = SMMU_IOMMU_PGSIZES,
956 };
957
958 static const char * const smmu_debugfs_mc[] = { "mc", };
959 static const char * const smmu_debugfs_cache[] = {  "tlb", "ptc", };
960
961 static ssize_t smmu_debugfs_stats_write(struct file *file,
962                                         const char __user *buffer,
963                                         size_t count, loff_t *pos)
964 {
965         struct smmu_device *smmu;
966         struct dentry *dent;
967         int i, cache, mc;
968         enum {
969                 _OFF = 0,
970                 _ON,
971                 _RESET,
972         };
973         const char * const command[] = {
974                 [_OFF]          = "off",
975                 [_ON]           = "on",
976                 [_RESET]        = "reset",
977         };
978         char str[] = "reset";
979         u32 val;
980         size_t offs;
981
982         count = min_t(size_t, count, sizeof(str));
983         if (copy_from_user(str, buffer, count))
984                 return -EINVAL;
985
986         for (i = 0; i < ARRAY_SIZE(command); i++)
987                 if (strncmp(str, command[i],
988                             strlen(command[i])) == 0)
989                         break;
990
991         if (i == ARRAY_SIZE(command))
992                 return -EINVAL;
993
994         dent = file->f_dentry;
995         cache = (int)dent->d_inode->i_private;
996         mc = (int)dent->d_parent->d_inode->i_private;
997         smmu = dent->d_parent->d_parent->d_inode->i_private;
998
999         offs = SMMU_CACHE_CONFIG(cache);
1000         val = smmu_read(smmu, offs);
1001         switch (i) {
1002         case _OFF:
1003                 val &= ~SMMU_CACHE_CONFIG_STATS_ENABLE;
1004                 val &= ~SMMU_CACHE_CONFIG_STATS_TEST;
1005                 smmu_write(smmu, val, offs);
1006                 break;
1007         case _ON:
1008                 val |= SMMU_CACHE_CONFIG_STATS_ENABLE;
1009                 val &= ~SMMU_CACHE_CONFIG_STATS_TEST;
1010                 smmu_write(smmu, val, offs);
1011                 break;
1012         case _RESET:
1013                 val |= SMMU_CACHE_CONFIG_STATS_TEST;
1014                 smmu_write(smmu, val, offs);
1015                 val &= ~SMMU_CACHE_CONFIG_STATS_TEST;
1016                 smmu_write(smmu, val, offs);
1017                 break;
1018         default:
1019                 BUG();
1020                 break;
1021         }
1022
1023         dev_dbg(smmu->dev, "%s() %08x, %08x @%08x\n", __func__,
1024                 val, smmu_read(smmu, offs), offs);
1025
1026         return count;
1027 }
1028
1029 static int smmu_debugfs_stats_show(struct seq_file *s, void *v)
1030 {
1031         struct smmu_device *smmu;
1032         struct dentry *dent;
1033         int i, cache, mc;
1034         const char * const stats[] = { "hit", "miss", };
1035
1036         dent = d_find_alias(s->private);
1037         cache = (int)dent->d_inode->i_private;
1038         mc = (int)dent->d_parent->d_inode->i_private;
1039         smmu = dent->d_parent->d_parent->d_inode->i_private;
1040
1041         for (i = 0; i < ARRAY_SIZE(stats); i++) {
1042                 u32 val;
1043                 size_t offs;
1044
1045                 offs = SMMU_STATS_CACHE_COUNT(mc, cache, i);
1046                 val = smmu_read(smmu, offs);
1047                 seq_printf(s, "%s:%08x ", stats[i], val);
1048
1049                 dev_dbg(smmu->dev, "%s() %s %08x @%08x\n", __func__,
1050                         stats[i], val, offs);
1051         }
1052         seq_printf(s, "\n");
1053
1054         return 0;
1055 }
1056
1057 static int smmu_debugfs_stats_open(struct inode *inode, struct file *file)
1058 {
1059         return single_open(file, smmu_debugfs_stats_show, inode);
1060 }
1061
1062 static const struct file_operations smmu_debugfs_stats_fops = {
1063         .open           = smmu_debugfs_stats_open,
1064         .read           = seq_read,
1065         .llseek         = seq_lseek,
1066         .release        = single_release,
1067         .write          = smmu_debugfs_stats_write,
1068 };
1069
1070 static void smmu_debugfs_delete(struct smmu_device *smmu)
1071 {
1072         debugfs_remove_recursive(smmu->debugfs_root);
1073 }
1074
1075 static void smmu_debugfs_create(struct smmu_device *smmu)
1076 {
1077         int i;
1078         struct dentry *root;
1079
1080         root = debugfs_create_file("smmu",
1081                                    S_IFDIR | S_IRWXU | S_IRUGO | S_IXUGO,
1082                                    NULL, smmu, NULL);
1083         if (!root)
1084                 goto err_out;
1085         smmu->debugfs_root = root;
1086
1087         for (i = 0; i < ARRAY_SIZE(smmu_debugfs_mc); i++) {
1088                 int j;
1089                 struct dentry *mc;
1090
1091                 mc = debugfs_create_file(smmu_debugfs_mc[i],
1092                                          S_IFDIR | S_IRWXU | S_IRUGO | S_IXUGO,
1093                                          root, (void *)i, NULL);
1094                 if (!mc)
1095                         goto err_out;
1096
1097                 for (j = 0; j < ARRAY_SIZE(smmu_debugfs_cache); j++) {
1098                         struct dentry *cache;
1099
1100                         cache = debugfs_create_file(smmu_debugfs_cache[j],
1101                                                     S_IWUGO | S_IRUGO, mc,
1102                                                     (void *)j,
1103                                                     &smmu_debugfs_stats_fops);
1104                         if (!cache)
1105                                 goto err_out;
1106                 }
1107         }
1108
1109         return;
1110
1111 err_out:
1112         smmu_debugfs_delete(smmu);
1113 }
1114
1115 static int tegra_smmu_suspend(struct device *dev)
1116 {
1117         struct smmu_device *smmu = dev_get_drvdata(dev);
1118
1119         smmu->translation_enable_0 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_0);
1120         smmu->translation_enable_1 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_1);
1121         smmu->translation_enable_2 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_2);
1122         smmu->asid_security = smmu_read(smmu, SMMU_ASID_SECURITY);
1123         return 0;
1124 }
1125
1126 static int tegra_smmu_resume(struct device *dev)
1127 {
1128         struct smmu_device *smmu = dev_get_drvdata(dev);
1129         unsigned long flags;
1130
1131         spin_lock_irqsave(&smmu->lock, flags);
1132         smmu_setup_regs(smmu);
1133         spin_unlock_irqrestore(&smmu->lock, flags);
1134         return 0;
1135 }
1136
1137 static int tegra_smmu_probe(struct platform_device *pdev)
1138 {
1139         struct smmu_device *smmu;
1140         struct resource *regs, *regs2, *window;
1141         struct device *dev = &pdev->dev;
1142         int i, err = 0;
1143
1144         if (smmu_handle)
1145                 return -EIO;
1146
1147         BUILD_BUG_ON(PAGE_SHIFT != SMMU_PAGE_SHIFT);
1148
1149         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1150         regs2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1151         window = tegra_smmu_window(0);
1152         if (!regs || !regs2 || !window) {
1153                 dev_err(dev, "No SMMU resources\n");
1154                 return -ENODEV;
1155         }
1156
1157         smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
1158         if (!smmu) {
1159                 dev_err(dev, "failed to allocate smmu_device\n");
1160                 return -ENOMEM;
1161         }
1162
1163         smmu->dev = dev;
1164         smmu->num_as = SMMU_NUM_ASIDS;
1165         smmu->iovmm_base = (unsigned long)window->start;
1166         smmu->page_count = (window->end + 1 - window->start) >> SMMU_PAGE_SHIFT;
1167         smmu->regs = devm_ioremap(dev, regs->start, resource_size(regs));
1168         smmu->regs_ahbarb = devm_ioremap(dev, regs2->start,
1169                                          resource_size(regs2));
1170         if (!smmu->regs || !smmu->regs_ahbarb) {
1171                 dev_err(dev, "failed to remap SMMU registers\n");
1172                 err = -ENXIO;
1173                 goto fail;
1174         }
1175
1176         smmu->translation_enable_0 = ~0;
1177         smmu->translation_enable_1 = ~0;
1178         smmu->translation_enable_2 = ~0;
1179         smmu->asid_security = 0;
1180
1181         smmu->as = devm_kzalloc(dev,
1182                         sizeof(smmu->as[0]) * smmu->num_as, GFP_KERNEL);
1183         if (!smmu->as) {
1184                 dev_err(dev, "failed to allocate smmu_as\n");
1185                 err = -ENOMEM;
1186                 goto fail;
1187         }
1188
1189         for (i = 0; i < smmu->num_as; i++) {
1190                 struct smmu_as *as = &smmu->as[i];
1191
1192                 as->smmu = smmu;
1193                 as->asid = i;
1194                 as->pdir_attr = _PDIR_ATTR;
1195                 as->pde_attr = _PDE_ATTR;
1196                 as->pte_attr = _PTE_ATTR;
1197
1198                 spin_lock_init(&as->lock);
1199                 INIT_LIST_HEAD(&as->client);
1200         }
1201         spin_lock_init(&smmu->lock);
1202         smmu_setup_regs(smmu);
1203         platform_set_drvdata(pdev, smmu);
1204
1205         smmu->avp_vector_page = alloc_page(GFP_KERNEL);
1206         if (!smmu->avp_vector_page)
1207                 goto fail;
1208
1209         smmu_debugfs_create(smmu);
1210         smmu_handle = smmu;
1211         return 0;
1212
1213 fail:
1214         if (smmu->avp_vector_page)
1215                 __free_page(smmu->avp_vector_page);
1216         if (smmu->regs)
1217                 devm_iounmap(dev, smmu->regs);
1218         if (smmu->regs_ahbarb)
1219                 devm_iounmap(dev, smmu->regs_ahbarb);
1220         if (smmu && smmu->as) {
1221                 for (i = 0; i < smmu->num_as; i++) {
1222                         if (smmu->as[i].pdir_page) {
1223                                 ClearPageReserved(smmu->as[i].pdir_page);
1224                                 __free_page(smmu->as[i].pdir_page);
1225                         }
1226                 }
1227                 devm_kfree(dev, smmu->as);
1228         }
1229         devm_kfree(dev, smmu);
1230         return err;
1231 }
1232
1233 static int tegra_smmu_remove(struct platform_device *pdev)
1234 {
1235         struct smmu_device *smmu = platform_get_drvdata(pdev);
1236         struct device *dev = smmu->dev;
1237
1238         smmu_debugfs_delete(smmu);
1239
1240         smmu_write(smmu, SMMU_CONFIG_DISABLE, SMMU_CONFIG);
1241         platform_set_drvdata(pdev, NULL);
1242         if (smmu->as) {
1243                 int i;
1244
1245                 for (i = 0; i < smmu->num_as; i++)
1246                         free_pdir(&smmu->as[i]);
1247                 devm_kfree(dev, smmu->as);
1248         }
1249         if (smmu->avp_vector_page)
1250                 __free_page(smmu->avp_vector_page);
1251         if (smmu->regs)
1252                 devm_iounmap(dev, smmu->regs);
1253         if (smmu->regs_ahbarb)
1254                 devm_iounmap(dev, smmu->regs_ahbarb);
1255         devm_kfree(dev, smmu);
1256         smmu_handle = NULL;
1257         return 0;
1258 }
1259
1260 const struct dev_pm_ops tegra_smmu_pm_ops = {
1261         .suspend        = tegra_smmu_suspend,
1262         .resume         = tegra_smmu_resume,
1263 };
1264
1265 static struct platform_driver tegra_smmu_driver = {
1266         .probe          = tegra_smmu_probe,
1267         .remove         = tegra_smmu_remove,
1268         .driver = {
1269                 .owner  = THIS_MODULE,
1270                 .name   = "tegra_smmu",
1271                 .pm     = &tegra_smmu_pm_ops,
1272         },
1273 };
1274
1275 static int __devinit tegra_smmu_init(void)
1276 {
1277         bus_set_iommu(&platform_bus_type, &smmu_iommu_ops);
1278         return platform_driver_register(&tegra_smmu_driver);
1279 }
1280
1281 static void __exit tegra_smmu_exit(void)
1282 {
1283         platform_driver_unregister(&tegra_smmu_driver);
1284 }
1285
1286 core_initcall(tegra_smmu_init);
1287 module_exit(tegra_smmu_exit);
1288
1289 MODULE_DESCRIPTION("IOMMU API for SMMU in Tegra30");
1290 MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
1291 MODULE_LICENSE("GPL v2");