iommu/amd: Add iommuv2 flag to struct amd_iommu
[linux-2.6.git] / drivers / iommu / tegra-smmu.c
1 /*
2  * IOMMU API for SMMU in Tegra30
3  *
4  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along with
16  * this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18  */
19
20 #define pr_fmt(fmt)     "%s(): " fmt, __func__
21
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/spinlock.h>
25 #include <linux/slab.h>
26 #include <linux/vmalloc.h>
27 #include <linux/mm.h>
28 #include <linux/pagemap.h>
29 #include <linux/device.h>
30 #include <linux/sched.h>
31 #include <linux/iommu.h>
32 #include <linux/io.h>
33
34 #include <asm/page.h>
35 #include <asm/cacheflush.h>
36
37 #include <mach/iomap.h>
38 #include <mach/smmu.h>
39 #include <mach/tegra_smmu.h>
40
41 #define SMMU_CONFIG                             0x10
42 #define SMMU_CONFIG_DISABLE                     0
43 #define SMMU_CONFIG_ENABLE                      1
44
45 #define SMMU_TLB_CONFIG                         0x14
46 #define SMMU_TLB_CONFIG_STATS__MASK             (1 << 31)
47 #define SMMU_TLB_CONFIG_STATS__ENABLE           (1 << 31)
48 #define SMMU_TLB_CONFIG_HIT_UNDER_MISS__ENABLE  (1 << 29)
49 #define SMMU_TLB_CONFIG_ACTIVE_LINES__VALUE     0x10
50 #define SMMU_TLB_CONFIG_RESET_VAL               0x20000010
51
52 #define SMMU_PTC_CONFIG                         0x18
53 #define SMMU_PTC_CONFIG_STATS__MASK             (1 << 31)
54 #define SMMU_PTC_CONFIG_STATS__ENABLE           (1 << 31)
55 #define SMMU_PTC_CONFIG_CACHE__ENABLE           (1 << 29)
56 #define SMMU_PTC_CONFIG_INDEX_MAP__PATTERN      0x3f
57 #define SMMU_PTC_CONFIG_RESET_VAL               0x2000003f
58
59 #define SMMU_PTB_ASID                           0x1c
60 #define SMMU_PTB_ASID_CURRENT_SHIFT             0
61
62 #define SMMU_PTB_DATA                           0x20
63 #define SMMU_PTB_DATA_RESET_VAL                 0
64 #define SMMU_PTB_DATA_ASID_NONSECURE_SHIFT      29
65 #define SMMU_PTB_DATA_ASID_WRITABLE_SHIFT       30
66 #define SMMU_PTB_DATA_ASID_READABLE_SHIFT       31
67
68 #define SMMU_TLB_FLUSH                          0x30
69 #define SMMU_TLB_FLUSH_VA_MATCH_ALL             0
70 #define SMMU_TLB_FLUSH_VA_MATCH_SECTION         2
71 #define SMMU_TLB_FLUSH_VA_MATCH_GROUP           3
72 #define SMMU_TLB_FLUSH_ASID_SHIFT               29
73 #define SMMU_TLB_FLUSH_ASID_MATCH_DISABLE       0
74 #define SMMU_TLB_FLUSH_ASID_MATCH_ENABLE        1
75 #define SMMU_TLB_FLUSH_ASID_MATCH_SHIFT         31
76
77 #define SMMU_PTC_FLUSH                          0x34
78 #define SMMU_PTC_FLUSH_TYPE_ALL                 0
79 #define SMMU_PTC_FLUSH_TYPE_ADR                 1
80 #define SMMU_PTC_FLUSH_ADR_SHIFT                4
81
82 #define SMMU_ASID_SECURITY                      0x38
83
84 #define SMMU_STATS_TLB_HIT_COUNT                0x1f0
85 #define SMMU_STATS_TLB_MISS_COUNT               0x1f4
86 #define SMMU_STATS_PTC_HIT_COUNT                0x1f8
87 #define SMMU_STATS_PTC_MISS_COUNT               0x1fc
88
89 #define SMMU_TRANSLATION_ENABLE_0               0x228
90 #define SMMU_TRANSLATION_ENABLE_1               0x22c
91 #define SMMU_TRANSLATION_ENABLE_2               0x230
92
93 #define SMMU_AFI_ASID   0x238   /* PCIE */
94 #define SMMU_AVPC_ASID  0x23c   /* AVP */
95 #define SMMU_DC_ASID    0x240   /* Display controller */
96 #define SMMU_DCB_ASID   0x244   /* Display controller B */
97 #define SMMU_EPP_ASID   0x248   /* Encoder pre-processor */
98 #define SMMU_G2_ASID    0x24c   /* 2D engine */
99 #define SMMU_HC_ASID    0x250   /* Host1x */
100 #define SMMU_HDA_ASID   0x254   /* High-def audio */
101 #define SMMU_ISP_ASID   0x258   /* Image signal processor */
102 #define SMMU_MPE_ASID   0x264   /* MPEG encoder */
103 #define SMMU_NV_ASID    0x268   /* (3D) */
104 #define SMMU_NV2_ASID   0x26c   /* (3D) */
105 #define SMMU_PPCS_ASID  0x270   /* AHB */
106 #define SMMU_SATA_ASID  0x278   /* SATA */
107 #define SMMU_VDE_ASID   0x27c   /* Video decoder */
108 #define SMMU_VI_ASID    0x280   /* Video input */
109
110 #define SMMU_PDE_NEXT_SHIFT             28
111
112 /* AHB Arbiter Registers */
113 #define AHB_XBAR_CTRL                           0xe0
114 #define AHB_XBAR_CTRL_SMMU_INIT_DONE_DONE       1
115 #define AHB_XBAR_CTRL_SMMU_INIT_DONE_SHIFT      17
116
117 #define SMMU_NUM_ASIDS                          4
118 #define SMMU_TLB_FLUSH_VA_SECTION__MASK         0xffc00000
119 #define SMMU_TLB_FLUSH_VA_SECTION__SHIFT        12 /* right shift */
120 #define SMMU_TLB_FLUSH_VA_GROUP__MASK           0xffffc000
121 #define SMMU_TLB_FLUSH_VA_GROUP__SHIFT          12 /* right shift */
122 #define SMMU_TLB_FLUSH_VA(iova, which)  \
123         ((((iova) & SMMU_TLB_FLUSH_VA_##which##__MASK) >> \
124                 SMMU_TLB_FLUSH_VA_##which##__SHIFT) |   \
125         SMMU_TLB_FLUSH_VA_MATCH_##which)
126 #define SMMU_PTB_ASID_CUR(n)    \
127                 ((n) << SMMU_PTB_ASID_CURRENT_SHIFT)
128 #define SMMU_TLB_FLUSH_ASID_MATCH_disable               \
129                 (SMMU_TLB_FLUSH_ASID_MATCH_DISABLE <<   \
130                         SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
131 #define SMMU_TLB_FLUSH_ASID_MATCH__ENABLE               \
132                 (SMMU_TLB_FLUSH_ASID_MATCH_ENABLE <<    \
133                         SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
134
135 #define SMMU_PAGE_SHIFT 12
136 #define SMMU_PAGE_SIZE  (1 << SMMU_PAGE_SHIFT)
137
138 #define SMMU_PDIR_COUNT 1024
139 #define SMMU_PDIR_SIZE  (sizeof(unsigned long) * SMMU_PDIR_COUNT)
140 #define SMMU_PTBL_COUNT 1024
141 #define SMMU_PTBL_SIZE  (sizeof(unsigned long) * SMMU_PTBL_COUNT)
142 #define SMMU_PDIR_SHIFT 12
143 #define SMMU_PDE_SHIFT  12
144 #define SMMU_PTE_SHIFT  12
145 #define SMMU_PFN_MASK   0x000fffff
146
147 #define SMMU_ADDR_TO_PFN(addr)  ((addr) >> 12)
148 #define SMMU_ADDR_TO_PDN(addr)  ((addr) >> 22)
149 #define SMMU_PDN_TO_ADDR(addr)  ((pdn) << 22)
150
151 #define _READABLE       (1 << SMMU_PTB_DATA_ASID_READABLE_SHIFT)
152 #define _WRITABLE       (1 << SMMU_PTB_DATA_ASID_WRITABLE_SHIFT)
153 #define _NONSECURE      (1 << SMMU_PTB_DATA_ASID_NONSECURE_SHIFT)
154 #define _PDE_NEXT       (1 << SMMU_PDE_NEXT_SHIFT)
155 #define _MASK_ATTR      (_READABLE | _WRITABLE | _NONSECURE)
156
157 #define _PDIR_ATTR      (_READABLE | _WRITABLE | _NONSECURE)
158
159 #define _PDE_ATTR       (_READABLE | _WRITABLE | _NONSECURE)
160 #define _PDE_ATTR_N     (_PDE_ATTR | _PDE_NEXT)
161 #define _PDE_VACANT(pdn)        (((pdn) << 10) | _PDE_ATTR)
162
163 #define _PTE_ATTR       (_READABLE | _WRITABLE | _NONSECURE)
164 #define _PTE_VACANT(addr)       (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR)
165
166 #define SMMU_MK_PDIR(page, attr)        \
167                 ((page_to_phys(page) >> SMMU_PDIR_SHIFT) | (attr))
168 #define SMMU_MK_PDE(page, attr)         \
169                 (unsigned long)((page_to_phys(page) >> SMMU_PDE_SHIFT) | (attr))
170 #define SMMU_EX_PTBL_PAGE(pde)          \
171                 pfn_to_page((unsigned long)(pde) & SMMU_PFN_MASK)
172 #define SMMU_PFN_TO_PTE(pfn, attr)      (unsigned long)((pfn) | (attr))
173
174 #define SMMU_ASID_ENABLE(asid)  ((asid) | (1 << 31))
175 #define SMMU_ASID_DISABLE       0
176 #define SMMU_ASID_ASID(n)       ((n) & ~SMMU_ASID_ENABLE(0))
177
178 #define smmu_client_enable_hwgrp(c, m)  smmu_client_set_hwgrp(c, m, 1)
179 #define smmu_client_disable_hwgrp(c)    smmu_client_set_hwgrp(c, 0, 0)
180 #define __smmu_client_enable_hwgrp(c, m) __smmu_client_set_hwgrp(c, m, 1)
181 #define __smmu_client_disable_hwgrp(c)  __smmu_client_set_hwgrp(c, 0, 0)
182
183 #define HWGRP_INIT(client)                      \
184         [HWGRP_##client] = SMMU_##client##_ASID
185
186 static const u32 smmu_hwgrp_asid_reg[] = {
187         HWGRP_INIT(AFI),
188         HWGRP_INIT(AVPC),
189         HWGRP_INIT(DC),
190         HWGRP_INIT(DCB),
191         HWGRP_INIT(EPP),
192         HWGRP_INIT(G2),
193         HWGRP_INIT(HC),
194         HWGRP_INIT(HDA),
195         HWGRP_INIT(ISP),
196         HWGRP_INIT(MPE),
197         HWGRP_INIT(NV),
198         HWGRP_INIT(NV2),
199         HWGRP_INIT(PPCS),
200         HWGRP_INIT(SATA),
201         HWGRP_INIT(VDE),
202         HWGRP_INIT(VI),
203 };
204 #define HWGRP_ASID_REG(x) (smmu_hwgrp_asid_reg[x])
205
206 /*
207  * Per client for address space
208  */
209 struct smmu_client {
210         struct device           *dev;
211         struct list_head        list;
212         struct smmu_as          *as;
213         u32                     hwgrp;
214 };
215
216 /*
217  * Per address space
218  */
219 struct smmu_as {
220         struct smmu_device      *smmu;  /* back pointer to container */
221         unsigned int            asid;
222         spinlock_t              lock;   /* for pagetable */
223         struct page             *pdir_page;
224         unsigned long           pdir_attr;
225         unsigned long           pde_attr;
226         unsigned long           pte_attr;
227         unsigned int            *pte_count;
228
229         struct list_head        client;
230         spinlock_t              client_lock; /* for client list */
231 };
232
233 /*
234  * Per SMMU device - IOMMU device
235  */
236 struct smmu_device {
237         void __iomem    *regs, *regs_ahbarb;
238         unsigned long   iovmm_base;     /* remappable base address */
239         unsigned long   page_count;     /* total remappable size */
240         spinlock_t      lock;
241         char            *name;
242         struct device   *dev;
243         int             num_as;
244         struct smmu_as  *as;            /* Run-time allocated array */
245         struct page *avp_vector_page;   /* dummy page shared by all AS's */
246
247         /*
248          * Register image savers for suspend/resume
249          */
250         unsigned long translation_enable_0;
251         unsigned long translation_enable_1;
252         unsigned long translation_enable_2;
253         unsigned long asid_security;
254 };
255
256 static struct smmu_device *smmu_handle; /* unique for a system */
257
258 /*
259  *      SMMU/AHB register accessors
260  */
261 static inline u32 smmu_read(struct smmu_device *smmu, size_t offs)
262 {
263         return readl(smmu->regs + offs);
264 }
265 static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs)
266 {
267         writel(val, smmu->regs + offs);
268 }
269
270 static inline u32 ahb_read(struct smmu_device *smmu, size_t offs)
271 {
272         return readl(smmu->regs_ahbarb + offs);
273 }
274 static inline void ahb_write(struct smmu_device *smmu, u32 val, size_t offs)
275 {
276         writel(val, smmu->regs_ahbarb + offs);
277 }
278
279 #define VA_PAGE_TO_PA(va, page) \
280         (page_to_phys(page) + ((unsigned long)(va) & ~PAGE_MASK))
281
282 #define FLUSH_CPU_DCACHE(va, page, size)        \
283         do {    \
284                 unsigned long _pa_ = VA_PAGE_TO_PA(va, page);           \
285                 __cpuc_flush_dcache_area((void *)(va), (size_t)(size)); \
286                 outer_flush_range(_pa_, _pa_+(size_t)(size));           \
287         } while (0)
288
289 /*
290  * Any interaction between any block on PPSB and a block on APB or AHB
291  * must have these read-back barriers to ensure the APB/AHB bus
292  * transaction is complete before initiating activity on the PPSB
293  * block.
294  */
295 #define FLUSH_SMMU_REGS(smmu)   smmu_read(smmu, SMMU_CONFIG)
296
297 #define smmu_client_hwgrp(c) (u32)((c)->dev->platform_data)
298
299 static int __smmu_client_set_hwgrp(struct smmu_client *c,
300                                    unsigned long map, int on)
301 {
302         int i;
303         struct smmu_as *as = c->as;
304         u32 val, offs, mask = SMMU_ASID_ENABLE(as->asid);
305         struct smmu_device *smmu = as->smmu;
306
307         WARN_ON(!on && map);
308         if (on && !map)
309                 return -EINVAL;
310         if (!on)
311                 map = smmu_client_hwgrp(c);
312
313         for_each_set_bit(i, &map, HWGRP_COUNT) {
314                 offs = HWGRP_ASID_REG(i);
315                 val = smmu_read(smmu, offs);
316                 if (on) {
317                         if (WARN_ON(val & mask))
318                                 goto err_hw_busy;
319                         val |= mask;
320                 } else {
321                         WARN_ON((val & mask) == mask);
322                         val &= ~mask;
323                 }
324                 smmu_write(smmu, val, offs);
325         }
326         FLUSH_SMMU_REGS(smmu);
327         c->hwgrp = map;
328         return 0;
329
330 err_hw_busy:
331         for_each_set_bit(i, &map, HWGRP_COUNT) {
332                 offs = HWGRP_ASID_REG(i);
333                 val = smmu_read(smmu, offs);
334                 val &= ~mask;
335                 smmu_write(smmu, val, offs);
336         }
337         return -EBUSY;
338 }
339
340 static int smmu_client_set_hwgrp(struct smmu_client *c, u32 map, int on)
341 {
342         u32 val;
343         unsigned long flags;
344         struct smmu_as *as = c->as;
345         struct smmu_device *smmu = as->smmu;
346
347         spin_lock_irqsave(&smmu->lock, flags);
348         val = __smmu_client_set_hwgrp(c, map, on);
349         spin_unlock_irqrestore(&smmu->lock, flags);
350         return val;
351 }
352
353 /*
354  * Flush all TLB entries and all PTC entries
355  * Caller must lock smmu
356  */
357 static void smmu_flush_regs(struct smmu_device *smmu, int enable)
358 {
359         u32 val;
360
361         smmu_write(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH);
362         FLUSH_SMMU_REGS(smmu);
363         val = SMMU_TLB_FLUSH_VA_MATCH_ALL |
364                 SMMU_TLB_FLUSH_ASID_MATCH_disable;
365         smmu_write(smmu, val, SMMU_TLB_FLUSH);
366
367         if (enable)
368                 smmu_write(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG);
369         FLUSH_SMMU_REGS(smmu);
370 }
371
372 static void smmu_setup_regs(struct smmu_device *smmu)
373 {
374         int i;
375         u32 val;
376
377         for (i = 0; i < smmu->num_as; i++) {
378                 struct smmu_as *as = &smmu->as[i];
379                 struct smmu_client *c;
380
381                 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
382                 val = as->pdir_page ?
383                         SMMU_MK_PDIR(as->pdir_page, as->pdir_attr) :
384                         SMMU_PTB_DATA_RESET_VAL;
385                 smmu_write(smmu, val, SMMU_PTB_DATA);
386
387                 list_for_each_entry(c, &as->client, list)
388                         __smmu_client_set_hwgrp(c, c->hwgrp, 1);
389         }
390
391         smmu_write(smmu, smmu->translation_enable_0, SMMU_TRANSLATION_ENABLE_0);
392         smmu_write(smmu, smmu->translation_enable_1, SMMU_TRANSLATION_ENABLE_1);
393         smmu_write(smmu, smmu->translation_enable_2, SMMU_TRANSLATION_ENABLE_2);
394         smmu_write(smmu, smmu->asid_security, SMMU_ASID_SECURITY);
395         smmu_write(smmu, SMMU_TLB_CONFIG_RESET_VAL, SMMU_TLB_CONFIG);
396         smmu_write(smmu, SMMU_PTC_CONFIG_RESET_VAL, SMMU_PTC_CONFIG);
397
398         smmu_flush_regs(smmu, 1);
399
400         val = ahb_read(smmu, AHB_XBAR_CTRL);
401         val |= AHB_XBAR_CTRL_SMMU_INIT_DONE_DONE <<
402                 AHB_XBAR_CTRL_SMMU_INIT_DONE_SHIFT;
403         ahb_write(smmu, val, AHB_XBAR_CTRL);
404 }
405
406 static void flush_ptc_and_tlb(struct smmu_device *smmu,
407                       struct smmu_as *as, dma_addr_t iova,
408                       unsigned long *pte, struct page *page, int is_pde)
409 {
410         u32 val;
411         unsigned long tlb_flush_va = is_pde
412                 ?  SMMU_TLB_FLUSH_VA(iova, SECTION)
413                 :  SMMU_TLB_FLUSH_VA(iova, GROUP);
414
415         val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pte, page);
416         smmu_write(smmu, val, SMMU_PTC_FLUSH);
417         FLUSH_SMMU_REGS(smmu);
418         val = tlb_flush_va |
419                 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE |
420                 (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT);
421         smmu_write(smmu, val, SMMU_TLB_FLUSH);
422         FLUSH_SMMU_REGS(smmu);
423 }
424
425 static void free_ptbl(struct smmu_as *as, dma_addr_t iova)
426 {
427         unsigned long pdn = SMMU_ADDR_TO_PDN(iova);
428         unsigned long *pdir = (unsigned long *)page_address(as->pdir_page);
429
430         if (pdir[pdn] != _PDE_VACANT(pdn)) {
431                 dev_dbg(as->smmu->dev, "pdn: %lx\n", pdn);
432
433                 ClearPageReserved(SMMU_EX_PTBL_PAGE(pdir[pdn]));
434                 __free_page(SMMU_EX_PTBL_PAGE(pdir[pdn]));
435                 pdir[pdn] = _PDE_VACANT(pdn);
436                 FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]);
437                 flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn],
438                                   as->pdir_page, 1);
439         }
440 }
441
442 static void free_pdir(struct smmu_as *as)
443 {
444         unsigned addr;
445         int count;
446         struct device *dev = as->smmu->dev;
447
448         if (!as->pdir_page)
449                 return;
450
451         addr = as->smmu->iovmm_base;
452         count = as->smmu->page_count;
453         while (count-- > 0) {
454                 free_ptbl(as, addr);
455                 addr += SMMU_PAGE_SIZE * SMMU_PTBL_COUNT;
456         }
457         ClearPageReserved(as->pdir_page);
458         __free_page(as->pdir_page);
459         as->pdir_page = NULL;
460         devm_kfree(dev, as->pte_count);
461         as->pte_count = NULL;
462 }
463
464 /*
465  * Maps PTBL for given iova and returns the PTE address
466  * Caller must unmap the mapped PTBL returned in *ptbl_page_p
467  */
468 static unsigned long *locate_pte(struct smmu_as *as,
469                                  dma_addr_t iova, bool allocate,
470                                  struct page **ptbl_page_p,
471                                  unsigned int **count)
472 {
473         unsigned long ptn = SMMU_ADDR_TO_PFN(iova);
474         unsigned long pdn = SMMU_ADDR_TO_PDN(iova);
475         unsigned long *pdir = page_address(as->pdir_page);
476         unsigned long *ptbl;
477
478         if (pdir[pdn] != _PDE_VACANT(pdn)) {
479                 /* Mapped entry table already exists */
480                 *ptbl_page_p = SMMU_EX_PTBL_PAGE(pdir[pdn]);
481                 ptbl = page_address(*ptbl_page_p);
482         } else if (!allocate) {
483                 return NULL;
484         } else {
485                 int pn;
486                 unsigned long addr = SMMU_PDN_TO_ADDR(pdn);
487
488                 /* Vacant - allocate a new page table */
489                 dev_dbg(as->smmu->dev, "New PTBL pdn: %lx\n", pdn);
490
491                 *ptbl_page_p = alloc_page(GFP_ATOMIC);
492                 if (!*ptbl_page_p) {
493                         dev_err(as->smmu->dev,
494                                 "failed to allocate smmu_device page table\n");
495                         return NULL;
496                 }
497                 SetPageReserved(*ptbl_page_p);
498                 ptbl = (unsigned long *)page_address(*ptbl_page_p);
499                 for (pn = 0; pn < SMMU_PTBL_COUNT;
500                      pn++, addr += SMMU_PAGE_SIZE) {
501                         ptbl[pn] = _PTE_VACANT(addr);
502                 }
503                 FLUSH_CPU_DCACHE(ptbl, *ptbl_page_p, SMMU_PTBL_SIZE);
504                 pdir[pdn] = SMMU_MK_PDE(*ptbl_page_p,
505                                         as->pde_attr | _PDE_NEXT);
506                 FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]);
507                 flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn],
508                                   as->pdir_page, 1);
509         }
510         *count = &as->pte_count[pdn];
511
512         return &ptbl[ptn % SMMU_PTBL_COUNT];
513 }
514
515 #ifdef CONFIG_SMMU_SIG_DEBUG
516 static void put_signature(struct smmu_as *as,
517                           dma_addr_t iova, unsigned long pfn)
518 {
519         struct page *page;
520         unsigned long *vaddr;
521
522         page = pfn_to_page(pfn);
523         vaddr = page_address(page);
524         if (!vaddr)
525                 return;
526
527         vaddr[0] = iova;
528         vaddr[1] = pfn << PAGE_SHIFT;
529         FLUSH_CPU_DCACHE(vaddr, page, sizeof(vaddr[0]) * 2);
530 }
531 #else
532 static inline void put_signature(struct smmu_as *as,
533                                  unsigned long addr, unsigned long pfn)
534 {
535 }
536 #endif
537
538 /*
539  * Caller must lock/unlock as
540  */
541 static int alloc_pdir(struct smmu_as *as)
542 {
543         unsigned long *pdir;
544         int pdn;
545         u32 val;
546         struct smmu_device *smmu = as->smmu;
547
548         if (as->pdir_page)
549                 return 0;
550
551         as->pte_count = devm_kzalloc(smmu->dev,
552                      sizeof(as->pte_count[0]) * SMMU_PDIR_COUNT, GFP_KERNEL);
553         if (!as->pte_count) {
554                 dev_err(smmu->dev,
555                         "failed to allocate smmu_device PTE cunters\n");
556                 return -ENOMEM;
557         }
558         as->pdir_page = alloc_page(GFP_KERNEL | __GFP_DMA);
559         if (!as->pdir_page) {
560                 dev_err(smmu->dev,
561                         "failed to allocate smmu_device page directory\n");
562                 devm_kfree(smmu->dev, as->pte_count);
563                 as->pte_count = NULL;
564                 return -ENOMEM;
565         }
566         SetPageReserved(as->pdir_page);
567         pdir = page_address(as->pdir_page);
568
569         for (pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++)
570                 pdir[pdn] = _PDE_VACANT(pdn);
571         FLUSH_CPU_DCACHE(pdir, as->pdir_page, SMMU_PDIR_SIZE);
572         val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pdir, as->pdir_page);
573         smmu_write(smmu, val, SMMU_PTC_FLUSH);
574         FLUSH_SMMU_REGS(as->smmu);
575         val = SMMU_TLB_FLUSH_VA_MATCH_ALL |
576                 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE |
577                 (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT);
578         smmu_write(smmu, val, SMMU_TLB_FLUSH);
579         FLUSH_SMMU_REGS(as->smmu);
580
581         return 0;
582 }
583
584 static void __smmu_iommu_unmap(struct smmu_as *as, dma_addr_t iova)
585 {
586         unsigned long *pte;
587         struct page *page;
588         unsigned int *count;
589
590         pte = locate_pte(as, iova, false, &page, &count);
591         if (WARN_ON(!pte))
592                 return;
593
594         if (WARN_ON(*pte == _PTE_VACANT(iova)))
595                 return;
596
597         *pte = _PTE_VACANT(iova);
598         FLUSH_CPU_DCACHE(pte, page, sizeof(*pte));
599         flush_ptc_and_tlb(as->smmu, as, iova, pte, page, 0);
600         if (!--(*count)) {
601                 free_ptbl(as, iova);
602                 smmu_flush_regs(as->smmu, 0);
603         }
604 }
605
606 static void __smmu_iommu_map_pfn(struct smmu_as *as, dma_addr_t iova,
607                                  unsigned long pfn)
608 {
609         struct smmu_device *smmu = as->smmu;
610         unsigned long *pte;
611         unsigned int *count;
612         struct page *page;
613
614         pte = locate_pte(as, iova, true, &page, &count);
615         if (WARN_ON(!pte))
616                 return;
617
618         if (*pte == _PTE_VACANT(iova))
619                 (*count)++;
620         *pte = SMMU_PFN_TO_PTE(pfn, as->pte_attr);
621         if (unlikely((*pte == _PTE_VACANT(iova))))
622                 (*count)--;
623         FLUSH_CPU_DCACHE(pte, page, sizeof(*pte));
624         flush_ptc_and_tlb(smmu, as, iova, pte, page, 0);
625         put_signature(as, iova, pfn);
626 }
627
628 static int smmu_iommu_map(struct iommu_domain *domain, unsigned long iova,
629                           phys_addr_t pa, int order, int prot)
630 {
631         unsigned long count = (PAGE_SIZE << order) >> SMMU_PAGE_SHIFT;
632         struct smmu_as *as = domain->priv;
633         unsigned long pfn = __phys_to_pfn(pa);
634         int i;
635         unsigned long flags;
636
637         dev_dbg(as->smmu->dev,
638                 "[%d] %08lx:%08x(%ld)\n", as->asid, iova, pa, count);
639
640         spin_lock_irqsave(&as->lock, flags);
641         for (i = 0; i < count; i++, pfn++) {
642                 if (!pfn_valid(pfn))
643                         goto fail;
644
645                 __smmu_iommu_map_pfn(as, iova, pfn);
646                 iova += SMMU_PAGE_SIZE;
647         }
648         spin_unlock_irqrestore(&as->lock, flags);
649         return 0;
650
651 fail:
652         while (i-- > 0) {
653                 iova -= SMMU_PAGE_SIZE;
654                 __smmu_iommu_unmap(as, iova);
655         }
656         spin_unlock_irqrestore(&as->lock, flags);
657         return -ENOMEM;
658 }
659
660 static int smmu_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
661                             int gfp_order)
662 {
663         struct smmu_as *as = domain->priv;
664         unsigned long count = (PAGE_SIZE << gfp_order) >> SMMU_PAGE_SHIFT;
665         int i;
666         unsigned long flags;
667
668         dev_dbg(as->smmu->dev, "[%d] %08lx(%ld)\n", as->asid, iova, count);
669
670         spin_lock_irqsave(&as->lock, flags);
671         for (i = 0; i < count; i++) {
672                 __smmu_iommu_unmap(as, iova);
673                 iova += SMMU_PAGE_SIZE;
674         }
675         spin_unlock_irqrestore(&as->lock, flags);
676         return 0;
677 }
678
679 static phys_addr_t smmu_iommu_iova_to_phys(struct iommu_domain *domain,
680                                            unsigned long iova)
681 {
682         struct smmu_as *as = domain->priv;
683         unsigned long *pte;
684         unsigned int *count;
685         struct page *page;
686         unsigned long pfn;
687         unsigned long flags;
688
689         spin_lock_irqsave(&as->lock, flags);
690
691         pte = locate_pte(as, iova, true, &page, &count);
692         pfn = *pte & SMMU_PFN_MASK;
693         WARN_ON(!pfn_valid(pfn));
694         dev_dbg(as->smmu->dev,
695                 "iova:%08lx pfn:%08lx asid:%d\n", iova, pfn, as->asid);
696
697         spin_unlock_irqrestore(&as->lock, flags);
698         return PFN_PHYS(pfn);
699 }
700
701 static int smmu_iommu_domain_has_cap(struct iommu_domain *domain,
702                                      unsigned long cap)
703 {
704         return 0;
705 }
706
707 static int smmu_iommu_domain_init(struct iommu_domain *domain)
708 {
709         int i;
710         unsigned long flags;
711         struct smmu_as *as;
712         struct smmu_device *smmu = smmu_handle;
713
714         /* Look for a free AS with lock held */
715         for  (i = 0; i < smmu->num_as; i++) {
716                 struct smmu_as *tmp = &smmu->as[i];
717
718                 spin_lock_irqsave(&tmp->lock, flags);
719                 if (!tmp->pdir_page) {
720                         as = tmp;
721                         goto found;
722                 }
723                 spin_unlock_irqrestore(&tmp->lock, flags);
724         }
725         dev_err(smmu->dev, "no free AS\n");
726         return -ENODEV;
727
728 found:
729         if (alloc_pdir(as) < 0)
730                 goto err_alloc_pdir;
731
732         spin_lock(&smmu->lock);
733
734         /* Update PDIR register */
735         smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
736         smmu_write(smmu,
737                    SMMU_MK_PDIR(as->pdir_page, as->pdir_attr), SMMU_PTB_DATA);
738         FLUSH_SMMU_REGS(smmu);
739
740         spin_unlock(&smmu->lock);
741
742         spin_unlock_irqrestore(&as->lock, flags);
743         domain->priv = as;
744         dev_dbg(smmu->dev, "smmu_as@%p\n", as);
745         return 0;
746
747 err_alloc_pdir:
748         spin_unlock_irqrestore(&as->lock, flags);
749         return -ENODEV;
750 }
751
752 static void smmu_iommu_domain_destroy(struct iommu_domain *domain)
753 {
754         struct smmu_as *as = domain->priv;
755         struct smmu_device *smmu = as->smmu;
756         unsigned long flags;
757
758         spin_lock_irqsave(&as->lock, flags);
759
760         if (as->pdir_page) {
761                 spin_lock(&smmu->lock);
762                 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
763                 smmu_write(smmu, SMMU_PTB_DATA_RESET_VAL, SMMU_PTB_DATA);
764                 FLUSH_SMMU_REGS(smmu);
765                 spin_unlock(&smmu->lock);
766
767                 free_pdir(as);
768         }
769
770         if (!list_empty(&as->client)) {
771                 struct smmu_client *c;
772
773                 list_for_each_entry(c, &as->client, list)
774                         dev_err(smmu->dev,
775                                 "%s is still attached\n", dev_name(c->dev));
776         }
777
778         spin_unlock_irqrestore(&as->lock, flags);
779
780         domain->priv = NULL;
781         dev_dbg(smmu->dev, "smmu_as@%p\n", as);
782 }
783
784 static int smmu_iommu_attach_dev(struct iommu_domain *domain,
785                                  struct device *dev)
786 {
787         struct smmu_as *as = domain->priv;
788         struct smmu_device *smmu = as->smmu;
789         struct smmu_client *client, *c;
790         u32 map;
791         int err;
792
793         client = devm_kzalloc(smmu->dev, sizeof(*c), GFP_KERNEL);
794         if (!client)
795                 return -ENOMEM;
796         client->dev = dev;
797         client->as = as;
798         map = (unsigned long)dev->platform_data;
799         if (!map)
800                 return -EINVAL;
801
802         err = smmu_client_enable_hwgrp(client, map);
803         if (err)
804                 goto err_hwgrp;
805
806         spin_lock(&as->client_lock);
807         list_for_each_entry(c, &as->client, list) {
808                 if (c->dev == dev) {
809                         dev_err(smmu->dev,
810                                 "%s is already attached\n", dev_name(c->dev));
811                         err = -EINVAL;
812                         goto err_client;
813                 }
814         }
815         list_add(&client->list, &as->client);
816         spin_unlock(&as->client_lock);
817
818         /*
819          * Reserve "page zero" for AVP vectors using a common dummy
820          * page.
821          */
822         if (map & HWG_AVPC) {
823                 struct page *page;
824
825                 page = as->smmu->avp_vector_page;
826                 __smmu_iommu_map_pfn(as, 0, page_to_pfn(page));
827
828                 pr_info("Reserve \"page zero\" for AVP vectors using a common dummy\n");
829         }
830
831         dev_dbg(smmu->dev, "%s is attached\n", dev_name(c->dev));
832         return 0;
833
834 err_client:
835         smmu_client_disable_hwgrp(client);
836         spin_unlock(&as->client_lock);
837 err_hwgrp:
838         devm_kfree(smmu->dev, client);
839         return err;
840 }
841
842 static void smmu_iommu_detach_dev(struct iommu_domain *domain,
843                                   struct device *dev)
844 {
845         struct smmu_as *as = domain->priv;
846         struct smmu_device *smmu = as->smmu;
847         struct smmu_client *c;
848
849         spin_lock(&as->client_lock);
850
851         list_for_each_entry(c, &as->client, list) {
852                 if (c->dev == dev) {
853                         smmu_client_disable_hwgrp(c);
854                         list_del(&c->list);
855                         devm_kfree(smmu->dev, c);
856                         c->as = NULL;
857                         dev_dbg(smmu->dev,
858                                 "%s is detached\n", dev_name(c->dev));
859                         goto out;
860                 }
861         }
862         dev_err(smmu->dev, "Couldn't find %s\n", dev_name(c->dev));
863 out:
864         spin_unlock(&as->client_lock);
865 }
866
867 static struct iommu_ops smmu_iommu_ops = {
868         .domain_init    = smmu_iommu_domain_init,
869         .domain_destroy = smmu_iommu_domain_destroy,
870         .attach_dev     = smmu_iommu_attach_dev,
871         .detach_dev     = smmu_iommu_detach_dev,
872         .map            = smmu_iommu_map,
873         .unmap          = smmu_iommu_unmap,
874         .iova_to_phys   = smmu_iommu_iova_to_phys,
875         .domain_has_cap = smmu_iommu_domain_has_cap,
876 };
877
878 static int tegra_smmu_suspend(struct device *dev)
879 {
880         struct smmu_device *smmu = dev_get_drvdata(dev);
881
882         smmu->translation_enable_0 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_0);
883         smmu->translation_enable_1 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_1);
884         smmu->translation_enable_2 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_2);
885         smmu->asid_security = smmu_read(smmu, SMMU_ASID_SECURITY);
886         return 0;
887 }
888
889 static int tegra_smmu_resume(struct device *dev)
890 {
891         struct smmu_device *smmu = dev_get_drvdata(dev);
892         unsigned long flags;
893
894         spin_lock_irqsave(&smmu->lock, flags);
895         smmu_setup_regs(smmu);
896         spin_unlock_irqrestore(&smmu->lock, flags);
897         return 0;
898 }
899
900 static int tegra_smmu_probe(struct platform_device *pdev)
901 {
902         struct smmu_device *smmu;
903         struct resource *regs, *regs2;
904         struct tegra_smmu_window *window;
905         struct device *dev = &pdev->dev;
906         int i, err = 0;
907
908         BUILD_BUG_ON(PAGE_SHIFT != SMMU_PAGE_SHIFT);
909
910         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
911         regs2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
912         window = tegra_smmu_window(0);
913         if (!regs || !regs2 || !window) {
914                 dev_err(dev, "No SMMU resources\n");
915                 return -ENODEV;
916         }
917
918         smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
919         if (!smmu) {
920                 dev_err(dev, "failed to allocate smmu_device\n");
921                 return -ENOMEM;
922         }
923
924         smmu->dev = dev;
925         smmu->num_as = SMMU_NUM_ASIDS;
926         smmu->iovmm_base = (unsigned long)window->start;
927         smmu->page_count = (window->end + 1 - window->start) >> SMMU_PAGE_SHIFT;
928         smmu->regs = devm_ioremap(dev, regs->start, resource_size(regs));
929         smmu->regs_ahbarb = devm_ioremap(dev, regs2->start,
930                                          resource_size(regs2));
931         if (!smmu->regs || !smmu->regs_ahbarb) {
932                 dev_err(dev, "failed to remap SMMU registers\n");
933                 err = -ENXIO;
934                 goto fail;
935         }
936
937         smmu->translation_enable_0 = ~0;
938         smmu->translation_enable_1 = ~0;
939         smmu->translation_enable_2 = ~0;
940         smmu->asid_security = 0;
941
942         smmu->as = devm_kzalloc(dev,
943                         sizeof(smmu->as[0]) * smmu->num_as, GFP_KERNEL);
944         if (!smmu->as) {
945                 dev_err(dev, "failed to allocate smmu_as\n");
946                 err = -ENOMEM;
947                 goto fail;
948         }
949
950         for (i = 0; i < smmu->num_as; i++) {
951                 struct smmu_as *as = &smmu->as[i];
952
953                 as->smmu = smmu;
954                 as->asid = i;
955                 as->pdir_attr = _PDIR_ATTR;
956                 as->pde_attr = _PDE_ATTR;
957                 as->pte_attr = _PTE_ATTR;
958
959                 spin_lock_init(&as->lock);
960                 INIT_LIST_HEAD(&as->client);
961         }
962         spin_lock_init(&smmu->lock);
963         smmu_setup_regs(smmu);
964         platform_set_drvdata(pdev, smmu);
965         smmu_handle = smmu;
966
967         smmu->avp_vector_page = alloc_page(GFP_KERNEL);
968         if (!smmu->avp_vector_page)
969                 goto fail;
970         return 0;
971
972 fail:
973         if (smmu->avp_vector_page)
974                 __free_page(smmu->avp_vector_page);
975         if (smmu->regs)
976                 devm_iounmap(dev, smmu->regs);
977         if (smmu->regs_ahbarb)
978                 devm_iounmap(dev, smmu->regs_ahbarb);
979         if (smmu && smmu->as) {
980                 for (i = 0; i < smmu->num_as; i++) {
981                         if (smmu->as[i].pdir_page) {
982                                 ClearPageReserved(smmu->as[i].pdir_page);
983                                 __free_page(smmu->as[i].pdir_page);
984                         }
985                 }
986                 devm_kfree(dev, smmu->as);
987         }
988         devm_kfree(dev, smmu);
989         return err;
990 }
991
992 static int tegra_smmu_remove(struct platform_device *pdev)
993 {
994         struct smmu_device *smmu = platform_get_drvdata(pdev);
995         struct device *dev = smmu->dev;
996
997         smmu_write(smmu, SMMU_CONFIG_DISABLE, SMMU_CONFIG);
998         platform_set_drvdata(pdev, NULL);
999         if (smmu->as) {
1000                 int i;
1001
1002                 for (i = 0; i < smmu->num_as; i++)
1003                         free_pdir(&smmu->as[i]);
1004                 devm_kfree(dev, smmu->as);
1005         }
1006         if (smmu->avp_vector_page)
1007                 __free_page(smmu->avp_vector_page);
1008         if (smmu->regs)
1009                 devm_iounmap(dev, smmu->regs);
1010         if (smmu->regs_ahbarb)
1011                 devm_iounmap(dev, smmu->regs_ahbarb);
1012         devm_kfree(dev, smmu);
1013         smmu_handle = NULL;
1014         return 0;
1015 }
1016
1017 const struct dev_pm_ops tegra_smmu_pm_ops = {
1018         .suspend        = tegra_smmu_suspend,
1019         .resume         = tegra_smmu_resume,
1020 };
1021
1022 static struct platform_driver tegra_smmu_driver = {
1023         .probe          = tegra_smmu_probe,
1024         .remove         = tegra_smmu_remove,
1025         .driver = {
1026                 .owner  = THIS_MODULE,
1027                 .name   = "tegra_smmu",
1028                 .pm     = &tegra_smmu_pm_ops,
1029         },
1030 };
1031
1032 static int __devinit tegra_smmu_init(void)
1033 {
1034         register_iommu(&smmu_iommu_ops);
1035         return platform_driver_register(&tegra_smmu_driver);
1036 }
1037
1038 static void __exit tegra_smmu_exit(void)
1039 {
1040         platform_driver_unregister(&tegra_smmu_driver);
1041 }
1042
1043 subsys_initcall(tegra_smmu_init);
1044 module_exit(tegra_smmu_exit);