2 * IOMMU API for SMMU in Tegra30
4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 #define pr_fmt(fmt) "%s(): " fmt, __func__
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/spinlock.h>
25 #include <linux/slab.h>
26 #include <linux/vmalloc.h>
28 #include <linux/pagemap.h>
29 #include <linux/device.h>
30 #include <linux/sched.h>
31 #include <linux/iommu.h>
35 #include <asm/cacheflush.h>
37 #include <mach/iomap.h>
38 #include <mach/smmu.h>
39 #include <mach/tegra_smmu.h>
41 #define SMMU_CONFIG 0x10
42 #define SMMU_CONFIG_DISABLE 0
43 #define SMMU_CONFIG_ENABLE 1
45 #define SMMU_TLB_CONFIG 0x14
46 #define SMMU_TLB_CONFIG_STATS__MASK (1 << 31)
47 #define SMMU_TLB_CONFIG_STATS__ENABLE (1 << 31)
48 #define SMMU_TLB_CONFIG_HIT_UNDER_MISS__ENABLE (1 << 29)
49 #define SMMU_TLB_CONFIG_ACTIVE_LINES__VALUE 0x10
50 #define SMMU_TLB_CONFIG_RESET_VAL 0x20000010
52 #define SMMU_PTC_CONFIG 0x18
53 #define SMMU_PTC_CONFIG_STATS__MASK (1 << 31)
54 #define SMMU_PTC_CONFIG_STATS__ENABLE (1 << 31)
55 #define SMMU_PTC_CONFIG_CACHE__ENABLE (1 << 29)
56 #define SMMU_PTC_CONFIG_INDEX_MAP__PATTERN 0x3f
57 #define SMMU_PTC_CONFIG_RESET_VAL 0x2000003f
59 #define SMMU_PTB_ASID 0x1c
60 #define SMMU_PTB_ASID_CURRENT_SHIFT 0
62 #define SMMU_PTB_DATA 0x20
63 #define SMMU_PTB_DATA_RESET_VAL 0
64 #define SMMU_PTB_DATA_ASID_NONSECURE_SHIFT 29
65 #define SMMU_PTB_DATA_ASID_WRITABLE_SHIFT 30
66 #define SMMU_PTB_DATA_ASID_READABLE_SHIFT 31
68 #define SMMU_TLB_FLUSH 0x30
69 #define SMMU_TLB_FLUSH_VA_MATCH_ALL 0
70 #define SMMU_TLB_FLUSH_VA_MATCH_SECTION 2
71 #define SMMU_TLB_FLUSH_VA_MATCH_GROUP 3
72 #define SMMU_TLB_FLUSH_ASID_SHIFT 29
73 #define SMMU_TLB_FLUSH_ASID_MATCH_DISABLE 0
74 #define SMMU_TLB_FLUSH_ASID_MATCH_ENABLE 1
75 #define SMMU_TLB_FLUSH_ASID_MATCH_SHIFT 31
77 #define SMMU_PTC_FLUSH 0x34
78 #define SMMU_PTC_FLUSH_TYPE_ALL 0
79 #define SMMU_PTC_FLUSH_TYPE_ADR 1
80 #define SMMU_PTC_FLUSH_ADR_SHIFT 4
82 #define SMMU_ASID_SECURITY 0x38
84 #define SMMU_STATS_TLB_HIT_COUNT 0x1f0
85 #define SMMU_STATS_TLB_MISS_COUNT 0x1f4
86 #define SMMU_STATS_PTC_HIT_COUNT 0x1f8
87 #define SMMU_STATS_PTC_MISS_COUNT 0x1fc
89 #define SMMU_TRANSLATION_ENABLE_0 0x228
90 #define SMMU_TRANSLATION_ENABLE_1 0x22c
91 #define SMMU_TRANSLATION_ENABLE_2 0x230
93 #define SMMU_AFI_ASID 0x238 /* PCIE */
94 #define SMMU_AVPC_ASID 0x23c /* AVP */
95 #define SMMU_DC_ASID 0x240 /* Display controller */
96 #define SMMU_DCB_ASID 0x244 /* Display controller B */
97 #define SMMU_EPP_ASID 0x248 /* Encoder pre-processor */
98 #define SMMU_G2_ASID 0x24c /* 2D engine */
99 #define SMMU_HC_ASID 0x250 /* Host1x */
100 #define SMMU_HDA_ASID 0x254 /* High-def audio */
101 #define SMMU_ISP_ASID 0x258 /* Image signal processor */
102 #define SMMU_MPE_ASID 0x264 /* MPEG encoder */
103 #define SMMU_NV_ASID 0x268 /* (3D) */
104 #define SMMU_NV2_ASID 0x26c /* (3D) */
105 #define SMMU_PPCS_ASID 0x270 /* AHB */
106 #define SMMU_SATA_ASID 0x278 /* SATA */
107 #define SMMU_VDE_ASID 0x27c /* Video decoder */
108 #define SMMU_VI_ASID 0x280 /* Video input */
110 #define SMMU_PDE_NEXT_SHIFT 28
112 /* AHB Arbiter Registers */
113 #define AHB_XBAR_CTRL 0xe0
114 #define AHB_XBAR_CTRL_SMMU_INIT_DONE_DONE 1
115 #define AHB_XBAR_CTRL_SMMU_INIT_DONE_SHIFT 17
117 #define SMMU_NUM_ASIDS 4
118 #define SMMU_TLB_FLUSH_VA_SECTION__MASK 0xffc00000
119 #define SMMU_TLB_FLUSH_VA_SECTION__SHIFT 12 /* right shift */
120 #define SMMU_TLB_FLUSH_VA_GROUP__MASK 0xffffc000
121 #define SMMU_TLB_FLUSH_VA_GROUP__SHIFT 12 /* right shift */
122 #define SMMU_TLB_FLUSH_VA(iova, which) \
123 ((((iova) & SMMU_TLB_FLUSH_VA_##which##__MASK) >> \
124 SMMU_TLB_FLUSH_VA_##which##__SHIFT) | \
125 SMMU_TLB_FLUSH_VA_MATCH_##which)
126 #define SMMU_PTB_ASID_CUR(n) \
127 ((n) << SMMU_PTB_ASID_CURRENT_SHIFT)
128 #define SMMU_TLB_FLUSH_ASID_MATCH_disable \
129 (SMMU_TLB_FLUSH_ASID_MATCH_DISABLE << \
130 SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
131 #define SMMU_TLB_FLUSH_ASID_MATCH__ENABLE \
132 (SMMU_TLB_FLUSH_ASID_MATCH_ENABLE << \
133 SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
135 #define SMMU_PAGE_SHIFT 12
136 #define SMMU_PAGE_SIZE (1 << SMMU_PAGE_SHIFT)
138 #define SMMU_PDIR_COUNT 1024
139 #define SMMU_PDIR_SIZE (sizeof(unsigned long) * SMMU_PDIR_COUNT)
140 #define SMMU_PTBL_COUNT 1024
141 #define SMMU_PTBL_SIZE (sizeof(unsigned long) * SMMU_PTBL_COUNT)
142 #define SMMU_PDIR_SHIFT 12
143 #define SMMU_PDE_SHIFT 12
144 #define SMMU_PTE_SHIFT 12
145 #define SMMU_PFN_MASK 0x000fffff
147 #define SMMU_ADDR_TO_PFN(addr) ((addr) >> 12)
148 #define SMMU_ADDR_TO_PDN(addr) ((addr) >> 22)
149 #define SMMU_PDN_TO_ADDR(addr) ((pdn) << 22)
151 #define _READABLE (1 << SMMU_PTB_DATA_ASID_READABLE_SHIFT)
152 #define _WRITABLE (1 << SMMU_PTB_DATA_ASID_WRITABLE_SHIFT)
153 #define _NONSECURE (1 << SMMU_PTB_DATA_ASID_NONSECURE_SHIFT)
154 #define _PDE_NEXT (1 << SMMU_PDE_NEXT_SHIFT)
155 #define _MASK_ATTR (_READABLE | _WRITABLE | _NONSECURE)
157 #define _PDIR_ATTR (_READABLE | _WRITABLE | _NONSECURE)
159 #define _PDE_ATTR (_READABLE | _WRITABLE | _NONSECURE)
160 #define _PDE_ATTR_N (_PDE_ATTR | _PDE_NEXT)
161 #define _PDE_VACANT(pdn) (((pdn) << 10) | _PDE_ATTR)
163 #define _PTE_ATTR (_READABLE | _WRITABLE | _NONSECURE)
164 #define _PTE_VACANT(addr) (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR)
166 #define SMMU_MK_PDIR(page, attr) \
167 ((page_to_phys(page) >> SMMU_PDIR_SHIFT) | (attr))
168 #define SMMU_MK_PDE(page, attr) \
169 (unsigned long)((page_to_phys(page) >> SMMU_PDE_SHIFT) | (attr))
170 #define SMMU_EX_PTBL_PAGE(pde) \
171 pfn_to_page((unsigned long)(pde) & SMMU_PFN_MASK)
172 #define SMMU_PFN_TO_PTE(pfn, attr) (unsigned long)((pfn) | (attr))
174 #define SMMU_ASID_ENABLE(asid) ((asid) | (1 << 31))
175 #define SMMU_ASID_DISABLE 0
176 #define SMMU_ASID_ASID(n) ((n) & ~SMMU_ASID_ENABLE(0))
178 #define smmu_client_enable_hwgrp(c, m) smmu_client_set_hwgrp(c, m, 1)
179 #define smmu_client_disable_hwgrp(c) smmu_client_set_hwgrp(c, 0, 0)
180 #define __smmu_client_enable_hwgrp(c, m) __smmu_client_set_hwgrp(c, m, 1)
181 #define __smmu_client_disable_hwgrp(c) __smmu_client_set_hwgrp(c, 0, 0)
183 #define HWGRP_INIT(client) \
184 [HWGRP_##client] = SMMU_##client##_ASID
186 static const u32 smmu_hwgrp_asid_reg[] = {
204 #define HWGRP_ASID_REG(x) (smmu_hwgrp_asid_reg[x])
207 * Per client for address space
211 struct list_head list;
220 struct smmu_device *smmu; /* back pointer to container */
222 spinlock_t lock; /* for pagetable */
223 struct page *pdir_page;
224 unsigned long pdir_attr;
225 unsigned long pde_attr;
226 unsigned long pte_attr;
227 unsigned int *pte_count;
229 struct list_head client;
230 spinlock_t client_lock; /* for client list */
234 * Per SMMU device - IOMMU device
237 void __iomem *regs, *regs_ahbarb;
238 unsigned long iovmm_base; /* remappable base address */
239 unsigned long page_count; /* total remappable size */
244 struct smmu_as *as; /* Run-time allocated array */
245 struct page *avp_vector_page; /* dummy page shared by all AS's */
248 * Register image savers for suspend/resume
250 unsigned long translation_enable_0;
251 unsigned long translation_enable_1;
252 unsigned long translation_enable_2;
253 unsigned long asid_security;
256 static struct smmu_device *smmu_handle; /* unique for a system */
259 * SMMU/AHB register accessors
261 static inline u32 smmu_read(struct smmu_device *smmu, size_t offs)
263 return readl(smmu->regs + offs);
265 static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs)
267 writel(val, smmu->regs + offs);
270 static inline u32 ahb_read(struct smmu_device *smmu, size_t offs)
272 return readl(smmu->regs_ahbarb + offs);
274 static inline void ahb_write(struct smmu_device *smmu, u32 val, size_t offs)
276 writel(val, smmu->regs_ahbarb + offs);
279 #define VA_PAGE_TO_PA(va, page) \
280 (page_to_phys(page) + ((unsigned long)(va) & ~PAGE_MASK))
282 #define FLUSH_CPU_DCACHE(va, page, size) \
284 unsigned long _pa_ = VA_PAGE_TO_PA(va, page); \
285 __cpuc_flush_dcache_area((void *)(va), (size_t)(size)); \
286 outer_flush_range(_pa_, _pa_+(size_t)(size)); \
290 * Any interaction between any block on PPSB and a block on APB or AHB
291 * must have these read-back barriers to ensure the APB/AHB bus
292 * transaction is complete before initiating activity on the PPSB
295 #define FLUSH_SMMU_REGS(smmu) smmu_read(smmu, SMMU_CONFIG)
297 #define smmu_client_hwgrp(c) (u32)((c)->dev->platform_data)
299 static int __smmu_client_set_hwgrp(struct smmu_client *c,
300 unsigned long map, int on)
303 struct smmu_as *as = c->as;
304 u32 val, offs, mask = SMMU_ASID_ENABLE(as->asid);
305 struct smmu_device *smmu = as->smmu;
311 map = smmu_client_hwgrp(c);
313 for_each_set_bit(i, &map, HWGRP_COUNT) {
314 offs = HWGRP_ASID_REG(i);
315 val = smmu_read(smmu, offs);
317 if (WARN_ON(val & mask))
321 WARN_ON((val & mask) == mask);
324 smmu_write(smmu, val, offs);
326 FLUSH_SMMU_REGS(smmu);
331 for_each_set_bit(i, &map, HWGRP_COUNT) {
332 offs = HWGRP_ASID_REG(i);
333 val = smmu_read(smmu, offs);
335 smmu_write(smmu, val, offs);
340 static int smmu_client_set_hwgrp(struct smmu_client *c, u32 map, int on)
344 struct smmu_as *as = c->as;
345 struct smmu_device *smmu = as->smmu;
347 spin_lock_irqsave(&smmu->lock, flags);
348 val = __smmu_client_set_hwgrp(c, map, on);
349 spin_unlock_irqrestore(&smmu->lock, flags);
354 * Flush all TLB entries and all PTC entries
355 * Caller must lock smmu
357 static void smmu_flush_regs(struct smmu_device *smmu, int enable)
361 smmu_write(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH);
362 FLUSH_SMMU_REGS(smmu);
363 val = SMMU_TLB_FLUSH_VA_MATCH_ALL |
364 SMMU_TLB_FLUSH_ASID_MATCH_disable;
365 smmu_write(smmu, val, SMMU_TLB_FLUSH);
368 smmu_write(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG);
369 FLUSH_SMMU_REGS(smmu);
372 static void smmu_setup_regs(struct smmu_device *smmu)
377 for (i = 0; i < smmu->num_as; i++) {
378 struct smmu_as *as = &smmu->as[i];
379 struct smmu_client *c;
381 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
382 val = as->pdir_page ?
383 SMMU_MK_PDIR(as->pdir_page, as->pdir_attr) :
384 SMMU_PTB_DATA_RESET_VAL;
385 smmu_write(smmu, val, SMMU_PTB_DATA);
387 list_for_each_entry(c, &as->client, list)
388 __smmu_client_set_hwgrp(c, c->hwgrp, 1);
391 smmu_write(smmu, smmu->translation_enable_0, SMMU_TRANSLATION_ENABLE_0);
392 smmu_write(smmu, smmu->translation_enable_1, SMMU_TRANSLATION_ENABLE_1);
393 smmu_write(smmu, smmu->translation_enable_2, SMMU_TRANSLATION_ENABLE_2);
394 smmu_write(smmu, smmu->asid_security, SMMU_ASID_SECURITY);
395 smmu_write(smmu, SMMU_TLB_CONFIG_RESET_VAL, SMMU_TLB_CONFIG);
396 smmu_write(smmu, SMMU_PTC_CONFIG_RESET_VAL, SMMU_PTC_CONFIG);
398 smmu_flush_regs(smmu, 1);
400 val = ahb_read(smmu, AHB_XBAR_CTRL);
401 val |= AHB_XBAR_CTRL_SMMU_INIT_DONE_DONE <<
402 AHB_XBAR_CTRL_SMMU_INIT_DONE_SHIFT;
403 ahb_write(smmu, val, AHB_XBAR_CTRL);
406 static void flush_ptc_and_tlb(struct smmu_device *smmu,
407 struct smmu_as *as, dma_addr_t iova,
408 unsigned long *pte, struct page *page, int is_pde)
411 unsigned long tlb_flush_va = is_pde
412 ? SMMU_TLB_FLUSH_VA(iova, SECTION)
413 : SMMU_TLB_FLUSH_VA(iova, GROUP);
415 val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pte, page);
416 smmu_write(smmu, val, SMMU_PTC_FLUSH);
417 FLUSH_SMMU_REGS(smmu);
419 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE |
420 (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT);
421 smmu_write(smmu, val, SMMU_TLB_FLUSH);
422 FLUSH_SMMU_REGS(smmu);
425 static void free_ptbl(struct smmu_as *as, dma_addr_t iova)
427 unsigned long pdn = SMMU_ADDR_TO_PDN(iova);
428 unsigned long *pdir = (unsigned long *)page_address(as->pdir_page);
430 if (pdir[pdn] != _PDE_VACANT(pdn)) {
431 dev_dbg(as->smmu->dev, "pdn: %lx\n", pdn);
433 ClearPageReserved(SMMU_EX_PTBL_PAGE(pdir[pdn]));
434 __free_page(SMMU_EX_PTBL_PAGE(pdir[pdn]));
435 pdir[pdn] = _PDE_VACANT(pdn);
436 FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]);
437 flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn],
442 static void free_pdir(struct smmu_as *as)
446 struct device *dev = as->smmu->dev;
451 addr = as->smmu->iovmm_base;
452 count = as->smmu->page_count;
453 while (count-- > 0) {
455 addr += SMMU_PAGE_SIZE * SMMU_PTBL_COUNT;
457 ClearPageReserved(as->pdir_page);
458 __free_page(as->pdir_page);
459 as->pdir_page = NULL;
460 devm_kfree(dev, as->pte_count);
461 as->pte_count = NULL;
465 * Maps PTBL for given iova and returns the PTE address
466 * Caller must unmap the mapped PTBL returned in *ptbl_page_p
468 static unsigned long *locate_pte(struct smmu_as *as,
469 dma_addr_t iova, bool allocate,
470 struct page **ptbl_page_p,
471 unsigned int **count)
473 unsigned long ptn = SMMU_ADDR_TO_PFN(iova);
474 unsigned long pdn = SMMU_ADDR_TO_PDN(iova);
475 unsigned long *pdir = page_address(as->pdir_page);
478 if (pdir[pdn] != _PDE_VACANT(pdn)) {
479 /* Mapped entry table already exists */
480 *ptbl_page_p = SMMU_EX_PTBL_PAGE(pdir[pdn]);
481 ptbl = page_address(*ptbl_page_p);
482 } else if (!allocate) {
486 unsigned long addr = SMMU_PDN_TO_ADDR(pdn);
488 /* Vacant - allocate a new page table */
489 dev_dbg(as->smmu->dev, "New PTBL pdn: %lx\n", pdn);
491 *ptbl_page_p = alloc_page(GFP_ATOMIC);
493 dev_err(as->smmu->dev,
494 "failed to allocate smmu_device page table\n");
497 SetPageReserved(*ptbl_page_p);
498 ptbl = (unsigned long *)page_address(*ptbl_page_p);
499 for (pn = 0; pn < SMMU_PTBL_COUNT;
500 pn++, addr += SMMU_PAGE_SIZE) {
501 ptbl[pn] = _PTE_VACANT(addr);
503 FLUSH_CPU_DCACHE(ptbl, *ptbl_page_p, SMMU_PTBL_SIZE);
504 pdir[pdn] = SMMU_MK_PDE(*ptbl_page_p,
505 as->pde_attr | _PDE_NEXT);
506 FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]);
507 flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn],
510 *count = &as->pte_count[pdn];
512 return &ptbl[ptn % SMMU_PTBL_COUNT];
515 #ifdef CONFIG_SMMU_SIG_DEBUG
516 static void put_signature(struct smmu_as *as,
517 dma_addr_t iova, unsigned long pfn)
520 unsigned long *vaddr;
522 page = pfn_to_page(pfn);
523 vaddr = page_address(page);
528 vaddr[1] = pfn << PAGE_SHIFT;
529 FLUSH_CPU_DCACHE(vaddr, page, sizeof(vaddr[0]) * 2);
532 static inline void put_signature(struct smmu_as *as,
533 unsigned long addr, unsigned long pfn)
539 * Caller must lock/unlock as
541 static int alloc_pdir(struct smmu_as *as)
546 struct smmu_device *smmu = as->smmu;
551 as->pte_count = devm_kzalloc(smmu->dev,
552 sizeof(as->pte_count[0]) * SMMU_PDIR_COUNT, GFP_KERNEL);
553 if (!as->pte_count) {
555 "failed to allocate smmu_device PTE cunters\n");
558 as->pdir_page = alloc_page(GFP_KERNEL | __GFP_DMA);
559 if (!as->pdir_page) {
561 "failed to allocate smmu_device page directory\n");
562 devm_kfree(smmu->dev, as->pte_count);
563 as->pte_count = NULL;
566 SetPageReserved(as->pdir_page);
567 pdir = page_address(as->pdir_page);
569 for (pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++)
570 pdir[pdn] = _PDE_VACANT(pdn);
571 FLUSH_CPU_DCACHE(pdir, as->pdir_page, SMMU_PDIR_SIZE);
572 val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pdir, as->pdir_page);
573 smmu_write(smmu, val, SMMU_PTC_FLUSH);
574 FLUSH_SMMU_REGS(as->smmu);
575 val = SMMU_TLB_FLUSH_VA_MATCH_ALL |
576 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE |
577 (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT);
578 smmu_write(smmu, val, SMMU_TLB_FLUSH);
579 FLUSH_SMMU_REGS(as->smmu);
584 static void __smmu_iommu_unmap(struct smmu_as *as, dma_addr_t iova)
590 pte = locate_pte(as, iova, false, &page, &count);
594 if (WARN_ON(*pte == _PTE_VACANT(iova)))
597 *pte = _PTE_VACANT(iova);
598 FLUSH_CPU_DCACHE(pte, page, sizeof(*pte));
599 flush_ptc_and_tlb(as->smmu, as, iova, pte, page, 0);
602 smmu_flush_regs(as->smmu, 0);
606 static void __smmu_iommu_map_pfn(struct smmu_as *as, dma_addr_t iova,
609 struct smmu_device *smmu = as->smmu;
614 pte = locate_pte(as, iova, true, &page, &count);
618 if (*pte == _PTE_VACANT(iova))
620 *pte = SMMU_PFN_TO_PTE(pfn, as->pte_attr);
621 if (unlikely((*pte == _PTE_VACANT(iova))))
623 FLUSH_CPU_DCACHE(pte, page, sizeof(*pte));
624 flush_ptc_and_tlb(smmu, as, iova, pte, page, 0);
625 put_signature(as, iova, pfn);
628 static int smmu_iommu_map(struct iommu_domain *domain, unsigned long iova,
629 phys_addr_t pa, int order, int prot)
631 unsigned long count = (PAGE_SIZE << order) >> SMMU_PAGE_SHIFT;
632 struct smmu_as *as = domain->priv;
633 unsigned long pfn = __phys_to_pfn(pa);
637 dev_dbg(as->smmu->dev,
638 "[%d] %08lx:%08x(%ld)\n", as->asid, iova, pa, count);
640 spin_lock_irqsave(&as->lock, flags);
641 for (i = 0; i < count; i++, pfn++) {
645 __smmu_iommu_map_pfn(as, iova, pfn);
646 iova += SMMU_PAGE_SIZE;
648 spin_unlock_irqrestore(&as->lock, flags);
653 iova -= SMMU_PAGE_SIZE;
654 __smmu_iommu_unmap(as, iova);
656 spin_unlock_irqrestore(&as->lock, flags);
660 static int smmu_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
663 struct smmu_as *as = domain->priv;
664 unsigned long count = (PAGE_SIZE << gfp_order) >> SMMU_PAGE_SHIFT;
668 dev_dbg(as->smmu->dev, "[%d] %08lx(%ld)\n", as->asid, iova, count);
670 spin_lock_irqsave(&as->lock, flags);
671 for (i = 0; i < count; i++) {
672 __smmu_iommu_unmap(as, iova);
673 iova += SMMU_PAGE_SIZE;
675 spin_unlock_irqrestore(&as->lock, flags);
679 static phys_addr_t smmu_iommu_iova_to_phys(struct iommu_domain *domain,
682 struct smmu_as *as = domain->priv;
689 spin_lock_irqsave(&as->lock, flags);
691 pte = locate_pte(as, iova, true, &page, &count);
692 pfn = *pte & SMMU_PFN_MASK;
693 WARN_ON(!pfn_valid(pfn));
694 dev_dbg(as->smmu->dev,
695 "iova:%08lx pfn:%08lx asid:%d\n", iova, pfn, as->asid);
697 spin_unlock_irqrestore(&as->lock, flags);
698 return PFN_PHYS(pfn);
701 static int smmu_iommu_domain_has_cap(struct iommu_domain *domain,
707 static int smmu_iommu_domain_init(struct iommu_domain *domain)
712 struct smmu_device *smmu = smmu_handle;
714 /* Look for a free AS with lock held */
715 for (i = 0; i < smmu->num_as; i++) {
716 struct smmu_as *tmp = &smmu->as[i];
718 spin_lock_irqsave(&tmp->lock, flags);
719 if (!tmp->pdir_page) {
723 spin_unlock_irqrestore(&tmp->lock, flags);
725 dev_err(smmu->dev, "no free AS\n");
729 if (alloc_pdir(as) < 0)
732 spin_lock(&smmu->lock);
734 /* Update PDIR register */
735 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
737 SMMU_MK_PDIR(as->pdir_page, as->pdir_attr), SMMU_PTB_DATA);
738 FLUSH_SMMU_REGS(smmu);
740 spin_unlock(&smmu->lock);
742 spin_unlock_irqrestore(&as->lock, flags);
744 dev_dbg(smmu->dev, "smmu_as@%p\n", as);
748 spin_unlock_irqrestore(&as->lock, flags);
752 static void smmu_iommu_domain_destroy(struct iommu_domain *domain)
754 struct smmu_as *as = domain->priv;
755 struct smmu_device *smmu = as->smmu;
758 spin_lock_irqsave(&as->lock, flags);
761 spin_lock(&smmu->lock);
762 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
763 smmu_write(smmu, SMMU_PTB_DATA_RESET_VAL, SMMU_PTB_DATA);
764 FLUSH_SMMU_REGS(smmu);
765 spin_unlock(&smmu->lock);
770 if (!list_empty(&as->client)) {
771 struct smmu_client *c;
773 list_for_each_entry(c, &as->client, list)
775 "%s is still attached\n", dev_name(c->dev));
778 spin_unlock_irqrestore(&as->lock, flags);
781 dev_dbg(smmu->dev, "smmu_as@%p\n", as);
784 static int smmu_iommu_attach_dev(struct iommu_domain *domain,
787 struct smmu_as *as = domain->priv;
788 struct smmu_device *smmu = as->smmu;
789 struct smmu_client *client, *c;
793 client = devm_kzalloc(smmu->dev, sizeof(*c), GFP_KERNEL);
798 map = (unsigned long)dev->platform_data;
802 err = smmu_client_enable_hwgrp(client, map);
806 spin_lock(&as->client_lock);
807 list_for_each_entry(c, &as->client, list) {
810 "%s is already attached\n", dev_name(c->dev));
815 list_add(&client->list, &as->client);
816 spin_unlock(&as->client_lock);
819 * Reserve "page zero" for AVP vectors using a common dummy
822 if (map & HWG_AVPC) {
825 page = as->smmu->avp_vector_page;
826 __smmu_iommu_map_pfn(as, 0, page_to_pfn(page));
828 pr_info("Reserve \"page zero\" for AVP vectors using a common dummy\n");
831 dev_dbg(smmu->dev, "%s is attached\n", dev_name(c->dev));
835 smmu_client_disable_hwgrp(client);
836 spin_unlock(&as->client_lock);
838 devm_kfree(smmu->dev, client);
842 static void smmu_iommu_detach_dev(struct iommu_domain *domain,
845 struct smmu_as *as = domain->priv;
846 struct smmu_device *smmu = as->smmu;
847 struct smmu_client *c;
849 spin_lock(&as->client_lock);
851 list_for_each_entry(c, &as->client, list) {
853 smmu_client_disable_hwgrp(c);
855 devm_kfree(smmu->dev, c);
858 "%s is detached\n", dev_name(c->dev));
862 dev_err(smmu->dev, "Couldn't find %s\n", dev_name(c->dev));
864 spin_unlock(&as->client_lock);
867 static struct iommu_ops smmu_iommu_ops = {
868 .domain_init = smmu_iommu_domain_init,
869 .domain_destroy = smmu_iommu_domain_destroy,
870 .attach_dev = smmu_iommu_attach_dev,
871 .detach_dev = smmu_iommu_detach_dev,
872 .map = smmu_iommu_map,
873 .unmap = smmu_iommu_unmap,
874 .iova_to_phys = smmu_iommu_iova_to_phys,
875 .domain_has_cap = smmu_iommu_domain_has_cap,
878 static int tegra_smmu_suspend(struct device *dev)
880 struct smmu_device *smmu = dev_get_drvdata(dev);
882 smmu->translation_enable_0 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_0);
883 smmu->translation_enable_1 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_1);
884 smmu->translation_enable_2 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_2);
885 smmu->asid_security = smmu_read(smmu, SMMU_ASID_SECURITY);
889 static int tegra_smmu_resume(struct device *dev)
891 struct smmu_device *smmu = dev_get_drvdata(dev);
894 spin_lock_irqsave(&smmu->lock, flags);
895 smmu_setup_regs(smmu);
896 spin_unlock_irqrestore(&smmu->lock, flags);
900 static int tegra_smmu_probe(struct platform_device *pdev)
902 struct smmu_device *smmu;
903 struct resource *regs, *regs2;
904 struct tegra_smmu_window *window;
905 struct device *dev = &pdev->dev;
908 BUILD_BUG_ON(PAGE_SHIFT != SMMU_PAGE_SHIFT);
910 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
911 regs2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
912 window = tegra_smmu_window(0);
913 if (!regs || !regs2 || !window) {
914 dev_err(dev, "No SMMU resources\n");
918 smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
920 dev_err(dev, "failed to allocate smmu_device\n");
925 smmu->num_as = SMMU_NUM_ASIDS;
926 smmu->iovmm_base = (unsigned long)window->start;
927 smmu->page_count = (window->end + 1 - window->start) >> SMMU_PAGE_SHIFT;
928 smmu->regs = devm_ioremap(dev, regs->start, resource_size(regs));
929 smmu->regs_ahbarb = devm_ioremap(dev, regs2->start,
930 resource_size(regs2));
931 if (!smmu->regs || !smmu->regs_ahbarb) {
932 dev_err(dev, "failed to remap SMMU registers\n");
937 smmu->translation_enable_0 = ~0;
938 smmu->translation_enable_1 = ~0;
939 smmu->translation_enable_2 = ~0;
940 smmu->asid_security = 0;
942 smmu->as = devm_kzalloc(dev,
943 sizeof(smmu->as[0]) * smmu->num_as, GFP_KERNEL);
945 dev_err(dev, "failed to allocate smmu_as\n");
950 for (i = 0; i < smmu->num_as; i++) {
951 struct smmu_as *as = &smmu->as[i];
955 as->pdir_attr = _PDIR_ATTR;
956 as->pde_attr = _PDE_ATTR;
957 as->pte_attr = _PTE_ATTR;
959 spin_lock_init(&as->lock);
960 INIT_LIST_HEAD(&as->client);
962 spin_lock_init(&smmu->lock);
963 smmu_setup_regs(smmu);
964 platform_set_drvdata(pdev, smmu);
967 smmu->avp_vector_page = alloc_page(GFP_KERNEL);
968 if (!smmu->avp_vector_page)
973 if (smmu->avp_vector_page)
974 __free_page(smmu->avp_vector_page);
976 devm_iounmap(dev, smmu->regs);
977 if (smmu->regs_ahbarb)
978 devm_iounmap(dev, smmu->regs_ahbarb);
979 if (smmu && smmu->as) {
980 for (i = 0; i < smmu->num_as; i++) {
981 if (smmu->as[i].pdir_page) {
982 ClearPageReserved(smmu->as[i].pdir_page);
983 __free_page(smmu->as[i].pdir_page);
986 devm_kfree(dev, smmu->as);
988 devm_kfree(dev, smmu);
992 static int tegra_smmu_remove(struct platform_device *pdev)
994 struct smmu_device *smmu = platform_get_drvdata(pdev);
995 struct device *dev = smmu->dev;
997 smmu_write(smmu, SMMU_CONFIG_DISABLE, SMMU_CONFIG);
998 platform_set_drvdata(pdev, NULL);
1002 for (i = 0; i < smmu->num_as; i++)
1003 free_pdir(&smmu->as[i]);
1004 devm_kfree(dev, smmu->as);
1006 if (smmu->avp_vector_page)
1007 __free_page(smmu->avp_vector_page);
1009 devm_iounmap(dev, smmu->regs);
1010 if (smmu->regs_ahbarb)
1011 devm_iounmap(dev, smmu->regs_ahbarb);
1012 devm_kfree(dev, smmu);
1017 const struct dev_pm_ops tegra_smmu_pm_ops = {
1018 .suspend = tegra_smmu_suspend,
1019 .resume = tegra_smmu_resume,
1022 static struct platform_driver tegra_smmu_driver = {
1023 .probe = tegra_smmu_probe,
1024 .remove = tegra_smmu_remove,
1026 .owner = THIS_MODULE,
1027 .name = "tegra_smmu",
1028 .pm = &tegra_smmu_pm_ops,
1032 static int __devinit tegra_smmu_init(void)
1034 register_iommu(&smmu_iommu_ops);
1035 return platform_driver_register(&tegra_smmu_driver);
1038 static void __exit tegra_smmu_exit(void)
1040 platform_driver_unregister(&tegra_smmu_driver);
1043 subsys_initcall(tegra_smmu_init);
1044 module_exit(tegra_smmu_exit);