Merge commit 'main-jb-2012.08.03-B4' into t114-0806
[linux-2.6.git] / drivers / iommu / tegra-smmu.c
1 /*
2  * IOMMU API for SMMU in Tegra30
3  *
4  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along with
16  * this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18  */
19
20 #define pr_fmt(fmt)     "%s(): " fmt, __func__
21
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/spinlock.h>
25 #include <linux/slab.h>
26 #include <linux/vmalloc.h>
27 #include <linux/mm.h>
28 #include <linux/pagemap.h>
29 #include <linux/device.h>
30 #include <linux/sched.h>
31 #include <linux/iommu.h>
32 #include <linux/io.h>
33 #include <linux/of.h>
34 #include <linux/of_iommu.h>
35 #include <linux/debugfs.h>
36 #include <linux/seq_file.h>
37
38 #include <asm/page.h>
39 #include <asm/cacheflush.h>
40
41 #include <mach/iomap.h>
42 #include <mach/smmu.h>
43 #include <mach/tegra_smmu.h>
44
45 /* REVISIT: With new configurations for t114/124/148 passed from DT */
46 #define SKIP_SWGRP_CHECK
47
48 /* bitmap of the page sizes currently supported */
49 #define SMMU_IOMMU_PGSIZES      (SZ_4K)
50
51 #define SMMU_CONFIG                             0x10
52 #define SMMU_CONFIG_DISABLE                     0
53 #define SMMU_CONFIG_ENABLE                      1
54
55 /* REVISIT: To support multiple MCs */
56 enum {
57         _MC = 0,
58 };
59
60 enum {
61         _TLB = 0,
62         _PTC,
63 };
64
65 #define SMMU_CACHE_CONFIG_BASE                  0x14
66 #define __SMMU_CACHE_CONFIG(mc, cache)          (SMMU_CACHE_CONFIG_BASE + 4 * cache)
67 #define SMMU_CACHE_CONFIG(cache)                __SMMU_CACHE_CONFIG(_MC, cache)
68
69 #define SMMU_CACHE_CONFIG_STATS_SHIFT           31
70 #define SMMU_CACHE_CONFIG_STATS_MASK            (1 << SMMU_CACHE_CONFIG_STATS_SHIFT)
71 #define SMMU_CACHE_CONFIG_STATS_ENABLE          (1 << SMMU_CACHE_CONFIG_STATS_SHIFT)
72 #define SMMU_CACHE_CONFIG_STATS_TEST_SHIFT      30
73 #define SMMU_CACHE_CONFIG_STATS_TEST_MASK       (1 << SMMU_CACHE_CONFIG_STATS_TEST_SHIFT)
74 #define SMMU_CACHE_CONFIG_STATS_TEST            (1 << SMMU_CACHE_CONFIG_STATS_TEST_SHIFT)
75
76 #define SMMU_TLB_CONFIG_HIT_UNDER_MISS__ENABLE  (1 << 29)
77 #define SMMU_TLB_CONFIG_ACTIVE_LINES__VALUE     0x10
78 #define SMMU_TLB_CONFIG_RESET_VAL               0x20000010
79
80 #define SMMU_PTC_CONFIG_CACHE__ENABLE           (1 << 29)
81 #define SMMU_PTC_CONFIG_INDEX_MAP__PATTERN      0x3f
82 #define SMMU_PTC_CONFIG_RESET_VAL               0x2000003f
83
84 #define SMMU_PTB_ASID                           0x1c
85 #define SMMU_PTB_ASID_CURRENT_SHIFT             0
86
87 #define SMMU_PTB_DATA                           0x20
88 #define SMMU_PTB_DATA_RESET_VAL                 0
89 #define SMMU_PTB_DATA_ASID_NONSECURE_SHIFT      29
90 #define SMMU_PTB_DATA_ASID_WRITABLE_SHIFT       30
91 #define SMMU_PTB_DATA_ASID_READABLE_SHIFT       31
92
93 #define SMMU_TLB_FLUSH                          0x30
94 #define SMMU_TLB_FLUSH_VA_MATCH_ALL             0
95 #define SMMU_TLB_FLUSH_VA_MATCH_SECTION         2
96 #define SMMU_TLB_FLUSH_VA_MATCH_GROUP           3
97 #define SMMU_TLB_FLUSH_ASID_SHIFT               29
98 #define SMMU_TLB_FLUSH_ASID_MATCH_DISABLE       0
99 #define SMMU_TLB_FLUSH_ASID_MATCH_ENABLE        1
100 #define SMMU_TLB_FLUSH_ASID_MATCH_SHIFT         31
101
102 #define SMMU_PTC_FLUSH                          0x34
103 #define SMMU_PTC_FLUSH_TYPE_ALL                 0
104 #define SMMU_PTC_FLUSH_TYPE_ADR                 1
105 #define SMMU_PTC_FLUSH_ADR_SHIFT                4
106
107 #define SMMU_ASID_SECURITY                      0x38
108
109 #define SMMU_STATS_CACHE_COUNT_BASE             0x1f0
110
111 #define SMMU_STATS_CACHE_COUNT(mc, cache, hitmiss)              \
112         (SMMU_STATS_CACHE_COUNT_BASE + 8 * cache + 4 * hitmiss)
113
114 #define SMMU_TRANSLATION_ENABLE_0               0x228
115 #define SMMU_TRANSLATION_ENABLE_1               0x22c
116 #define SMMU_TRANSLATION_ENABLE_2               0x230
117
118 #define SMMU_AFI_ASID   0x238   /* PCIE */
119 #define SMMU_AVPC_ASID  0x23c   /* AVP */
120 #define SMMU_DC_ASID    0x240   /* Display controller */
121 #define SMMU_DCB_ASID   0x244   /* Display controller B */
122 #define SMMU_EPP_ASID   0x248   /* Encoder pre-processor */
123 #define SMMU_G2_ASID    0x24c   /* 2D engine */
124 #define SMMU_HC_ASID    0x250   /* Host1x */
125 #define SMMU_HDA_ASID   0x254   /* High-def audio */
126 #define SMMU_ISP_ASID   0x258   /* Image signal processor */
127 #define SMMU_MPE_ASID   0x264   /* MPEG encoder */
128 #define SMMU_NV_ASID    0x268   /* (3D) */
129 #define SMMU_NV2_ASID   0x26c   /* (3D) */
130 #define SMMU_PPCS_ASID  0x270   /* AHB */
131 #define SMMU_SATA_ASID  0x278   /* SATA */
132 #define SMMU_VDE_ASID   0x27c   /* Video decoder */
133 #define SMMU_VI_ASID    0x280   /* Video input */
134
135 #define SMMU_PDE_NEXT_SHIFT             28
136
137 /* AHB Arbiter Registers */
138 #define AHB_XBAR_CTRL                           0xe0
139 #define AHB_XBAR_CTRL_SMMU_INIT_DONE_DONE       1
140 #define AHB_XBAR_CTRL_SMMU_INIT_DONE_SHIFT      17
141
142 #define SMMU_NUM_ASIDS                          4
143 #define SMMU_TLB_FLUSH_VA_SECTION__MASK         0xffc00000
144 #define SMMU_TLB_FLUSH_VA_SECTION__SHIFT        12 /* right shift */
145 #define SMMU_TLB_FLUSH_VA_GROUP__MASK           0xffffc000
146 #define SMMU_TLB_FLUSH_VA_GROUP__SHIFT          12 /* right shift */
147 #define SMMU_TLB_FLUSH_VA(iova, which)  \
148         ((((iova) & SMMU_TLB_FLUSH_VA_##which##__MASK) >> \
149                 SMMU_TLB_FLUSH_VA_##which##__SHIFT) |   \
150         SMMU_TLB_FLUSH_VA_MATCH_##which)
151 #define SMMU_PTB_ASID_CUR(n)    \
152                 ((n) << SMMU_PTB_ASID_CURRENT_SHIFT)
153 #define SMMU_TLB_FLUSH_ASID_MATCH_disable               \
154                 (SMMU_TLB_FLUSH_ASID_MATCH_DISABLE <<   \
155                         SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
156 #define SMMU_TLB_FLUSH_ASID_MATCH__ENABLE               \
157                 (SMMU_TLB_FLUSH_ASID_MATCH_ENABLE <<    \
158                         SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
159
160 #define SMMU_PAGE_SHIFT 12
161 #define SMMU_PAGE_SIZE  (1 << SMMU_PAGE_SHIFT)
162
163 #define SMMU_PDIR_COUNT 1024
164 #define SMMU_PDIR_SIZE  (sizeof(unsigned long) * SMMU_PDIR_COUNT)
165 #define SMMU_PTBL_COUNT 1024
166 #define SMMU_PTBL_SIZE  (sizeof(unsigned long) * SMMU_PTBL_COUNT)
167 #define SMMU_PDIR_SHIFT 12
168 #define SMMU_PDE_SHIFT  12
169 #define SMMU_PTE_SHIFT  12
170 #define SMMU_PFN_MASK   0x000fffff
171
172 #define SMMU_ADDR_TO_PFN(addr)  ((addr) >> 12)
173 #define SMMU_ADDR_TO_PDN(addr)  ((addr) >> 22)
174 #define SMMU_PDN_TO_ADDR(addr)  ((pdn) << 22)
175
176 #define _READABLE       (1 << SMMU_PTB_DATA_ASID_READABLE_SHIFT)
177 #define _WRITABLE       (1 << SMMU_PTB_DATA_ASID_WRITABLE_SHIFT)
178 #define _NONSECURE      (1 << SMMU_PTB_DATA_ASID_NONSECURE_SHIFT)
179 #define _PDE_NEXT       (1 << SMMU_PDE_NEXT_SHIFT)
180 #define _MASK_ATTR      (_READABLE | _WRITABLE | _NONSECURE)
181
182 #define _PDIR_ATTR      (_READABLE | _WRITABLE | _NONSECURE)
183
184 #define _PDE_ATTR       (_READABLE | _WRITABLE | _NONSECURE)
185 #define _PDE_ATTR_N     (_PDE_ATTR | _PDE_NEXT)
186 #define _PDE_VACANT(pdn)        (0)
187
188 #define _PTE_ATTR       (_READABLE | _WRITABLE | _NONSECURE)
189 #define _PTE_VACANT(addr)       (0)
190
191 #ifdef  CONFIG_TEGRA_IOMMU_SMMU_LINEAR
192 #undef  _PDE_VACANT(pdn)
193 #undef  _PTE_VACANT(addr)
194 #define _PDE_VACANT(pdn)        (((pdn) << 10) | _PDE_ATTR)
195 #define _PTE_VACANT(addr)       (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR)
196 #endif
197
198 #define SMMU_MK_PDIR(page, attr)        \
199                 ((page_to_phys(page) >> SMMU_PDIR_SHIFT) | (attr))
200 #define SMMU_MK_PDE(page, attr)         \
201                 (unsigned long)((page_to_phys(page) >> SMMU_PDE_SHIFT) | (attr))
202 #define SMMU_EX_PTBL_PAGE(pde)          \
203                 pfn_to_page((unsigned long)(pde) & SMMU_PFN_MASK)
204 #define SMMU_PFN_TO_PTE(pfn, attr)      (unsigned long)((pfn) | (attr))
205
206 #define SMMU_ASID_ENABLE(asid)  ((asid) | (1 << 31))
207 #define SMMU_ASID_DISABLE       0
208 #define SMMU_ASID_ASID(n)       ((n) & ~SMMU_ASID_ENABLE(0))
209
210 #define smmu_client_enable_hwgrp(c, m)  smmu_client_set_hwgrp(c, m, 1)
211 #define smmu_client_disable_hwgrp(c)    smmu_client_set_hwgrp(c, 0, 0)
212 #define __smmu_client_enable_hwgrp(c, m) __smmu_client_set_hwgrp(c, m, 1)
213 #define __smmu_client_disable_hwgrp(c)  __smmu_client_set_hwgrp(c, 0, 0)
214
215 #define HWGRP_INIT(client) [HWGRP_##client] = SMMU_##client##_ASID
216
217 static const u32 smmu_hwgrp_asid_reg[] = {
218         HWGRP_INIT(AFI),
219         HWGRP_INIT(AVPC),
220         HWGRP_INIT(DC),
221         HWGRP_INIT(DCB),
222         HWGRP_INIT(EPP),
223         HWGRP_INIT(G2),
224         HWGRP_INIT(HC),
225         HWGRP_INIT(HDA),
226         HWGRP_INIT(ISP),
227         HWGRP_INIT(MPE),
228         HWGRP_INIT(NV),
229         HWGRP_INIT(NV2),
230         HWGRP_INIT(PPCS),
231         HWGRP_INIT(SATA),
232         HWGRP_INIT(VDE),
233         HWGRP_INIT(VI),
234 };
235 #define HWGRP_ASID_REG(x) (smmu_hwgrp_asid_reg[x])
236
237 /*
238  * Per client for address space
239  */
240 struct smmu_client {
241         struct device           *dev;
242         struct list_head        list;
243         struct smmu_as          *as;
244         u32                     hwgrp;
245 };
246
247 /*
248  * Per address space
249  */
250 struct smmu_as {
251         struct smmu_device      *smmu;  /* back pointer to container */
252         unsigned int            asid;
253         spinlock_t              lock;   /* for pagetable */
254         struct page             *pdir_page;
255         unsigned long           pdir_attr;
256         unsigned long           pde_attr;
257         unsigned long           pte_attr;
258         unsigned int            *pte_count;
259
260         struct list_head        client;
261         spinlock_t              client_lock; /* for client list */
262 };
263
264 /*
265  * Per SMMU device - IOMMU device
266  */
267 struct smmu_device {
268         void __iomem    *regs, *regs_ahbarb;
269         unsigned long   iovmm_base;     /* remappable base address */
270         unsigned long   page_count;     /* total remappable size */
271         spinlock_t      lock;
272         char            *name;
273         struct device   *dev;
274         int             num_as;
275         struct smmu_as  *as;            /* Run-time allocated array */
276         struct page *avp_vector_page;   /* dummy page shared by all AS's */
277
278         /*
279          * Register image savers for suspend/resume
280          */
281         unsigned long translation_enable_0;
282         unsigned long translation_enable_1;
283         unsigned long translation_enable_2;
284         unsigned long asid_security;
285
286         struct dentry *debugfs_root;
287
288         struct device_node *ahb;
289
290         int             num_as;
291         struct smmu_as  as[0];          /* Run-time allocated array */
292 };
293
294 static struct smmu_device *smmu_handle; /* unique for a system */
295
296 /*
297  *      SMMU/AHB register accessors
298  */
299 static inline u32 smmu_read(struct smmu_device *smmu, size_t offs)
300 {
301         return readl(smmu->regs + offs);
302 }
303 static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs)
304 {
305         writel(val, smmu->regs + offs);
306 }
307
308 static inline u32 ahb_read(struct smmu_device *smmu, size_t offs)
309 {
310         return readl(smmu->regs_ahbarb + offs);
311 }
312 static inline void ahb_write(struct smmu_device *smmu, u32 val, size_t offs)
313 {
314         writel(val, smmu->regs_ahbarb + offs);
315 }
316
317 #define VA_PAGE_TO_PA(va, page) \
318         (page_to_phys(page) + ((unsigned long)(va) & ~PAGE_MASK))
319
320 #define FLUSH_CPU_DCACHE(va, page, size)        \
321         do {    \
322                 unsigned long _pa_ = VA_PAGE_TO_PA(va, page);           \
323                 __cpuc_flush_dcache_area((void *)(va), (size_t)(size)); \
324                 outer_flush_range(_pa_, _pa_+(size_t)(size));           \
325         } while (0)
326
327 /*
328  * Any interaction between any block on PPSB and a block on APB or AHB
329  * must have these read-back barriers to ensure the APB/AHB bus
330  * transaction is complete before initiating activity on the PPSB
331  * block.
332  */
333 #define FLUSH_SMMU_REGS(smmu)   smmu_read(smmu, SMMU_CONFIG)
334
335 #define smmu_client_hwgrp(c) (u32)((c)->dev->platform_data)
336
337 static int __smmu_client_set_hwgrp(struct smmu_client *c,
338                                    unsigned long map, int on)
339 {
340         int i;
341         struct smmu_as *as = c->as;
342         u32 val, offs, mask = SMMU_ASID_ENABLE(as->asid);
343         struct smmu_device *smmu = as->smmu;
344
345         WARN_ON(!on && map);
346         if (on && !map)
347                 return -EINVAL;
348         if (!on)
349                 map = smmu_client_hwgrp(c);
350
351         for_each_set_bit(i, &map, HWGRP_COUNT) {
352                 offs = HWGRP_ASID_REG(i);
353                 val = smmu_read(smmu, offs);
354                 if (on) {
355 #if !defined(SKIP_SWGRP_CHECK)
356                         if (WARN_ON(val & mask)) {
357                                 for_each_set_bit(i, &map, HWGRP_COUNT) {
358                                         offs = HWGRP_ASID_REG(i);
359                                         val = smmu_read(smmu, offs);
360                                         val &= ~mask;
361                                         smmu_write(smmu, val, offs);
362                                 }
363                                 return -EBUSY;
364                         }
365 #endif
366                         val |= mask;
367                 } else {
368 #if !defined(SKIP_SWGRP_CHECK)
369                         WARN_ON((val & mask) == mask);
370 #endif
371                         val &= ~mask;
372                 }
373                 smmu_write(smmu, val, offs);
374         }
375         FLUSH_SMMU_REGS(smmu);
376         c->hwgrp = map;
377         return 0;
378
379 }
380
381 static int smmu_client_set_hwgrp(struct smmu_client *c, u32 map, int on)
382 {
383         u32 val;
384         unsigned long flags;
385         struct smmu_as *as = c->as;
386         struct smmu_device *smmu = as->smmu;
387
388         spin_lock_irqsave(&smmu->lock, flags);
389         val = __smmu_client_set_hwgrp(c, map, on);
390         spin_unlock_irqrestore(&smmu->lock, flags);
391         return val;
392 }
393
394 /*
395  * Flush all TLB entries and all PTC entries
396  * Caller must lock smmu
397  */
398 static void smmu_flush_regs(struct smmu_device *smmu, int enable)
399 {
400         u32 val;
401
402         smmu_write(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH);
403         FLUSH_SMMU_REGS(smmu);
404         val = SMMU_TLB_FLUSH_VA_MATCH_ALL |
405                 SMMU_TLB_FLUSH_ASID_MATCH_disable;
406         smmu_write(smmu, val, SMMU_TLB_FLUSH);
407
408         if (enable)
409                 smmu_write(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG);
410         FLUSH_SMMU_REGS(smmu);
411 }
412
413 static void smmu_setup_regs(struct smmu_device *smmu)
414 {
415         int i;
416         u32 val;
417
418         for (i = 0; i < smmu->num_as; i++) {
419                 struct smmu_as *as = &smmu->as[i];
420                 struct smmu_client *c;
421
422                 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
423                 val = as->pdir_page ?
424                         SMMU_MK_PDIR(as->pdir_page, as->pdir_attr) :
425                         SMMU_PTB_DATA_RESET_VAL;
426                 smmu_write(smmu, val, SMMU_PTB_DATA);
427
428                 list_for_each_entry(c, &as->client, list)
429                         __smmu_client_set_hwgrp(c, c->hwgrp, 1);
430         }
431
432         smmu_write(smmu, smmu->translation_enable_0, SMMU_TRANSLATION_ENABLE_0);
433         smmu_write(smmu, smmu->translation_enable_1, SMMU_TRANSLATION_ENABLE_1);
434         smmu_write(smmu, smmu->translation_enable_2, SMMU_TRANSLATION_ENABLE_2);
435         smmu_write(smmu, smmu->asid_security, SMMU_ASID_SECURITY);
436         smmu_write(smmu, SMMU_TLB_CONFIG_RESET_VAL, SMMU_CACHE_CONFIG(_TLB));
437         smmu_write(smmu, SMMU_PTC_CONFIG_RESET_VAL, SMMU_CACHE_CONFIG(_PTC));
438
439         smmu_flush_regs(smmu, 1);
440
441         val = ahb_read(smmu, AHB_XBAR_CTRL);
442         val |= AHB_XBAR_CTRL_SMMU_INIT_DONE_DONE <<
443                 AHB_XBAR_CTRL_SMMU_INIT_DONE_SHIFT;
444         ahb_write(smmu, val, AHB_XBAR_CTRL);
445 }
446
447 static void flush_ptc_and_tlb(struct smmu_device *smmu,
448                       struct smmu_as *as, dma_addr_t iova,
449                       unsigned long *pte, struct page *page, int is_pde)
450 {
451         u32 val;
452         unsigned long tlb_flush_va = is_pde
453                 ?  SMMU_TLB_FLUSH_VA(iova, SECTION)
454                 :  SMMU_TLB_FLUSH_VA(iova, GROUP);
455
456         val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pte, page);
457         smmu_write(smmu, val, SMMU_PTC_FLUSH);
458         FLUSH_SMMU_REGS(smmu);
459         val = tlb_flush_va |
460                 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE |
461                 (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT);
462         smmu_write(smmu, val, SMMU_TLB_FLUSH);
463         FLUSH_SMMU_REGS(smmu);
464 }
465
466 static void free_ptbl(struct smmu_as *as, dma_addr_t iova)
467 {
468         unsigned long pdn = SMMU_ADDR_TO_PDN(iova);
469         unsigned long *pdir = (unsigned long *)page_address(as->pdir_page);
470
471         if (pdir[pdn] != _PDE_VACANT(pdn)) {
472                 dev_dbg(as->smmu->dev, "pdn: %lx\n", pdn);
473
474                 ClearPageReserved(SMMU_EX_PTBL_PAGE(pdir[pdn]));
475                 __free_page(SMMU_EX_PTBL_PAGE(pdir[pdn]));
476                 pdir[pdn] = _PDE_VACANT(pdn);
477                 FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]);
478                 flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn],
479                                   as->pdir_page, 1);
480         }
481 }
482
483 static void free_pdir(struct smmu_as *as)
484 {
485         unsigned addr;
486         int count;
487         struct device *dev = as->smmu->dev;
488
489         if (!as->pdir_page)
490                 return;
491
492         addr = as->smmu->iovmm_base;
493         count = as->smmu->page_count;
494         while (count-- > 0) {
495                 free_ptbl(as, addr);
496                 addr += SMMU_PAGE_SIZE * SMMU_PTBL_COUNT;
497         }
498         ClearPageReserved(as->pdir_page);
499         __free_page(as->pdir_page);
500         as->pdir_page = NULL;
501         devm_kfree(dev, as->pte_count);
502         as->pte_count = NULL;
503 }
504
505 /*
506  * Maps PTBL for given iova and returns the PTE address
507  * Caller must unmap the mapped PTBL returned in *ptbl_page_p
508  */
509 static unsigned long *locate_pte(struct smmu_as *as,
510                                  dma_addr_t iova, bool allocate,
511                                  struct page **ptbl_page_p,
512                                  unsigned int **count)
513 {
514         unsigned long ptn = SMMU_ADDR_TO_PFN(iova);
515         unsigned long pdn = SMMU_ADDR_TO_PDN(iova);
516         unsigned long *pdir = page_address(as->pdir_page);
517         unsigned long *ptbl;
518
519         if (pdir[pdn] != _PDE_VACANT(pdn)) {
520                 /* Mapped entry table already exists */
521                 *ptbl_page_p = SMMU_EX_PTBL_PAGE(pdir[pdn]);
522                 ptbl = page_address(*ptbl_page_p);
523         } else if (!allocate) {
524                 return NULL;
525         } else {
526                 int pn;
527                 unsigned long addr = SMMU_PDN_TO_ADDR(pdn);
528
529                 /* Vacant - allocate a new page table */
530                 dev_dbg(as->smmu->dev, "New PTBL pdn: %lx\n", pdn);
531
532                 *ptbl_page_p = alloc_page(GFP_ATOMIC);
533                 if (!*ptbl_page_p) {
534                         dev_err(as->smmu->dev,
535                                 "failed to allocate smmu_device page table\n");
536                         return NULL;
537                 }
538                 SetPageReserved(*ptbl_page_p);
539                 ptbl = (unsigned long *)page_address(*ptbl_page_p);
540                 for (pn = 0; pn < SMMU_PTBL_COUNT;
541                      pn++, addr += SMMU_PAGE_SIZE) {
542                         ptbl[pn] = _PTE_VACANT(addr);
543                 }
544                 FLUSH_CPU_DCACHE(ptbl, *ptbl_page_p, SMMU_PTBL_SIZE);
545                 pdir[pdn] = SMMU_MK_PDE(*ptbl_page_p,
546                                         as->pde_attr | _PDE_NEXT);
547                 FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]);
548                 flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn],
549                                   as->pdir_page, 1);
550         }
551         *count = &as->pte_count[pdn];
552
553         return &ptbl[ptn % SMMU_PTBL_COUNT];
554 }
555
556 #ifdef CONFIG_SMMU_SIG_DEBUG
557 static void put_signature(struct smmu_as *as,
558                           dma_addr_t iova, unsigned long pfn)
559 {
560         struct page *page;
561         unsigned long *vaddr;
562
563         page = pfn_to_page(pfn);
564         vaddr = page_address(page);
565         if (!vaddr)
566                 return;
567
568         vaddr[0] = iova;
569         vaddr[1] = pfn << PAGE_SHIFT;
570         FLUSH_CPU_DCACHE(vaddr, page, sizeof(vaddr[0]) * 2);
571 }
572 #else
573 static inline void put_signature(struct smmu_as *as,
574                                  unsigned long addr, unsigned long pfn)
575 {
576 }
577 #endif
578
579 /*
580  * Caller must not hold as->lock
581  */
582 static int alloc_pdir(struct smmu_as *as)
583 {
584         unsigned long *pdir, flags;
585         int pdn, err = 0;
586         u32 val;
587         struct smmu_device *smmu = as->smmu;
588         struct page *page;
589         unsigned int *cnt;
590
591         /*
592          * do the allocation outside the as lock
593          */
594         cnt = devm_kzalloc(smmu->dev,
595                            sizeof(cnt[0]) * SMMU_PDIR_COUNT, GFP_KERNEL);
596         page = alloc_page(GFP_KERNEL | __GFP_DMA);
597
598         spin_lock_irqsave(&as->lock, flags);
599
600         if (as->pdir_page) {
601                 /* We raced, free the redundant */
602                 err = -EAGAIN;
603                 goto err_out;
604         }
605
606         if (!page || !cnt) {
607                 dev_err(smmu->dev, "failed to allocate at %s\n", __func__);
608                 err = -ENOMEM;
609                 goto err_out;
610         }
611
612         as->pdir_page = page;
613         as->pte_count = cnt;
614
615         SetPageReserved(as->pdir_page);
616         pdir = page_address(as->pdir_page);
617
618         for (pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++)
619                 pdir[pdn] = _PDE_VACANT(pdn);
620         FLUSH_CPU_DCACHE(pdir, as->pdir_page, SMMU_PDIR_SIZE);
621         val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pdir, as->pdir_page);
622         smmu_write(smmu, val, SMMU_PTC_FLUSH);
623         FLUSH_SMMU_REGS(as->smmu);
624         val = SMMU_TLB_FLUSH_VA_MATCH_ALL |
625                 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE |
626                 (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT);
627         smmu_write(smmu, val, SMMU_TLB_FLUSH);
628         FLUSH_SMMU_REGS(as->smmu);
629
630         spin_unlock_irqrestore(&as->lock, flags);
631
632         return 0;
633
634 err_out:
635         spin_unlock_irqrestore(&as->lock, flags);
636
637         devm_kfree(smmu->dev, cnt);
638         if (page)
639                 __free_page(page);
640         return err;
641 }
642
643 static void __smmu_iommu_unmap(struct smmu_as *as, dma_addr_t iova)
644 {
645         unsigned long *pte;
646         struct page *page;
647         unsigned int *count;
648
649         pte = locate_pte(as, iova, false, &page, &count);
650         if (WARN_ON(!pte))
651                 return;
652
653         if (WARN_ON(*pte == _PTE_VACANT(iova)))
654                 return;
655
656         *pte = _PTE_VACANT(iova);
657         FLUSH_CPU_DCACHE(pte, page, sizeof(*pte));
658         flush_ptc_and_tlb(as->smmu, as, iova, pte, page, 0);
659         if (!--(*count)) {
660                 free_ptbl(as, iova);
661                 smmu_flush_regs(as->smmu, 0);
662         }
663 }
664
665 static void __smmu_iommu_map_pfn(struct smmu_as *as, dma_addr_t iova,
666                                  unsigned long pfn)
667 {
668         struct smmu_device *smmu = as->smmu;
669         unsigned long *pte;
670         unsigned int *count;
671         struct page *page;
672
673         pte = locate_pte(as, iova, true, &page, &count);
674         if (WARN_ON(!pte))
675                 return;
676
677         if (*pte == _PTE_VACANT(iova))
678                 (*count)++;
679         *pte = SMMU_PFN_TO_PTE(pfn, as->pte_attr);
680         if (unlikely((*pte == _PTE_VACANT(iova))))
681                 (*count)--;
682         FLUSH_CPU_DCACHE(pte, page, sizeof(*pte));
683         flush_ptc_and_tlb(smmu, as, iova, pte, page, 0);
684         put_signature(as, iova, pfn);
685 }
686
687 static int smmu_iommu_map(struct iommu_domain *domain, unsigned long iova,
688                           phys_addr_t pa, size_t bytes, int prot)
689 {
690         struct smmu_as *as = domain->priv;
691         unsigned long pfn = __phys_to_pfn(pa);
692         unsigned long flags;
693
694         dev_dbg(as->smmu->dev, "[%d] %08lx:%08x\n", as->asid, iova, pa);
695
696         if (!pfn_valid(pfn))
697                 return -ENOMEM;
698
699         spin_lock_irqsave(&as->lock, flags);
700         __smmu_iommu_map_pfn(as, iova, pfn);
701         spin_unlock_irqrestore(&as->lock, flags);
702         return 0;
703 }
704
705 static size_t smmu_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
706                                size_t bytes)
707 {
708         struct smmu_as *as = domain->priv;
709         unsigned long flags;
710
711         dev_dbg(as->smmu->dev, "[%d] %08lx\n", as->asid, iova);
712
713         spin_lock_irqsave(&as->lock, flags);
714         __smmu_iommu_unmap(as, iova);
715         spin_unlock_irqrestore(&as->lock, flags);
716         return SMMU_PAGE_SIZE;
717 }
718
719 static phys_addr_t smmu_iommu_iova_to_phys(struct iommu_domain *domain,
720                                            unsigned long iova)
721 {
722         struct smmu_as *as = domain->priv;
723         unsigned long *pte;
724         unsigned int *count;
725         struct page *page;
726         unsigned long pfn;
727         unsigned long flags;
728
729         spin_lock_irqsave(&as->lock, flags);
730
731         pte = locate_pte(as, iova, true, &page, &count);
732         pfn = *pte & SMMU_PFN_MASK;
733         WARN_ON(!pfn_valid(pfn));
734         dev_dbg(as->smmu->dev,
735                 "iova:%08lx pfn:%08lx asid:%d\n", iova, pfn, as->asid);
736
737         spin_unlock_irqrestore(&as->lock, flags);
738         return PFN_PHYS(pfn);
739 }
740
741 static int smmu_iommu_domain_has_cap(struct iommu_domain *domain,
742                                      unsigned long cap)
743 {
744         return 0;
745 }
746
747 static int smmu_iommu_attach_dev(struct iommu_domain *domain,
748                                  struct device *dev)
749 {
750         struct smmu_as *as = domain->priv;
751         struct smmu_device *smmu = as->smmu;
752         struct smmu_client *client, *c;
753         u32 map;
754         int err;
755
756         client = devm_kzalloc(smmu->dev, sizeof(*c), GFP_KERNEL);
757         if (!client)
758                 return -ENOMEM;
759         client->dev = dev;
760         client->as = as;
761
762 #ifdef SKIP_SWGRP_CHECK
763         /* Enable all SWGRP blindly by default */
764         map = (1 << HWGRP_COUNT) - 1;
765 #else
766         map = (unsigned long)dev->platform_data;
767         if (!map)
768                 return -EINVAL;
769 #endif
770
771         err = smmu_client_enable_hwgrp(client, map);
772         if (err)
773                 goto err_hwgrp;
774
775         spin_lock(&as->client_lock);
776         list_for_each_entry(c, &as->client, list) {
777                 if (c->dev == dev) {
778                         dev_err(smmu->dev,
779                                 "%s is already attached\n", dev_name(c->dev));
780                         err = -EINVAL;
781                         goto err_client;
782                 }
783         }
784         list_add(&client->list, &as->client);
785         spin_unlock(&as->client_lock);
786
787         /*
788          * Reserve "page zero" for AVP vectors using a common dummy
789          * page.
790          */
791         if (map & HWG_AVPC) {
792                 struct page *page;
793
794                 page = as->smmu->avp_vector_page;
795                 __smmu_iommu_map_pfn(as, 0, page_to_pfn(page));
796
797                 pr_info("Reserve \"page zero\" for AVP vectors using a common dummy\n");
798         }
799
800         dev_dbg(smmu->dev, "%s is attached\n", dev_name(dev));
801         return 0;
802
803 err_client:
804         smmu_client_disable_hwgrp(client);
805         spin_unlock(&as->client_lock);
806 err_hwgrp:
807         devm_kfree(smmu->dev, client);
808         return err;
809 }
810
811 static void smmu_iommu_detach_dev(struct iommu_domain *domain,
812                                   struct device *dev)
813 {
814         struct smmu_as *as = domain->priv;
815         struct smmu_device *smmu = as->smmu;
816         struct smmu_client *c;
817
818         spin_lock(&as->client_lock);
819
820         list_for_each_entry(c, &as->client, list) {
821                 if (c->dev == dev) {
822                         smmu_client_disable_hwgrp(c);
823                         list_del(&c->list);
824                         devm_kfree(smmu->dev, c);
825                         c->as = NULL;
826                         dev_dbg(smmu->dev,
827                                 "%s is detached\n", dev_name(c->dev));
828                         goto out;
829                 }
830         }
831         dev_err(smmu->dev, "Couldn't find %s\n", dev_name(c->dev));
832 out:
833         spin_unlock(&as->client_lock);
834 }
835
836 #if !defined(CONFIG_TEGRA_IOMMU_SMMU_LINEAR)
837 static inline void __smmu_iommu_map_linear(struct smmu_as *as,
838                                            unsigned long start, size_t size)
839 {
840         int i;
841         unsigned long count = size >> PAGE_SHIFT;
842
843         for (i = 0; i < count; i++) {
844                 unsigned long addr;
845
846                 addr = start + i * PAGE_SIZE;
847                 __smmu_iommu_map_pfn(as, addr, __phys_to_pfn(addr));
848         }
849 }
850
851 void smmu_iommu_map_linear(unsigned long start, size_t size)
852 {
853         int i;
854         struct smmu_device *smmu = smmu_handle;
855
856         for  (i = 0; i < smmu->num_as; i++) {
857                 struct smmu_as *as;
858
859                 as = &smmu->as[i];
860                 if (!as->pdir_page)
861                         continue;
862
863                 __smmu_iommu_map_linear(as, start, size);
864
865                 dev_dbg(smmu->dev, "%s as[%d]: %08lx(%x)\n",
866                         __func__, i, start, size);
867         }
868 }
869 EXPORT_SYMBOL_GPL(smmu_iommu_map_linear);
870 #endif
871
872 static int smmu_iommu_domain_init(struct iommu_domain *domain)
873 {
874         int i, err = -EAGAIN;
875         unsigned long flags;
876         struct smmu_as *as;
877         struct smmu_device *smmu = smmu_handle;
878
879         /* Look for a free AS with lock held */
880         for  (i = 0; i < smmu->num_as; i++) {
881                 as = &smmu->as[i];
882
883                 if (as->pdir_page)
884                         continue;
885
886                 err = alloc_pdir(as);
887                 if (!err)
888                         goto found;
889
890                 if (err != -EAGAIN)
891                         break;
892         }
893         if (i == smmu->num_as)
894                 dev_err(smmu->dev,  "no free AS\n");
895         return err;
896
897 found:
898         spin_lock_irqsave(&smmu->lock, flags);
899
900         /* Update PDIR register */
901         smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
902         smmu_write(smmu,
903                    SMMU_MK_PDIR(as->pdir_page, as->pdir_attr), SMMU_PTB_DATA);
904         FLUSH_SMMU_REGS(smmu);
905
906         spin_unlock_irqrestore(&smmu->lock, flags);
907
908         domain->priv = as;
909
910         dev_dbg(smmu->dev, "smmu_as@%p\n", as);
911         return 0;
912 }
913
914 static void smmu_iommu_domain_destroy(struct iommu_domain *domain)
915 {
916         struct smmu_as *as = domain->priv;
917         struct smmu_device *smmu = as->smmu;
918         unsigned long flags;
919
920         spin_lock_irqsave(&as->lock, flags);
921
922         if (as->pdir_page) {
923                 spin_lock(&smmu->lock);
924                 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
925                 smmu_write(smmu, SMMU_PTB_DATA_RESET_VAL, SMMU_PTB_DATA);
926                 FLUSH_SMMU_REGS(smmu);
927                 spin_unlock(&smmu->lock);
928
929                 free_pdir(as);
930         }
931
932         if (!list_empty(&as->client)) {
933                 struct smmu_client *c;
934
935                 list_for_each_entry(c, &as->client, list)
936                         smmu_iommu_detach_dev(domain, c->dev);
937         }
938
939         spin_unlock_irqrestore(&as->lock, flags);
940
941         domain->priv = NULL;
942         dev_dbg(smmu->dev, "smmu_as@%p\n", as);
943 }
944
945 static struct iommu_ops smmu_iommu_ops = {
946         .domain_init    = smmu_iommu_domain_init,
947         .domain_destroy = smmu_iommu_domain_destroy,
948         .attach_dev     = smmu_iommu_attach_dev,
949         .detach_dev     = smmu_iommu_detach_dev,
950         .map            = smmu_iommu_map,
951         .unmap          = smmu_iommu_unmap,
952         .iova_to_phys   = smmu_iommu_iova_to_phys,
953         .domain_has_cap = smmu_iommu_domain_has_cap,
954         .pgsize_bitmap  = SMMU_IOMMU_PGSIZES,
955 };
956
957 static const char * const smmu_debugfs_mc[] = { "mc", };
958 static const char * const smmu_debugfs_cache[] = {  "tlb", "ptc", };
959
960 static ssize_t smmu_debugfs_stats_write(struct file *file,
961                                         const char __user *buffer,
962                                         size_t count, loff_t *pos)
963 {
964         struct smmu_device *smmu;
965         struct dentry *dent;
966         int i, cache, mc;
967         enum {
968                 _OFF = 0,
969                 _ON,
970                 _RESET,
971         };
972         const char * const command[] = {
973                 [_OFF]          = "off",
974                 [_ON]           = "on",
975                 [_RESET]        = "reset",
976         };
977         char str[] = "reset";
978         u32 val;
979         size_t offs;
980
981         count = min_t(size_t, count, sizeof(str));
982         if (copy_from_user(str, buffer, count))
983                 return -EINVAL;
984
985         for (i = 0; i < ARRAY_SIZE(command); i++)
986                 if (strncmp(str, command[i],
987                             strlen(command[i])) == 0)
988                         break;
989
990         if (i == ARRAY_SIZE(command))
991                 return -EINVAL;
992
993         dent = file->f_dentry;
994         cache = (int)dent->d_inode->i_private;
995         mc = (int)dent->d_parent->d_inode->i_private;
996         smmu = dent->d_parent->d_parent->d_inode->i_private;
997
998         offs = SMMU_CACHE_CONFIG(cache);
999         val = smmu_read(smmu, offs);
1000         switch (i) {
1001         case _OFF:
1002                 val &= ~SMMU_CACHE_CONFIG_STATS_ENABLE;
1003                 val &= ~SMMU_CACHE_CONFIG_STATS_TEST;
1004                 smmu_write(smmu, val, offs);
1005                 break;
1006         case _ON:
1007                 val |= SMMU_CACHE_CONFIG_STATS_ENABLE;
1008                 val &= ~SMMU_CACHE_CONFIG_STATS_TEST;
1009                 smmu_write(smmu, val, offs);
1010                 break;
1011         case _RESET:
1012                 val |= SMMU_CACHE_CONFIG_STATS_TEST;
1013                 smmu_write(smmu, val, offs);
1014                 val &= ~SMMU_CACHE_CONFIG_STATS_TEST;
1015                 smmu_write(smmu, val, offs);
1016                 break;
1017         default:
1018                 BUG();
1019                 break;
1020         }
1021
1022         dev_dbg(smmu->dev, "%s() %08x, %08x @%08x\n", __func__,
1023                 val, smmu_read(smmu, offs), offs);
1024
1025         return count;
1026 }
1027
1028 static int smmu_debugfs_stats_show(struct seq_file *s, void *v)
1029 {
1030         struct smmu_device *smmu;
1031         struct dentry *dent;
1032         int i, cache, mc;
1033         const char * const stats[] = { "hit", "miss", };
1034
1035         dent = d_find_alias(s->private);
1036         cache = (int)dent->d_inode->i_private;
1037         mc = (int)dent->d_parent->d_inode->i_private;
1038         smmu = dent->d_parent->d_parent->d_inode->i_private;
1039
1040         for (i = 0; i < ARRAY_SIZE(stats); i++) {
1041                 u32 val;
1042                 size_t offs;
1043
1044                 offs = SMMU_STATS_CACHE_COUNT(mc, cache, i);
1045                 val = smmu_read(smmu, offs);
1046                 seq_printf(s, "%s:%08x ", stats[i], val);
1047
1048                 dev_dbg(smmu->dev, "%s() %s %08x @%08x\n", __func__,
1049                         stats[i], val, offs);
1050         }
1051         seq_printf(s, "\n");
1052
1053         return 0;
1054 }
1055
1056 static int smmu_debugfs_stats_open(struct inode *inode, struct file *file)
1057 {
1058         return single_open(file, smmu_debugfs_stats_show, inode);
1059 }
1060
1061 static const struct file_operations smmu_debugfs_stats_fops = {
1062         .open           = smmu_debugfs_stats_open,
1063         .read           = seq_read,
1064         .llseek         = seq_lseek,
1065         .release        = single_release,
1066         .write          = smmu_debugfs_stats_write,
1067 };
1068
1069 static void smmu_debugfs_delete(struct smmu_device *smmu)
1070 {
1071         debugfs_remove_recursive(smmu->debugfs_root);
1072 }
1073
1074 static void smmu_debugfs_create(struct smmu_device *smmu)
1075 {
1076         int i;
1077         struct dentry *root;
1078
1079         root = debugfs_create_file("smmu",
1080                                    S_IFDIR | S_IRWXU | S_IRUGO | S_IXUGO,
1081                                    NULL, smmu, NULL);
1082         if (!root)
1083                 goto err_out;
1084         smmu->debugfs_root = root;
1085
1086         for (i = 0; i < ARRAY_SIZE(smmu_debugfs_mc); i++) {
1087                 int j;
1088                 struct dentry *mc;
1089
1090                 mc = debugfs_create_file(smmu_debugfs_mc[i],
1091                                          S_IFDIR | S_IRWXU | S_IRUGO | S_IXUGO,
1092                                          root, (void *)i, NULL);
1093                 if (!mc)
1094                         goto err_out;
1095
1096                 for (j = 0; j < ARRAY_SIZE(smmu_debugfs_cache); j++) {
1097                         struct dentry *cache;
1098
1099                         cache = debugfs_create_file(smmu_debugfs_cache[j],
1100                                                     S_IWUGO | S_IRUGO, mc,
1101                                                     (void *)j,
1102                                                     &smmu_debugfs_stats_fops);
1103                         if (!cache)
1104                                 goto err_out;
1105                 }
1106         }
1107
1108         return;
1109
1110 err_out:
1111         smmu_debugfs_delete(smmu);
1112 }
1113
1114 static int tegra_smmu_suspend(struct device *dev)
1115 {
1116         struct smmu_device *smmu = dev_get_drvdata(dev);
1117
1118         smmu->translation_enable_0 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_0);
1119         smmu->translation_enable_1 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_1);
1120         smmu->translation_enable_2 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_2);
1121         smmu->asid_security = smmu_read(smmu, SMMU_ASID_SECURITY);
1122         return 0;
1123 }
1124
1125 static int tegra_smmu_resume(struct device *dev)
1126 {
1127         struct smmu_device *smmu = dev_get_drvdata(dev);
1128         unsigned long flags;
1129
1130         spin_lock_irqsave(&smmu->lock, flags);
1131         smmu_setup_regs(smmu);
1132         spin_unlock_irqrestore(&smmu->lock, flags);
1133         return 0;
1134 }
1135
1136 static int tegra_smmu_probe(struct platform_device *pdev)
1137 {
1138         struct smmu_device *smmu;
1139         struct resource *regs, *regs2, *window;
1140         struct device *dev = &pdev->dev;
1141         int i, err = 0;
1142
1143         if (smmu_handle)
1144                 return -EIO;
1145
1146         BUILD_BUG_ON(PAGE_SHIFT != SMMU_PAGE_SHIFT);
1147
1148         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1149         regs2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1150         window = tegra_smmu_window(0);
1151         if (!regs || !regs2 || !window) {
1152                 dev_err(dev, "No SMMU resources\n");
1153                 return -ENODEV;
1154         }
1155
1156         smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
1157         if (!smmu) {
1158                 dev_err(dev, "failed to allocate smmu_device\n");
1159                 return -ENOMEM;
1160         }
1161
1162         smmu->dev = dev;
1163         smmu->num_as = SMMU_NUM_ASIDS;
1164         smmu->iovmm_base = (unsigned long)window->start;
1165         smmu->page_count = (window->end + 1 - window->start) >> SMMU_PAGE_SHIFT;
1166         smmu->regs = devm_ioremap(dev, regs->start, resource_size(regs));
1167         smmu->regs_ahbarb = devm_ioremap(dev, regs2->start,
1168                                          resource_size(regs2));
1169         if (!smmu->regs || !smmu->regs_ahbarb) {
1170                 dev_err(dev, "failed to remap SMMU registers\n");
1171                 err = -ENXIO;
1172                 goto fail;
1173         }
1174
1175         smmu->translation_enable_0 = ~0;
1176         smmu->translation_enable_1 = ~0;
1177         smmu->translation_enable_2 = ~0;
1178         smmu->asid_security = 0;
1179
1180         smmu->as = devm_kzalloc(dev,
1181                         sizeof(smmu->as[0]) * smmu->num_as, GFP_KERNEL);
1182         if (!smmu->as) {
1183                 dev_err(dev, "failed to allocate smmu_as\n");
1184                 err = -ENOMEM;
1185                 goto fail;
1186         }
1187
1188         for (i = 0; i < smmu->num_as; i++) {
1189                 struct smmu_as *as = &smmu->as[i];
1190
1191                 as->smmu = smmu;
1192                 as->asid = i;
1193                 as->pdir_attr = _PDIR_ATTR;
1194                 as->pde_attr = _PDE_ATTR;
1195                 as->pte_attr = _PTE_ATTR;
1196
1197                 spin_lock_init(&as->lock);
1198                 INIT_LIST_HEAD(&as->client);
1199         }
1200         spin_lock_init(&smmu->lock);
1201         smmu_setup_regs(smmu);
1202         platform_set_drvdata(pdev, smmu);
1203
1204         smmu->avp_vector_page = alloc_page(GFP_KERNEL);
1205         if (!smmu->avp_vector_page)
1206                 goto fail;
1207
1208         smmu_debugfs_create(smmu);
1209         smmu_handle = smmu;
1210         return 0;
1211
1212 fail:
1213         if (smmu->avp_vector_page)
1214                 __free_page(smmu->avp_vector_page);
1215         if (smmu->regs)
1216                 devm_iounmap(dev, smmu->regs);
1217         if (smmu->regs_ahbarb)
1218                 devm_iounmap(dev, smmu->regs_ahbarb);
1219         if (smmu && smmu->as) {
1220                 for (i = 0; i < smmu->num_as; i++) {
1221                         if (smmu->as[i].pdir_page) {
1222                                 ClearPageReserved(smmu->as[i].pdir_page);
1223                                 __free_page(smmu->as[i].pdir_page);
1224                         }
1225                 }
1226                 devm_kfree(dev, smmu->as);
1227         }
1228         devm_kfree(dev, smmu);
1229         return err;
1230 }
1231
1232 static int tegra_smmu_remove(struct platform_device *pdev)
1233 {
1234         struct smmu_device *smmu = platform_get_drvdata(pdev);
1235         struct device *dev = smmu->dev;
1236
1237         smmu_debugfs_delete(smmu);
1238
1239         smmu_write(smmu, SMMU_CONFIG_DISABLE, SMMU_CONFIG);
1240         platform_set_drvdata(pdev, NULL);
1241         if (smmu->as) {
1242                 int i;
1243
1244                 for (i = 0; i < smmu->num_as; i++)
1245                         free_pdir(&smmu->as[i]);
1246                 devm_kfree(dev, smmu->as);
1247         }
1248         if (smmu->avp_vector_page)
1249                 __free_page(smmu->avp_vector_page);
1250         if (smmu->regs)
1251                 devm_iounmap(dev, smmu->regs);
1252         if (smmu->regs_ahbarb)
1253                 devm_iounmap(dev, smmu->regs_ahbarb);
1254         devm_kfree(dev, smmu);
1255         smmu_handle = NULL;
1256         return 0;
1257 }
1258
1259 const struct dev_pm_ops tegra_smmu_pm_ops = {
1260         .suspend        = tegra_smmu_suspend,
1261         .resume         = tegra_smmu_resume,
1262 };
1263
1264 static struct platform_driver tegra_smmu_driver = {
1265         .probe          = tegra_smmu_probe,
1266         .remove         = tegra_smmu_remove,
1267         .driver = {
1268                 .owner  = THIS_MODULE,
1269                 .name   = "tegra_smmu",
1270                 .pm     = &tegra_smmu_pm_ops,
1271         },
1272 };
1273
1274 static int __devinit tegra_smmu_init(void)
1275 {
1276         bus_set_iommu(&platform_bus_type, &smmu_iommu_ops);
1277         return platform_driver_register(&tegra_smmu_driver);
1278 }
1279
1280 static void __exit tegra_smmu_exit(void)
1281 {
1282         platform_driver_unregister(&tegra_smmu_driver);
1283 }
1284
1285 core_initcall(tegra_smmu_init);
1286 module_exit(tegra_smmu_exit);
1287
1288 MODULE_DESCRIPTION("IOMMU API for SMMU in Tegra30");
1289 MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
1290 MODULE_LICENSE("GPL v2");