622d7d0774a835da21430192dc92e373b21e5407
[linux-2.6.git] / drivers / iommu / tegra-smmu.c
1 /*
2  * IOMMU API for SMMU in Tegra30
3  *
4  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along with
16  * this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18  */
19
20 #define pr_fmt(fmt)     "%s(): " fmt, __func__
21
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/spinlock.h>
25 #include <linux/slab.h>
26 #include <linux/vmalloc.h>
27 #include <linux/mm.h>
28 #include <linux/pagemap.h>
29 #include <linux/device.h>
30 #include <linux/sched.h>
31 #include <linux/iommu.h>
32 #include <linux/io.h>
33 #include <linux/of.h>
34 #include <linux/of_iommu.h>
35 #include <linux/debugfs.h>
36 #include <linux/seq_file.h>
37
38 #include <asm/page.h>
39 #include <asm/cacheflush.h>
40
41 #include <mach/iomap.h>
42 #include <mach/smmu.h>
43 #include <mach/tegra_smmu.h>
44
45 /* REVISIT: With new configurations for t114/124/148 passed from DT */
46 #define SKIP_SWGRP_CHECK
47
48 /* bitmap of the page sizes currently supported */
49 #define SMMU_IOMMU_PGSIZES      (SZ_4K)
50
51 #define SMMU_CONFIG                             0x10
52 #define SMMU_CONFIG_DISABLE                     0
53 #define SMMU_CONFIG_ENABLE                      1
54
55 /* REVISIT: To support multiple MCs */
56 enum {
57         _MC = 0,
58 };
59
60 enum {
61         _TLB = 0,
62         _PTC,
63 };
64
65 #define SMMU_CACHE_CONFIG_BASE                  0x14
66 #define __SMMU_CACHE_CONFIG(mc, cache)          (SMMU_CACHE_CONFIG_BASE + 4 * cache)
67 #define SMMU_CACHE_CONFIG(cache)                __SMMU_CACHE_CONFIG(_MC, cache)
68
69 #define SMMU_CACHE_CONFIG_STATS_SHIFT           31
70 #define SMMU_CACHE_CONFIG_STATS_MASK            (1 << SMMU_CACHE_CONFIG_STATS_SHIFT)
71 #define SMMU_CACHE_CONFIG_STATS_ENABLE          (1 << SMMU_CACHE_CONFIG_STATS_SHIFT)
72 #define SMMU_CACHE_CONFIG_STATS_TEST_SHIFT      30
73 #define SMMU_CACHE_CONFIG_STATS_TEST_MASK       (1 << SMMU_CACHE_CONFIG_STATS_TEST_SHIFT)
74 #define SMMU_CACHE_CONFIG_STATS_TEST            (1 << SMMU_CACHE_CONFIG_STATS_TEST_SHIFT)
75
76 #define SMMU_TLB_CONFIG_HIT_UNDER_MISS__ENABLE  (1 << 29)
77 #define SMMU_TLB_CONFIG_ACTIVE_LINES__VALUE     0x10
78 #define SMMU_TLB_CONFIG_RESET_VAL               0x20000010
79
80 #define SMMU_PTC_CONFIG_CACHE__ENABLE           (1 << 29)
81 #define SMMU_PTC_CONFIG_INDEX_MAP__PATTERN      0x3f
82 #define SMMU_PTC_CONFIG_RESET_VAL               0x2000003f
83
84 #define SMMU_PTB_ASID                           0x1c
85 #define SMMU_PTB_ASID_CURRENT_SHIFT             0
86
87 #define SMMU_PTB_DATA                           0x20
88 #define SMMU_PTB_DATA_RESET_VAL                 0
89 #define SMMU_PTB_DATA_ASID_NONSECURE_SHIFT      29
90 #define SMMU_PTB_DATA_ASID_WRITABLE_SHIFT       30
91 #define SMMU_PTB_DATA_ASID_READABLE_SHIFT       31
92
93 #define SMMU_TLB_FLUSH                          0x30
94 #define SMMU_TLB_FLUSH_VA_MATCH_ALL             0
95 #define SMMU_TLB_FLUSH_VA_MATCH_SECTION         2
96 #define SMMU_TLB_FLUSH_VA_MATCH_GROUP           3
97 #define SMMU_TLB_FLUSH_ASID_SHIFT               29
98 #define SMMU_TLB_FLUSH_ASID_MATCH_DISABLE       0
99 #define SMMU_TLB_FLUSH_ASID_MATCH_ENABLE        1
100 #define SMMU_TLB_FLUSH_ASID_MATCH_SHIFT         31
101
102 #define SMMU_PTC_FLUSH                          0x34
103 #define SMMU_PTC_FLUSH_TYPE_ALL                 0
104 #define SMMU_PTC_FLUSH_TYPE_ADR                 1
105 #define SMMU_PTC_FLUSH_ADR_SHIFT                4
106
107 #define SMMU_ASID_SECURITY                      0x38
108
109 #define SMMU_STATS_CACHE_COUNT_BASE             0x1f0
110
111 #define SMMU_STATS_CACHE_COUNT(mc, cache, hitmiss)              \
112         (SMMU_STATS_CACHE_COUNT_BASE + 8 * cache + 4 * hitmiss)
113
114 #define SMMU_TRANSLATION_ENABLE_0               0x228
115 #define SMMU_TRANSLATION_ENABLE_1               0x22c
116 #define SMMU_TRANSLATION_ENABLE_2               0x230
117
118 #define SMMU_AFI_ASID   0x238   /* PCIE */
119 #define SMMU_AVPC_ASID  0x23c   /* AVP */
120 #define SMMU_DC_ASID    0x240   /* Display controller */
121 #define SMMU_DCB_ASID   0x244   /* Display controller B */
122 #define SMMU_EPP_ASID   0x248   /* Encoder pre-processor */
123 #define SMMU_G2_ASID    0x24c   /* 2D engine */
124 #define SMMU_HC_ASID    0x250   /* Host1x */
125 #define SMMU_HDA_ASID   0x254   /* High-def audio */
126 #define SMMU_ISP_ASID   0x258   /* Image signal processor */
127 #define SMMU_MPE_ASID   0x264   /* MPEG encoder */
128 #define SMMU_NV_ASID    0x268   /* (3D) */
129 #define SMMU_NV2_ASID   0x26c   /* (3D) */
130 #define SMMU_PPCS_ASID  0x270   /* AHB */
131 #define SMMU_SATA_ASID  0x278   /* SATA */
132 #define SMMU_VDE_ASID   0x27c   /* Video decoder */
133 #define SMMU_VI_ASID    0x280   /* Video input */
134
135 #define SMMU_PDE_NEXT_SHIFT             28
136
137 /* AHB Arbiter Registers */
138 #define AHB_XBAR_CTRL                           0xe0
139 #define AHB_XBAR_CTRL_SMMU_INIT_DONE_DONE       1
140 #define AHB_XBAR_CTRL_SMMU_INIT_DONE_SHIFT      17
141
142 #define SMMU_NUM_ASIDS                          4
143 #define SMMU_TLB_FLUSH_VA_SECTION__MASK         0xffc00000
144 #define SMMU_TLB_FLUSH_VA_SECTION__SHIFT        12 /* right shift */
145 #define SMMU_TLB_FLUSH_VA_GROUP__MASK           0xffffc000
146 #define SMMU_TLB_FLUSH_VA_GROUP__SHIFT          12 /* right shift */
147 #define SMMU_TLB_FLUSH_VA(iova, which)  \
148         ((((iova) & SMMU_TLB_FLUSH_VA_##which##__MASK) >> \
149                 SMMU_TLB_FLUSH_VA_##which##__SHIFT) |   \
150         SMMU_TLB_FLUSH_VA_MATCH_##which)
151 #define SMMU_PTB_ASID_CUR(n)    \
152                 ((n) << SMMU_PTB_ASID_CURRENT_SHIFT)
153 #define SMMU_TLB_FLUSH_ASID_MATCH_disable               \
154                 (SMMU_TLB_FLUSH_ASID_MATCH_DISABLE <<   \
155                         SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
156 #define SMMU_TLB_FLUSH_ASID_MATCH__ENABLE               \
157                 (SMMU_TLB_FLUSH_ASID_MATCH_ENABLE <<    \
158                         SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
159
160 #define SMMU_PAGE_SHIFT 12
161 #define SMMU_PAGE_SIZE  (1 << SMMU_PAGE_SHIFT)
162
163 #define SMMU_PDIR_COUNT 1024
164 #define SMMU_PDIR_SIZE  (sizeof(unsigned long) * SMMU_PDIR_COUNT)
165 #define SMMU_PTBL_COUNT 1024
166 #define SMMU_PTBL_SIZE  (sizeof(unsigned long) * SMMU_PTBL_COUNT)
167 #define SMMU_PDIR_SHIFT 12
168 #define SMMU_PDE_SHIFT  12
169 #define SMMU_PTE_SHIFT  12
170 #define SMMU_PFN_MASK   0x000fffff
171
172 #define SMMU_ADDR_TO_PFN(addr)  ((addr) >> 12)
173 #define SMMU_ADDR_TO_PDN(addr)  ((addr) >> 22)
174 #define SMMU_PDN_TO_ADDR(addr)  ((pdn) << 22)
175
176 #define _READABLE       (1 << SMMU_PTB_DATA_ASID_READABLE_SHIFT)
177 #define _WRITABLE       (1 << SMMU_PTB_DATA_ASID_WRITABLE_SHIFT)
178 #define _NONSECURE      (1 << SMMU_PTB_DATA_ASID_NONSECURE_SHIFT)
179 #define _PDE_NEXT       (1 << SMMU_PDE_NEXT_SHIFT)
180 #define _MASK_ATTR      (_READABLE | _WRITABLE | _NONSECURE)
181
182 #define _PDIR_ATTR      (_READABLE | _WRITABLE | _NONSECURE)
183
184 #define _PDE_ATTR       (_READABLE | _WRITABLE | _NONSECURE)
185 #define _PDE_ATTR_N     (_PDE_ATTR | _PDE_NEXT)
186 #define _PDE_VACANT(pdn)        (((pdn) << 10) | _PDE_ATTR)
187
188 #define _PTE_ATTR       (_READABLE | _WRITABLE | _NONSECURE)
189 #define _PTE_VACANT(addr)       (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR)
190
191 #define SMMU_MK_PDIR(page, attr)        \
192                 ((page_to_phys(page) >> SMMU_PDIR_SHIFT) | (attr))
193 #define SMMU_MK_PDE(page, attr)         \
194                 (unsigned long)((page_to_phys(page) >> SMMU_PDE_SHIFT) | (attr))
195 #define SMMU_EX_PTBL_PAGE(pde)          \
196                 pfn_to_page((unsigned long)(pde) & SMMU_PFN_MASK)
197 #define SMMU_PFN_TO_PTE(pfn, attr)      (unsigned long)((pfn) | (attr))
198
199 #define SMMU_ASID_ENABLE(asid)  ((asid) | (1 << 31))
200 #define SMMU_ASID_DISABLE       0
201 #define SMMU_ASID_ASID(n)       ((n) & ~SMMU_ASID_ENABLE(0))
202
203 #define smmu_client_enable_hwgrp(c, m)  smmu_client_set_hwgrp(c, m, 1)
204 #define smmu_client_disable_hwgrp(c)    smmu_client_set_hwgrp(c, 0, 0)
205 #define __smmu_client_enable_hwgrp(c, m) __smmu_client_set_hwgrp(c, m, 1)
206 #define __smmu_client_disable_hwgrp(c)  __smmu_client_set_hwgrp(c, 0, 0)
207
208 #define HWGRP_INIT(client) [HWGRP_##client] = SMMU_##client##_ASID
209
210 static const u32 smmu_hwgrp_asid_reg[] = {
211         HWGRP_INIT(AFI),
212         HWGRP_INIT(AVPC),
213         HWGRP_INIT(DC),
214         HWGRP_INIT(DCB),
215         HWGRP_INIT(EPP),
216         HWGRP_INIT(G2),
217         HWGRP_INIT(HC),
218         HWGRP_INIT(HDA),
219         HWGRP_INIT(ISP),
220         HWGRP_INIT(MPE),
221         HWGRP_INIT(NV),
222         HWGRP_INIT(NV2),
223         HWGRP_INIT(PPCS),
224         HWGRP_INIT(SATA),
225         HWGRP_INIT(VDE),
226         HWGRP_INIT(VI),
227 };
228 #define HWGRP_ASID_REG(x) (smmu_hwgrp_asid_reg[x])
229
230 /*
231  * Per client for address space
232  */
233 struct smmu_client {
234         struct device           *dev;
235         struct list_head        list;
236         struct smmu_as          *as;
237         u32                     hwgrp;
238 };
239
240 /*
241  * Per address space
242  */
243 struct smmu_as {
244         struct smmu_device      *smmu;  /* back pointer to container */
245         unsigned int            asid;
246         spinlock_t              lock;   /* for pagetable */
247         struct page             *pdir_page;
248         unsigned long           pdir_attr;
249         unsigned long           pde_attr;
250         unsigned long           pte_attr;
251         unsigned int            *pte_count;
252
253         struct list_head        client;
254         spinlock_t              client_lock; /* for client list */
255 };
256
257 /*
258  * Per SMMU device - IOMMU device
259  */
260 struct smmu_device {
261         void __iomem    *regs, *regs_ahbarb;
262         unsigned long   iovmm_base;     /* remappable base address */
263         unsigned long   page_count;     /* total remappable size */
264         spinlock_t      lock;
265         char            *name;
266         struct device   *dev;
267         int             num_as;
268         struct smmu_as  *as;            /* Run-time allocated array */
269         struct page *avp_vector_page;   /* dummy page shared by all AS's */
270
271         /*
272          * Register image savers for suspend/resume
273          */
274         unsigned long translation_enable_0;
275         unsigned long translation_enable_1;
276         unsigned long translation_enable_2;
277         unsigned long asid_security;
278
279         struct dentry *debugfs_root;
280
281         struct device_node *ahb;
282
283         int             num_as;
284         struct smmu_as  as[0];          /* Run-time allocated array */
285 };
286
287 static struct smmu_device *smmu_handle; /* unique for a system */
288
289 /*
290  *      SMMU/AHB register accessors
291  */
292 static inline u32 smmu_read(struct smmu_device *smmu, size_t offs)
293 {
294         return readl(smmu->regs + offs);
295 }
296 static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs)
297 {
298         writel(val, smmu->regs + offs);
299 }
300
301 static inline u32 ahb_read(struct smmu_device *smmu, size_t offs)
302 {
303         return readl(smmu->regs_ahbarb + offs);
304 }
305 static inline void ahb_write(struct smmu_device *smmu, u32 val, size_t offs)
306 {
307         writel(val, smmu->regs_ahbarb + offs);
308 }
309
310 #define VA_PAGE_TO_PA(va, page) \
311         (page_to_phys(page) + ((unsigned long)(va) & ~PAGE_MASK))
312
313 #define FLUSH_CPU_DCACHE(va, page, size)        \
314         do {    \
315                 unsigned long _pa_ = VA_PAGE_TO_PA(va, page);           \
316                 __cpuc_flush_dcache_area((void *)(va), (size_t)(size)); \
317                 outer_flush_range(_pa_, _pa_+(size_t)(size));           \
318         } while (0)
319
320 /*
321  * Any interaction between any block on PPSB and a block on APB or AHB
322  * must have these read-back barriers to ensure the APB/AHB bus
323  * transaction is complete before initiating activity on the PPSB
324  * block.
325  */
326 #define FLUSH_SMMU_REGS(smmu)   smmu_read(smmu, SMMU_CONFIG)
327
328 #define smmu_client_hwgrp(c) (u32)((c)->dev->platform_data)
329
330 static int __smmu_client_set_hwgrp(struct smmu_client *c,
331                                    unsigned long map, int on)
332 {
333         int i;
334         struct smmu_as *as = c->as;
335         u32 val, offs, mask = SMMU_ASID_ENABLE(as->asid);
336         struct smmu_device *smmu = as->smmu;
337
338         WARN_ON(!on && map);
339         if (on && !map)
340                 return -EINVAL;
341         if (!on)
342                 map = smmu_client_hwgrp(c);
343
344         for_each_set_bit(i, &map, HWGRP_COUNT) {
345                 offs = HWGRP_ASID_REG(i);
346                 val = smmu_read(smmu, offs);
347                 if (on) {
348 #if !defined(SKIP_SWGRP_CHECK)
349                         if (WARN_ON(val & mask))
350                                 goto err_hw_busy;
351 #endif
352                         val |= mask;
353                 } else {
354 #if !defined(SKIP_SWGRP_CHECK)
355                         WARN_ON((val & mask) == mask);
356 #endif
357                         val &= ~mask;
358                 }
359                 smmu_write(smmu, val, offs);
360         }
361         FLUSH_SMMU_REGS(smmu);
362         c->hwgrp = map;
363         return 0;
364
365 err_hw_busy:
366         for_each_set_bit(i, &map, HWGRP_COUNT) {
367                 offs = HWGRP_ASID_REG(i);
368                 val = smmu_read(smmu, offs);
369                 val &= ~mask;
370                 smmu_write(smmu, val, offs);
371         }
372         return -EBUSY;
373 }
374
375 static int smmu_client_set_hwgrp(struct smmu_client *c, u32 map, int on)
376 {
377         u32 val;
378         unsigned long flags;
379         struct smmu_as *as = c->as;
380         struct smmu_device *smmu = as->smmu;
381
382         spin_lock_irqsave(&smmu->lock, flags);
383         val = __smmu_client_set_hwgrp(c, map, on);
384         spin_unlock_irqrestore(&smmu->lock, flags);
385         return val;
386 }
387
388 /*
389  * Flush all TLB entries and all PTC entries
390  * Caller must lock smmu
391  */
392 static void smmu_flush_regs(struct smmu_device *smmu, int enable)
393 {
394         u32 val;
395
396         smmu_write(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH);
397         FLUSH_SMMU_REGS(smmu);
398         val = SMMU_TLB_FLUSH_VA_MATCH_ALL |
399                 SMMU_TLB_FLUSH_ASID_MATCH_disable;
400         smmu_write(smmu, val, SMMU_TLB_FLUSH);
401
402         if (enable)
403                 smmu_write(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG);
404         FLUSH_SMMU_REGS(smmu);
405 }
406
407 static void smmu_setup_regs(struct smmu_device *smmu)
408 {
409         int i;
410         u32 val;
411
412         for (i = 0; i < smmu->num_as; i++) {
413                 struct smmu_as *as = &smmu->as[i];
414                 struct smmu_client *c;
415
416                 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
417                 val = as->pdir_page ?
418                         SMMU_MK_PDIR(as->pdir_page, as->pdir_attr) :
419                         SMMU_PTB_DATA_RESET_VAL;
420                 smmu_write(smmu, val, SMMU_PTB_DATA);
421
422                 list_for_each_entry(c, &as->client, list)
423                         __smmu_client_set_hwgrp(c, c->hwgrp, 1);
424         }
425
426         smmu_write(smmu, smmu->translation_enable_0, SMMU_TRANSLATION_ENABLE_0);
427         smmu_write(smmu, smmu->translation_enable_1, SMMU_TRANSLATION_ENABLE_1);
428         smmu_write(smmu, smmu->translation_enable_2, SMMU_TRANSLATION_ENABLE_2);
429         smmu_write(smmu, smmu->asid_security, SMMU_ASID_SECURITY);
430         smmu_write(smmu, SMMU_TLB_CONFIG_RESET_VAL, SMMU_CACHE_CONFIG(_TLB));
431         smmu_write(smmu, SMMU_PTC_CONFIG_RESET_VAL, SMMU_CACHE_CONFIG(_PTC));
432
433         smmu_flush_regs(smmu, 1);
434
435         val = ahb_read(smmu, AHB_XBAR_CTRL);
436         val |= AHB_XBAR_CTRL_SMMU_INIT_DONE_DONE <<
437                 AHB_XBAR_CTRL_SMMU_INIT_DONE_SHIFT;
438         ahb_write(smmu, val, AHB_XBAR_CTRL);
439 }
440
441 static void flush_ptc_and_tlb(struct smmu_device *smmu,
442                       struct smmu_as *as, dma_addr_t iova,
443                       unsigned long *pte, struct page *page, int is_pde)
444 {
445         u32 val;
446         unsigned long tlb_flush_va = is_pde
447                 ?  SMMU_TLB_FLUSH_VA(iova, SECTION)
448                 :  SMMU_TLB_FLUSH_VA(iova, GROUP);
449
450         val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pte, page);
451         smmu_write(smmu, val, SMMU_PTC_FLUSH);
452         FLUSH_SMMU_REGS(smmu);
453         val = tlb_flush_va |
454                 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE |
455                 (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT);
456         smmu_write(smmu, val, SMMU_TLB_FLUSH);
457         FLUSH_SMMU_REGS(smmu);
458 }
459
460 static void free_ptbl(struct smmu_as *as, dma_addr_t iova)
461 {
462         unsigned long pdn = SMMU_ADDR_TO_PDN(iova);
463         unsigned long *pdir = (unsigned long *)page_address(as->pdir_page);
464
465         if (pdir[pdn] != _PDE_VACANT(pdn)) {
466                 dev_dbg(as->smmu->dev, "pdn: %lx\n", pdn);
467
468                 ClearPageReserved(SMMU_EX_PTBL_PAGE(pdir[pdn]));
469                 __free_page(SMMU_EX_PTBL_PAGE(pdir[pdn]));
470                 pdir[pdn] = _PDE_VACANT(pdn);
471                 FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]);
472                 flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn],
473                                   as->pdir_page, 1);
474         }
475 }
476
477 static void free_pdir(struct smmu_as *as)
478 {
479         unsigned addr;
480         int count;
481         struct device *dev = as->smmu->dev;
482
483         if (!as->pdir_page)
484                 return;
485
486         addr = as->smmu->iovmm_base;
487         count = as->smmu->page_count;
488         while (count-- > 0) {
489                 free_ptbl(as, addr);
490                 addr += SMMU_PAGE_SIZE * SMMU_PTBL_COUNT;
491         }
492         ClearPageReserved(as->pdir_page);
493         __free_page(as->pdir_page);
494         as->pdir_page = NULL;
495         devm_kfree(dev, as->pte_count);
496         as->pte_count = NULL;
497 }
498
499 /*
500  * Maps PTBL for given iova and returns the PTE address
501  * Caller must unmap the mapped PTBL returned in *ptbl_page_p
502  */
503 static unsigned long *locate_pte(struct smmu_as *as,
504                                  dma_addr_t iova, bool allocate,
505                                  struct page **ptbl_page_p,
506                                  unsigned int **count)
507 {
508         unsigned long ptn = SMMU_ADDR_TO_PFN(iova);
509         unsigned long pdn = SMMU_ADDR_TO_PDN(iova);
510         unsigned long *pdir = page_address(as->pdir_page);
511         unsigned long *ptbl;
512
513         if (pdir[pdn] != _PDE_VACANT(pdn)) {
514                 /* Mapped entry table already exists */
515                 *ptbl_page_p = SMMU_EX_PTBL_PAGE(pdir[pdn]);
516                 ptbl = page_address(*ptbl_page_p);
517         } else if (!allocate) {
518                 return NULL;
519         } else {
520                 int pn;
521                 unsigned long addr = SMMU_PDN_TO_ADDR(pdn);
522
523                 /* Vacant - allocate a new page table */
524                 dev_dbg(as->smmu->dev, "New PTBL pdn: %lx\n", pdn);
525
526                 *ptbl_page_p = alloc_page(GFP_ATOMIC);
527                 if (!*ptbl_page_p) {
528                         dev_err(as->smmu->dev,
529                                 "failed to allocate smmu_device page table\n");
530                         return NULL;
531                 }
532                 SetPageReserved(*ptbl_page_p);
533                 ptbl = (unsigned long *)page_address(*ptbl_page_p);
534                 for (pn = 0; pn < SMMU_PTBL_COUNT;
535                      pn++, addr += SMMU_PAGE_SIZE) {
536                         ptbl[pn] = _PTE_VACANT(addr);
537                 }
538                 FLUSH_CPU_DCACHE(ptbl, *ptbl_page_p, SMMU_PTBL_SIZE);
539                 pdir[pdn] = SMMU_MK_PDE(*ptbl_page_p,
540                                         as->pde_attr | _PDE_NEXT);
541                 FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]);
542                 flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn],
543                                   as->pdir_page, 1);
544         }
545         *count = &as->pte_count[pdn];
546
547         return &ptbl[ptn % SMMU_PTBL_COUNT];
548 }
549
550 #ifdef CONFIG_SMMU_SIG_DEBUG
551 static void put_signature(struct smmu_as *as,
552                           dma_addr_t iova, unsigned long pfn)
553 {
554         struct page *page;
555         unsigned long *vaddr;
556
557         page = pfn_to_page(pfn);
558         vaddr = page_address(page);
559         if (!vaddr)
560                 return;
561
562         vaddr[0] = iova;
563         vaddr[1] = pfn << PAGE_SHIFT;
564         FLUSH_CPU_DCACHE(vaddr, page, sizeof(vaddr[0]) * 2);
565 }
566 #else
567 static inline void put_signature(struct smmu_as *as,
568                                  unsigned long addr, unsigned long pfn)
569 {
570 }
571 #endif
572
573 /*
574  * Caller must lock/unlock as
575  */
576 static int alloc_pdir(struct smmu_as *as)
577 {
578         unsigned long *pdir;
579         int pdn;
580         u32 val;
581         struct smmu_device *smmu = as->smmu;
582
583         if (as->pdir_page)
584                 return 0;
585
586         as->pte_count = devm_kzalloc(smmu->dev,
587                      sizeof(as->pte_count[0]) * SMMU_PDIR_COUNT, GFP_ATOMIC);
588         if (!as->pte_count) {
589                 dev_err(smmu->dev,
590                         "failed to allocate smmu_device PTE cunters\n");
591                 return -ENOMEM;
592         }
593         as->pdir_page = alloc_page(GFP_ATOMIC | __GFP_DMA);
594         if (!as->pdir_page) {
595                 dev_err(smmu->dev,
596                         "failed to allocate smmu_device page directory\n");
597                 devm_kfree(smmu->dev, as->pte_count);
598                 as->pte_count = NULL;
599                 return -ENOMEM;
600         }
601         SetPageReserved(as->pdir_page);
602         pdir = page_address(as->pdir_page);
603
604         for (pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++)
605                 pdir[pdn] = _PDE_VACANT(pdn);
606         FLUSH_CPU_DCACHE(pdir, as->pdir_page, SMMU_PDIR_SIZE);
607         val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pdir, as->pdir_page);
608         smmu_write(smmu, val, SMMU_PTC_FLUSH);
609         FLUSH_SMMU_REGS(as->smmu);
610         val = SMMU_TLB_FLUSH_VA_MATCH_ALL |
611                 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE |
612                 (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT);
613         smmu_write(smmu, val, SMMU_TLB_FLUSH);
614         FLUSH_SMMU_REGS(as->smmu);
615
616         return 0;
617 }
618
619 static void __smmu_iommu_unmap(struct smmu_as *as, dma_addr_t iova)
620 {
621         unsigned long *pte;
622         struct page *page;
623         unsigned int *count;
624
625         pte = locate_pte(as, iova, false, &page, &count);
626         if (WARN_ON(!pte))
627                 return;
628
629         if (WARN_ON(*pte == _PTE_VACANT(iova)))
630                 return;
631
632         *pte = _PTE_VACANT(iova);
633         FLUSH_CPU_DCACHE(pte, page, sizeof(*pte));
634         flush_ptc_and_tlb(as->smmu, as, iova, pte, page, 0);
635         if (!--(*count)) {
636                 free_ptbl(as, iova);
637                 smmu_flush_regs(as->smmu, 0);
638         }
639 }
640
641 static void __smmu_iommu_map_pfn(struct smmu_as *as, dma_addr_t iova,
642                                  unsigned long pfn)
643 {
644         struct smmu_device *smmu = as->smmu;
645         unsigned long *pte;
646         unsigned int *count;
647         struct page *page;
648
649         pte = locate_pte(as, iova, true, &page, &count);
650         if (WARN_ON(!pte))
651                 return;
652
653         if (*pte == _PTE_VACANT(iova))
654                 (*count)++;
655         *pte = SMMU_PFN_TO_PTE(pfn, as->pte_attr);
656         if (unlikely((*pte == _PTE_VACANT(iova))))
657                 (*count)--;
658         FLUSH_CPU_DCACHE(pte, page, sizeof(*pte));
659         flush_ptc_and_tlb(smmu, as, iova, pte, page, 0);
660         put_signature(as, iova, pfn);
661 }
662
663 static int smmu_iommu_map(struct iommu_domain *domain, unsigned long iova,
664                           phys_addr_t pa, size_t bytes, int prot)
665 {
666         struct smmu_as *as = domain->priv;
667         unsigned long pfn = __phys_to_pfn(pa);
668         unsigned long flags;
669
670         dev_dbg(as->smmu->dev, "[%d] %08lx:%08x\n", as->asid, iova, pa);
671
672         if (!pfn_valid(pfn))
673                 return -ENOMEM;
674
675         spin_lock_irqsave(&as->lock, flags);
676         __smmu_iommu_map_pfn(as, iova, pfn);
677         spin_unlock_irqrestore(&as->lock, flags);
678         return 0;
679 }
680
681 static size_t smmu_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
682                                size_t bytes)
683 {
684         struct smmu_as *as = domain->priv;
685         unsigned long flags;
686
687         dev_dbg(as->smmu->dev, "[%d] %08lx\n", as->asid, iova);
688
689         spin_lock_irqsave(&as->lock, flags);
690         __smmu_iommu_unmap(as, iova);
691         spin_unlock_irqrestore(&as->lock, flags);
692         return SMMU_PAGE_SIZE;
693 }
694
695 static phys_addr_t smmu_iommu_iova_to_phys(struct iommu_domain *domain,
696                                            unsigned long iova)
697 {
698         struct smmu_as *as = domain->priv;
699         unsigned long *pte;
700         unsigned int *count;
701         struct page *page;
702         unsigned long pfn;
703         unsigned long flags;
704
705         spin_lock_irqsave(&as->lock, flags);
706
707         pte = locate_pte(as, iova, true, &page, &count);
708         pfn = *pte & SMMU_PFN_MASK;
709         WARN_ON(!pfn_valid(pfn));
710         dev_dbg(as->smmu->dev,
711                 "iova:%08lx pfn:%08lx asid:%d\n", iova, pfn, as->asid);
712
713         spin_unlock_irqrestore(&as->lock, flags);
714         return PFN_PHYS(pfn);
715 }
716
717 static int smmu_iommu_domain_has_cap(struct iommu_domain *domain,
718                                      unsigned long cap)
719 {
720         return 0;
721 }
722
723 static int smmu_iommu_attach_dev(struct iommu_domain *domain,
724                                  struct device *dev)
725 {
726         struct smmu_as *as = domain->priv;
727         struct smmu_device *smmu = as->smmu;
728         struct smmu_client *client, *c;
729         u32 map;
730         int err;
731
732         client = devm_kzalloc(smmu->dev, sizeof(*c), GFP_KERNEL);
733         if (!client)
734                 return -ENOMEM;
735         client->dev = dev;
736         client->as = as;
737
738 #ifdef SKIP_SWGRP_CHECK
739         /* Enable all SWGRP blindly by default */
740         map = (1 << HWGRP_COUNT) - 1;
741 #else
742         map = (unsigned long)dev->platform_data;
743         if (!map)
744                 return -EINVAL;
745 #endif
746
747         err = smmu_client_enable_hwgrp(client, map);
748         if (err)
749                 goto err_hwgrp;
750
751         spin_lock(&as->client_lock);
752         list_for_each_entry(c, &as->client, list) {
753                 if (c->dev == dev) {
754                         dev_err(smmu->dev,
755                                 "%s is already attached\n", dev_name(c->dev));
756                         err = -EINVAL;
757                         goto err_client;
758                 }
759         }
760         list_add(&client->list, &as->client);
761         spin_unlock(&as->client_lock);
762
763         /*
764          * Reserve "page zero" for AVP vectors using a common dummy
765          * page.
766          */
767         if (map & HWG_AVPC) {
768                 struct page *page;
769
770                 page = as->smmu->avp_vector_page;
771                 __smmu_iommu_map_pfn(as, 0, page_to_pfn(page));
772
773                 pr_info("Reserve \"page zero\" for AVP vectors using a common dummy\n");
774         }
775
776         dev_dbg(smmu->dev, "%s is attached\n", dev_name(dev));
777         return 0;
778
779 err_client:
780         smmu_client_disable_hwgrp(client);
781         spin_unlock(&as->client_lock);
782 err_hwgrp:
783         devm_kfree(smmu->dev, client);
784         return err;
785 }
786
787 static void smmu_iommu_detach_dev(struct iommu_domain *domain,
788                                   struct device *dev)
789 {
790         struct smmu_as *as = domain->priv;
791         struct smmu_device *smmu = as->smmu;
792         struct smmu_client *c;
793
794         spin_lock(&as->client_lock);
795
796         list_for_each_entry(c, &as->client, list) {
797                 if (c->dev == dev) {
798                         smmu_client_disable_hwgrp(c);
799                         list_del(&c->list);
800                         devm_kfree(smmu->dev, c);
801                         c->as = NULL;
802                         dev_dbg(smmu->dev,
803                                 "%s is detached\n", dev_name(c->dev));
804                         goto out;
805                 }
806         }
807         dev_err(smmu->dev, "Couldn't find %s\n", dev_name(c->dev));
808 out:
809         spin_unlock(&as->client_lock);
810 }
811
812 static int smmu_iommu_domain_init(struct iommu_domain *domain)
813 {
814         int i;
815         unsigned long flags;
816         struct smmu_as *as;
817         struct smmu_device *smmu = smmu_handle;
818
819         /* Look for a free AS with lock held */
820         for  (i = 0; i < smmu->num_as; i++) {
821                 struct smmu_as *tmp = &smmu->as[i];
822
823                 spin_lock_irqsave(&tmp->lock, flags);
824                 if (!tmp->pdir_page) {
825                         as = tmp;
826                         goto found;
827                 }
828                 spin_unlock_irqrestore(&tmp->lock, flags);
829         }
830         dev_err(smmu->dev, "no free AS\n");
831         return -ENODEV;
832
833 found:
834         if (alloc_pdir(as) < 0)
835                 goto err_alloc_pdir;
836
837         spin_lock(&smmu->lock);
838
839         /* Update PDIR register */
840         smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
841         smmu_write(smmu,
842                    SMMU_MK_PDIR(as->pdir_page, as->pdir_attr), SMMU_PTB_DATA);
843         FLUSH_SMMU_REGS(smmu);
844
845         spin_unlock(&smmu->lock);
846
847         spin_unlock_irqrestore(&as->lock, flags);
848         domain->priv = as;
849
850         dev_dbg(smmu->dev, "smmu_as@%p\n", as);
851         return 0;
852
853 err_alloc_pdir:
854         spin_unlock_irqrestore(&as->lock, flags);
855         return -ENODEV;
856 }
857
858 static void smmu_iommu_domain_destroy(struct iommu_domain *domain)
859 {
860         struct smmu_as *as = domain->priv;
861         struct smmu_device *smmu = as->smmu;
862         unsigned long flags;
863
864         spin_lock_irqsave(&as->lock, flags);
865
866         if (as->pdir_page) {
867                 spin_lock(&smmu->lock);
868                 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
869                 smmu_write(smmu, SMMU_PTB_DATA_RESET_VAL, SMMU_PTB_DATA);
870                 FLUSH_SMMU_REGS(smmu);
871                 spin_unlock(&smmu->lock);
872
873                 free_pdir(as);
874         }
875
876         if (!list_empty(&as->client)) {
877                 struct smmu_client *c;
878
879                 list_for_each_entry(c, &as->client, list)
880                         smmu_iommu_detach_dev(domain, c->dev);
881         }
882
883         spin_unlock_irqrestore(&as->lock, flags);
884
885         domain->priv = NULL;
886         dev_dbg(smmu->dev, "smmu_as@%p\n", as);
887 }
888
889 static struct iommu_ops smmu_iommu_ops = {
890         .domain_init    = smmu_iommu_domain_init,
891         .domain_destroy = smmu_iommu_domain_destroy,
892         .attach_dev     = smmu_iommu_attach_dev,
893         .detach_dev     = smmu_iommu_detach_dev,
894         .map            = smmu_iommu_map,
895         .unmap          = smmu_iommu_unmap,
896         .iova_to_phys   = smmu_iommu_iova_to_phys,
897         .domain_has_cap = smmu_iommu_domain_has_cap,
898         .pgsize_bitmap  = SMMU_IOMMU_PGSIZES,
899 };
900
901 static const char * const smmu_debugfs_mc[] = { "mc", };
902 static const char * const smmu_debugfs_cache[] = {  "tlb", "ptc", };
903
904 static ssize_t smmu_debugfs_stats_write(struct file *file,
905                                         const char __user *buffer,
906                                         size_t count, loff_t *pos)
907 {
908         struct smmu_device *smmu;
909         struct dentry *dent;
910         int i, cache, mc;
911         enum {
912                 _OFF = 0,
913                 _ON,
914                 _RESET,
915         };
916         const char * const command[] = {
917                 [_OFF]          = "off",
918                 [_ON]           = "on",
919                 [_RESET]        = "reset",
920         };
921         char str[] = "reset";
922         u32 val;
923         size_t offs;
924
925         count = min_t(size_t, count, sizeof(str));
926         if (copy_from_user(str, buffer, count))
927                 return -EINVAL;
928
929         for (i = 0; i < ARRAY_SIZE(command); i++)
930                 if (strncmp(str, command[i],
931                             strlen(command[i])) == 0)
932                         break;
933
934         if (i == ARRAY_SIZE(command))
935                 return -EINVAL;
936
937         dent = file->f_dentry;
938         cache = (int)dent->d_inode->i_private;
939         mc = (int)dent->d_parent->d_inode->i_private;
940         smmu = dent->d_parent->d_parent->d_inode->i_private;
941
942         offs = SMMU_CACHE_CONFIG(cache);
943         val = smmu_read(smmu, offs);
944         switch (i) {
945         case _OFF:
946                 val &= ~SMMU_CACHE_CONFIG_STATS_ENABLE;
947                 val &= ~SMMU_CACHE_CONFIG_STATS_TEST;
948                 smmu_write(smmu, val, offs);
949                 break;
950         case _ON:
951                 val |= SMMU_CACHE_CONFIG_STATS_ENABLE;
952                 val &= ~SMMU_CACHE_CONFIG_STATS_TEST;
953                 smmu_write(smmu, val, offs);
954                 break;
955         case _RESET:
956                 val |= SMMU_CACHE_CONFIG_STATS_TEST;
957                 smmu_write(smmu, val, offs);
958                 val &= ~SMMU_CACHE_CONFIG_STATS_TEST;
959                 smmu_write(smmu, val, offs);
960                 break;
961         default:
962                 BUG();
963                 break;
964         }
965
966         dev_dbg(smmu->dev, "%s() %08x, %08x @%08x\n", __func__,
967                 val, smmu_read(smmu, offs), offs);
968
969         return count;
970 }
971
972 static int smmu_debugfs_stats_show(struct seq_file *s, void *v)
973 {
974         struct smmu_device *smmu;
975         struct dentry *dent;
976         int i, cache, mc;
977         const char * const stats[] = { "hit", "miss", };
978
979         dent = d_find_alias(s->private);
980         cache = (int)dent->d_inode->i_private;
981         mc = (int)dent->d_parent->d_inode->i_private;
982         smmu = dent->d_parent->d_parent->d_inode->i_private;
983
984         for (i = 0; i < ARRAY_SIZE(stats); i++) {
985                 u32 val;
986                 size_t offs;
987
988                 offs = SMMU_STATS_CACHE_COUNT(mc, cache, i);
989                 val = smmu_read(smmu, offs);
990                 seq_printf(s, "%s %08x ", stats[i], val);
991
992                 dev_dbg(smmu->dev, "%s() %s %08x @%08x\n", __func__,
993                         stats[i], val, offs);
994         }
995         seq_printf(s, "\n");
996
997         return 0;
998 }
999
1000 static int smmu_debugfs_stats_open(struct inode *inode, struct file *file)
1001 {
1002         return single_open(file, smmu_debugfs_stats_show, inode);
1003 }
1004
1005 static const struct file_operations smmu_debugfs_stats_fops = {
1006         .open           = smmu_debugfs_stats_open,
1007         .read           = seq_read,
1008         .llseek         = seq_lseek,
1009         .release        = single_release,
1010         .write          = smmu_debugfs_stats_write,
1011 };
1012
1013 static void smmu_debugfs_delete(struct smmu_device *smmu)
1014 {
1015         debugfs_remove_recursive(smmu->debugfs_root);
1016 }
1017
1018 static void smmu_debugfs_create(struct smmu_device *smmu)
1019 {
1020         int i;
1021         struct dentry *root;
1022
1023         root = debugfs_create_file(dev_name(smmu->dev),
1024                                    S_IFDIR | S_IRWXU | S_IRUGO | S_IXUGO,
1025                                    NULL, smmu, NULL);
1026         if (!root)
1027                 goto err_out;
1028         smmu->debugfs_root = root;
1029
1030         for (i = 0; i < ARRAY_SIZE(smmu_debugfs_mc); i++) {
1031                 int j;
1032                 struct dentry *mc;
1033
1034                 mc = debugfs_create_file(smmu_debugfs_mc[i],
1035                                          S_IFDIR | S_IRWXU | S_IRUGO | S_IXUGO,
1036                                          root, (void *)i, NULL);
1037                 if (!mc)
1038                         goto err_out;
1039
1040                 for (j = 0; j < ARRAY_SIZE(smmu_debugfs_cache); j++) {
1041                         struct dentry *cache;
1042
1043                         cache = debugfs_create_file(smmu_debugfs_cache[j],
1044                                                     S_IWUGO | S_IRUGO, mc,
1045                                                     (void *)j,
1046                                                     &smmu_debugfs_stats_fops);
1047                         if (!cache)
1048                                 goto err_out;
1049                 }
1050         }
1051
1052         return;
1053
1054 err_out:
1055         smmu_debugfs_delete(smmu);
1056 }
1057
1058 static int tegra_smmu_suspend(struct device *dev)
1059 {
1060         struct smmu_device *smmu = dev_get_drvdata(dev);
1061
1062         smmu->translation_enable_0 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_0);
1063         smmu->translation_enable_1 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_1);
1064         smmu->translation_enable_2 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_2);
1065         smmu->asid_security = smmu_read(smmu, SMMU_ASID_SECURITY);
1066         return 0;
1067 }
1068
1069 static int tegra_smmu_resume(struct device *dev)
1070 {
1071         struct smmu_device *smmu = dev_get_drvdata(dev);
1072         unsigned long flags;
1073
1074         spin_lock_irqsave(&smmu->lock, flags);
1075         smmu_setup_regs(smmu);
1076         spin_unlock_irqrestore(&smmu->lock, flags);
1077         return 0;
1078 }
1079
1080 static int tegra_smmu_probe(struct platform_device *pdev)
1081 {
1082         struct smmu_device *smmu;
1083         struct resource *regs, *regs2, *window;
1084         struct device *dev = &pdev->dev;
1085         int i, err = 0;
1086
1087         if (smmu_handle)
1088                 return -EIO;
1089
1090         BUILD_BUG_ON(PAGE_SHIFT != SMMU_PAGE_SHIFT);
1091
1092         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1093         regs2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1094         window = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1095         if (!regs || !regs2 || !window) {
1096                 dev_err(dev, "No SMMU resources\n");
1097                 return -ENODEV;
1098         }
1099
1100         smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
1101         if (!smmu) {
1102                 dev_err(dev, "failed to allocate smmu_device\n");
1103                 return -ENOMEM;
1104         }
1105
1106         smmu->dev = dev;
1107         smmu->num_as = SMMU_NUM_ASIDS;
1108         smmu->iovmm_base = (unsigned long)window->start;
1109         smmu->page_count = resource_size(window) >> SMMU_PAGE_SHIFT;
1110         smmu->regs = devm_ioremap(dev, regs->start, resource_size(regs));
1111         smmu->regs_ahbarb = devm_ioremap(dev, regs2->start,
1112                                          resource_size(regs2));
1113         if (!smmu->regs || !smmu->regs_ahbarb) {
1114                 dev_err(dev, "failed to remap SMMU registers\n");
1115                 err = -ENXIO;
1116                 goto fail;
1117         }
1118
1119         smmu->translation_enable_0 = ~0;
1120         smmu->translation_enable_1 = ~0;
1121         smmu->translation_enable_2 = ~0;
1122         smmu->asid_security = 0;
1123
1124         smmu->as = devm_kzalloc(dev,
1125                         sizeof(smmu->as[0]) * smmu->num_as, GFP_KERNEL);
1126         if (!smmu->as) {
1127                 dev_err(dev, "failed to allocate smmu_as\n");
1128                 err = -ENOMEM;
1129                 goto fail;
1130         }
1131
1132         for (i = 0; i < smmu->num_as; i++) {
1133                 struct smmu_as *as = &smmu->as[i];
1134
1135                 as->smmu = smmu;
1136                 as->asid = i;
1137                 as->pdir_attr = _PDIR_ATTR;
1138                 as->pde_attr = _PDE_ATTR;
1139                 as->pte_attr = _PTE_ATTR;
1140
1141                 spin_lock_init(&as->lock);
1142                 INIT_LIST_HEAD(&as->client);
1143         }
1144         spin_lock_init(&smmu->lock);
1145         smmu_setup_regs(smmu);
1146         platform_set_drvdata(pdev, smmu);
1147
1148         smmu->avp_vector_page = alloc_page(GFP_KERNEL);
1149         if (!smmu->avp_vector_page)
1150                 goto fail;
1151
1152         smmu_debugfs_create(smmu);
1153         smmu_handle = smmu;
1154         return 0;
1155
1156 fail:
1157         if (smmu->avp_vector_page)
1158                 __free_page(smmu->avp_vector_page);
1159         if (smmu->regs)
1160                 devm_iounmap(dev, smmu->regs);
1161         if (smmu->regs_ahbarb)
1162                 devm_iounmap(dev, smmu->regs_ahbarb);
1163         if (smmu && smmu->as) {
1164                 for (i = 0; i < smmu->num_as; i++) {
1165                         if (smmu->as[i].pdir_page) {
1166                                 ClearPageReserved(smmu->as[i].pdir_page);
1167                                 __free_page(smmu->as[i].pdir_page);
1168                         }
1169                 }
1170                 devm_kfree(dev, smmu->as);
1171         }
1172         devm_kfree(dev, smmu);
1173         return err;
1174 }
1175
1176 static int tegra_smmu_remove(struct platform_device *pdev)
1177 {
1178         struct smmu_device *smmu = platform_get_drvdata(pdev);
1179         struct device *dev = smmu->dev;
1180
1181         smmu_debugfs_delete(smmu);
1182
1183         smmu_write(smmu, SMMU_CONFIG_DISABLE, SMMU_CONFIG);
1184         platform_set_drvdata(pdev, NULL);
1185         if (smmu->as) {
1186                 int i;
1187
1188                 for (i = 0; i < smmu->num_as; i++)
1189                         free_pdir(&smmu->as[i]);
1190                 devm_kfree(dev, smmu->as);
1191         }
1192         if (smmu->avp_vector_page)
1193                 __free_page(smmu->avp_vector_page);
1194         if (smmu->regs)
1195                 devm_iounmap(dev, smmu->regs);
1196         if (smmu->regs_ahbarb)
1197                 devm_iounmap(dev, smmu->regs_ahbarb);
1198         devm_kfree(dev, smmu);
1199         smmu_handle = NULL;
1200         return 0;
1201 }
1202
1203 const struct dev_pm_ops tegra_smmu_pm_ops = {
1204         .suspend        = tegra_smmu_suspend,
1205         .resume         = tegra_smmu_resume,
1206 };
1207
1208 static struct platform_driver tegra_smmu_driver = {
1209         .probe          = tegra_smmu_probe,
1210         .remove         = tegra_smmu_remove,
1211         .driver = {
1212                 .owner  = THIS_MODULE,
1213                 .name   = "tegra_smmu",
1214                 .pm     = &tegra_smmu_pm_ops,
1215         },
1216 };
1217
1218 static int __devinit tegra_smmu_init(void)
1219 {
1220         bus_set_iommu(&platform_bus_type, &smmu_iommu_ops);
1221         return platform_driver_register(&tegra_smmu_driver);
1222 }
1223
1224 static void __exit tegra_smmu_exit(void)
1225 {
1226         platform_driver_unregister(&tegra_smmu_driver);
1227 }
1228
1229 core_initcall(tegra_smmu_init);
1230 module_exit(tegra_smmu_exit);
1231
1232 MODULE_DESCRIPTION("IOMMU API for SMMU in Tegra30");
1233 MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
1234 MODULE_LICENSE("GPL v2");