i2c: tegra: Add stub runtime power management
[linux-2.6.git] / drivers / iommu / tegra-smmu.c
1 /*
2  * IOMMU API for SMMU in Tegra30
3  *
4  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along with
16  * this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18  */
19
20 #define pr_fmt(fmt)     "%s(): " fmt, __func__
21
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/spinlock.h>
25 #include <linux/slab.h>
26 #include <linux/vmalloc.h>
27 #include <linux/mm.h>
28 #include <linux/pagemap.h>
29 #include <linux/device.h>
30 #include <linux/sched.h>
31 #include <linux/iommu.h>
32 #include <linux/io.h>
33
34 #include <asm/page.h>
35 #include <asm/cacheflush.h>
36
37 #include <mach/iomap.h>
38 #include <mach/smmu.h>
39 #include <mach/tegra_smmu.h>
40
41 /* REVISIT: With new configurations for t114/124/148 passed from DT */
42 #define SKIP_SWGRP_CHECK
43
44 /* bitmap of the page sizes currently supported */
45 #define SMMU_IOMMU_PGSIZES      (SZ_4K)
46
47 #define SMMU_CONFIG                             0x10
48 #define SMMU_CONFIG_DISABLE                     0
49 #define SMMU_CONFIG_ENABLE                      1
50
51 #define SMMU_TLB_CONFIG                         0x14
52 #define SMMU_TLB_CONFIG_STATS__MASK             (1 << 31)
53 #define SMMU_TLB_CONFIG_STATS__ENABLE           (1 << 31)
54 #define SMMU_TLB_CONFIG_HIT_UNDER_MISS__ENABLE  (1 << 29)
55 #define SMMU_TLB_CONFIG_ACTIVE_LINES__VALUE     0x10
56 #define SMMU_TLB_CONFIG_RESET_VAL               0x20000010
57
58 #define SMMU_PTC_CONFIG                         0x18
59 #define SMMU_PTC_CONFIG_STATS__MASK             (1 << 31)
60 #define SMMU_PTC_CONFIG_STATS__ENABLE           (1 << 31)
61 #define SMMU_PTC_CONFIG_CACHE__ENABLE           (1 << 29)
62 #define SMMU_PTC_CONFIG_INDEX_MAP__PATTERN      0x3f
63 #define SMMU_PTC_CONFIG_RESET_VAL               0x2000003f
64
65 #define SMMU_PTB_ASID                           0x1c
66 #define SMMU_PTB_ASID_CURRENT_SHIFT             0
67
68 #define SMMU_PTB_DATA                           0x20
69 #define SMMU_PTB_DATA_RESET_VAL                 0
70 #define SMMU_PTB_DATA_ASID_NONSECURE_SHIFT      29
71 #define SMMU_PTB_DATA_ASID_WRITABLE_SHIFT       30
72 #define SMMU_PTB_DATA_ASID_READABLE_SHIFT       31
73
74 #define SMMU_TLB_FLUSH                          0x30
75 #define SMMU_TLB_FLUSH_VA_MATCH_ALL             0
76 #define SMMU_TLB_FLUSH_VA_MATCH_SECTION         2
77 #define SMMU_TLB_FLUSH_VA_MATCH_GROUP           3
78 #define SMMU_TLB_FLUSH_ASID_SHIFT               29
79 #define SMMU_TLB_FLUSH_ASID_MATCH_DISABLE       0
80 #define SMMU_TLB_FLUSH_ASID_MATCH_ENABLE        1
81 #define SMMU_TLB_FLUSH_ASID_MATCH_SHIFT         31
82
83 #define SMMU_PTC_FLUSH                          0x34
84 #define SMMU_PTC_FLUSH_TYPE_ALL                 0
85 #define SMMU_PTC_FLUSH_TYPE_ADR                 1
86 #define SMMU_PTC_FLUSH_ADR_SHIFT                4
87
88 #define SMMU_ASID_SECURITY                      0x38
89
90 #define SMMU_STATS_TLB_HIT_COUNT                0x1f0
91 #define SMMU_STATS_TLB_MISS_COUNT               0x1f4
92 #define SMMU_STATS_PTC_HIT_COUNT                0x1f8
93 #define SMMU_STATS_PTC_MISS_COUNT               0x1fc
94
95 #define SMMU_TRANSLATION_ENABLE_0               0x228
96 #define SMMU_TRANSLATION_ENABLE_1               0x22c
97 #define SMMU_TRANSLATION_ENABLE_2               0x230
98
99 #define SMMU_AFI_ASID   0x238   /* PCIE */
100 #define SMMU_AVPC_ASID  0x23c   /* AVP */
101 #define SMMU_DC_ASID    0x240   /* Display controller */
102 #define SMMU_DCB_ASID   0x244   /* Display controller B */
103 #define SMMU_EPP_ASID   0x248   /* Encoder pre-processor */
104 #define SMMU_G2_ASID    0x24c   /* 2D engine */
105 #define SMMU_HC_ASID    0x250   /* Host1x */
106 #define SMMU_HDA_ASID   0x254   /* High-def audio */
107 #define SMMU_ISP_ASID   0x258   /* Image signal processor */
108 #define SMMU_MPE_ASID   0x264   /* MPEG encoder */
109 #define SMMU_NV_ASID    0x268   /* (3D) */
110 #define SMMU_NV2_ASID   0x26c   /* (3D) */
111 #define SMMU_PPCS_ASID  0x270   /* AHB */
112 #define SMMU_SATA_ASID  0x278   /* SATA */
113 #define SMMU_VDE_ASID   0x27c   /* Video decoder */
114 #define SMMU_VI_ASID    0x280   /* Video input */
115
116 #define SMMU_PDE_NEXT_SHIFT             28
117
118 /* AHB Arbiter Registers */
119 #define AHB_XBAR_CTRL                           0xe0
120 #define AHB_XBAR_CTRL_SMMU_INIT_DONE_DONE       1
121 #define AHB_XBAR_CTRL_SMMU_INIT_DONE_SHIFT      17
122
123 #define SMMU_NUM_ASIDS                          4
124 #define SMMU_TLB_FLUSH_VA_SECTION__MASK         0xffc00000
125 #define SMMU_TLB_FLUSH_VA_SECTION__SHIFT        12 /* right shift */
126 #define SMMU_TLB_FLUSH_VA_GROUP__MASK           0xffffc000
127 #define SMMU_TLB_FLUSH_VA_GROUP__SHIFT          12 /* right shift */
128 #define SMMU_TLB_FLUSH_VA(iova, which)  \
129         ((((iova) & SMMU_TLB_FLUSH_VA_##which##__MASK) >> \
130                 SMMU_TLB_FLUSH_VA_##which##__SHIFT) |   \
131         SMMU_TLB_FLUSH_VA_MATCH_##which)
132 #define SMMU_PTB_ASID_CUR(n)    \
133                 ((n) << SMMU_PTB_ASID_CURRENT_SHIFT)
134 #define SMMU_TLB_FLUSH_ASID_MATCH_disable               \
135                 (SMMU_TLB_FLUSH_ASID_MATCH_DISABLE <<   \
136                         SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
137 #define SMMU_TLB_FLUSH_ASID_MATCH__ENABLE               \
138                 (SMMU_TLB_FLUSH_ASID_MATCH_ENABLE <<    \
139                         SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
140
141 #define SMMU_PAGE_SHIFT 12
142 #define SMMU_PAGE_SIZE  (1 << SMMU_PAGE_SHIFT)
143
144 #define SMMU_PDIR_COUNT 1024
145 #define SMMU_PDIR_SIZE  (sizeof(unsigned long) * SMMU_PDIR_COUNT)
146 #define SMMU_PTBL_COUNT 1024
147 #define SMMU_PTBL_SIZE  (sizeof(unsigned long) * SMMU_PTBL_COUNT)
148 #define SMMU_PDIR_SHIFT 12
149 #define SMMU_PDE_SHIFT  12
150 #define SMMU_PTE_SHIFT  12
151 #define SMMU_PFN_MASK   0x000fffff
152
153 #define SMMU_ADDR_TO_PFN(addr)  ((addr) >> 12)
154 #define SMMU_ADDR_TO_PDN(addr)  ((addr) >> 22)
155 #define SMMU_PDN_TO_ADDR(addr)  ((pdn) << 22)
156
157 #define _READABLE       (1 << SMMU_PTB_DATA_ASID_READABLE_SHIFT)
158 #define _WRITABLE       (1 << SMMU_PTB_DATA_ASID_WRITABLE_SHIFT)
159 #define _NONSECURE      (1 << SMMU_PTB_DATA_ASID_NONSECURE_SHIFT)
160 #define _PDE_NEXT       (1 << SMMU_PDE_NEXT_SHIFT)
161 #define _MASK_ATTR      (_READABLE | _WRITABLE | _NONSECURE)
162
163 #define _PDIR_ATTR      (_READABLE | _WRITABLE | _NONSECURE)
164
165 #define _PDE_ATTR       (_READABLE | _WRITABLE | _NONSECURE)
166 #define _PDE_ATTR_N     (_PDE_ATTR | _PDE_NEXT)
167 #define _PDE_VACANT(pdn)        (((pdn) << 10) | _PDE_ATTR)
168
169 #define _PTE_ATTR       (_READABLE | _WRITABLE | _NONSECURE)
170 #define _PTE_VACANT(addr)       (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR)
171
172 #define SMMU_MK_PDIR(page, attr)        \
173                 ((page_to_phys(page) >> SMMU_PDIR_SHIFT) | (attr))
174 #define SMMU_MK_PDE(page, attr)         \
175                 (unsigned long)((page_to_phys(page) >> SMMU_PDE_SHIFT) | (attr))
176 #define SMMU_EX_PTBL_PAGE(pde)          \
177                 pfn_to_page((unsigned long)(pde) & SMMU_PFN_MASK)
178 #define SMMU_PFN_TO_PTE(pfn, attr)      (unsigned long)((pfn) | (attr))
179
180 #define SMMU_ASID_ENABLE(asid)  ((asid) | (1 << 31))
181 #define SMMU_ASID_DISABLE       0
182 #define SMMU_ASID_ASID(n)       ((n) & ~SMMU_ASID_ENABLE(0))
183
184 #define smmu_client_enable_hwgrp(c, m)  smmu_client_set_hwgrp(c, m, 1)
185 #define smmu_client_disable_hwgrp(c)    smmu_client_set_hwgrp(c, 0, 0)
186 #define __smmu_client_enable_hwgrp(c, m) __smmu_client_set_hwgrp(c, m, 1)
187 #define __smmu_client_disable_hwgrp(c)  __smmu_client_set_hwgrp(c, 0, 0)
188
189 #define HWGRP_INIT(client) [HWGRP_##client] = SMMU_##client##_ASID
190
191 static const u32 smmu_hwgrp_asid_reg[] = {
192         HWGRP_INIT(AFI),
193         HWGRP_INIT(AVPC),
194         HWGRP_INIT(DC),
195         HWGRP_INIT(DCB),
196         HWGRP_INIT(EPP),
197         HWGRP_INIT(G2),
198         HWGRP_INIT(HC),
199         HWGRP_INIT(HDA),
200         HWGRP_INIT(ISP),
201         HWGRP_INIT(MPE),
202         HWGRP_INIT(NV),
203         HWGRP_INIT(NV2),
204         HWGRP_INIT(PPCS),
205         HWGRP_INIT(SATA),
206         HWGRP_INIT(VDE),
207         HWGRP_INIT(VI),
208 };
209 #define HWGRP_ASID_REG(x) (smmu_hwgrp_asid_reg[x])
210
211 /*
212  * Per client for address space
213  */
214 struct smmu_client {
215         struct device           *dev;
216         struct list_head        list;
217         struct smmu_as          *as;
218         u32                     hwgrp;
219 };
220
221 /*
222  * Per address space
223  */
224 struct smmu_as {
225         struct smmu_device      *smmu;  /* back pointer to container */
226         unsigned int            asid;
227         spinlock_t              lock;   /* for pagetable */
228         struct page             *pdir_page;
229         unsigned long           pdir_attr;
230         unsigned long           pde_attr;
231         unsigned long           pte_attr;
232         unsigned int            *pte_count;
233
234         struct list_head        client;
235         spinlock_t              client_lock; /* for client list */
236 };
237
238 /*
239  * Per SMMU device - IOMMU device
240  */
241 struct smmu_device {
242         void __iomem    *regs, *regs_ahbarb;
243         unsigned long   iovmm_base;     /* remappable base address */
244         unsigned long   page_count;     /* total remappable size */
245         spinlock_t      lock;
246         char            *name;
247         struct device   *dev;
248         int             num_as;
249         struct smmu_as  *as;            /* Run-time allocated array */
250         struct page *avp_vector_page;   /* dummy page shared by all AS's */
251
252         /*
253          * Register image savers for suspend/resume
254          */
255         unsigned long translation_enable_0;
256         unsigned long translation_enable_1;
257         unsigned long translation_enable_2;
258         unsigned long asid_security;
259 };
260
261 static struct smmu_device *smmu_handle; /* unique for a system */
262
263 /*
264  *      SMMU/AHB register accessors
265  */
266 static inline u32 smmu_read(struct smmu_device *smmu, size_t offs)
267 {
268         return readl(smmu->regs + offs);
269 }
270 static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs)
271 {
272         writel(val, smmu->regs + offs);
273 }
274
275 static inline u32 ahb_read(struct smmu_device *smmu, size_t offs)
276 {
277         return readl(smmu->regs_ahbarb + offs);
278 }
279 static inline void ahb_write(struct smmu_device *smmu, u32 val, size_t offs)
280 {
281         writel(val, smmu->regs_ahbarb + offs);
282 }
283
284 #define VA_PAGE_TO_PA(va, page) \
285         (page_to_phys(page) + ((unsigned long)(va) & ~PAGE_MASK))
286
287 #define FLUSH_CPU_DCACHE(va, page, size)        \
288         do {    \
289                 unsigned long _pa_ = VA_PAGE_TO_PA(va, page);           \
290                 __cpuc_flush_dcache_area((void *)(va), (size_t)(size)); \
291                 outer_flush_range(_pa_, _pa_+(size_t)(size));           \
292         } while (0)
293
294 /*
295  * Any interaction between any block on PPSB and a block on APB or AHB
296  * must have these read-back barriers to ensure the APB/AHB bus
297  * transaction is complete before initiating activity on the PPSB
298  * block.
299  */
300 #define FLUSH_SMMU_REGS(smmu)   smmu_read(smmu, SMMU_CONFIG)
301
302 #define smmu_client_hwgrp(c) (u32)((c)->dev->platform_data)
303
304 static int __smmu_client_set_hwgrp(struct smmu_client *c,
305                                    unsigned long map, int on)
306 {
307         int i;
308         struct smmu_as *as = c->as;
309         u32 val, offs, mask = SMMU_ASID_ENABLE(as->asid);
310         struct smmu_device *smmu = as->smmu;
311
312         WARN_ON(!on && map);
313         if (on && !map)
314                 return -EINVAL;
315         if (!on)
316                 map = smmu_client_hwgrp(c);
317
318         for_each_set_bit(i, &map, HWGRP_COUNT) {
319                 offs = HWGRP_ASID_REG(i);
320                 val = smmu_read(smmu, offs);
321                 if (on) {
322 #if !defined(SKIP_SWGRP_CHECK)
323                         if (WARN_ON(val & mask)) {
324                                 for_each_set_bit(i, &map, HWGRP_COUNT) {
325                                         offs = HWGRP_ASID_REG(i);
326                                         val = smmu_read(smmu, offs);
327                                         val &= ~mask;
328                                         smmu_write(smmu, val, offs);
329                                 }
330                                 return -EBUSY;
331                         }
332 #endif
333                         val |= mask;
334                 } else {
335 #if !defined(SKIP_SWGRP_CHECK)
336                         WARN_ON((val & mask) == mask);
337 #endif
338                         val &= ~mask;
339                 }
340                 smmu_write(smmu, val, offs);
341         }
342         FLUSH_SMMU_REGS(smmu);
343         c->hwgrp = map;
344         return 0;
345
346 }
347
348 static int smmu_client_set_hwgrp(struct smmu_client *c, u32 map, int on)
349 {
350         u32 val;
351         unsigned long flags;
352         struct smmu_as *as = c->as;
353         struct smmu_device *smmu = as->smmu;
354
355         spin_lock_irqsave(&smmu->lock, flags);
356         val = __smmu_client_set_hwgrp(c, map, on);
357         spin_unlock_irqrestore(&smmu->lock, flags);
358         return val;
359 }
360
361 /*
362  * Flush all TLB entries and all PTC entries
363  * Caller must lock smmu
364  */
365 static void smmu_flush_regs(struct smmu_device *smmu, int enable)
366 {
367         u32 val;
368
369         smmu_write(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH);
370         FLUSH_SMMU_REGS(smmu);
371         val = SMMU_TLB_FLUSH_VA_MATCH_ALL |
372                 SMMU_TLB_FLUSH_ASID_MATCH_disable;
373         smmu_write(smmu, val, SMMU_TLB_FLUSH);
374
375         if (enable)
376                 smmu_write(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG);
377         FLUSH_SMMU_REGS(smmu);
378 }
379
380 static void smmu_setup_regs(struct smmu_device *smmu)
381 {
382         int i;
383         u32 val;
384
385         for (i = 0; i < smmu->num_as; i++) {
386                 struct smmu_as *as = &smmu->as[i];
387                 struct smmu_client *c;
388
389                 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
390                 val = as->pdir_page ?
391                         SMMU_MK_PDIR(as->pdir_page, as->pdir_attr) :
392                         SMMU_PTB_DATA_RESET_VAL;
393                 smmu_write(smmu, val, SMMU_PTB_DATA);
394
395                 list_for_each_entry(c, &as->client, list)
396                         __smmu_client_set_hwgrp(c, c->hwgrp, 1);
397         }
398
399         smmu_write(smmu, smmu->translation_enable_0, SMMU_TRANSLATION_ENABLE_0);
400         smmu_write(smmu, smmu->translation_enable_1, SMMU_TRANSLATION_ENABLE_1);
401         smmu_write(smmu, smmu->translation_enable_2, SMMU_TRANSLATION_ENABLE_2);
402         smmu_write(smmu, smmu->asid_security, SMMU_ASID_SECURITY);
403         smmu_write(smmu, SMMU_TLB_CONFIG_RESET_VAL, SMMU_TLB_CONFIG);
404         smmu_write(smmu, SMMU_PTC_CONFIG_RESET_VAL, SMMU_PTC_CONFIG);
405
406         smmu_flush_regs(smmu, 1);
407
408         val = ahb_read(smmu, AHB_XBAR_CTRL);
409         val |= AHB_XBAR_CTRL_SMMU_INIT_DONE_DONE <<
410                 AHB_XBAR_CTRL_SMMU_INIT_DONE_SHIFT;
411         ahb_write(smmu, val, AHB_XBAR_CTRL);
412 }
413
414 static void flush_ptc_and_tlb(struct smmu_device *smmu,
415                       struct smmu_as *as, dma_addr_t iova,
416                       unsigned long *pte, struct page *page, int is_pde)
417 {
418         u32 val;
419         unsigned long tlb_flush_va = is_pde
420                 ?  SMMU_TLB_FLUSH_VA(iova, SECTION)
421                 :  SMMU_TLB_FLUSH_VA(iova, GROUP);
422
423         val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pte, page);
424         smmu_write(smmu, val, SMMU_PTC_FLUSH);
425         FLUSH_SMMU_REGS(smmu);
426         val = tlb_flush_va |
427                 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE |
428                 (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT);
429         smmu_write(smmu, val, SMMU_TLB_FLUSH);
430         FLUSH_SMMU_REGS(smmu);
431 }
432
433 static void free_ptbl(struct smmu_as *as, dma_addr_t iova)
434 {
435         unsigned long pdn = SMMU_ADDR_TO_PDN(iova);
436         unsigned long *pdir = (unsigned long *)page_address(as->pdir_page);
437
438         if (pdir[pdn] != _PDE_VACANT(pdn)) {
439                 dev_dbg(as->smmu->dev, "pdn: %lx\n", pdn);
440
441                 ClearPageReserved(SMMU_EX_PTBL_PAGE(pdir[pdn]));
442                 __free_page(SMMU_EX_PTBL_PAGE(pdir[pdn]));
443                 pdir[pdn] = _PDE_VACANT(pdn);
444                 FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]);
445                 flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn],
446                                   as->pdir_page, 1);
447         }
448 }
449
450 static void free_pdir(struct smmu_as *as)
451 {
452         unsigned addr;
453         int count;
454         struct device *dev = as->smmu->dev;
455
456         if (!as->pdir_page)
457                 return;
458
459         addr = as->smmu->iovmm_base;
460         count = as->smmu->page_count;
461         while (count-- > 0) {
462                 free_ptbl(as, addr);
463                 addr += SMMU_PAGE_SIZE * SMMU_PTBL_COUNT;
464         }
465         ClearPageReserved(as->pdir_page);
466         __free_page(as->pdir_page);
467         as->pdir_page = NULL;
468         devm_kfree(dev, as->pte_count);
469         as->pte_count = NULL;
470 }
471
472 /*
473  * Maps PTBL for given iova and returns the PTE address
474  * Caller must unmap the mapped PTBL returned in *ptbl_page_p
475  */
476 static unsigned long *locate_pte(struct smmu_as *as,
477                                  dma_addr_t iova, bool allocate,
478                                  struct page **ptbl_page_p,
479                                  unsigned int **count)
480 {
481         unsigned long ptn = SMMU_ADDR_TO_PFN(iova);
482         unsigned long pdn = SMMU_ADDR_TO_PDN(iova);
483         unsigned long *pdir = page_address(as->pdir_page);
484         unsigned long *ptbl;
485
486         if (pdir[pdn] != _PDE_VACANT(pdn)) {
487                 /* Mapped entry table already exists */
488                 *ptbl_page_p = SMMU_EX_PTBL_PAGE(pdir[pdn]);
489                 ptbl = page_address(*ptbl_page_p);
490         } else if (!allocate) {
491                 return NULL;
492         } else {
493                 int pn;
494                 unsigned long addr = SMMU_PDN_TO_ADDR(pdn);
495
496                 /* Vacant - allocate a new page table */
497                 dev_dbg(as->smmu->dev, "New PTBL pdn: %lx\n", pdn);
498
499                 *ptbl_page_p = alloc_page(GFP_ATOMIC);
500                 if (!*ptbl_page_p) {
501                         dev_err(as->smmu->dev,
502                                 "failed to allocate smmu_device page table\n");
503                         return NULL;
504                 }
505                 SetPageReserved(*ptbl_page_p);
506                 ptbl = (unsigned long *)page_address(*ptbl_page_p);
507                 for (pn = 0; pn < SMMU_PTBL_COUNT;
508                      pn++, addr += SMMU_PAGE_SIZE) {
509                         ptbl[pn] = _PTE_VACANT(addr);
510                 }
511                 FLUSH_CPU_DCACHE(ptbl, *ptbl_page_p, SMMU_PTBL_SIZE);
512                 pdir[pdn] = SMMU_MK_PDE(*ptbl_page_p,
513                                         as->pde_attr | _PDE_NEXT);
514                 FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]);
515                 flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn],
516                                   as->pdir_page, 1);
517         }
518         *count = &as->pte_count[pdn];
519
520         return &ptbl[ptn % SMMU_PTBL_COUNT];
521 }
522
523 #ifdef CONFIG_SMMU_SIG_DEBUG
524 static void put_signature(struct smmu_as *as,
525                           dma_addr_t iova, unsigned long pfn)
526 {
527         struct page *page;
528         unsigned long *vaddr;
529
530         page = pfn_to_page(pfn);
531         vaddr = page_address(page);
532         if (!vaddr)
533                 return;
534
535         vaddr[0] = iova;
536         vaddr[1] = pfn << PAGE_SHIFT;
537         FLUSH_CPU_DCACHE(vaddr, page, sizeof(vaddr[0]) * 2);
538 }
539 #else
540 static inline void put_signature(struct smmu_as *as,
541                                  unsigned long addr, unsigned long pfn)
542 {
543 }
544 #endif
545
546 /*
547  * Caller must lock/unlock as
548  */
549 static int alloc_pdir(struct smmu_as *as)
550 {
551         unsigned long *pdir;
552         int pdn;
553         u32 val;
554         struct smmu_device *smmu = as->smmu;
555
556         if (as->pdir_page)
557                 return 0;
558
559         as->pte_count = devm_kzalloc(smmu->dev,
560                      sizeof(as->pte_count[0]) * SMMU_PDIR_COUNT, GFP_KERNEL);
561         if (!as->pte_count) {
562                 dev_err(smmu->dev,
563                         "failed to allocate smmu_device PTE cunters\n");
564                 return -ENOMEM;
565         }
566         as->pdir_page = alloc_page(GFP_KERNEL | __GFP_DMA);
567         if (!as->pdir_page) {
568                 dev_err(smmu->dev,
569                         "failed to allocate smmu_device page directory\n");
570                 devm_kfree(smmu->dev, as->pte_count);
571                 as->pte_count = NULL;
572                 return -ENOMEM;
573         }
574         SetPageReserved(as->pdir_page);
575         pdir = page_address(as->pdir_page);
576
577         for (pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++)
578                 pdir[pdn] = _PDE_VACANT(pdn);
579         FLUSH_CPU_DCACHE(pdir, as->pdir_page, SMMU_PDIR_SIZE);
580         val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pdir, as->pdir_page);
581         smmu_write(smmu, val, SMMU_PTC_FLUSH);
582         FLUSH_SMMU_REGS(as->smmu);
583         val = SMMU_TLB_FLUSH_VA_MATCH_ALL |
584                 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE |
585                 (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT);
586         smmu_write(smmu, val, SMMU_TLB_FLUSH);
587         FLUSH_SMMU_REGS(as->smmu);
588
589         return 0;
590 }
591
592 static void __smmu_iommu_unmap(struct smmu_as *as, dma_addr_t iova)
593 {
594         unsigned long *pte;
595         struct page *page;
596         unsigned int *count;
597
598         pte = locate_pte(as, iova, false, &page, &count);
599         if (WARN_ON(!pte))
600                 return;
601
602         if (WARN_ON(*pte == _PTE_VACANT(iova)))
603                 return;
604
605         *pte = _PTE_VACANT(iova);
606         FLUSH_CPU_DCACHE(pte, page, sizeof(*pte));
607         flush_ptc_and_tlb(as->smmu, as, iova, pte, page, 0);
608         if (!--(*count)) {
609                 free_ptbl(as, iova);
610                 smmu_flush_regs(as->smmu, 0);
611         }
612 }
613
614 static void __smmu_iommu_map_pfn(struct smmu_as *as, dma_addr_t iova,
615                                  unsigned long pfn)
616 {
617         struct smmu_device *smmu = as->smmu;
618         unsigned long *pte;
619         unsigned int *count;
620         struct page *page;
621
622         pte = locate_pte(as, iova, true, &page, &count);
623         if (WARN_ON(!pte))
624                 return;
625
626         if (*pte == _PTE_VACANT(iova))
627                 (*count)++;
628         *pte = SMMU_PFN_TO_PTE(pfn, as->pte_attr);
629         if (unlikely((*pte == _PTE_VACANT(iova))))
630                 (*count)--;
631         FLUSH_CPU_DCACHE(pte, page, sizeof(*pte));
632         flush_ptc_and_tlb(smmu, as, iova, pte, page, 0);
633         put_signature(as, iova, pfn);
634 }
635
636 static int smmu_iommu_map(struct iommu_domain *domain, unsigned long iova,
637                           phys_addr_t pa, size_t bytes, int prot)
638 {
639         struct smmu_as *as = domain->priv;
640         unsigned long pfn = __phys_to_pfn(pa);
641         unsigned long flags;
642
643         dev_dbg(as->smmu->dev, "[%d] %08lx:%08x\n", as->asid, iova, pa);
644
645         if (!pfn_valid(pfn))
646                 return -ENOMEM;
647
648         spin_lock_irqsave(&as->lock, flags);
649         __smmu_iommu_map_pfn(as, iova, pfn);
650         spin_unlock_irqrestore(&as->lock, flags);
651         return 0;
652 }
653
654 static size_t smmu_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
655                                size_t bytes)
656 {
657         struct smmu_as *as = domain->priv;
658         unsigned long flags;
659
660         dev_dbg(as->smmu->dev, "[%d] %08lx\n", as->asid, iova);
661
662         spin_lock_irqsave(&as->lock, flags);
663         __smmu_iommu_unmap(as, iova);
664         spin_unlock_irqrestore(&as->lock, flags);
665         return SMMU_PAGE_SIZE;
666 }
667
668 static phys_addr_t smmu_iommu_iova_to_phys(struct iommu_domain *domain,
669                                            unsigned long iova)
670 {
671         struct smmu_as *as = domain->priv;
672         unsigned long *pte;
673         unsigned int *count;
674         struct page *page;
675         unsigned long pfn;
676         unsigned long flags;
677
678         spin_lock_irqsave(&as->lock, flags);
679
680         pte = locate_pte(as, iova, true, &page, &count);
681         pfn = *pte & SMMU_PFN_MASK;
682         WARN_ON(!pfn_valid(pfn));
683         dev_dbg(as->smmu->dev,
684                 "iova:%08lx pfn:%08lx asid:%d\n", iova, pfn, as->asid);
685
686         spin_unlock_irqrestore(&as->lock, flags);
687         return PFN_PHYS(pfn);
688 }
689
690 static int smmu_iommu_domain_has_cap(struct iommu_domain *domain,
691                                      unsigned long cap)
692 {
693         return 0;
694 }
695
696 static int smmu_iommu_attach_dev(struct iommu_domain *domain,
697                                  struct device *dev)
698 {
699         struct smmu_as *as = domain->priv;
700         struct smmu_device *smmu = as->smmu;
701         struct smmu_client *client, *c;
702         u32 map;
703         int err;
704
705         client = devm_kzalloc(smmu->dev, sizeof(*c), GFP_KERNEL);
706         if (!client)
707                 return -ENOMEM;
708         client->dev = dev;
709         client->as = as;
710
711 #ifdef SKIP_SWGRP_CHECK
712         /* Enable all SWGRP blindly by default */
713         map = (1 << HWGRP_COUNT) - 1;
714 #else
715         map = (unsigned long)dev->platform_data;
716         if (!map)
717                 return -EINVAL;
718 #endif
719
720         err = smmu_client_enable_hwgrp(client, map);
721         if (err)
722                 goto err_hwgrp;
723
724         spin_lock(&as->client_lock);
725         list_for_each_entry(c, &as->client, list) {
726                 if (c->dev == dev) {
727                         dev_err(smmu->dev,
728                                 "%s is already attached\n", dev_name(c->dev));
729                         err = -EINVAL;
730                         goto err_client;
731                 }
732         }
733         list_add(&client->list, &as->client);
734         spin_unlock(&as->client_lock);
735
736         /*
737          * Reserve "page zero" for AVP vectors using a common dummy
738          * page.
739          */
740         if (map & HWG_AVPC) {
741                 struct page *page;
742
743                 page = as->smmu->avp_vector_page;
744                 __smmu_iommu_map_pfn(as, 0, page_to_pfn(page));
745
746                 pr_info("Reserve \"page zero\" for AVP vectors using a common dummy\n");
747         }
748
749         dev_dbg(smmu->dev, "%s is attached\n", dev_name(dev));
750         return 0;
751
752 err_client:
753         smmu_client_disable_hwgrp(client);
754         spin_unlock(&as->client_lock);
755 err_hwgrp:
756         devm_kfree(smmu->dev, client);
757         return err;
758 }
759
760 static void smmu_iommu_detach_dev(struct iommu_domain *domain,
761                                   struct device *dev)
762 {
763         struct smmu_as *as = domain->priv;
764         struct smmu_device *smmu = as->smmu;
765         struct smmu_client *c;
766
767         spin_lock(&as->client_lock);
768
769         list_for_each_entry(c, &as->client, list) {
770                 if (c->dev == dev) {
771                         smmu_client_disable_hwgrp(c);
772                         list_del(&c->list);
773                         devm_kfree(smmu->dev, c);
774                         c->as = NULL;
775                         dev_dbg(smmu->dev,
776                                 "%s is detached\n", dev_name(c->dev));
777                         goto out;
778                 }
779         }
780         dev_err(smmu->dev, "Couldn't find %s\n", dev_name(c->dev));
781 out:
782         spin_unlock(&as->client_lock);
783 }
784
785 static int smmu_iommu_domain_init(struct iommu_domain *domain)
786 {
787         int i;
788         unsigned long flags;
789         struct smmu_as *as;
790         struct smmu_device *smmu = smmu_handle;
791
792         /* Look for a free AS with lock held */
793         for  (i = 0; i < smmu->num_as; i++) {
794                 struct smmu_as *tmp = &smmu->as[i];
795
796                 spin_lock_irqsave(&tmp->lock, flags);
797                 if (!tmp->pdir_page) {
798                         as = tmp;
799                         goto found;
800                 }
801                 spin_unlock_irqrestore(&tmp->lock, flags);
802         }
803         dev_err(smmu->dev, "no free AS\n");
804         return -ENODEV;
805
806 found:
807         if (alloc_pdir(as) < 0)
808                 goto err_alloc_pdir;
809
810         spin_lock(&smmu->lock);
811
812         /* Update PDIR register */
813         smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
814         smmu_write(smmu,
815                    SMMU_MK_PDIR(as->pdir_page, as->pdir_attr), SMMU_PTB_DATA);
816         FLUSH_SMMU_REGS(smmu);
817
818         spin_unlock(&smmu->lock);
819
820         spin_unlock_irqrestore(&as->lock, flags);
821         domain->priv = as;
822
823         dev_dbg(smmu->dev, "smmu_as@%p\n", as);
824         return 0;
825
826 err_alloc_pdir:
827         spin_unlock_irqrestore(&as->lock, flags);
828         return -ENODEV;
829 }
830
831 static void smmu_iommu_domain_destroy(struct iommu_domain *domain)
832 {
833         struct smmu_as *as = domain->priv;
834         struct smmu_device *smmu = as->smmu;
835         unsigned long flags;
836
837         spin_lock_irqsave(&as->lock, flags);
838
839         if (as->pdir_page) {
840                 spin_lock(&smmu->lock);
841                 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
842                 smmu_write(smmu, SMMU_PTB_DATA_RESET_VAL, SMMU_PTB_DATA);
843                 FLUSH_SMMU_REGS(smmu);
844                 spin_unlock(&smmu->lock);
845
846                 free_pdir(as);
847         }
848
849         if (!list_empty(&as->client)) {
850                 struct smmu_client *c;
851
852                 list_for_each_entry(c, &as->client, list)
853                         smmu_iommu_detach_dev(domain, c->dev);
854         }
855
856         spin_unlock_irqrestore(&as->lock, flags);
857
858         domain->priv = NULL;
859         dev_dbg(smmu->dev, "smmu_as@%p\n", as);
860 }
861
862 static struct iommu_ops smmu_iommu_ops = {
863         .domain_init    = smmu_iommu_domain_init,
864         .domain_destroy = smmu_iommu_domain_destroy,
865         .attach_dev     = smmu_iommu_attach_dev,
866         .detach_dev     = smmu_iommu_detach_dev,
867         .map            = smmu_iommu_map,
868         .unmap          = smmu_iommu_unmap,
869         .iova_to_phys   = smmu_iommu_iova_to_phys,
870         .domain_has_cap = smmu_iommu_domain_has_cap,
871         .pgsize_bitmap  = SMMU_IOMMU_PGSIZES,
872 };
873
874 static int tegra_smmu_suspend(struct device *dev)
875 {
876         struct smmu_device *smmu = dev_get_drvdata(dev);
877
878         smmu->translation_enable_0 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_0);
879         smmu->translation_enable_1 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_1);
880         smmu->translation_enable_2 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_2);
881         smmu->asid_security = smmu_read(smmu, SMMU_ASID_SECURITY);
882         return 0;
883 }
884
885 static int tegra_smmu_resume(struct device *dev)
886 {
887         struct smmu_device *smmu = dev_get_drvdata(dev);
888         unsigned long flags;
889
890         spin_lock_irqsave(&smmu->lock, flags);
891         smmu_setup_regs(smmu);
892         spin_unlock_irqrestore(&smmu->lock, flags);
893         return 0;
894 }
895
896 static int tegra_smmu_probe(struct platform_device *pdev)
897 {
898         struct smmu_device *smmu;
899         struct resource *regs, *regs2;
900         struct tegra_smmu_window *window;
901         struct device *dev = &pdev->dev;
902         int i, err = 0;
903
904         if (smmu_handle)
905                 return -EIO;
906
907         BUILD_BUG_ON(PAGE_SHIFT != SMMU_PAGE_SHIFT);
908
909         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
910         regs2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
911         window = tegra_smmu_window(0);
912         if (!regs || !regs2 || !window) {
913                 dev_err(dev, "No SMMU resources\n");
914                 return -ENODEV;
915         }
916
917         smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
918         if (!smmu) {
919                 dev_err(dev, "failed to allocate smmu_device\n");
920                 return -ENOMEM;
921         }
922
923         smmu->dev = dev;
924         smmu->num_as = SMMU_NUM_ASIDS;
925         smmu->iovmm_base = (unsigned long)window->start;
926         smmu->page_count = (window->end + 1 - window->start) >> SMMU_PAGE_SHIFT;
927         smmu->regs = devm_ioremap(dev, regs->start, resource_size(regs));
928         smmu->regs_ahbarb = devm_ioremap(dev, regs2->start,
929                                          resource_size(regs2));
930         if (!smmu->regs || !smmu->regs_ahbarb) {
931                 dev_err(dev, "failed to remap SMMU registers\n");
932                 err = -ENXIO;
933                 goto fail;
934         }
935
936         smmu->translation_enable_0 = ~0;
937         smmu->translation_enable_1 = ~0;
938         smmu->translation_enable_2 = ~0;
939         smmu->asid_security = 0;
940
941         smmu->as = devm_kzalloc(dev,
942                         sizeof(smmu->as[0]) * smmu->num_as, GFP_KERNEL);
943         if (!smmu->as) {
944                 dev_err(dev, "failed to allocate smmu_as\n");
945                 err = -ENOMEM;
946                 goto fail;
947         }
948
949         for (i = 0; i < smmu->num_as; i++) {
950                 struct smmu_as *as = &smmu->as[i];
951
952                 as->smmu = smmu;
953                 as->asid = i;
954                 as->pdir_attr = _PDIR_ATTR;
955                 as->pde_attr = _PDE_ATTR;
956                 as->pte_attr = _PTE_ATTR;
957
958                 spin_lock_init(&as->lock);
959                 INIT_LIST_HEAD(&as->client);
960         }
961         spin_lock_init(&smmu->lock);
962         smmu_setup_regs(smmu);
963         platform_set_drvdata(pdev, smmu);
964
965         smmu->avp_vector_page = alloc_page(GFP_KERNEL);
966         if (!smmu->avp_vector_page)
967                 goto fail;
968
969         smmu_handle = smmu;
970         return 0;
971
972 fail:
973         if (smmu->avp_vector_page)
974                 __free_page(smmu->avp_vector_page);
975         if (smmu->regs)
976                 devm_iounmap(dev, smmu->regs);
977         if (smmu->regs_ahbarb)
978                 devm_iounmap(dev, smmu->regs_ahbarb);
979         if (smmu && smmu->as) {
980                 for (i = 0; i < smmu->num_as; i++) {
981                         if (smmu->as[i].pdir_page) {
982                                 ClearPageReserved(smmu->as[i].pdir_page);
983                                 __free_page(smmu->as[i].pdir_page);
984                         }
985                 }
986                 devm_kfree(dev, smmu->as);
987         }
988         devm_kfree(dev, smmu);
989         return err;
990 }
991
992 static int tegra_smmu_remove(struct platform_device *pdev)
993 {
994         struct smmu_device *smmu = platform_get_drvdata(pdev);
995         struct device *dev = smmu->dev;
996
997         smmu_write(smmu, SMMU_CONFIG_DISABLE, SMMU_CONFIG);
998         platform_set_drvdata(pdev, NULL);
999         if (smmu->as) {
1000                 int i;
1001
1002                 for (i = 0; i < smmu->num_as; i++)
1003                         free_pdir(&smmu->as[i]);
1004                 devm_kfree(dev, smmu->as);
1005         }
1006         if (smmu->avp_vector_page)
1007                 __free_page(smmu->avp_vector_page);
1008         if (smmu->regs)
1009                 devm_iounmap(dev, smmu->regs);
1010         if (smmu->regs_ahbarb)
1011                 devm_iounmap(dev, smmu->regs_ahbarb);
1012         devm_kfree(dev, smmu);
1013         smmu_handle = NULL;
1014         return 0;
1015 }
1016
1017 const struct dev_pm_ops tegra_smmu_pm_ops = {
1018         .suspend        = tegra_smmu_suspend,
1019         .resume         = tegra_smmu_resume,
1020 };
1021
1022 static struct platform_driver tegra_smmu_driver = {
1023         .probe          = tegra_smmu_probe,
1024         .remove         = tegra_smmu_remove,
1025         .driver = {
1026                 .owner  = THIS_MODULE,
1027                 .name   = "tegra_smmu",
1028                 .pm     = &tegra_smmu_pm_ops,
1029         },
1030 };
1031
1032 static int __devinit tegra_smmu_init(void)
1033 {
1034         bus_set_iommu(&platform_bus_type, &smmu_iommu_ops);
1035         return platform_driver_register(&tegra_smmu_driver);
1036 }
1037
1038 static void __exit tegra_smmu_exit(void)
1039 {
1040         platform_driver_unregister(&tegra_smmu_driver);
1041 }
1042
1043 core_initcall(tegra_smmu_init);
1044 module_exit(tegra_smmu_exit);