768df7265b81175408bb051f1b09d581363b13f8
[linux-2.6.git] / drivers / infiniband / hw / mthca / mthca_cmd.c
1 /*
2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
3  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
4  * Copyright (c) 2005, 2006 Cisco Systems.  All rights reserved.
5  *
6  * This software is available to you under a choice of one of two
7  * licenses.  You may choose to be licensed under the terms of the GNU
8  * General Public License (GPL) Version 2, available from the file
9  * COPYING in the main directory of this source tree, or the
10  * OpenIB.org BSD license below:
11  *
12  *     Redistribution and use in source and binary forms, with or
13  *     without modification, are permitted provided that the following
14  *     conditions are met:
15  *
16  *      - Redistributions of source code must retain the above
17  *        copyright notice, this list of conditions and the following
18  *        disclaimer.
19  *
20  *      - Redistributions in binary form must reproduce the above
21  *        copyright notice, this list of conditions and the following
22  *        disclaimer in the documentation and/or other materials
23  *        provided with the distribution.
24  *
25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32  * SOFTWARE.
33  *
34  * $Id: mthca_cmd.c 1349 2004-12-16 21:09:43Z roland $
35  */
36
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/errno.h>
40 #include <asm/io.h>
41 #include <rdma/ib_mad.h>
42
43 #include "mthca_dev.h"
44 #include "mthca_config_reg.h"
45 #include "mthca_cmd.h"
46 #include "mthca_memfree.h"
47
48 #define CMD_POLL_TOKEN 0xffff
49
50 enum {
51         HCR_IN_PARAM_OFFSET    = 0x00,
52         HCR_IN_MODIFIER_OFFSET = 0x08,
53         HCR_OUT_PARAM_OFFSET   = 0x0c,
54         HCR_TOKEN_OFFSET       = 0x14,
55         HCR_STATUS_OFFSET      = 0x18,
56
57         HCR_OPMOD_SHIFT        = 12,
58         HCA_E_BIT              = 22,
59         HCR_GO_BIT             = 23
60 };
61
62 enum {
63         /* initialization and general commands */
64         CMD_SYS_EN          = 0x1,
65         CMD_SYS_DIS         = 0x2,
66         CMD_MAP_FA          = 0xfff,
67         CMD_UNMAP_FA        = 0xffe,
68         CMD_RUN_FW          = 0xff6,
69         CMD_MOD_STAT_CFG    = 0x34,
70         CMD_QUERY_DEV_LIM   = 0x3,
71         CMD_QUERY_FW        = 0x4,
72         CMD_ENABLE_LAM      = 0xff8,
73         CMD_DISABLE_LAM     = 0xff7,
74         CMD_QUERY_DDR       = 0x5,
75         CMD_QUERY_ADAPTER   = 0x6,
76         CMD_INIT_HCA        = 0x7,
77         CMD_CLOSE_HCA       = 0x8,
78         CMD_INIT_IB         = 0x9,
79         CMD_CLOSE_IB        = 0xa,
80         CMD_QUERY_HCA       = 0xb,
81         CMD_SET_IB          = 0xc,
82         CMD_ACCESS_DDR      = 0x2e,
83         CMD_MAP_ICM         = 0xffa,
84         CMD_UNMAP_ICM       = 0xff9,
85         CMD_MAP_ICM_AUX     = 0xffc,
86         CMD_UNMAP_ICM_AUX   = 0xffb,
87         CMD_SET_ICM_SIZE    = 0xffd,
88
89         /* TPT commands */
90         CMD_SW2HW_MPT       = 0xd,
91         CMD_QUERY_MPT       = 0xe,
92         CMD_HW2SW_MPT       = 0xf,
93         CMD_READ_MTT        = 0x10,
94         CMD_WRITE_MTT       = 0x11,
95         CMD_SYNC_TPT        = 0x2f,
96
97         /* EQ commands */
98         CMD_MAP_EQ          = 0x12,
99         CMD_SW2HW_EQ        = 0x13,
100         CMD_HW2SW_EQ        = 0x14,
101         CMD_QUERY_EQ        = 0x15,
102
103         /* CQ commands */
104         CMD_SW2HW_CQ        = 0x16,
105         CMD_HW2SW_CQ        = 0x17,
106         CMD_QUERY_CQ        = 0x18,
107         CMD_RESIZE_CQ       = 0x2c,
108
109         /* SRQ commands */
110         CMD_SW2HW_SRQ       = 0x35,
111         CMD_HW2SW_SRQ       = 0x36,
112         CMD_QUERY_SRQ       = 0x37,
113         CMD_ARM_SRQ         = 0x40,
114
115         /* QP/EE commands */
116         CMD_RST2INIT_QPEE   = 0x19,
117         CMD_INIT2RTR_QPEE   = 0x1a,
118         CMD_RTR2RTS_QPEE    = 0x1b,
119         CMD_RTS2RTS_QPEE    = 0x1c,
120         CMD_SQERR2RTS_QPEE  = 0x1d,
121         CMD_2ERR_QPEE       = 0x1e,
122         CMD_RTS2SQD_QPEE    = 0x1f,
123         CMD_SQD2SQD_QPEE    = 0x38,
124         CMD_SQD2RTS_QPEE    = 0x20,
125         CMD_ERR2RST_QPEE    = 0x21,
126         CMD_QUERY_QPEE      = 0x22,
127         CMD_INIT2INIT_QPEE  = 0x2d,
128         CMD_SUSPEND_QPEE    = 0x32,
129         CMD_UNSUSPEND_QPEE  = 0x33,
130         /* special QPs and management commands */
131         CMD_CONF_SPECIAL_QP = 0x23,
132         CMD_MAD_IFC         = 0x24,
133
134         /* multicast commands */
135         CMD_READ_MGM        = 0x25,
136         CMD_WRITE_MGM       = 0x26,
137         CMD_MGID_HASH       = 0x27,
138
139         /* miscellaneous commands */
140         CMD_DIAG_RPRT       = 0x30,
141         CMD_NOP             = 0x31,
142
143         /* debug commands */
144         CMD_QUERY_DEBUG_MSG = 0x2a,
145         CMD_SET_DEBUG_MSG   = 0x2b,
146 };
147
148 /*
149  * According to Mellanox code, FW may be starved and never complete
150  * commands.  So we can't use strict timeouts described in PRM -- we
151  * just arbitrarily select 60 seconds for now.
152  */
153 #if 0
154 /*
155  * Round up and add 1 to make sure we get the full wait time (since we
156  * will be starting in the middle of a jiffy)
157  */
158 enum {
159         CMD_TIME_CLASS_A = (HZ + 999) / 1000 + 1,
160         CMD_TIME_CLASS_B = (HZ +  99) /  100 + 1,
161         CMD_TIME_CLASS_C = (HZ +   9) /   10 + 1
162 };
163 #else
164 enum {
165         CMD_TIME_CLASS_A = 60 * HZ,
166         CMD_TIME_CLASS_B = 60 * HZ,
167         CMD_TIME_CLASS_C = 60 * HZ
168 };
169 #endif
170
171 enum {
172         GO_BIT_TIMEOUT = HZ * 10
173 };
174
175 struct mthca_cmd_context {
176         struct completion done;
177         int               result;
178         int               next;
179         u64               out_param;
180         u16               token;
181         u8                status;
182 };
183
184 static int fw_cmd_doorbell = 0;
185 module_param(fw_cmd_doorbell, int, 0644);
186 MODULE_PARM_DESC(fw_cmd_doorbell, "post FW commands through doorbell page if nonzero "
187                  "(and supported by FW)");
188
189 static inline int go_bit(struct mthca_dev *dev)
190 {
191         return readl(dev->hcr + HCR_STATUS_OFFSET) &
192                 swab32(1 << HCR_GO_BIT);
193 }
194
195 static void mthca_cmd_post_dbell(struct mthca_dev *dev,
196                                  u64 in_param,
197                                  u64 out_param,
198                                  u32 in_modifier,
199                                  u8 op_modifier,
200                                  u16 op,
201                                  u16 token)
202 {
203         void __iomem *ptr = dev->cmd.dbell_map;
204         u16 *offs = dev->cmd.dbell_offsets;
205
206         __raw_writel((__force u32) cpu_to_be32(in_param >> 32),           ptr + offs[0]);
207         wmb();
208         __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful),  ptr + offs[1]);
209         wmb();
210         __raw_writel((__force u32) cpu_to_be32(in_modifier),              ptr + offs[2]);
211         wmb();
212         __raw_writel((__force u32) cpu_to_be32(out_param >> 32),          ptr + offs[3]);
213         wmb();
214         __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), ptr + offs[4]);
215         wmb();
216         __raw_writel((__force u32) cpu_to_be32(token << 16),              ptr + offs[5]);
217         wmb();
218         __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT)                |
219                                                (1 << HCA_E_BIT)                 |
220                                                (op_modifier << HCR_OPMOD_SHIFT) |
221                                                 op),                      ptr + offs[6]);
222         wmb();
223         __raw_writel((__force u32) 0,                                     ptr + offs[7]);
224         wmb();
225 }
226
227 static int mthca_cmd_post_hcr(struct mthca_dev *dev,
228                               u64 in_param,
229                               u64 out_param,
230                               u32 in_modifier,
231                               u8 op_modifier,
232                               u16 op,
233                               u16 token,
234                               int event)
235 {
236         if (event) {
237                 unsigned long end = jiffies + GO_BIT_TIMEOUT;
238
239                 while (go_bit(dev) && time_before(jiffies, end)) {
240                         set_current_state(TASK_RUNNING);
241                         schedule();
242                 }
243         }
244
245         if (go_bit(dev))
246                 return -EAGAIN;
247
248         /*
249          * We use writel (instead of something like memcpy_toio)
250          * because writes of less than 32 bits to the HCR don't work
251          * (and some architectures such as ia64 implement memcpy_toio
252          * in terms of writeb).
253          */
254         __raw_writel((__force u32) cpu_to_be32(in_param >> 32),           dev->hcr + 0 * 4);
255         __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful),  dev->hcr + 1 * 4);
256         __raw_writel((__force u32) cpu_to_be32(in_modifier),              dev->hcr + 2 * 4);
257         __raw_writel((__force u32) cpu_to_be32(out_param >> 32),          dev->hcr + 3 * 4);
258         __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4);
259         __raw_writel((__force u32) cpu_to_be32(token << 16),              dev->hcr + 5 * 4);
260
261         /* __raw_writel may not order writes. */
262         wmb();
263
264         __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT)                |
265                                                (event ? (1 << HCA_E_BIT) : 0)   |
266                                                (op_modifier << HCR_OPMOD_SHIFT) |
267                                                op),                       dev->hcr + 6 * 4);
268
269         return 0;
270 }
271
272 static int mthca_cmd_post(struct mthca_dev *dev,
273                           u64 in_param,
274                           u64 out_param,
275                           u32 in_modifier,
276                           u8 op_modifier,
277                           u16 op,
278                           u16 token,
279                           int event)
280 {
281         int err = 0;
282
283         mutex_lock(&dev->cmd.hcr_mutex);
284
285         if (event && dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS && fw_cmd_doorbell)
286                 mthca_cmd_post_dbell(dev, in_param, out_param, in_modifier,
287                                            op_modifier, op, token);
288         else
289                 err = mthca_cmd_post_hcr(dev, in_param, out_param, in_modifier,
290                                          op_modifier, op, token, event);
291
292         mutex_unlock(&dev->cmd.hcr_mutex);
293         return err;
294 }
295
296 static int mthca_cmd_poll(struct mthca_dev *dev,
297                           u64 in_param,
298                           u64 *out_param,
299                           int out_is_imm,
300                           u32 in_modifier,
301                           u8 op_modifier,
302                           u16 op,
303                           unsigned long timeout,
304                           u8 *status)
305 {
306         int err = 0;
307         unsigned long end;
308
309         down(&dev->cmd.poll_sem);
310
311         err = mthca_cmd_post(dev, in_param,
312                              out_param ? *out_param : 0,
313                              in_modifier, op_modifier,
314                              op, CMD_POLL_TOKEN, 0);
315         if (err)
316                 goto out;
317
318         end = timeout + jiffies;
319         while (go_bit(dev) && time_before(jiffies, end)) {
320                 set_current_state(TASK_RUNNING);
321                 schedule();
322         }
323
324         if (go_bit(dev)) {
325                 err = -EBUSY;
326                 goto out;
327         }
328
329         if (out_is_imm)
330                 *out_param =
331                         (u64) be32_to_cpu((__force __be32)
332                                           __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
333                         (u64) be32_to_cpu((__force __be32)
334                                           __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET + 4));
335
336         *status = be32_to_cpu((__force __be32) __raw_readl(dev->hcr + HCR_STATUS_OFFSET)) >> 24;
337
338 out:
339         up(&dev->cmd.poll_sem);
340         return err;
341 }
342
343 void mthca_cmd_event(struct mthca_dev *dev,
344                      u16 token,
345                      u8  status,
346                      u64 out_param)
347 {
348         struct mthca_cmd_context *context =
349                 &dev->cmd.context[token & dev->cmd.token_mask];
350
351         /* previously timed out command completing at long last */
352         if (token != context->token)
353                 return;
354
355         context->result    = 0;
356         context->status    = status;
357         context->out_param = out_param;
358
359         context->token += dev->cmd.token_mask + 1;
360
361         complete(&context->done);
362 }
363
364 static int mthca_cmd_wait(struct mthca_dev *dev,
365                           u64 in_param,
366                           u64 *out_param,
367                           int out_is_imm,
368                           u32 in_modifier,
369                           u8 op_modifier,
370                           u16 op,
371                           unsigned long timeout,
372                           u8 *status)
373 {
374         int err = 0;
375         struct mthca_cmd_context *context;
376
377         down(&dev->cmd.event_sem);
378
379         spin_lock(&dev->cmd.context_lock);
380         BUG_ON(dev->cmd.free_head < 0);
381         context = &dev->cmd.context[dev->cmd.free_head];
382         dev->cmd.free_head = context->next;
383         spin_unlock(&dev->cmd.context_lock);
384
385         init_completion(&context->done);
386
387         err = mthca_cmd_post(dev, in_param,
388                              out_param ? *out_param : 0,
389                              in_modifier, op_modifier,
390                              op, context->token, 1);
391         if (err)
392                 goto out;
393
394         if (!wait_for_completion_timeout(&context->done, timeout)) {
395                 err = -EBUSY;
396                 goto out;
397         }
398
399         err = context->result;
400         if (err)
401                 goto out;
402
403         *status = context->status;
404         if (*status)
405                 mthca_dbg(dev, "Command %02x completed with status %02x\n",
406                           op, *status);
407
408         if (out_is_imm)
409                 *out_param = context->out_param;
410
411 out:
412         spin_lock(&dev->cmd.context_lock);
413         context->next = dev->cmd.free_head;
414         dev->cmd.free_head = context - dev->cmd.context;
415         spin_unlock(&dev->cmd.context_lock);
416
417         up(&dev->cmd.event_sem);
418         return err;
419 }
420
421 /* Invoke a command with an output mailbox */
422 static int mthca_cmd_box(struct mthca_dev *dev,
423                          u64 in_param,
424                          u64 out_param,
425                          u32 in_modifier,
426                          u8 op_modifier,
427                          u16 op,
428                          unsigned long timeout,
429                          u8 *status)
430 {
431         if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS)
432                 return mthca_cmd_wait(dev, in_param, &out_param, 0,
433                                       in_modifier, op_modifier, op,
434                                       timeout, status);
435         else
436                 return mthca_cmd_poll(dev, in_param, &out_param, 0,
437                                       in_modifier, op_modifier, op,
438                                       timeout, status);
439 }
440
441 /* Invoke a command with no output parameter */
442 static int mthca_cmd(struct mthca_dev *dev,
443                      u64 in_param,
444                      u32 in_modifier,
445                      u8 op_modifier,
446                      u16 op,
447                      unsigned long timeout,
448                      u8 *status)
449 {
450         return mthca_cmd_box(dev, in_param, 0, in_modifier,
451                              op_modifier, op, timeout, status);
452 }
453
454 /*
455  * Invoke a command with an immediate output parameter (and copy the
456  * output into the caller's out_param pointer after the command
457  * executes).
458  */
459 static int mthca_cmd_imm(struct mthca_dev *dev,
460                          u64 in_param,
461                          u64 *out_param,
462                          u32 in_modifier,
463                          u8 op_modifier,
464                          u16 op,
465                          unsigned long timeout,
466                          u8 *status)
467 {
468         if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS)
469                 return mthca_cmd_wait(dev, in_param, out_param, 1,
470                                       in_modifier, op_modifier, op,
471                                       timeout, status);
472         else
473                 return mthca_cmd_poll(dev, in_param, out_param, 1,
474                                       in_modifier, op_modifier, op,
475                                       timeout, status);
476 }
477
478 int mthca_cmd_init(struct mthca_dev *dev)
479 {
480         mutex_init(&dev->cmd.hcr_mutex);
481         sema_init(&dev->cmd.poll_sem, 1);
482         dev->cmd.flags = 0;
483
484         dev->hcr = ioremap(pci_resource_start(dev->pdev, 0) + MTHCA_HCR_BASE,
485                            MTHCA_HCR_SIZE);
486         if (!dev->hcr) {
487                 mthca_err(dev, "Couldn't map command register.");
488                 return -ENOMEM;
489         }
490
491         dev->cmd.pool = pci_pool_create("mthca_cmd", dev->pdev,
492                                         MTHCA_MAILBOX_SIZE,
493                                         MTHCA_MAILBOX_SIZE, 0);
494         if (!dev->cmd.pool) {
495                 iounmap(dev->hcr);
496                 return -ENOMEM;
497         }
498
499         return 0;
500 }
501
502 void mthca_cmd_cleanup(struct mthca_dev *dev)
503 {
504         pci_pool_destroy(dev->cmd.pool);
505         iounmap(dev->hcr);
506         if (dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS)
507                 iounmap(dev->cmd.dbell_map);
508 }
509
510 /*
511  * Switch to using events to issue FW commands (should be called after
512  * event queue to command events has been initialized).
513  */
514 int mthca_cmd_use_events(struct mthca_dev *dev)
515 {
516         int i;
517
518         dev->cmd.context = kmalloc(dev->cmd.max_cmds *
519                                    sizeof (struct mthca_cmd_context),
520                                    GFP_KERNEL);
521         if (!dev->cmd.context)
522                 return -ENOMEM;
523
524         for (i = 0; i < dev->cmd.max_cmds; ++i) {
525                 dev->cmd.context[i].token = i;
526                 dev->cmd.context[i].next = i + 1;
527         }
528
529         dev->cmd.context[dev->cmd.max_cmds - 1].next = -1;
530         dev->cmd.free_head = 0;
531
532         sema_init(&dev->cmd.event_sem, dev->cmd.max_cmds);
533         spin_lock_init(&dev->cmd.context_lock);
534
535         for (dev->cmd.token_mask = 1;
536              dev->cmd.token_mask < dev->cmd.max_cmds;
537              dev->cmd.token_mask <<= 1)
538                 ; /* nothing */
539         --dev->cmd.token_mask;
540
541         dev->cmd.flags |= MTHCA_CMD_USE_EVENTS;
542
543         down(&dev->cmd.poll_sem);
544
545         return 0;
546 }
547
548 /*
549  * Switch back to polling (used when shutting down the device)
550  */
551 void mthca_cmd_use_polling(struct mthca_dev *dev)
552 {
553         int i;
554
555         dev->cmd.flags &= ~MTHCA_CMD_USE_EVENTS;
556
557         for (i = 0; i < dev->cmd.max_cmds; ++i)
558                 down(&dev->cmd.event_sem);
559
560         kfree(dev->cmd.context);
561
562         up(&dev->cmd.poll_sem);
563 }
564
565 struct mthca_mailbox *mthca_alloc_mailbox(struct mthca_dev *dev,
566                                           gfp_t gfp_mask)
567 {
568         struct mthca_mailbox *mailbox;
569
570         mailbox = kmalloc(sizeof *mailbox, gfp_mask);
571         if (!mailbox)
572                 return ERR_PTR(-ENOMEM);
573
574         mailbox->buf = pci_pool_alloc(dev->cmd.pool, gfp_mask, &mailbox->dma);
575         if (!mailbox->buf) {
576                 kfree(mailbox);
577                 return ERR_PTR(-ENOMEM);
578         }
579
580         return mailbox;
581 }
582
583 void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox)
584 {
585         if (!mailbox)
586                 return;
587
588         pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
589         kfree(mailbox);
590 }
591
592 int mthca_SYS_EN(struct mthca_dev *dev, u8 *status)
593 {
594         u64 out;
595         int ret;
596
597         ret = mthca_cmd_imm(dev, 0, &out, 0, 0, CMD_SYS_EN, HZ, status);
598
599         if (*status == MTHCA_CMD_STAT_DDR_MEM_ERR)
600                 mthca_warn(dev, "SYS_EN DDR error: syn=%x, sock=%d, "
601                            "sladdr=%d, SPD source=%s\n",
602                            (int) (out >> 6) & 0xf, (int) (out >> 4) & 3,
603                            (int) (out >> 1) & 7, (int) out & 1 ? "NVMEM" : "DIMM");
604
605         return ret;
606 }
607
608 int mthca_SYS_DIS(struct mthca_dev *dev, u8 *status)
609 {
610         return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, HZ, status);
611 }
612
613 static int mthca_map_cmd(struct mthca_dev *dev, u16 op, struct mthca_icm *icm,
614                          u64 virt, u8 *status)
615 {
616         struct mthca_mailbox *mailbox;
617         struct mthca_icm_iter iter;
618         __be64 *pages;
619         int lg;
620         int nent = 0;
621         int i;
622         int err = 0;
623         int ts = 0, tc = 0;
624
625         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
626         if (IS_ERR(mailbox))
627                 return PTR_ERR(mailbox);
628         memset(mailbox->buf, 0, MTHCA_MAILBOX_SIZE);
629         pages = mailbox->buf;
630
631         for (mthca_icm_first(icm, &iter);
632              !mthca_icm_last(&iter);
633              mthca_icm_next(&iter)) {
634                 /*
635                  * We have to pass pages that are aligned to their
636                  * size, so find the least significant 1 in the
637                  * address or size and use that as our log2 size.
638                  */
639                 lg = ffs(mthca_icm_addr(&iter) | mthca_icm_size(&iter)) - 1;
640                 if (lg < MTHCA_ICM_PAGE_SHIFT) {
641                         mthca_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
642                                    MTHCA_ICM_PAGE_SIZE,
643                                    (unsigned long long) mthca_icm_addr(&iter),
644                                    mthca_icm_size(&iter));
645                         err = -EINVAL;
646                         goto out;
647                 }
648                 for (i = 0; i < mthca_icm_size(&iter) >> lg; ++i) {
649                         if (virt != -1) {
650                                 pages[nent * 2] = cpu_to_be64(virt);
651                                 virt += 1 << lg;
652                         }
653
654                         pages[nent * 2 + 1] =
655                                 cpu_to_be64((mthca_icm_addr(&iter) + (i << lg)) |
656                                             (lg - MTHCA_ICM_PAGE_SHIFT));
657                         ts += 1 << (lg - 10);
658                         ++tc;
659
660                         if (++nent == MTHCA_MAILBOX_SIZE / 16) {
661                                 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
662                                                 CMD_TIME_CLASS_B, status);
663                                 if (err || *status)
664                                         goto out;
665                                 nent = 0;
666                         }
667                 }
668         }
669
670         if (nent)
671                 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
672                                 CMD_TIME_CLASS_B, status);
673
674         switch (op) {
675         case CMD_MAP_FA:
676                 mthca_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
677                 break;
678         case CMD_MAP_ICM_AUX:
679                 mthca_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
680                 break;
681         case CMD_MAP_ICM:
682                 mthca_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
683                           tc, ts, (unsigned long long) virt - (ts << 10));
684                 break;
685         }
686
687 out:
688         mthca_free_mailbox(dev, mailbox);
689         return err;
690 }
691
692 int mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status)
693 {
694         return mthca_map_cmd(dev, CMD_MAP_FA, icm, -1, status);
695 }
696
697 int mthca_UNMAP_FA(struct mthca_dev *dev, u8 *status)
698 {
699         return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_FA, CMD_TIME_CLASS_B, status);
700 }
701
702 int mthca_RUN_FW(struct mthca_dev *dev, u8 *status)
703 {
704         return mthca_cmd(dev, 0, 0, 0, CMD_RUN_FW, CMD_TIME_CLASS_A, status);
705 }
706
707 static void mthca_setup_cmd_doorbells(struct mthca_dev *dev, u64 base)
708 {
709         unsigned long addr;
710         u16 max_off = 0;
711         int i;
712
713         for (i = 0; i < 8; ++i)
714                 max_off = max(max_off, dev->cmd.dbell_offsets[i]);
715
716         if ((base & PAGE_MASK) != ((base + max_off) & PAGE_MASK)) {
717                 mthca_warn(dev, "Firmware doorbell region at 0x%016llx, "
718                            "length 0x%x crosses a page boundary\n",
719                            (unsigned long long) base, max_off);
720                 return;
721         }
722
723         addr = pci_resource_start(dev->pdev, 2) +
724                 ((pci_resource_len(dev->pdev, 2) - 1) & base);
725         dev->cmd.dbell_map = ioremap(addr, max_off + sizeof(u32));
726         if (!dev->cmd.dbell_map)
727                 return;
728
729         dev->cmd.flags |= MTHCA_CMD_POST_DOORBELLS;
730         mthca_dbg(dev, "Mapped doorbell page for posting FW commands\n");
731 }
732
733 int mthca_QUERY_FW(struct mthca_dev *dev, u8 *status)
734 {
735         struct mthca_mailbox *mailbox;
736         u32 *outbox;
737         u64 base;
738         u32 tmp;
739         int err = 0;
740         u8 lg;
741         int i;
742
743 #define QUERY_FW_OUT_SIZE             0x100
744 #define QUERY_FW_VER_OFFSET            0x00
745 #define QUERY_FW_MAX_CMD_OFFSET        0x0f
746 #define QUERY_FW_ERR_START_OFFSET      0x30
747 #define QUERY_FW_ERR_SIZE_OFFSET       0x38
748
749 #define QUERY_FW_CMD_DB_EN_OFFSET      0x10
750 #define QUERY_FW_CMD_DB_OFFSET         0x50
751 #define QUERY_FW_CMD_DB_BASE           0x60
752
753 #define QUERY_FW_START_OFFSET          0x20
754 #define QUERY_FW_END_OFFSET            0x28
755
756 #define QUERY_FW_SIZE_OFFSET           0x00
757 #define QUERY_FW_CLR_INT_BASE_OFFSET   0x20
758 #define QUERY_FW_EQ_ARM_BASE_OFFSET    0x40
759 #define QUERY_FW_EQ_SET_CI_BASE_OFFSET 0x48
760
761         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
762         if (IS_ERR(mailbox))
763                 return PTR_ERR(mailbox);
764         outbox = mailbox->buf;
765
766         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_FW,
767                             CMD_TIME_CLASS_A, status);
768
769         if (err)
770                 goto out;
771
772         MTHCA_GET(dev->fw_ver,   outbox, QUERY_FW_VER_OFFSET);
773         /*
774          * FW subminor version is at more signifant bits than minor
775          * version, so swap here.
776          */
777         dev->fw_ver = (dev->fw_ver & 0xffff00000000ull) |
778                 ((dev->fw_ver & 0xffff0000ull) >> 16) |
779                 ((dev->fw_ver & 0x0000ffffull) << 16);
780
781         MTHCA_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
782         dev->cmd.max_cmds = 1 << lg;
783
784         mthca_dbg(dev, "FW version %012llx, max commands %d\n",
785                   (unsigned long long) dev->fw_ver, dev->cmd.max_cmds);
786
787         MTHCA_GET(dev->catas_err.addr, outbox, QUERY_FW_ERR_START_OFFSET);
788         MTHCA_GET(dev->catas_err.size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
789
790         mthca_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x\n",
791                   (unsigned long long) dev->catas_err.addr, dev->catas_err.size);
792
793         MTHCA_GET(tmp, outbox, QUERY_FW_CMD_DB_EN_OFFSET);
794         if (tmp & 0x1) {
795                 mthca_dbg(dev, "FW supports commands through doorbells\n");
796
797                 MTHCA_GET(base, outbox, QUERY_FW_CMD_DB_BASE);
798                 for (i = 0; i < MTHCA_CMD_NUM_DBELL_DWORDS; ++i)
799                         MTHCA_GET(dev->cmd.dbell_offsets[i], outbox,
800                                   QUERY_FW_CMD_DB_OFFSET + (i << 1));
801
802                 mthca_setup_cmd_doorbells(dev, base);
803         }
804
805         if (mthca_is_memfree(dev)) {
806                 MTHCA_GET(dev->fw.arbel.fw_pages,       outbox, QUERY_FW_SIZE_OFFSET);
807                 MTHCA_GET(dev->fw.arbel.clr_int_base,   outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
808                 MTHCA_GET(dev->fw.arbel.eq_arm_base,    outbox, QUERY_FW_EQ_ARM_BASE_OFFSET);
809                 MTHCA_GET(dev->fw.arbel.eq_set_ci_base, outbox, QUERY_FW_EQ_SET_CI_BASE_OFFSET);
810                 mthca_dbg(dev, "FW size %d KB\n", dev->fw.arbel.fw_pages << 2);
811
812                 /*
813                  * Round up number of system pages needed in case
814                  * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE.
815                  */
816                 dev->fw.arbel.fw_pages =
817                         ALIGN(dev->fw.arbel.fw_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >>
818                                 (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT);
819
820                 mthca_dbg(dev, "Clear int @ %llx, EQ arm @ %llx, EQ set CI @ %llx\n",
821                           (unsigned long long) dev->fw.arbel.clr_int_base,
822                           (unsigned long long) dev->fw.arbel.eq_arm_base,
823                           (unsigned long long) dev->fw.arbel.eq_set_ci_base);
824         } else {
825                 MTHCA_GET(dev->fw.tavor.fw_start, outbox, QUERY_FW_START_OFFSET);
826                 MTHCA_GET(dev->fw.tavor.fw_end,   outbox, QUERY_FW_END_OFFSET);
827
828                 mthca_dbg(dev, "FW size %d KB (start %llx, end %llx)\n",
829                           (int) ((dev->fw.tavor.fw_end - dev->fw.tavor.fw_start) >> 10),
830                           (unsigned long long) dev->fw.tavor.fw_start,
831                           (unsigned long long) dev->fw.tavor.fw_end);
832         }
833
834 out:
835         mthca_free_mailbox(dev, mailbox);
836         return err;
837 }
838
839 int mthca_ENABLE_LAM(struct mthca_dev *dev, u8 *status)
840 {
841         struct mthca_mailbox *mailbox;
842         u8 info;
843         u32 *outbox;
844         int err = 0;
845
846 #define ENABLE_LAM_OUT_SIZE         0x100
847 #define ENABLE_LAM_START_OFFSET     0x00
848 #define ENABLE_LAM_END_OFFSET       0x08
849 #define ENABLE_LAM_INFO_OFFSET      0x13
850
851 #define ENABLE_LAM_INFO_HIDDEN_FLAG (1 << 4)
852 #define ENABLE_LAM_INFO_ECC_MASK    0x3
853
854         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
855         if (IS_ERR(mailbox))
856                 return PTR_ERR(mailbox);
857         outbox = mailbox->buf;
858
859         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_ENABLE_LAM,
860                             CMD_TIME_CLASS_C, status);
861
862         if (err)
863                 goto out;
864
865         if (*status == MTHCA_CMD_STAT_LAM_NOT_PRE)
866                 goto out;
867
868         MTHCA_GET(dev->ddr_start, outbox, ENABLE_LAM_START_OFFSET);
869         MTHCA_GET(dev->ddr_end,   outbox, ENABLE_LAM_END_OFFSET);
870         MTHCA_GET(info,           outbox, ENABLE_LAM_INFO_OFFSET);
871
872         if (!!(info & ENABLE_LAM_INFO_HIDDEN_FLAG) !=
873             !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
874                 mthca_info(dev, "FW reports that HCA-attached memory "
875                            "is %s hidden; does not match PCI config\n",
876                            (info & ENABLE_LAM_INFO_HIDDEN_FLAG) ?
877                            "" : "not");
878         }
879         if (info & ENABLE_LAM_INFO_HIDDEN_FLAG)
880                 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
881
882         mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
883                   (int) ((dev->ddr_end - dev->ddr_start) >> 10),
884                   (unsigned long long) dev->ddr_start,
885                   (unsigned long long) dev->ddr_end);
886
887 out:
888         mthca_free_mailbox(dev, mailbox);
889         return err;
890 }
891
892 int mthca_DISABLE_LAM(struct mthca_dev *dev, u8 *status)
893 {
894         return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C, status);
895 }
896
897 int mthca_QUERY_DDR(struct mthca_dev *dev, u8 *status)
898 {
899         struct mthca_mailbox *mailbox;
900         u8 info;
901         u32 *outbox;
902         int err = 0;
903
904 #define QUERY_DDR_OUT_SIZE         0x100
905 #define QUERY_DDR_START_OFFSET     0x00
906 #define QUERY_DDR_END_OFFSET       0x08
907 #define QUERY_DDR_INFO_OFFSET      0x13
908
909 #define QUERY_DDR_INFO_HIDDEN_FLAG (1 << 4)
910 #define QUERY_DDR_INFO_ECC_MASK    0x3
911
912         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
913         if (IS_ERR(mailbox))
914                 return PTR_ERR(mailbox);
915         outbox = mailbox->buf;
916
917         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DDR,
918                             CMD_TIME_CLASS_A, status);
919
920         if (err)
921                 goto out;
922
923         MTHCA_GET(dev->ddr_start, outbox, QUERY_DDR_START_OFFSET);
924         MTHCA_GET(dev->ddr_end,   outbox, QUERY_DDR_END_OFFSET);
925         MTHCA_GET(info,           outbox, QUERY_DDR_INFO_OFFSET);
926
927         if (!!(info & QUERY_DDR_INFO_HIDDEN_FLAG) !=
928             !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
929                 mthca_info(dev, "FW reports that HCA-attached memory "
930                            "is %s hidden; does not match PCI config\n",
931                            (info & QUERY_DDR_INFO_HIDDEN_FLAG) ?
932                            "" : "not");
933         }
934         if (info & QUERY_DDR_INFO_HIDDEN_FLAG)
935                 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
936
937         mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
938                   (int) ((dev->ddr_end - dev->ddr_start) >> 10),
939                   (unsigned long long) dev->ddr_start,
940                   (unsigned long long) dev->ddr_end);
941
942 out:
943         mthca_free_mailbox(dev, mailbox);
944         return err;
945 }
946
947 int mthca_QUERY_DEV_LIM(struct mthca_dev *dev,
948                         struct mthca_dev_lim *dev_lim, u8 *status)
949 {
950         struct mthca_mailbox *mailbox;
951         u32 *outbox;
952         u8 field;
953         u16 size;
954         u16 stat_rate;
955         int err;
956
957 #define QUERY_DEV_LIM_OUT_SIZE             0x100
958 #define QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET     0x10
959 #define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET      0x11
960 #define QUERY_DEV_LIM_RSVD_QP_OFFSET        0x12
961 #define QUERY_DEV_LIM_MAX_QP_OFFSET         0x13
962 #define QUERY_DEV_LIM_RSVD_SRQ_OFFSET       0x14
963 #define QUERY_DEV_LIM_MAX_SRQ_OFFSET        0x15
964 #define QUERY_DEV_LIM_RSVD_EEC_OFFSET       0x16
965 #define QUERY_DEV_LIM_MAX_EEC_OFFSET        0x17
966 #define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET      0x19
967 #define QUERY_DEV_LIM_RSVD_CQ_OFFSET        0x1a
968 #define QUERY_DEV_LIM_MAX_CQ_OFFSET         0x1b
969 #define QUERY_DEV_LIM_MAX_MPT_OFFSET        0x1d
970 #define QUERY_DEV_LIM_RSVD_EQ_OFFSET        0x1e
971 #define QUERY_DEV_LIM_MAX_EQ_OFFSET         0x1f
972 #define QUERY_DEV_LIM_RSVD_MTT_OFFSET       0x20
973 #define QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET     0x21
974 #define QUERY_DEV_LIM_RSVD_MRW_OFFSET       0x22
975 #define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET    0x23
976 #define QUERY_DEV_LIM_MAX_AV_OFFSET         0x27
977 #define QUERY_DEV_LIM_MAX_REQ_QP_OFFSET     0x29
978 #define QUERY_DEV_LIM_MAX_RES_QP_OFFSET     0x2b
979 #define QUERY_DEV_LIM_MAX_RDMA_OFFSET       0x2f
980 #define QUERY_DEV_LIM_RSZ_SRQ_OFFSET        0x33
981 #define QUERY_DEV_LIM_ACK_DELAY_OFFSET      0x35
982 #define QUERY_DEV_LIM_MTU_WIDTH_OFFSET      0x36
983 #define QUERY_DEV_LIM_VL_PORT_OFFSET        0x37
984 #define QUERY_DEV_LIM_MAX_GID_OFFSET        0x3b
985 #define QUERY_DEV_LIM_RATE_SUPPORT_OFFSET   0x3c
986 #define QUERY_DEV_LIM_MAX_PKEY_OFFSET       0x3f
987 #define QUERY_DEV_LIM_FLAGS_OFFSET          0x44
988 #define QUERY_DEV_LIM_RSVD_UAR_OFFSET       0x48
989 #define QUERY_DEV_LIM_UAR_SZ_OFFSET         0x49
990 #define QUERY_DEV_LIM_PAGE_SZ_OFFSET        0x4b
991 #define QUERY_DEV_LIM_MAX_SG_OFFSET         0x51
992 #define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET    0x52
993 #define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET      0x55
994 #define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET 0x56
995 #define QUERY_DEV_LIM_MAX_QP_MCG_OFFSET     0x61
996 #define QUERY_DEV_LIM_RSVD_MCG_OFFSET       0x62
997 #define QUERY_DEV_LIM_MAX_MCG_OFFSET        0x63
998 #define QUERY_DEV_LIM_RSVD_PD_OFFSET        0x64
999 #define QUERY_DEV_LIM_MAX_PD_OFFSET         0x65
1000 #define QUERY_DEV_LIM_RSVD_RDD_OFFSET       0x66
1001 #define QUERY_DEV_LIM_MAX_RDD_OFFSET        0x67
1002 #define QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET   0x80
1003 #define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET   0x82
1004 #define QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET  0x84
1005 #define QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET  0x86
1006 #define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET   0x88
1007 #define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET   0x8a
1008 #define QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET   0x8c
1009 #define QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET   0x8e
1010 #define QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET   0x90
1011 #define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET   0x92
1012 #define QUERY_DEV_LIM_PBL_SZ_OFFSET         0x96
1013 #define QUERY_DEV_LIM_BMME_FLAGS_OFFSET     0x97
1014 #define QUERY_DEV_LIM_RSVD_LKEY_OFFSET      0x98
1015 #define QUERY_DEV_LIM_LAMR_OFFSET           0x9f
1016 #define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET     0xa0
1017
1018         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1019         if (IS_ERR(mailbox))
1020                 return PTR_ERR(mailbox);
1021         outbox = mailbox->buf;
1022
1023         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DEV_LIM,
1024                             CMD_TIME_CLASS_A, status);
1025
1026         if (err)
1027                 goto out;
1028
1029         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_QP_OFFSET);
1030         dev_lim->reserved_qps = 1 << (field & 0xf);
1031         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_OFFSET);
1032         dev_lim->max_qps = 1 << (field & 0x1f);
1033         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_SRQ_OFFSET);
1034         dev_lim->reserved_srqs = 1 << (field >> 4);
1035         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_OFFSET);
1036         dev_lim->max_srqs = 1 << (field & 0x1f);
1037         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EEC_OFFSET);
1038         dev_lim->reserved_eecs = 1 << (field & 0xf);
1039         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EEC_OFFSET);
1040         dev_lim->max_eecs = 1 << (field & 0x1f);
1041         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET);
1042         dev_lim->max_cq_sz = 1 << field;
1043         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_CQ_OFFSET);
1044         dev_lim->reserved_cqs = 1 << (field & 0xf);
1045         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_OFFSET);
1046         dev_lim->max_cqs = 1 << (field & 0x1f);
1047         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MPT_OFFSET);
1048         dev_lim->max_mpts = 1 << (field & 0x3f);
1049         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EQ_OFFSET);
1050         dev_lim->reserved_eqs = 1 << (field & 0xf);
1051         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EQ_OFFSET);
1052         dev_lim->max_eqs = 1 << (field & 0x7);
1053         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MTT_OFFSET);
1054         dev_lim->reserved_mtts = 1 << (field >> 4);
1055         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET);
1056         dev_lim->max_mrw_sz = 1 << field;
1057         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MRW_OFFSET);
1058         dev_lim->reserved_mrws = 1 << (field & 0xf);
1059         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET);
1060         dev_lim->max_mtt_seg = 1 << (field & 0x3f);
1061         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_REQ_QP_OFFSET);
1062         dev_lim->max_requester_per_qp = 1 << (field & 0x3f);
1063         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RES_QP_OFFSET);
1064         dev_lim->max_responder_per_qp = 1 << (field & 0x3f);
1065         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDMA_OFFSET);
1066         dev_lim->max_rdma_global = 1 << (field & 0x3f);
1067         MTHCA_GET(field, outbox, QUERY_DEV_LIM_ACK_DELAY_OFFSET);
1068         dev_lim->local_ca_ack_delay = field & 0x1f;
1069         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MTU_WIDTH_OFFSET);
1070         dev_lim->max_mtu        = field >> 4;
1071         dev_lim->max_port_width = field & 0xf;
1072         MTHCA_GET(field, outbox, QUERY_DEV_LIM_VL_PORT_OFFSET);
1073         dev_lim->max_vl    = field >> 4;
1074         dev_lim->num_ports = field & 0xf;
1075         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_GID_OFFSET);
1076         dev_lim->max_gids = 1 << (field & 0xf);
1077         MTHCA_GET(stat_rate, outbox, QUERY_DEV_LIM_RATE_SUPPORT_OFFSET);
1078         dev_lim->stat_rate_support = stat_rate;
1079         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PKEY_OFFSET);
1080         dev_lim->max_pkeys = 1 << (field & 0xf);
1081         MTHCA_GET(dev_lim->flags, outbox, QUERY_DEV_LIM_FLAGS_OFFSET);
1082         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_UAR_OFFSET);
1083         dev_lim->reserved_uars = field >> 4;
1084         MTHCA_GET(field, outbox, QUERY_DEV_LIM_UAR_SZ_OFFSET);
1085         dev_lim->uar_size = 1 << ((field & 0x3f) + 20);
1086         MTHCA_GET(field, outbox, QUERY_DEV_LIM_PAGE_SZ_OFFSET);
1087         dev_lim->min_page_sz = 1 << field;
1088         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_OFFSET);
1089         dev_lim->max_sg = field;
1090
1091         MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET);
1092         dev_lim->max_desc_sz = size;
1093
1094         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_MCG_OFFSET);
1095         dev_lim->max_qp_per_mcg = 1 << field;
1096         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MCG_OFFSET);
1097         dev_lim->reserved_mgms = field & 0xf;
1098         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MCG_OFFSET);
1099         dev_lim->max_mcgs = 1 << field;
1100         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_PD_OFFSET);
1101         dev_lim->reserved_pds = field >> 4;
1102         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PD_OFFSET);
1103         dev_lim->max_pds = 1 << (field & 0x3f);
1104         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_RDD_OFFSET);
1105         dev_lim->reserved_rdds = field >> 4;
1106         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDD_OFFSET);
1107         dev_lim->max_rdds = 1 << (field & 0x3f);
1108
1109         MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET);
1110         dev_lim->eec_entry_sz = size;
1111         MTHCA_GET(size, outbox, QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET);
1112         dev_lim->qpc_entry_sz = size;
1113         MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET);
1114         dev_lim->eeec_entry_sz = size;
1115         MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET);
1116         dev_lim->eqpc_entry_sz = size;
1117         MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET);
1118         dev_lim->eqc_entry_sz = size;
1119         MTHCA_GET(size, outbox, QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET);
1120         dev_lim->cqc_entry_sz = size;
1121         MTHCA_GET(size, outbox, QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET);
1122         dev_lim->srq_entry_sz = size;
1123         MTHCA_GET(size, outbox, QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET);
1124         dev_lim->uar_scratch_entry_sz = size;
1125
1126         if (mthca_is_memfree(dev)) {
1127                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
1128                 dev_lim->max_srq_sz = 1 << field;
1129                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
1130                 dev_lim->max_qp_sz = 1 << field;
1131                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSZ_SRQ_OFFSET);
1132                 dev_lim->hca.arbel.resize_srq = field & 1;
1133                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_RQ_OFFSET);
1134                 dev_lim->max_sg = min_t(int, field, dev_lim->max_sg);
1135                 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET);
1136                 dev_lim->max_desc_sz = min_t(int, size, dev_lim->max_desc_sz);
1137                 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET);
1138                 dev_lim->mpt_entry_sz = size;
1139                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_PBL_SZ_OFFSET);
1140                 dev_lim->hca.arbel.max_pbl_sz = 1 << (field & 0x3f);
1141                 MTHCA_GET(dev_lim->hca.arbel.bmme_flags, outbox,
1142                           QUERY_DEV_LIM_BMME_FLAGS_OFFSET);
1143                 MTHCA_GET(dev_lim->hca.arbel.reserved_lkey, outbox,
1144                           QUERY_DEV_LIM_RSVD_LKEY_OFFSET);
1145                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_LAMR_OFFSET);
1146                 dev_lim->hca.arbel.lam_required = field & 1;
1147                 MTHCA_GET(dev_lim->hca.arbel.max_icm_sz, outbox,
1148                           QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET);
1149
1150                 if (dev_lim->hca.arbel.bmme_flags & 1)
1151                         mthca_dbg(dev, "Base MM extensions: yes "
1152                                   "(flags %d, max PBL %d, rsvd L_Key %08x)\n",
1153                                   dev_lim->hca.arbel.bmme_flags,
1154                                   dev_lim->hca.arbel.max_pbl_sz,
1155                                   dev_lim->hca.arbel.reserved_lkey);
1156                 else
1157                         mthca_dbg(dev, "Base MM extensions: no\n");
1158
1159                 mthca_dbg(dev, "Max ICM size %lld MB\n",
1160                           (unsigned long long) dev_lim->hca.arbel.max_icm_sz >> 20);
1161         } else {
1162                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
1163                 dev_lim->max_srq_sz = (1 << field) - 1;
1164                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
1165                 dev_lim->max_qp_sz = (1 << field) - 1;
1166                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_AV_OFFSET);
1167                 dev_lim->hca.tavor.max_avs = 1 << (field & 0x3f);
1168                 dev_lim->mpt_entry_sz = MTHCA_MPT_ENTRY_SIZE;
1169         }
1170
1171         mthca_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
1172                   dev_lim->max_qps, dev_lim->reserved_qps, dev_lim->qpc_entry_sz);
1173         mthca_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
1174                   dev_lim->max_srqs, dev_lim->reserved_srqs, dev_lim->srq_entry_sz);
1175         mthca_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
1176                   dev_lim->max_cqs, dev_lim->reserved_cqs, dev_lim->cqc_entry_sz);
1177         mthca_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
1178                   dev_lim->max_eqs, dev_lim->reserved_eqs, dev_lim->eqc_entry_sz);
1179         mthca_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
1180                   dev_lim->reserved_mrws, dev_lim->reserved_mtts);
1181         mthca_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
1182                   dev_lim->max_pds, dev_lim->reserved_pds, dev_lim->reserved_uars);
1183         mthca_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
1184                   dev_lim->max_pds, dev_lim->reserved_mgms);
1185         mthca_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
1186                   dev_lim->max_cq_sz, dev_lim->max_qp_sz, dev_lim->max_srq_sz);
1187
1188         mthca_dbg(dev, "Flags: %08x\n", dev_lim->flags);
1189
1190 out:
1191         mthca_free_mailbox(dev, mailbox);
1192         return err;
1193 }
1194
1195 static void get_board_id(void *vsd, char *board_id)
1196 {
1197         int i;
1198
1199 #define VSD_OFFSET_SIG1         0x00
1200 #define VSD_OFFSET_SIG2         0xde
1201 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
1202 #define VSD_OFFSET_TS_BOARD_ID  0x20
1203
1204 #define VSD_SIGNATURE_TOPSPIN   0x5ad
1205
1206         memset(board_id, 0, MTHCA_BOARD_ID_LEN);
1207
1208         if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1209             be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1210                 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MTHCA_BOARD_ID_LEN);
1211         } else {
1212                 /*
1213                  * The board ID is a string but the firmware byte
1214                  * swaps each 4-byte word before passing it back to
1215                  * us.  Therefore we need to swab it before printing.
1216                  */
1217                 for (i = 0; i < 4; ++i)
1218                         ((u32 *) board_id)[i] =
1219                                 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1220         }
1221 }
1222
1223 int mthca_QUERY_ADAPTER(struct mthca_dev *dev,
1224                         struct mthca_adapter *adapter, u8 *status)
1225 {
1226         struct mthca_mailbox *mailbox;
1227         u32 *outbox;
1228         int err;
1229
1230 #define QUERY_ADAPTER_OUT_SIZE             0x100
1231 #define QUERY_ADAPTER_VENDOR_ID_OFFSET     0x00
1232 #define QUERY_ADAPTER_DEVICE_ID_OFFSET     0x04
1233 #define QUERY_ADAPTER_REVISION_ID_OFFSET   0x08
1234 #define QUERY_ADAPTER_INTA_PIN_OFFSET      0x10
1235 #define QUERY_ADAPTER_VSD_OFFSET           0x20
1236
1237         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1238         if (IS_ERR(mailbox))
1239                 return PTR_ERR(mailbox);
1240         outbox = mailbox->buf;
1241
1242         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_ADAPTER,
1243                             CMD_TIME_CLASS_A, status);
1244
1245         if (err)
1246                 goto out;
1247
1248         MTHCA_GET(adapter->vendor_id, outbox,   QUERY_ADAPTER_VENDOR_ID_OFFSET);
1249         MTHCA_GET(adapter->device_id, outbox,   QUERY_ADAPTER_DEVICE_ID_OFFSET);
1250         MTHCA_GET(adapter->revision_id, outbox, QUERY_ADAPTER_REVISION_ID_OFFSET);
1251         MTHCA_GET(adapter->inta_pin, outbox,    QUERY_ADAPTER_INTA_PIN_OFFSET);
1252
1253         get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1254                      adapter->board_id);
1255
1256 out:
1257         mthca_free_mailbox(dev, mailbox);
1258         return err;
1259 }
1260
1261 int mthca_INIT_HCA(struct mthca_dev *dev,
1262                    struct mthca_init_hca_param *param,
1263                    u8 *status)
1264 {
1265         struct mthca_mailbox *mailbox;
1266         __be32 *inbox;
1267         int err;
1268
1269 #define INIT_HCA_IN_SIZE                 0x200
1270 #define INIT_HCA_FLAGS1_OFFSET           0x00c
1271 #define INIT_HCA_FLAGS2_OFFSET           0x014
1272 #define INIT_HCA_QPC_OFFSET              0x020
1273 #define  INIT_HCA_QPC_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x10)
1274 #define  INIT_HCA_LOG_QP_OFFSET          (INIT_HCA_QPC_OFFSET + 0x17)
1275 #define  INIT_HCA_EEC_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x20)
1276 #define  INIT_HCA_LOG_EEC_OFFSET         (INIT_HCA_QPC_OFFSET + 0x27)
1277 #define  INIT_HCA_SRQC_BASE_OFFSET       (INIT_HCA_QPC_OFFSET + 0x28)
1278 #define  INIT_HCA_LOG_SRQ_OFFSET         (INIT_HCA_QPC_OFFSET + 0x2f)
1279 #define  INIT_HCA_CQC_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x30)
1280 #define  INIT_HCA_LOG_CQ_OFFSET          (INIT_HCA_QPC_OFFSET + 0x37)
1281 #define  INIT_HCA_EQPC_BASE_OFFSET       (INIT_HCA_QPC_OFFSET + 0x40)
1282 #define  INIT_HCA_EEEC_BASE_OFFSET       (INIT_HCA_QPC_OFFSET + 0x50)
1283 #define  INIT_HCA_EQC_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x60)
1284 #define  INIT_HCA_LOG_EQ_OFFSET          (INIT_HCA_QPC_OFFSET + 0x67)
1285 #define  INIT_HCA_RDB_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x70)
1286 #define INIT_HCA_UDAV_OFFSET             0x0b0
1287 #define  INIT_HCA_UDAV_LKEY_OFFSET       (INIT_HCA_UDAV_OFFSET + 0x0)
1288 #define  INIT_HCA_UDAV_PD_OFFSET         (INIT_HCA_UDAV_OFFSET + 0x4)
1289 #define INIT_HCA_MCAST_OFFSET            0x0c0
1290 #define  INIT_HCA_MC_BASE_OFFSET         (INIT_HCA_MCAST_OFFSET + 0x00)
1291 #define  INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1292 #define  INIT_HCA_MC_HASH_SZ_OFFSET      (INIT_HCA_MCAST_OFFSET + 0x16)
1293 #define  INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1294 #define INIT_HCA_TPT_OFFSET              0x0f0
1295 #define  INIT_HCA_MPT_BASE_OFFSET        (INIT_HCA_TPT_OFFSET + 0x00)
1296 #define  INIT_HCA_MTT_SEG_SZ_OFFSET      (INIT_HCA_TPT_OFFSET + 0x09)
1297 #define  INIT_HCA_LOG_MPT_SZ_OFFSET      (INIT_HCA_TPT_OFFSET + 0x0b)
1298 #define  INIT_HCA_MTT_BASE_OFFSET        (INIT_HCA_TPT_OFFSET + 0x10)
1299 #define INIT_HCA_UAR_OFFSET              0x120
1300 #define  INIT_HCA_UAR_BASE_OFFSET        (INIT_HCA_UAR_OFFSET + 0x00)
1301 #define  INIT_HCA_UARC_SZ_OFFSET         (INIT_HCA_UAR_OFFSET + 0x09)
1302 #define  INIT_HCA_LOG_UAR_SZ_OFFSET      (INIT_HCA_UAR_OFFSET + 0x0a)
1303 #define  INIT_HCA_UAR_PAGE_SZ_OFFSET     (INIT_HCA_UAR_OFFSET + 0x0b)
1304 #define  INIT_HCA_UAR_SCATCH_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x10)
1305 #define  INIT_HCA_UAR_CTX_BASE_OFFSET    (INIT_HCA_UAR_OFFSET + 0x18)
1306
1307         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1308         if (IS_ERR(mailbox))
1309                 return PTR_ERR(mailbox);
1310         inbox = mailbox->buf;
1311
1312         memset(inbox, 0, INIT_HCA_IN_SIZE);
1313
1314         if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
1315                 MTHCA_PUT(inbox, 0x1, INIT_HCA_FLAGS1_OFFSET);
1316
1317 #if defined(__LITTLE_ENDIAN)
1318         *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1319 #elif defined(__BIG_ENDIAN)
1320         *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1 << 1);
1321 #else
1322 #error Host endianness not defined
1323 #endif
1324         /* Check port for UD address vector: */
1325         *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1);
1326
1327         /* We leave wqe_quota, responder_exu, etc as 0 (default) */
1328
1329         /* QPC/EEC/CQC/EQC/RDB attributes */
1330
1331         MTHCA_PUT(inbox, param->qpc_base,     INIT_HCA_QPC_BASE_OFFSET);
1332         MTHCA_PUT(inbox, param->log_num_qps,  INIT_HCA_LOG_QP_OFFSET);
1333         MTHCA_PUT(inbox, param->eec_base,     INIT_HCA_EEC_BASE_OFFSET);
1334         MTHCA_PUT(inbox, param->log_num_eecs, INIT_HCA_LOG_EEC_OFFSET);
1335         MTHCA_PUT(inbox, param->srqc_base,    INIT_HCA_SRQC_BASE_OFFSET);
1336         MTHCA_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1337         MTHCA_PUT(inbox, param->cqc_base,     INIT_HCA_CQC_BASE_OFFSET);
1338         MTHCA_PUT(inbox, param->log_num_cqs,  INIT_HCA_LOG_CQ_OFFSET);
1339         MTHCA_PUT(inbox, param->eqpc_base,    INIT_HCA_EQPC_BASE_OFFSET);
1340         MTHCA_PUT(inbox, param->eeec_base,    INIT_HCA_EEEC_BASE_OFFSET);
1341         MTHCA_PUT(inbox, param->eqc_base,     INIT_HCA_EQC_BASE_OFFSET);
1342         MTHCA_PUT(inbox, param->log_num_eqs,  INIT_HCA_LOG_EQ_OFFSET);
1343         MTHCA_PUT(inbox, param->rdb_base,     INIT_HCA_RDB_BASE_OFFSET);
1344
1345         /* UD AV attributes */
1346
1347         /* multicast attributes */
1348
1349         MTHCA_PUT(inbox, param->mc_base,         INIT_HCA_MC_BASE_OFFSET);
1350         MTHCA_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1351         MTHCA_PUT(inbox, param->mc_hash_sz,      INIT_HCA_MC_HASH_SZ_OFFSET);
1352         MTHCA_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1353
1354         /* TPT attributes */
1355
1356         MTHCA_PUT(inbox, param->mpt_base,   INIT_HCA_MPT_BASE_OFFSET);
1357         if (!mthca_is_memfree(dev))
1358                 MTHCA_PUT(inbox, param->mtt_seg_sz, INIT_HCA_MTT_SEG_SZ_OFFSET);
1359         MTHCA_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1360         MTHCA_PUT(inbox, param->mtt_base,   INIT_HCA_MTT_BASE_OFFSET);
1361
1362         /* UAR attributes */
1363         {
1364                 u8 uar_page_sz = PAGE_SHIFT - 12;
1365                 MTHCA_PUT(inbox, uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1366         }
1367
1368         MTHCA_PUT(inbox, param->uar_scratch_base, INIT_HCA_UAR_SCATCH_BASE_OFFSET);
1369
1370         if (mthca_is_memfree(dev)) {
1371                 MTHCA_PUT(inbox, param->log_uarc_sz, INIT_HCA_UARC_SZ_OFFSET);
1372                 MTHCA_PUT(inbox, param->log_uar_sz,  INIT_HCA_LOG_UAR_SZ_OFFSET);
1373                 MTHCA_PUT(inbox, param->uarc_base,   INIT_HCA_UAR_CTX_BASE_OFFSET);
1374         }
1375
1376         err = mthca_cmd(dev, mailbox->dma, 0, 0, CMD_INIT_HCA, HZ, status);
1377
1378         mthca_free_mailbox(dev, mailbox);
1379         return err;
1380 }
1381
1382 int mthca_INIT_IB(struct mthca_dev *dev,
1383                   struct mthca_init_ib_param *param,
1384                   int port, u8 *status)
1385 {
1386         struct mthca_mailbox *mailbox;
1387         u32 *inbox;
1388         int err;
1389         u32 flags;
1390
1391 #define INIT_IB_IN_SIZE          56
1392 #define INIT_IB_FLAGS_OFFSET     0x00
1393 #define INIT_IB_FLAG_SIG         (1 << 18)
1394 #define INIT_IB_FLAG_NG          (1 << 17)
1395 #define INIT_IB_FLAG_G0          (1 << 16)
1396 #define INIT_IB_VL_SHIFT         4
1397 #define INIT_IB_PORT_WIDTH_SHIFT 8
1398 #define INIT_IB_MTU_SHIFT        12
1399 #define INIT_IB_MAX_GID_OFFSET   0x06
1400 #define INIT_IB_MAX_PKEY_OFFSET  0x0a
1401 #define INIT_IB_GUID0_OFFSET     0x10
1402 #define INIT_IB_NODE_GUID_OFFSET 0x18
1403 #define INIT_IB_SI_GUID_OFFSET   0x20
1404
1405         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1406         if (IS_ERR(mailbox))
1407                 return PTR_ERR(mailbox);
1408         inbox = mailbox->buf;
1409
1410         memset(inbox, 0, INIT_IB_IN_SIZE);
1411
1412         flags = 0;
1413         flags |= param->set_guid0     ? INIT_IB_FLAG_G0  : 0;
1414         flags |= param->set_node_guid ? INIT_IB_FLAG_NG  : 0;
1415         flags |= param->set_si_guid   ? INIT_IB_FLAG_SIG : 0;
1416         flags |= param->vl_cap << INIT_IB_VL_SHIFT;
1417         flags |= param->port_width << INIT_IB_PORT_WIDTH_SHIFT;
1418         flags |= param->mtu_cap << INIT_IB_MTU_SHIFT;
1419         MTHCA_PUT(inbox, flags, INIT_IB_FLAGS_OFFSET);
1420
1421         MTHCA_PUT(inbox, param->gid_cap,   INIT_IB_MAX_GID_OFFSET);
1422         MTHCA_PUT(inbox, param->pkey_cap,  INIT_IB_MAX_PKEY_OFFSET);
1423         MTHCA_PUT(inbox, param->guid0,     INIT_IB_GUID0_OFFSET);
1424         MTHCA_PUT(inbox, param->node_guid, INIT_IB_NODE_GUID_OFFSET);
1425         MTHCA_PUT(inbox, param->si_guid,   INIT_IB_SI_GUID_OFFSET);
1426
1427         err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_INIT_IB,
1428                         CMD_TIME_CLASS_A, status);
1429
1430         mthca_free_mailbox(dev, mailbox);
1431         return err;
1432 }
1433
1434 int mthca_CLOSE_IB(struct mthca_dev *dev, int port, u8 *status)
1435 {
1436         return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, HZ, status);
1437 }
1438
1439 int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic, u8 *status)
1440 {
1441         return mthca_cmd(dev, 0, 0, panic, CMD_CLOSE_HCA, HZ, status);
1442 }
1443
1444 int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param,
1445                  int port, u8 *status)
1446 {
1447         struct mthca_mailbox *mailbox;
1448         u32 *inbox;
1449         int err;
1450         u32 flags = 0;
1451
1452 #define SET_IB_IN_SIZE         0x40
1453 #define SET_IB_FLAGS_OFFSET    0x00
1454 #define SET_IB_FLAG_SIG        (1 << 18)
1455 #define SET_IB_FLAG_RQK        (1 <<  0)
1456 #define SET_IB_CAP_MASK_OFFSET 0x04
1457 #define SET_IB_SI_GUID_OFFSET  0x08
1458
1459         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1460         if (IS_ERR(mailbox))
1461                 return PTR_ERR(mailbox);
1462         inbox = mailbox->buf;
1463
1464         memset(inbox, 0, SET_IB_IN_SIZE);
1465
1466         flags |= param->set_si_guid     ? SET_IB_FLAG_SIG : 0;
1467         flags |= param->reset_qkey_viol ? SET_IB_FLAG_RQK : 0;
1468         MTHCA_PUT(inbox, flags, SET_IB_FLAGS_OFFSET);
1469
1470         MTHCA_PUT(inbox, param->cap_mask, SET_IB_CAP_MASK_OFFSET);
1471         MTHCA_PUT(inbox, param->si_guid,  SET_IB_SI_GUID_OFFSET);
1472
1473         err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_SET_IB,
1474                         CMD_TIME_CLASS_B, status);
1475
1476         mthca_free_mailbox(dev, mailbox);
1477         return err;
1478 }
1479
1480 int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt, u8 *status)
1481 {
1482         return mthca_map_cmd(dev, CMD_MAP_ICM, icm, virt, status);
1483 }
1484
1485 int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt, u8 *status)
1486 {
1487         struct mthca_mailbox *mailbox;
1488         __be64 *inbox;
1489         int err;
1490
1491         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1492         if (IS_ERR(mailbox))
1493                 return PTR_ERR(mailbox);
1494         inbox = mailbox->buf;
1495
1496         inbox[0] = cpu_to_be64(virt);
1497         inbox[1] = cpu_to_be64(dma_addr);
1498
1499         err = mthca_cmd(dev, mailbox->dma, 1, 0, CMD_MAP_ICM,
1500                         CMD_TIME_CLASS_B, status);
1501
1502         mthca_free_mailbox(dev, mailbox);
1503
1504         if (!err)
1505                 mthca_dbg(dev, "Mapped page at %llx to %llx for ICM.\n",
1506                           (unsigned long long) dma_addr, (unsigned long long) virt);
1507
1508         return err;
1509 }
1510
1511 int mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count, u8 *status)
1512 {
1513         mthca_dbg(dev, "Unmapping %d pages at %llx from ICM.\n",
1514                   page_count, (unsigned long long) virt);
1515
1516         return mthca_cmd(dev, virt, page_count, 0, CMD_UNMAP_ICM, CMD_TIME_CLASS_B, status);
1517 }
1518
1519 int mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status)
1520 {
1521         return mthca_map_cmd(dev, CMD_MAP_ICM_AUX, icm, -1, status);
1522 }
1523
1524 int mthca_UNMAP_ICM_AUX(struct mthca_dev *dev, u8 *status)
1525 {
1526         return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_ICM_AUX, CMD_TIME_CLASS_B, status);
1527 }
1528
1529 int mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages,
1530                        u8 *status)
1531 {
1532         int ret = mthca_cmd_imm(dev, icm_size, aux_pages, 0, 0, CMD_SET_ICM_SIZE,
1533                                 CMD_TIME_CLASS_A, status);
1534
1535         if (ret || status)
1536                 return ret;
1537
1538         /*
1539          * Round up number of system pages needed in case
1540          * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE.
1541          */
1542         *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >>
1543                 (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT);
1544
1545         return 0;
1546 }
1547
1548 int mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1549                     int mpt_index, u8 *status)
1550 {
1551         return mthca_cmd(dev, mailbox->dma, mpt_index, 0, CMD_SW2HW_MPT,
1552                          CMD_TIME_CLASS_B, status);
1553 }
1554
1555 int mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1556                     int mpt_index, u8 *status)
1557 {
1558         return mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
1559                              !mailbox, CMD_HW2SW_MPT,
1560                              CMD_TIME_CLASS_B, status);
1561 }
1562
1563 int mthca_WRITE_MTT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1564                     int num_mtt, u8 *status)
1565 {
1566         return mthca_cmd(dev, mailbox->dma, num_mtt, 0, CMD_WRITE_MTT,
1567                          CMD_TIME_CLASS_B, status);
1568 }
1569
1570 int mthca_SYNC_TPT(struct mthca_dev *dev, u8 *status)
1571 {
1572         return mthca_cmd(dev, 0, 0, 0, CMD_SYNC_TPT, CMD_TIME_CLASS_B, status);
1573 }
1574
1575 int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap,
1576                  int eq_num, u8 *status)
1577 {
1578         mthca_dbg(dev, "%s mask %016llx for eqn %d\n",
1579                   unmap ? "Clearing" : "Setting",
1580                   (unsigned long long) event_mask, eq_num);
1581         return mthca_cmd(dev, event_mask, (unmap << 31) | eq_num,
1582                          0, CMD_MAP_EQ, CMD_TIME_CLASS_B, status);
1583 }
1584
1585 int mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1586                    int eq_num, u8 *status)
1587 {
1588         return mthca_cmd(dev, mailbox->dma, eq_num, 0, CMD_SW2HW_EQ,
1589                          CMD_TIME_CLASS_A, status);
1590 }
1591
1592 int mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1593                    int eq_num, u8 *status)
1594 {
1595         return mthca_cmd_box(dev, 0, mailbox->dma, eq_num, 0,
1596                              CMD_HW2SW_EQ,
1597                              CMD_TIME_CLASS_A, status);
1598 }
1599
1600 int mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1601                    int cq_num, u8 *status)
1602 {
1603         return mthca_cmd(dev, mailbox->dma, cq_num, 0, CMD_SW2HW_CQ,
1604                         CMD_TIME_CLASS_A, status);
1605 }
1606
1607 int mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1608                    int cq_num, u8 *status)
1609 {
1610         return mthca_cmd_box(dev, 0, mailbox->dma, cq_num, 0,
1611                              CMD_HW2SW_CQ,
1612                              CMD_TIME_CLASS_A, status);
1613 }
1614
1615 int mthca_RESIZE_CQ(struct mthca_dev *dev, int cq_num, u32 lkey, u8 log_size,
1616                     u8 *status)
1617 {
1618         struct mthca_mailbox *mailbox;
1619         __be32 *inbox;
1620         int err;
1621
1622 #define RESIZE_CQ_IN_SIZE               0x40
1623 #define RESIZE_CQ_LOG_SIZE_OFFSET       0x0c
1624 #define RESIZE_CQ_LKEY_OFFSET           0x1c
1625
1626         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1627         if (IS_ERR(mailbox))
1628                 return PTR_ERR(mailbox);
1629         inbox = mailbox->buf;
1630
1631         memset(inbox, 0, RESIZE_CQ_IN_SIZE);
1632         /*
1633          * Leave start address fields zeroed out -- mthca assumes that
1634          * MRs for CQs always start at virtual address 0.
1635          */
1636         MTHCA_PUT(inbox, log_size, RESIZE_CQ_LOG_SIZE_OFFSET);
1637         MTHCA_PUT(inbox, lkey,     RESIZE_CQ_LKEY_OFFSET);
1638
1639         err = mthca_cmd(dev, mailbox->dma, cq_num, 1, CMD_RESIZE_CQ,
1640                         CMD_TIME_CLASS_B, status);
1641
1642         mthca_free_mailbox(dev, mailbox);
1643         return err;
1644 }
1645
1646 int mthca_SW2HW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1647                     int srq_num, u8 *status)
1648 {
1649         return mthca_cmd(dev, mailbox->dma, srq_num, 0, CMD_SW2HW_SRQ,
1650                         CMD_TIME_CLASS_A, status);
1651 }
1652
1653 int mthca_HW2SW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1654                     int srq_num, u8 *status)
1655 {
1656         return mthca_cmd_box(dev, 0, mailbox->dma, srq_num, 0,
1657                              CMD_HW2SW_SRQ,
1658                              CMD_TIME_CLASS_A, status);
1659 }
1660
1661 int mthca_QUERY_SRQ(struct mthca_dev *dev, u32 num,
1662                     struct mthca_mailbox *mailbox, u8 *status)
1663 {
1664         return mthca_cmd_box(dev, 0, mailbox->dma, num, 0,
1665                              CMD_QUERY_SRQ, CMD_TIME_CLASS_A, status);
1666 }
1667
1668 int mthca_ARM_SRQ(struct mthca_dev *dev, int srq_num, int limit, u8 *status)
1669 {
1670         return mthca_cmd(dev, limit, srq_num, 0, CMD_ARM_SRQ,
1671                          CMD_TIME_CLASS_B, status);
1672 }
1673
1674 int mthca_MODIFY_QP(struct mthca_dev *dev, enum ib_qp_state cur,
1675                     enum ib_qp_state next, u32 num, int is_ee,
1676                     struct mthca_mailbox *mailbox, u32 optmask,
1677                     u8 *status)
1678 {
1679         static const u16 op[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = {
1680                 [IB_QPS_RESET] = {
1681                         [IB_QPS_RESET]  = CMD_ERR2RST_QPEE,
1682                         [IB_QPS_ERR]    = CMD_2ERR_QPEE,
1683                         [IB_QPS_INIT]   = CMD_RST2INIT_QPEE,
1684                 },
1685                 [IB_QPS_INIT]  = {
1686                         [IB_QPS_RESET]  = CMD_ERR2RST_QPEE,
1687                         [IB_QPS_ERR]    = CMD_2ERR_QPEE,
1688                         [IB_QPS_INIT]   = CMD_INIT2INIT_QPEE,
1689                         [IB_QPS_RTR]    = CMD_INIT2RTR_QPEE,
1690                 },
1691                 [IB_QPS_RTR]   = {
1692                         [IB_QPS_RESET]  = CMD_ERR2RST_QPEE,
1693                         [IB_QPS_ERR]    = CMD_2ERR_QPEE,
1694                         [IB_QPS_RTS]    = CMD_RTR2RTS_QPEE,
1695                 },
1696                 [IB_QPS_RTS]   = {
1697                         [IB_QPS_RESET]  = CMD_ERR2RST_QPEE,
1698                         [IB_QPS_ERR]    = CMD_2ERR_QPEE,
1699                         [IB_QPS_RTS]    = CMD_RTS2RTS_QPEE,
1700                         [IB_QPS_SQD]    = CMD_RTS2SQD_QPEE,
1701                 },
1702                 [IB_QPS_SQD] = {
1703                         [IB_QPS_RESET]  = CMD_ERR2RST_QPEE,
1704                         [IB_QPS_ERR]    = CMD_2ERR_QPEE,
1705                         [IB_QPS_RTS]    = CMD_SQD2RTS_QPEE,
1706                         [IB_QPS_SQD]    = CMD_SQD2SQD_QPEE,
1707                 },
1708                 [IB_QPS_SQE] = {
1709                         [IB_QPS_RESET]  = CMD_ERR2RST_QPEE,
1710                         [IB_QPS_ERR]    = CMD_2ERR_QPEE,
1711                         [IB_QPS_RTS]    = CMD_SQERR2RTS_QPEE,
1712                 },
1713                 [IB_QPS_ERR] = {
1714                         [IB_QPS_RESET]  = CMD_ERR2RST_QPEE,
1715                         [IB_QPS_ERR]    = CMD_2ERR_QPEE,
1716                 }
1717         };
1718
1719         u8 op_mod = 0;
1720         int my_mailbox = 0;
1721         int err;
1722
1723         if (op[cur][next] == CMD_ERR2RST_QPEE) {
1724                 op_mod = 3;     /* don't write outbox, any->reset */
1725
1726                 /* For debugging */
1727                 if (!mailbox) {
1728                         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1729                         if (!IS_ERR(mailbox)) {
1730                                 my_mailbox = 1;
1731                                 op_mod     = 2; /* write outbox, any->reset */
1732                         } else
1733                                 mailbox = NULL;
1734                 }
1735
1736                 err = mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0,
1737                                     (!!is_ee << 24) | num, op_mod,
1738                                     op[cur][next], CMD_TIME_CLASS_C, status);
1739
1740                 if (0 && mailbox) {
1741                         int i;
1742                         mthca_dbg(dev, "Dumping QP context:\n");
1743                         printk(" %08x\n", be32_to_cpup(mailbox->buf));
1744                         for (i = 0; i < 0x100 / 4; ++i) {
1745                                 if (i % 8 == 0)
1746                                         printk("[%02x] ", i * 4);
1747                                 printk(" %08x",
1748                                        be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
1749                                 if ((i + 1) % 8 == 0)
1750                                         printk("\n");
1751                         }
1752                 }
1753
1754                 if (my_mailbox)
1755                         mthca_free_mailbox(dev, mailbox);
1756         } else {
1757                 if (0) {
1758                         int i;
1759                         mthca_dbg(dev, "Dumping QP context:\n");
1760                         printk("  opt param mask: %08x\n", be32_to_cpup(mailbox->buf));
1761                         for (i = 0; i < 0x100 / 4; ++i) {
1762                                 if (i % 8 == 0)
1763                                         printk("  [%02x] ", i * 4);
1764                                 printk(" %08x",
1765                                        be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
1766                                 if ((i + 1) % 8 == 0)
1767                                         printk("\n");
1768                         }
1769                 }
1770
1771                 err = mthca_cmd(dev, mailbox->dma, optmask | (!!is_ee << 24) | num,
1772                                 op_mod, op[cur][next], CMD_TIME_CLASS_C, status);
1773         }
1774
1775         return err;
1776 }
1777
1778 int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee,
1779                    struct mthca_mailbox *mailbox, u8 *status)
1780 {
1781         return mthca_cmd_box(dev, 0, mailbox->dma, (!!is_ee << 24) | num, 0,
1782                              CMD_QUERY_QPEE, CMD_TIME_CLASS_A, status);
1783 }
1784
1785 int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn,
1786                           u8 *status)
1787 {
1788         u8 op_mod;
1789
1790         switch (type) {
1791         case IB_QPT_SMI:
1792                 op_mod = 0;
1793                 break;
1794         case IB_QPT_GSI:
1795                 op_mod = 1;
1796                 break;
1797         case IB_QPT_RAW_IPV6:
1798                 op_mod = 2;
1799                 break;
1800         case IB_QPT_RAW_ETY:
1801                 op_mod = 3;
1802                 break;
1803         default:
1804                 return -EINVAL;
1805         }
1806
1807         return mthca_cmd(dev, 0, qpn, op_mod, CMD_CONF_SPECIAL_QP,
1808                          CMD_TIME_CLASS_B, status);
1809 }
1810
1811 int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey,
1812                   int port, struct ib_wc *in_wc, struct ib_grh *in_grh,
1813                   void *in_mad, void *response_mad, u8 *status)
1814 {
1815         struct mthca_mailbox *inmailbox, *outmailbox;
1816         void *inbox;
1817         int err;
1818         u32 in_modifier = port;
1819         u8 op_modifier = 0;
1820
1821 #define MAD_IFC_BOX_SIZE      0x400
1822 #define MAD_IFC_MY_QPN_OFFSET 0x100
1823 #define MAD_IFC_RQPN_OFFSET   0x108
1824 #define MAD_IFC_SL_OFFSET     0x10c
1825 #define MAD_IFC_G_PATH_OFFSET 0x10d
1826 #define MAD_IFC_RLID_OFFSET   0x10e
1827 #define MAD_IFC_PKEY_OFFSET   0x112
1828 #define MAD_IFC_GRH_OFFSET    0x140
1829
1830         inmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1831         if (IS_ERR(inmailbox))
1832                 return PTR_ERR(inmailbox);
1833         inbox = inmailbox->buf;
1834
1835         outmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1836         if (IS_ERR(outmailbox)) {
1837                 mthca_free_mailbox(dev, inmailbox);
1838                 return PTR_ERR(outmailbox);
1839         }
1840
1841         memcpy(inbox, in_mad, 256);
1842
1843         /*
1844          * Key check traps can't be generated unless we have in_wc to
1845          * tell us where to send the trap.
1846          */
1847         if (ignore_mkey || !in_wc)
1848                 op_modifier |= 0x1;
1849         if (ignore_bkey || !in_wc)
1850                 op_modifier |= 0x2;
1851
1852         if (in_wc) {
1853                 u8 val;
1854
1855                 memset(inbox + 256, 0, 256);
1856
1857                 MTHCA_PUT(inbox, in_wc->qp_num,     MAD_IFC_MY_QPN_OFFSET);
1858                 MTHCA_PUT(inbox, in_wc->src_qp,     MAD_IFC_RQPN_OFFSET);
1859
1860                 val = in_wc->sl << 4;
1861                 MTHCA_PUT(inbox, val,               MAD_IFC_SL_OFFSET);
1862
1863                 val = in_wc->dlid_path_bits |
1864                         (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0);
1865                 MTHCA_PUT(inbox, val,               MAD_IFC_G_PATH_OFFSET);
1866
1867                 MTHCA_PUT(inbox, in_wc->slid,       MAD_IFC_RLID_OFFSET);
1868                 MTHCA_PUT(inbox, in_wc->pkey_index, MAD_IFC_PKEY_OFFSET);
1869
1870                 if (in_grh)
1871                         memcpy(inbox + MAD_IFC_GRH_OFFSET, in_grh, 40);
1872
1873                 op_modifier |= 0x4;
1874
1875                 in_modifier |= in_wc->slid << 16;
1876         }
1877
1878         err = mthca_cmd_box(dev, inmailbox->dma, outmailbox->dma,
1879                             in_modifier, op_modifier,
1880                             CMD_MAD_IFC, CMD_TIME_CLASS_C, status);
1881
1882         if (!err && !*status)
1883                 memcpy(response_mad, outmailbox->buf, 256);
1884
1885         mthca_free_mailbox(dev, inmailbox);
1886         mthca_free_mailbox(dev, outmailbox);
1887         return err;
1888 }
1889
1890 int mthca_READ_MGM(struct mthca_dev *dev, int index,
1891                    struct mthca_mailbox *mailbox, u8 *status)
1892 {
1893         return mthca_cmd_box(dev, 0, mailbox->dma, index, 0,
1894                              CMD_READ_MGM, CMD_TIME_CLASS_A, status);
1895 }
1896
1897 int mthca_WRITE_MGM(struct mthca_dev *dev, int index,
1898                     struct mthca_mailbox *mailbox, u8 *status)
1899 {
1900         return mthca_cmd(dev, mailbox->dma, index, 0, CMD_WRITE_MGM,
1901                          CMD_TIME_CLASS_A, status);
1902 }
1903
1904 int mthca_MGID_HASH(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1905                     u16 *hash, u8 *status)
1906 {
1907         u64 imm;
1908         int err;
1909
1910         err = mthca_cmd_imm(dev, mailbox->dma, &imm, 0, 0, CMD_MGID_HASH,
1911                             CMD_TIME_CLASS_A, status);
1912
1913         *hash = imm;
1914         return err;
1915 }
1916
1917 int mthca_NOP(struct mthca_dev *dev, u8 *status)
1918 {
1919         return mthca_cmd(dev, 0, 0x1f, 0, CMD_NOP, msecs_to_jiffies(100), status);
1920 }