ae8bf9950c6d43bad85bcda0863af08468cfb681
[linux-2.6.git] / drivers / infiniband / hw / ipath / ipath_iba6120.c
1 /*
2  * Copyright (c) 2006 QLogic, Inc. All rights reserved.
3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
4  *
5  * This software is available to you under a choice of one of two
6  * licenses.  You may choose to be licensed under the terms of the GNU
7  * General Public License (GPL) Version 2, available from the file
8  * COPYING in the main directory of this source tree, or the
9  * OpenIB.org BSD license below:
10  *
11  *     Redistribution and use in source and binary forms, with or
12  *     without modification, are permitted provided that the following
13  *     conditions are met:
14  *
15  *      - Redistributions of source code must retain the above
16  *        copyright notice, this list of conditions and the following
17  *        disclaimer.
18  *
19  *      - Redistributions in binary form must reproduce the above
20  *        copyright notice, this list of conditions and the following
21  *        disclaimer in the documentation and/or other materials
22  *        provided with the distribution.
23  *
24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31  * SOFTWARE.
32  */
33 /*
34  * This file contains all of the code that is specific to the
35  * InfiniPath PCIe chip.
36  */
37
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
41
42
43 #include "ipath_kernel.h"
44 #include "ipath_registers.h"
45
46 /*
47  * This file contains all the chip-specific register information and
48  * access functions for the QLogic InfiniPath PCI-Express chip.
49  *
50  * This lists the InfiniPath registers, in the actual chip layout.
51  * This structure should never be directly accessed.
52  */
53 struct _infinipath_do_not_use_kernel_regs {
54         unsigned long long Revision;
55         unsigned long long Control;
56         unsigned long long PageAlign;
57         unsigned long long PortCnt;
58         unsigned long long DebugPortSelect;
59         unsigned long long Reserved0;
60         unsigned long long SendRegBase;
61         unsigned long long UserRegBase;
62         unsigned long long CounterRegBase;
63         unsigned long long Scratch;
64         unsigned long long Reserved1;
65         unsigned long long Reserved2;
66         unsigned long long IntBlocked;
67         unsigned long long IntMask;
68         unsigned long long IntStatus;
69         unsigned long long IntClear;
70         unsigned long long ErrorMask;
71         unsigned long long ErrorStatus;
72         unsigned long long ErrorClear;
73         unsigned long long HwErrMask;
74         unsigned long long HwErrStatus;
75         unsigned long long HwErrClear;
76         unsigned long long HwDiagCtrl;
77         unsigned long long MDIO;
78         unsigned long long IBCStatus;
79         unsigned long long IBCCtrl;
80         unsigned long long ExtStatus;
81         unsigned long long ExtCtrl;
82         unsigned long long GPIOOut;
83         unsigned long long GPIOMask;
84         unsigned long long GPIOStatus;
85         unsigned long long GPIOClear;
86         unsigned long long RcvCtrl;
87         unsigned long long RcvBTHQP;
88         unsigned long long RcvHdrSize;
89         unsigned long long RcvHdrCnt;
90         unsigned long long RcvHdrEntSize;
91         unsigned long long RcvTIDBase;
92         unsigned long long RcvTIDCnt;
93         unsigned long long RcvEgrBase;
94         unsigned long long RcvEgrCnt;
95         unsigned long long RcvBufBase;
96         unsigned long long RcvBufSize;
97         unsigned long long RxIntMemBase;
98         unsigned long long RxIntMemSize;
99         unsigned long long RcvPartitionKey;
100         unsigned long long Reserved3;
101         unsigned long long RcvPktLEDCnt;
102         unsigned long long Reserved4[8];
103         unsigned long long SendCtrl;
104         unsigned long long SendPIOBufBase;
105         unsigned long long SendPIOSize;
106         unsigned long long SendPIOBufCnt;
107         unsigned long long SendPIOAvailAddr;
108         unsigned long long TxIntMemBase;
109         unsigned long long TxIntMemSize;
110         unsigned long long Reserved5;
111         unsigned long long PCIeRBufTestReg0;
112         unsigned long long PCIeRBufTestReg1;
113         unsigned long long Reserved51[6];
114         unsigned long long SendBufferError;
115         unsigned long long SendBufferErrorCONT1;
116         unsigned long long Reserved6SBE[6];
117         unsigned long long RcvHdrAddr0;
118         unsigned long long RcvHdrAddr1;
119         unsigned long long RcvHdrAddr2;
120         unsigned long long RcvHdrAddr3;
121         unsigned long long RcvHdrAddr4;
122         unsigned long long Reserved7RHA[11];
123         unsigned long long RcvHdrTailAddr0;
124         unsigned long long RcvHdrTailAddr1;
125         unsigned long long RcvHdrTailAddr2;
126         unsigned long long RcvHdrTailAddr3;
127         unsigned long long RcvHdrTailAddr4;
128         unsigned long long Reserved8RHTA[11];
129         unsigned long long Reserved9SW[8];
130         unsigned long long SerdesConfig0;
131         unsigned long long SerdesConfig1;
132         unsigned long long SerdesStatus;
133         unsigned long long XGXSConfig;
134         unsigned long long IBPLLCfg;
135         unsigned long long Reserved10SW2[3];
136         unsigned long long PCIEQ0SerdesConfig0;
137         unsigned long long PCIEQ0SerdesConfig1;
138         unsigned long long PCIEQ0SerdesStatus;
139         unsigned long long Reserved11;
140         unsigned long long PCIEQ1SerdesConfig0;
141         unsigned long long PCIEQ1SerdesConfig1;
142         unsigned long long PCIEQ1SerdesStatus;
143         unsigned long long Reserved12;
144 };
145
146 #define IPATH_KREG_OFFSET(field) (offsetof(struct \
147     _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
148 #define IPATH_CREG_OFFSET(field) (offsetof( \
149     struct infinipath_counters, field) / sizeof(u64))
150
151 static const struct ipath_kregs ipath_pe_kregs = {
152         .kr_control = IPATH_KREG_OFFSET(Control),
153         .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
154         .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
155         .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
156         .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
157         .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
158         .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
159         .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
160         .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
161         .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
162         .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
163         .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
164         .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
165         .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
166         .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
167         .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
168         .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
169         .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
170         .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
171         .kr_intclear = IPATH_KREG_OFFSET(IntClear),
172         .kr_intmask = IPATH_KREG_OFFSET(IntMask),
173         .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
174         .kr_mdio = IPATH_KREG_OFFSET(MDIO),
175         .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
176         .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
177         .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
178         .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
179         .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
180         .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
181         .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
182         .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
183         .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
184         .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
185         .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
186         .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
187         .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
188         .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
189         .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
190         .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
191         .kr_revision = IPATH_KREG_OFFSET(Revision),
192         .kr_scratch = IPATH_KREG_OFFSET(Scratch),
193         .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
194         .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
195         .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
196         .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
197         .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
198         .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
199         .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
200         .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
201         .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
202         .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
203         .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
204         .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
205         .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
206         .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
207         .kr_ibpllcfg = IPATH_KREG_OFFSET(IBPLLCfg),
208
209         /*
210          * These should not be used directly via ipath_read_kreg64(),
211          * use them with ipath_read_kreg64_port()
212          */
213         .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
214         .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0),
215
216         /* The rcvpktled register controls one of the debug port signals, so
217          * a packet activity LED can be connected to it. */
218         .kr_rcvpktledcnt = IPATH_KREG_OFFSET(RcvPktLEDCnt),
219         .kr_pcierbuftestreg0 = IPATH_KREG_OFFSET(PCIeRBufTestReg0),
220         .kr_pcierbuftestreg1 = IPATH_KREG_OFFSET(PCIeRBufTestReg1),
221         .kr_pcieq0serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig0),
222         .kr_pcieq0serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig1),
223         .kr_pcieq0serdesstatus = IPATH_KREG_OFFSET(PCIEQ0SerdesStatus),
224         .kr_pcieq1serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig0),
225         .kr_pcieq1serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig1),
226         .kr_pcieq1serdesstatus = IPATH_KREG_OFFSET(PCIEQ1SerdesStatus)
227 };
228
229 static const struct ipath_cregs ipath_pe_cregs = {
230         .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
231         .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
232         .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
233         .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
234         .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
235         .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
236         .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
237         .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
238         .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
239         .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
240         .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
241         .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
242         .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
243         .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
244         .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
245         .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
246         .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
247         .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
248         .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
249         .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
250         .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
251         .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
252         .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
253         .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
254         .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
255         .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
256         .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
257         .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
258         .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
259         .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
260         .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
261         .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
262         .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
263 };
264
265 /* kr_intstatus, kr_intclear, kr_intmask bits */
266 #define INFINIPATH_I_RCVURG_MASK ((1U<<5)-1)
267 #define INFINIPATH_I_RCVAVAIL_MASK ((1U<<5)-1)
268
269 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
270 #define INFINIPATH_HWE_PCIEMEMPARITYERR_MASK  0x000000000000003fULL
271 #define INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT 0
272 #define INFINIPATH_HWE_PCIEPOISONEDTLP      0x0000000010000000ULL
273 #define INFINIPATH_HWE_PCIECPLTIMEOUT       0x0000000020000000ULL
274 #define INFINIPATH_HWE_PCIEBUSPARITYXTLH    0x0000000040000000ULL
275 #define INFINIPATH_HWE_PCIEBUSPARITYXADM    0x0000000080000000ULL
276 #define INFINIPATH_HWE_PCIEBUSPARITYRADM    0x0000000100000000ULL
277 #define INFINIPATH_HWE_COREPLL_FBSLIP       0x0080000000000000ULL
278 #define INFINIPATH_HWE_COREPLL_RFSLIP       0x0100000000000000ULL
279 #define INFINIPATH_HWE_PCIE1PLLFAILED       0x0400000000000000ULL
280 #define INFINIPATH_HWE_PCIE0PLLFAILED       0x0800000000000000ULL
281 #define INFINIPATH_HWE_SERDESPLLFAILED      0x1000000000000000ULL
282
283 /* kr_extstatus bits */
284 #define INFINIPATH_EXTS_FREQSEL 0x2
285 #define INFINIPATH_EXTS_SERDESSEL 0x4
286 #define INFINIPATH_EXTS_MEMBIST_ENDTEST     0x0000000000004000
287 #define INFINIPATH_EXTS_MEMBIST_FOUND       0x0000000000008000
288
289 #define _IPATH_GPIO_SDA_NUM 1
290 #define _IPATH_GPIO_SCL_NUM 0
291
292 #define IPATH_GPIO_SDA (1ULL << \
293         (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
294 #define IPATH_GPIO_SCL (1ULL << \
295         (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
296
297 /*
298  * Rev2 silicon allows suppressing check for ArmLaunch errors.
299  * this can speed up short packet sends on systems that do
300  * not guaranteee write-order.
301  */
302 #define INFINIPATH_XGXS_SUPPRESS_ARMLAUNCH_ERR (1ULL<<63)
303
304 /* 6120 specific hardware errors... */
305 static const struct ipath_hwerror_msgs ipath_6120_hwerror_msgs[] = {
306         INFINIPATH_HWE_MSG(PCIEPOISONEDTLP, "PCIe Poisoned TLP"),
307         INFINIPATH_HWE_MSG(PCIECPLTIMEOUT, "PCIe completion timeout"),
308         /*
309          * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
310          * parity or memory parity error failures, because most likely we
311          * won't be able to talk to the core of the chip.  Nonetheless, we
312          * might see them, if they are in parts of the PCIe core that aren't
313          * essential.
314          */
315         INFINIPATH_HWE_MSG(PCIE1PLLFAILED, "PCIePLL1"),
316         INFINIPATH_HWE_MSG(PCIE0PLLFAILED, "PCIePLL0"),
317         INFINIPATH_HWE_MSG(PCIEBUSPARITYXTLH, "PCIe XTLH core parity"),
318         INFINIPATH_HWE_MSG(PCIEBUSPARITYXADM, "PCIe ADM TX core parity"),
319         INFINIPATH_HWE_MSG(PCIEBUSPARITYRADM, "PCIe ADM RX core parity"),
320         INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
321         INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
322 };
323
324 /**
325  * ipath_pe_handle_hwerrors - display hardware errors.
326  * @dd: the infinipath device
327  * @msg: the output buffer
328  * @msgl: the size of the output buffer
329  *
330  * Use same msg buffer as regular errors to avoid excessive stack
331  * use.  Most hardware errors are catastrophic, but for right now,
332  * we'll print them and continue.  We reuse the same message buffer as
333  * ipath_handle_errors() to avoid excessive stack usage.
334  */
335 static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
336                                      size_t msgl)
337 {
338         ipath_err_t hwerrs;
339         u32 bits, ctrl;
340         int isfatal = 0;
341         char bitsmsg[64];
342
343         hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
344         if (!hwerrs) {
345                 /*
346                  * better than printing cofusing messages
347                  * This seems to be related to clearing the crc error, or
348                  * the pll error during init.
349                  */
350                 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
351                 return;
352         } else if (hwerrs == ~0ULL) {
353                 ipath_dev_err(dd, "Read of hardware error status failed "
354                               "(all bits set); ignoring\n");
355                 return;
356         }
357         ipath_stats.sps_hwerrs++;
358
359         /* Always clear the error status register, except MEMBISTFAIL,
360          * regardless of whether we continue or stop using the chip.
361          * We want that set so we know it failed, even across driver reload.
362          * We'll still ignore it in the hwerrmask.  We do this partly for
363          * diagnostics, but also for support */
364         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
365                          hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
366
367         hwerrs &= dd->ipath_hwerrmask;
368
369         /*
370          * make sure we get this much out, unless told to be quiet,
371          * or it's occurred within the last 5 seconds
372          */
373         if ((hwerrs & ~(dd->ipath_lasthwerror |
374                         ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
375                           INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
376                          << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT))) ||
377             (ipath_debug & __IPATH_VERBDBG))
378                 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
379                          "(cleared)\n", (unsigned long long) hwerrs);
380         dd->ipath_lasthwerror |= hwerrs;
381
382         if (hwerrs & ~dd->ipath_hwe_bitsextant)
383                 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
384                               "%llx set\n", (unsigned long long)
385                               (hwerrs & ~dd->ipath_hwe_bitsextant));
386
387         ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
388         if (ctrl & INFINIPATH_C_FREEZEMODE) {
389                 /*
390                  * parity errors in send memory are recoverable,
391                  * just cancel the send (if indicated in * sendbuffererror),
392                  * count the occurrence, unfreeze (if no other handled
393                  * hardware error bits are set), and continue. They can
394                  * occur if a processor speculative read is done to the PIO
395                  * buffer while we are sending a packet, for example.
396                  */
397                 if (hwerrs & ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
398                                INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
399                               << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)) {
400                         ipath_stats.sps_txeparity++;
401                         ipath_dbg("Recovering from TXE parity error (%llu), "
402                                   "hwerrstatus=%llx\n",
403                                   (unsigned long long) ipath_stats.sps_txeparity,
404                                   (unsigned long long) hwerrs);
405                         ipath_disarm_senderrbufs(dd);
406                         hwerrs &= ~((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
407                                      INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
408                                     << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT);
409                         if (!hwerrs) { /* else leave in freeze mode */
410                                 ipath_write_kreg(dd,
411                                                  dd->ipath_kregs->kr_control,
412                                                  dd->ipath_control);
413                             return;
414                         }
415                 }
416                 if (hwerrs) {
417                         /*
418                          * if any set that we aren't ignoring only make the
419                          * complaint once, in case it's stuck or recurring,
420                          * and we get here multiple times
421                          */
422                         if (dd->ipath_flags & IPATH_INITTED) {
423                                 ipath_dev_err(dd, "Fatal Hardware Error (freeze "
424                                               "mode), no longer usable, SN %.16s\n",
425                                                   dd->ipath_serial);
426                                 isfatal = 1;
427                         }
428                         /*
429                          * Mark as having had an error for driver, and also
430                          * for /sys and status word mapped to user programs.
431                          * This marks unit as not usable, until reset
432                          */
433                         *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
434                         *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
435                         dd->ipath_flags &= ~IPATH_INITTED;
436                 } else {
437                         ipath_dbg("Clearing freezemode on ignored hardware "
438                                   "error\n");
439                         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
440                                          dd->ipath_control);
441                 }
442         }
443
444         *msg = '\0';
445
446         if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
447                 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
448                         msgl);
449                 /* ignore from now on, so disable until driver reloaded */
450                 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
451                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
452                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
453                                  dd->ipath_hwerrmask);
454         }
455
456         ipath_format_hwerrors(hwerrs,
457                               ipath_6120_hwerror_msgs,
458                               sizeof(ipath_6120_hwerror_msgs)/
459                               sizeof(ipath_6120_hwerror_msgs[0]),
460                               msg, msgl);
461
462         if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK
463                       << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) {
464                 bits = (u32) ((hwerrs >>
465                                INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) &
466                               INFINIPATH_HWE_PCIEMEMPARITYERR_MASK);
467                 snprintf(bitsmsg, sizeof bitsmsg,
468                          "[PCIe Mem Parity Errs %x] ", bits);
469                 strlcat(msg, bitsmsg, msgl);
470         }
471
472 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP |        \
473                          INFINIPATH_HWE_COREPLL_RFSLIP )
474
475         if (hwerrs & _IPATH_PLL_FAIL) {
476                 snprintf(bitsmsg, sizeof bitsmsg,
477                          "[PLL failed (%llx), InfiniPath hardware unusable]",
478                          (unsigned long long) hwerrs & _IPATH_PLL_FAIL);
479                 strlcat(msg, bitsmsg, msgl);
480                 /* ignore from now on, so disable until driver reloaded */
481                 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
482                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
483                                  dd->ipath_hwerrmask);
484         }
485
486         if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
487                 /*
488                  * If it occurs, it is left masked since the eternal
489                  * interface is unused
490                  */
491                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
492                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
493                                  dd->ipath_hwerrmask);
494         }
495
496         ipath_dev_err(dd, "%s hardware error\n", msg);
497         if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg) {
498                 /*
499                  * for /sys status file ; if no trailing } is copied, we'll
500                  * know it was truncated.
501                  */
502                 snprintf(dd->ipath_freezemsg, dd->ipath_freezelen,
503                          "{%s}", msg);
504         }
505 }
506
507 /**
508  * ipath_pe_boardname - fill in the board name
509  * @dd: the infinipath device
510  * @name: the output buffer
511  * @namelen: the size of the output buffer
512  *
513  * info is based on the board revision register
514  */
515 static int ipath_pe_boardname(struct ipath_devdata *dd, char *name,
516                               size_t namelen)
517 {
518         char *n = NULL;
519         u8 boardrev = dd->ipath_boardrev;
520         int ret;
521
522         switch (boardrev) {
523         case 0:
524                 n = "InfiniPath_Emulation";
525                 break;
526         case 1:
527                 n = "InfiniPath_QLE7140-Bringup";
528                 break;
529         case 2:
530                 n = "InfiniPath_QLE7140";
531                 break;
532         case 3:
533                 n = "InfiniPath_QMI7140";
534                 break;
535         case 4:
536                 n = "InfiniPath_QEM7140";
537                 break;
538         case 5:
539                 n = "InfiniPath_QMH7140";
540                 break;
541         case 6:
542                 n = "InfiniPath_QLE7142";
543                 break;
544         default:
545                 ipath_dev_err(dd,
546                               "Don't yet know about board with ID %u\n",
547                               boardrev);
548                 snprintf(name, namelen, "Unknown_InfiniPath_PCIe_%u",
549                          boardrev);
550                 break;
551         }
552         if (n)
553                 snprintf(name, namelen, "%s", n);
554
555         if (dd->ipath_majrev != 4 || !dd->ipath_minrev || dd->ipath_minrev>2) {
556                 ipath_dev_err(dd, "Unsupported InfiniPath hardware revision %u.%u!\n",
557                               dd->ipath_majrev, dd->ipath_minrev);
558                 ret = 1;
559         } else
560                 ret = 0;
561
562         return ret;
563 }
564
565 /**
566  * ipath_pe_init_hwerrors - enable hardware errors
567  * @dd: the infinipath device
568  *
569  * now that we have finished initializing everything that might reasonably
570  * cause a hardware error, and cleared those errors bits as they occur,
571  * we can enable hardware errors in the mask (potentially enabling
572  * freeze mode), and enable hardware errors as errors (along with
573  * everything else) in errormask
574  */
575 static void ipath_pe_init_hwerrors(struct ipath_devdata *dd)
576 {
577         ipath_err_t val;
578         u64 extsval;
579
580         extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
581
582         if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
583                 ipath_dev_err(dd, "MemBIST did not complete!\n");
584
585         val = ~0ULL;    /* barring bugs, all hwerrors become interrupts, */
586
587         if (!dd->ipath_boardrev)        // no PLL for Emulator
588                 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
589
590         if (dd->ipath_minrev < 2) {
591                 /* workaround bug 9460 in internal interface bus parity
592                  * checking. Fixed (HW bug 9490) in Rev2.
593                  */
594                 val &= ~INFINIPATH_HWE_PCIEBUSPARITYRADM;
595         }
596         dd->ipath_hwerrmask = val;
597 }
598
599 /**
600  * ipath_pe_bringup_serdes - bring up the serdes
601  * @dd: the infinipath device
602  */
603 static int ipath_pe_bringup_serdes(struct ipath_devdata *dd)
604 {
605         u64 val, config1, prev_val;
606         int ret = 0;
607
608         ipath_dbg("Trying to bringup serdes\n");
609
610         if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
611             INFINIPATH_HWE_SERDESPLLFAILED) {
612                 ipath_dbg("At start, serdes PLL failed bit set "
613                           "in hwerrstatus, clearing and continuing\n");
614                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
615                                  INFINIPATH_HWE_SERDESPLLFAILED);
616         }
617
618         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
619         config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
620
621         ipath_cdbg(VERBOSE, "SerDes status config0=%llx config1=%llx, "
622                    "xgxsconfig %llx\n", (unsigned long long) val,
623                    (unsigned long long) config1, (unsigned long long)
624                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
625
626         /*
627          * Force reset on, also set rxdetect enable.  Must do before reading
628          * serdesstatus at least for simulation, or some of the bits in
629          * serdes status will come back as undefined and cause simulation
630          * failures
631          */
632         val |= INFINIPATH_SERDC0_RESET_PLL | INFINIPATH_SERDC0_RXDETECT_EN
633                 | INFINIPATH_SERDC0_L1PWR_DN;
634         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
635         /* be sure chip saw it */
636         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
637         udelay(5);              /* need pll reset set at least for a bit */
638         /*
639          * after PLL is reset, set the per-lane Resets and TxIdle and
640          * clear the PLL reset and rxdetect (to get falling edge).
641          * Leave L1PWR bits set (permanently)
642          */
643         val &= ~(INFINIPATH_SERDC0_RXDETECT_EN | INFINIPATH_SERDC0_RESET_PLL
644                  | INFINIPATH_SERDC0_L1PWR_DN);
645         val |= INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE;
646         ipath_cdbg(VERBOSE, "Clearing pll reset and setting lane resets "
647                    "and txidle (%llx)\n", (unsigned long long) val);
648         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
649         /* be sure chip saw it */
650         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
651         /* need PLL reset clear for at least 11 usec before lane
652          * resets cleared; give it a few more to be sure */
653         udelay(15);
654         val &= ~(INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE);
655
656         ipath_cdbg(VERBOSE, "Clearing lane resets and txidle "
657                    "(writing %llx)\n", (unsigned long long) val);
658         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
659         /* be sure chip saw it */
660         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
661
662         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
663         prev_val = val;
664         if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) &
665              INFINIPATH_XGXS_MDIOADDR_MASK) != 3) {
666                 val &=
667                         ~(INFINIPATH_XGXS_MDIOADDR_MASK <<
668                           INFINIPATH_XGXS_MDIOADDR_SHIFT);
669                 /* MDIO address 3 */
670                 val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT;
671         }
672         if (val & INFINIPATH_XGXS_RESET) {
673                 val &= ~INFINIPATH_XGXS_RESET;
674         }
675         if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
676              INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
677                 /* need to compensate for Tx inversion in partner */
678                 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
679                          INFINIPATH_XGXS_RX_POL_SHIFT);
680                 val |= dd->ipath_rx_pol_inv <<
681                         INFINIPATH_XGXS_RX_POL_SHIFT;
682         }
683         if (dd->ipath_minrev >= 2) {
684                 /* Rev 2. can tolerate multiple writes to PBC, and
685                  * allowing them can provide lower latency on some
686                  * CPUs, but this feature is off by default, only
687                  * turned on by setting D63 of XGXSconfig reg.
688                  * May want to make this conditional more
689                  * fine-grained in future. This is not exactly
690                  * related to XGXS, but where the bit ended up.
691                  */
692                 val |= INFINIPATH_XGXS_SUPPRESS_ARMLAUNCH_ERR;
693         }
694         if (val != prev_val)
695                 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
696
697         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
698
699         /* clear current and de-emphasis bits */
700         config1 &= ~0x0ffffffff00ULL;
701         /* set current to 20ma */
702         config1 |= 0x00000000000ULL;
703         /* set de-emphasis to -5.68dB */
704         config1 |= 0x0cccc000000ULL;
705         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
706
707         ipath_cdbg(VERBOSE, "done: SerDes status config0=%llx "
708                    "config1=%llx, sstatus=%llx xgxs=%llx\n",
709                    (unsigned long long) val, (unsigned long long) config1,
710                    (unsigned long long)
711                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
712                    (unsigned long long)
713                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
714
715         if (!ipath_waitfor_mdio_cmdready(dd)) {
716                 ipath_write_kreg(
717                         dd, dd->ipath_kregs->kr_mdio,
718                         ipath_mdio_req(IPATH_MDIO_CMD_READ, 31,
719                                        IPATH_MDIO_CTRL_XGXS_REG_8, 0));
720                 if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio,
721                                            IPATH_MDIO_DATAVALID, &val))
722                         ipath_dbg("Never got MDIO data for XGXS "
723                                   "status read\n");
724                 else
725                         ipath_cdbg(VERBOSE, "MDIO Read reg8, "
726                                    "'bank' 31 %x\n", (u32) val);
727         } else
728                 ipath_dbg("Never got MDIO cmdready for XGXS status read\n");
729
730         return ret;
731 }
732
733 /**
734  * ipath_pe_quiet_serdes - set serdes to txidle
735  * @dd: the infinipath device
736  * Called when driver is being unloaded
737  */
738 static void ipath_pe_quiet_serdes(struct ipath_devdata *dd)
739 {
740         u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
741
742         val |= INFINIPATH_SERDC0_TXIDLE;
743         ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
744                   (unsigned long long) val);
745         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
746 }
747
748 static int ipath_pe_intconfig(struct ipath_devdata *dd)
749 {
750         u64 val;
751         u32 chiprev;
752
753         /*
754          * If the chip supports added error indication via GPIO pins,
755          * enable interrupts on those bits so the interrupt routine
756          * can count the events. Also set flag so interrupt routine
757          * can know they are expected.
758          */
759         chiprev = dd->ipath_revision >> INFINIPATH_R_CHIPREVMINOR_SHIFT;
760         if ((chiprev & INFINIPATH_R_CHIPREVMINOR_MASK) > 1) {
761                 /* Rev2+ reports extra errors via internal GPIO pins */
762                 dd->ipath_flags |= IPATH_GPIO_ERRINTRS;
763                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_gpio_mask);
764                 val |= IPATH_GPIO_ERRINTR_MASK;
765                 ipath_write_kreg( dd, dd->ipath_kregs->kr_gpio_mask, val);
766         }
767         return 0;
768 }
769
770 /**
771  * ipath_setup_pe_setextled - set the state of the two external LEDs
772  * @dd: the infinipath device
773  * @lst: the L state
774  * @ltst: the LT state
775
776  * These LEDs indicate the physical and logical state of IB link.
777  * For this chip (at least with recommended board pinouts), LED1
778  * is Yellow (logical state) and LED2 is Green (physical state),
779  *
780  * Note:  We try to match the Mellanox HCA LED behavior as best
781  * we can.  Green indicates physical link state is OK (something is
782  * plugged in, and we can train).
783  * Amber indicates the link is logically up (ACTIVE).
784  * Mellanox further blinks the amber LED to indicate data packet
785  * activity, but we have no hardware support for that, so it would
786  * require waking up every 10-20 msecs and checking the counters
787  * on the chip, and then turning the LED off if appropriate.  That's
788  * visible overhead, so not something we will do.
789  *
790  */
791 static void ipath_setup_pe_setextled(struct ipath_devdata *dd, u64 lst,
792                                      u64 ltst)
793 {
794         u64 extctl;
795
796         /* the diags use the LED to indicate diag info, so we leave
797          * the external LED alone when the diags are running */
798         if (ipath_diag_inuse)
799                 return;
800
801         extctl = dd->ipath_extctrl & ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
802                                        INFINIPATH_EXTC_LED2PRIPORT_ON);
803
804         if (ltst & INFINIPATH_IBCS_LT_STATE_LINKUP)
805                 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
806         if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
807                 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
808         dd->ipath_extctrl = extctl;
809         ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
810 }
811
812 /**
813  * ipath_setup_pe_cleanup - clean up any per-chip chip-specific stuff
814  * @dd: the infinipath device
815  *
816  * This is called during driver unload.
817  * We do the pci_disable_msi here, not in generic code, because it
818  * isn't used for the HT chips. If we do end up needing pci_enable_msi
819  * at some point in the future for HT, we'll move the call back
820  * into the main init_one code.
821  */
822 static void ipath_setup_pe_cleanup(struct ipath_devdata *dd)
823 {
824         dd->ipath_msi_lo = 0;   /* just in case unload fails */
825         pci_disable_msi(dd->pcidev);
826 }
827
828 /**
829  * ipath_setup_pe_config - setup PCIe config related stuff
830  * @dd: the infinipath device
831  * @pdev: the PCI device
832  *
833  * The pci_enable_msi() call will fail on systems with MSI quirks
834  * such as those with AMD8131, even if the device of interest is not
835  * attached to that device, (in the 2.6.13 - 2.6.15 kernels, at least, fixed
836  * late in 2.6.16).
837  * All that can be done is to edit the kernel source to remove the quirk
838  * check until that is fixed.
839  * We do not need to call enable_msi() for our HyperTransport chip,
840  * even though it uses MSI, and we want to avoid the quirk warning, so
841  * So we call enable_msi only for PCIe.  If we do end up needing
842  * pci_enable_msi at some point in the future for HT, we'll move the
843  * call back into the main init_one code.
844  * We save the msi lo and hi values, so we can restore them after
845  * chip reset (the kernel PCI infrastructure doesn't yet handle that
846  * correctly).
847  */
848 static int ipath_setup_pe_config(struct ipath_devdata *dd,
849                                  struct pci_dev *pdev)
850 {
851         int pos, ret;
852
853         dd->ipath_msi_lo = 0;   /* used as a flag during reset processing */
854         ret = pci_enable_msi(dd->pcidev);
855         if (ret)
856                 ipath_dev_err(dd, "pci_enable_msi failed: %d, "
857                               "interrupts may not work\n", ret);
858         /* continue even if it fails, we may still be OK... */
859         dd->ipath_irq = pdev->irq;
860
861         if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
862                 u16 control;
863                 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
864                                       &dd->ipath_msi_lo);
865                 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
866                                       &dd->ipath_msi_hi);
867                 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
868                                      &control);
869                 /* now save the data (vector) info */
870                 pci_read_config_word(dd->pcidev,
871                                      pos + ((control & PCI_MSI_FLAGS_64BIT)
872                                             ? 12 : 8),
873                                      &dd->ipath_msi_data);
874                 ipath_cdbg(VERBOSE, "Read msi data 0x%x from config offset "
875                            "0x%x, control=0x%x\n", dd->ipath_msi_data,
876                            pos + ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
877                            control);
878                 /* we save the cachelinesize also, although it doesn't
879                  * really matter */
880                 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
881                                      &dd->ipath_pci_cacheline);
882         } else
883                 ipath_dev_err(dd, "Can't find MSI capability, "
884                               "can't save MSI settings for reset\n");
885         if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP))) {
886                 u16 linkstat;
887                 pci_read_config_word(dd->pcidev, pos + PCI_EXP_LNKSTA,
888                                      &linkstat);
889                 linkstat >>= 4;
890                 linkstat &= 0x1f;
891                 if (linkstat != 8)
892                         ipath_dev_err(dd, "PCIe width %u, "
893                                       "performance reduced\n", linkstat);
894         }
895         else
896                 ipath_dev_err(dd, "Can't find PCI Express "
897                               "capability!\n");
898         return 0;
899 }
900
901 static void ipath_init_pe_variables(struct ipath_devdata *dd)
902 {
903         /*
904          * bits for selecting i2c direction and values,
905          * used for I2C serial flash
906          */
907         dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
908         dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
909         dd->ipath_gpio_sda = IPATH_GPIO_SDA;
910         dd->ipath_gpio_scl = IPATH_GPIO_SCL;
911
912         /* variables for sanity checking interrupt and errors */
913         dd->ipath_hwe_bitsextant =
914                 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
915                  INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
916                 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
917                  INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
918                 (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK <<
919                  INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) |
920                 INFINIPATH_HWE_PCIE1PLLFAILED |
921                 INFINIPATH_HWE_PCIE0PLLFAILED |
922                 INFINIPATH_HWE_PCIEPOISONEDTLP |
923                 INFINIPATH_HWE_PCIECPLTIMEOUT |
924                 INFINIPATH_HWE_PCIEBUSPARITYXTLH |
925                 INFINIPATH_HWE_PCIEBUSPARITYXADM |
926                 INFINIPATH_HWE_PCIEBUSPARITYRADM |
927                 INFINIPATH_HWE_MEMBISTFAILED |
928                 INFINIPATH_HWE_COREPLL_FBSLIP |
929                 INFINIPATH_HWE_COREPLL_RFSLIP |
930                 INFINIPATH_HWE_SERDESPLLFAILED |
931                 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
932                 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
933         dd->ipath_i_bitsextant =
934                 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
935                 (INFINIPATH_I_RCVAVAIL_MASK <<
936                  INFINIPATH_I_RCVAVAIL_SHIFT) |
937                 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
938                 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
939         dd->ipath_e_bitsextant =
940                 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
941                 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
942                 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
943                 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
944                 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
945                 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
946                 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
947                 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
948                 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
949                 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
950                 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
951                 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
952                 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
953                 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
954                 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
955                 INFINIPATH_E_HARDWARE;
956
957         dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
958         dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
959 }
960
961 /* setup the MSI stuff again after a reset.  I'd like to just call
962  * pci_enable_msi() and request_irq() again, but when I do that,
963  * the MSI enable bit doesn't get set in the command word, and
964  * we switch to to a different interrupt vector, which is confusing,
965  * so I instead just do it all inline.  Perhaps somehow can tie this
966  * into the PCIe hotplug support at some point
967  * Note, because I'm doing it all here, I don't call pci_disable_msi()
968  * or free_irq() at the start of ipath_setup_pe_reset().
969  */
970 static int ipath_reinit_msi(struct ipath_devdata *dd)
971 {
972         int pos;
973         u16 control;
974         int ret;
975
976         if (!dd->ipath_msi_lo) {
977                 dev_info(&dd->pcidev->dev, "Can't restore MSI config, "
978                          "initial setup failed?\n");
979                 ret = 0;
980                 goto bail;
981         }
982
983         if (!(pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
984                 ipath_dev_err(dd, "Can't find MSI capability, "
985                               "can't restore MSI settings\n");
986                 ret = 0;
987                 goto bail;
988         }
989         ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
990                    dd->ipath_msi_lo, pos + PCI_MSI_ADDRESS_LO);
991         pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
992                                dd->ipath_msi_lo);
993         ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
994                    dd->ipath_msi_hi, pos + PCI_MSI_ADDRESS_HI);
995         pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
996                                dd->ipath_msi_hi);
997         pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
998         if (!(control & PCI_MSI_FLAGS_ENABLE)) {
999                 ipath_cdbg(VERBOSE, "MSI control at off %x was %x, "
1000                            "setting MSI enable (%x)\n", pos + PCI_MSI_FLAGS,
1001                            control, control | PCI_MSI_FLAGS_ENABLE);
1002                 control |= PCI_MSI_FLAGS_ENABLE;
1003                 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
1004                                       control);
1005         }
1006         /* now rewrite the data (vector) info */
1007         pci_write_config_word(dd->pcidev, pos +
1008                               ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
1009                               dd->ipath_msi_data);
1010         /* we restore the cachelinesize also, although it doesn't really
1011          * matter */
1012         pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
1013                               dd->ipath_pci_cacheline);
1014         /* and now set the pci master bit again */
1015         pci_set_master(dd->pcidev);
1016         ret = 1;
1017
1018 bail:
1019         return ret;
1020 }
1021
1022 /* This routine sleeps, so it can only be called from user context, not
1023  * from interrupt context.  If we need interrupt context, we can split
1024  * it into two routines.
1025 */
1026 static int ipath_setup_pe_reset(struct ipath_devdata *dd)
1027 {
1028         u64 val;
1029         int i;
1030         int ret;
1031
1032         /* Use ERROR so it shows up in logs, etc. */
1033         ipath_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->ipath_unit);
1034         /* keep chip from being accessed in a few places */
1035         dd->ipath_flags &= ~(IPATH_INITTED|IPATH_PRESENT);
1036         val = dd->ipath_control | INFINIPATH_C_RESET;
1037         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, val);
1038         mb();
1039
1040         for (i = 1; i <= 5; i++) {
1041                 int r;
1042                 /* allow MBIST, etc. to complete; longer on each retry.
1043                  * We sometimes get machine checks from bus timeout if no
1044                  * response, so for now, make it *really* long.
1045                  */
1046                 msleep(1000 + (1 + i) * 2000);
1047                 if ((r =
1048                      pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
1049                                             dd->ipath_pcibar0)))
1050                         ipath_dev_err(dd, "rewrite of BAR0 failed: %d\n",
1051                                       r);
1052                 if ((r =
1053                      pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
1054                                             dd->ipath_pcibar1)))
1055                         ipath_dev_err(dd, "rewrite of BAR1 failed: %d\n",
1056                                       r);
1057                 /* now re-enable memory access */
1058                 if ((r = pci_enable_device(dd->pcidev)))
1059                         ipath_dev_err(dd, "pci_enable_device failed after "
1060                                       "reset: %d\n", r);
1061                 /* whether it worked or not, mark as present, again */
1062                 dd->ipath_flags |= IPATH_PRESENT;
1063                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
1064                 if (val == dd->ipath_revision) {
1065                         ipath_cdbg(VERBOSE, "Got matching revision "
1066                                    "register %llx on try %d\n",
1067                                    (unsigned long long) val, i);
1068                         ret = ipath_reinit_msi(dd);
1069                         goto bail;
1070                 }
1071                 /* Probably getting -1 back */
1072                 ipath_dbg("Didn't get expected revision register, "
1073                           "got %llx, try %d\n", (unsigned long long) val,
1074                           i + 1);
1075         }
1076         ret = 0; /* failed */
1077
1078 bail:
1079         return ret;
1080 }
1081
1082 /**
1083  * ipath_pe_put_tid - write a TID in chip
1084  * @dd: the infinipath device
1085  * @tidptr: pointer to the expected TID (in chip) to udpate
1086  * @tidtype: 0 for eager, 1 for expected
1087  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1088  *
1089  * This exists as a separate routine to allow for special locking etc.
1090  * It's used for both the full cleanup on exit, as well as the normal
1091  * setup and teardown.
1092  */
1093 static void ipath_pe_put_tid(struct ipath_devdata *dd, u64 __iomem *tidptr,
1094                              u32 type, unsigned long pa)
1095 {
1096         u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1097         unsigned long flags = 0; /* keep gcc quiet */
1098
1099         if (pa != dd->ipath_tidinvalid) {
1100                 if (pa & ((1U << 11) - 1)) {
1101                         dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1102                                  "not 4KB aligned!\n", pa);
1103                         return;
1104                 }
1105                 pa >>= 11;
1106                 /* paranoia check */
1107                 if (pa & (7<<29))
1108                         ipath_dev_err(dd,
1109                                       "BUG: Physical page address 0x%lx "
1110                                       "has bits set in 31-29\n", pa);
1111
1112                 if (type == 0)
1113                         pa |= dd->ipath_tidtemplate;
1114                 else /* for now, always full 4KB page */
1115                         pa |= 2 << 29;
1116         }
1117
1118         /* workaround chip bug 9437 by writing each TID twice
1119          * and holding a spinlock around the writes, so they don't
1120          * intermix with other TID (eager or expected) writes
1121          * Unfortunately, this call can be done from interrupt level
1122          * for the port 0 eager TIDs, so we have to use irqsave
1123          */
1124         spin_lock_irqsave(&dd->ipath_tid_lock, flags);
1125         ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xfeeddeaf);
1126         if (dd->ipath_kregbase)
1127                 writel(pa, tidp32);
1128         ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xdeadbeef);
1129         mmiowb();
1130         spin_unlock_irqrestore(&dd->ipath_tid_lock, flags);
1131 }
1132 /**
1133  * ipath_pe_put_tid_2 - write a TID in chip, Revision 2 or higher
1134  * @dd: the infinipath device
1135  * @tidptr: pointer to the expected TID (in chip) to udpate
1136  * @tidtype: 0 for eager, 1 for expected
1137  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1138  *
1139  * This exists as a separate routine to allow for selection of the
1140  * appropriate "flavor". The static calls in cleanup just use the
1141  * revision-agnostic form, as they are not performance critical.
1142  */
1143 static void ipath_pe_put_tid_2(struct ipath_devdata *dd, u64 __iomem *tidptr,
1144                              u32 type, unsigned long pa)
1145 {
1146         u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1147
1148         if (pa != dd->ipath_tidinvalid) {
1149                 if (pa & ((1U << 11) - 1)) {
1150                         dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1151                                  "not 2KB aligned!\n", pa);
1152                         return;
1153                 }
1154                 pa >>= 11;
1155                 /* paranoia check */
1156                 if (pa & (7<<29))
1157                         ipath_dev_err(dd,
1158                                       "BUG: Physical page address 0x%lx "
1159                                       "has bits set in 31-29\n", pa);
1160
1161                 if (type == 0)
1162                         pa |= dd->ipath_tidtemplate;
1163                 else /* for now, always full 4KB page */
1164                         pa |= 2 << 29;
1165         }
1166         if (dd->ipath_kregbase)
1167                 writel(pa, tidp32);
1168         mmiowb();
1169 }
1170
1171
1172 /**
1173  * ipath_pe_clear_tid - clear all TID entries for a port, expected and eager
1174  * @dd: the infinipath device
1175  * @port: the port
1176  *
1177  * clear all TID entries for a port, expected and eager.
1178  * Used from ipath_close().  On this chip, TIDs are only 32 bits,
1179  * not 64, but they are still on 64 bit boundaries, so tidbase
1180  * is declared as u64 * for the pointer math, even though we write 32 bits
1181  */
1182 static void ipath_pe_clear_tids(struct ipath_devdata *dd, unsigned port)
1183 {
1184         u64 __iomem *tidbase;
1185         unsigned long tidinv;
1186         int i;
1187
1188         if (!dd->ipath_kregbase)
1189                 return;
1190
1191         ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1192
1193         tidinv = dd->ipath_tidinvalid;
1194         tidbase = (u64 __iomem *)
1195                 ((char __iomem *)(dd->ipath_kregbase) +
1196                  dd->ipath_rcvtidbase +
1197                  port * dd->ipath_rcvtidcnt * sizeof(*tidbase));
1198
1199         for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1200                 ipath_pe_put_tid(dd, &tidbase[i], 0, tidinv);
1201
1202         tidbase = (u64 __iomem *)
1203                 ((char __iomem *)(dd->ipath_kregbase) +
1204                  dd->ipath_rcvegrbase +
1205                  port * dd->ipath_rcvegrcnt * sizeof(*tidbase));
1206
1207         for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1208                 ipath_pe_put_tid(dd, &tidbase[i], 1, tidinv);
1209 }
1210
1211 /**
1212  * ipath_pe_tidtemplate - setup constants for TID updates
1213  * @dd: the infinipath device
1214  *
1215  * We setup stuff that we use a lot, to avoid calculating each time
1216  */
1217 static void ipath_pe_tidtemplate(struct ipath_devdata *dd)
1218 {
1219         u32 egrsize = dd->ipath_rcvegrbufsize;
1220
1221         /* For now, we always allocate 4KB buffers (at init) so we can
1222          * receive max size packets.  We may want a module parameter to
1223          * specify 2KB or 4KB and/or make be per port instead of per device
1224          * for those who want to reduce memory footprint.  Note that the
1225          * ipath_rcvhdrentsize size must be large enough to hold the largest
1226          * IB header (currently 96 bytes) that we expect to handle (plus of
1227          * course the 2 dwords of RHF).
1228          */
1229         if (egrsize == 2048)
1230                 dd->ipath_tidtemplate = 1U << 29;
1231         else if (egrsize == 4096)
1232                 dd->ipath_tidtemplate = 2U << 29;
1233         else {
1234                 egrsize = 4096;
1235                 dev_info(&dd->pcidev->dev, "BUG: unsupported egrbufsize "
1236                          "%u, using %u\n", dd->ipath_rcvegrbufsize,
1237                          egrsize);
1238                 dd->ipath_tidtemplate = 2U << 29;
1239         }
1240         dd->ipath_tidinvalid = 0;
1241 }
1242
1243 static int ipath_pe_early_init(struct ipath_devdata *dd)
1244 {
1245         dd->ipath_flags |= IPATH_4BYTE_TID;
1246
1247         /*
1248          * For openfabrics, we need to be able to handle an IB header of
1249          * 24 dwords.  HT chip has arbitrary sized receive buffers, so we
1250          * made them the same size as the PIO buffers.  This chip does not
1251          * handle arbitrary size buffers, so we need the header large enough
1252          * to handle largest IB header, but still have room for a 2KB MTU
1253          * standard IB packet.
1254          */
1255         dd->ipath_rcvhdrentsize = 24;
1256         dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1257
1258         /*
1259          * To truly support a 4KB MTU (for usermode), we need to
1260          * bump this to a larger value.  For now, we use them for
1261          * the kernel only.
1262          */
1263         dd->ipath_rcvegrbufsize = 2048;
1264         /*
1265          * the min() check here is currently a nop, but it may not always
1266          * be, depending on just how we do ipath_rcvegrbufsize
1267          */
1268         dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1269                                  dd->ipath_rcvegrbufsize +
1270                                  (dd->ipath_rcvhdrentsize << 2));
1271         dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1272
1273         /*
1274          * We can request a receive interrupt for 1 or
1275          * more packets from current offset.  For now, we set this
1276          * up for a single packet.
1277          */
1278         dd->ipath_rhdrhead_intr_off = 1ULL<<32;
1279
1280         ipath_get_eeprom_info(dd);
1281
1282         return 0;
1283 }
1284
1285 int __attribute__((weak)) ipath_unordered_wc(void)
1286 {
1287         return 0;
1288 }
1289
1290 /**
1291  * ipath_init_pe_get_base_info - set chip-specific flags for user code
1292  * @pd: the infinipath port
1293  * @kbase: ipath_base_info pointer
1294  *
1295  * We set the PCIE flag because the lower bandwidth on PCIe vs
1296  * HyperTransport can affect some user packet algorithims.
1297  */
1298 static int ipath_pe_get_base_info(struct ipath_portdata *pd, void *kbase)
1299 {
1300         struct ipath_base_info *kinfo = kbase;
1301         struct ipath_devdata *dd;
1302
1303         if (ipath_unordered_wc()) {
1304                 kinfo->spi_runtime_flags |= IPATH_RUNTIME_FORCE_WC_ORDER;
1305                 ipath_cdbg(PROC, "Intel processor, forcing WC order\n");
1306         }
1307         else
1308                 ipath_cdbg(PROC, "Not Intel processor, WC ordered\n");
1309
1310         if (pd == NULL)
1311                 goto done;
1312
1313         dd = pd->port_dd;
1314
1315         if (dd != NULL && dd->ipath_minrev >= 2) {
1316                 ipath_cdbg(PROC, "IBA6120 Rev2, allow multiple PBC write\n");
1317                 kinfo->spi_runtime_flags |= IPATH_RUNTIME_PBC_REWRITE;
1318                 ipath_cdbg(PROC, "IBA6120 Rev2, allow loose DMA alignment\n");
1319                 kinfo->spi_runtime_flags |= IPATH_RUNTIME_LOOSE_DMA_ALIGN;
1320         }
1321
1322 done:
1323         kinfo->spi_runtime_flags |= IPATH_RUNTIME_PCIE;
1324         return 0;
1325 }
1326
1327 static void ipath_pe_free_irq(struct ipath_devdata *dd)
1328 {
1329         free_irq(dd->ipath_irq, dd);
1330         dd->ipath_irq = 0;
1331 }
1332
1333 /**
1334  * ipath_init_iba6120_funcs - set up the chip-specific function pointers
1335  * @dd: the infinipath device
1336  *
1337  * This is global, and is called directly at init to set up the
1338  * chip-specific function pointers for later use.
1339  */
1340 void ipath_init_iba6120_funcs(struct ipath_devdata *dd)
1341 {
1342         dd->ipath_f_intrsetup = ipath_pe_intconfig;
1343         dd->ipath_f_bus = ipath_setup_pe_config;
1344         dd->ipath_f_reset = ipath_setup_pe_reset;
1345         dd->ipath_f_get_boardname = ipath_pe_boardname;
1346         dd->ipath_f_init_hwerrors = ipath_pe_init_hwerrors;
1347         dd->ipath_f_early_init = ipath_pe_early_init;
1348         dd->ipath_f_handle_hwerrors = ipath_pe_handle_hwerrors;
1349         dd->ipath_f_quiet_serdes = ipath_pe_quiet_serdes;
1350         dd->ipath_f_bringup_serdes = ipath_pe_bringup_serdes;
1351         dd->ipath_f_clear_tids = ipath_pe_clear_tids;
1352         if (dd->ipath_minrev >= 2)
1353                 dd->ipath_f_put_tid = ipath_pe_put_tid_2;
1354         else
1355                 dd->ipath_f_put_tid = ipath_pe_put_tid;
1356         dd->ipath_f_cleanup = ipath_setup_pe_cleanup;
1357         dd->ipath_f_setextled = ipath_setup_pe_setextled;
1358         dd->ipath_f_get_base_info = ipath_pe_get_base_info;
1359         dd->ipath_f_free_irq = ipath_pe_free_irq;
1360
1361         /* initialize chip-specific variables */
1362         dd->ipath_f_tidtemplate = ipath_pe_tidtemplate;
1363
1364         /*
1365          * setup the register offsets, since they are different for each
1366          * chip
1367          */
1368         dd->ipath_kregs = &ipath_pe_kregs;
1369         dd->ipath_cregs = &ipath_pe_cregs;
1370
1371         ipath_init_pe_variables(dd);
1372 }
1373