tty/n_gsm: fix bug in CRC calculation for gsm1 mode
[linux-2.6.git] / drivers / ide / pdc202xx_old.c
1 /*
2  *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
3  *  Copyright (C) 2006-2007, 2009       MontaVista Software, Inc.
4  *  Copyright (C) 2007-2010             Bartlomiej Zolnierkiewicz
5  *
6  *  Portions Copyright (C) 1999 Promise Technology, Inc.
7  *  Author: Frank Tiernan (frankt@promise.com)
8  *  Released under terms of General Public License
9  */
10
11 #include <linux/types.h>
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/delay.h>
15 #include <linux/blkdev.h>
16 #include <linux/pci.h>
17 #include <linux/init.h>
18 #include <linux/ide.h>
19
20 #include <asm/io.h>
21
22 #define DRV_NAME "pdc202xx_old"
23
24 static void pdc202xx_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
25 {
26         struct pci_dev *dev     = to_pci_dev(hwif->dev);
27         u8 drive_pci            = 0x60 + (drive->dn << 2);
28         const u8 speed          = drive->dma_mode;
29
30         u8                      AP = 0, BP = 0, CP = 0;
31         u8                      TA = 0, TB = 0, TC = 0;
32
33         pci_read_config_byte(dev, drive_pci,     &AP);
34         pci_read_config_byte(dev, drive_pci + 1, &BP);
35         pci_read_config_byte(dev, drive_pci + 2, &CP);
36
37         switch(speed) {
38                 case XFER_UDMA_5:
39                 case XFER_UDMA_4:       TB = 0x20; TC = 0x01; break;
40                 case XFER_UDMA_2:       TB = 0x20; TC = 0x01; break;
41                 case XFER_UDMA_3:
42                 case XFER_UDMA_1:       TB = 0x40; TC = 0x02; break;
43                 case XFER_UDMA_0:
44                 case XFER_MW_DMA_2:     TB = 0x60; TC = 0x03; break;
45                 case XFER_MW_DMA_1:     TB = 0x60; TC = 0x04; break;
46                 case XFER_MW_DMA_0:     TB = 0xE0; TC = 0x0F; break;
47                 case XFER_PIO_4:        TA = 0x01; TB = 0x04; break;
48                 case XFER_PIO_3:        TA = 0x02; TB = 0x06; break;
49                 case XFER_PIO_2:        TA = 0x03; TB = 0x08; break;
50                 case XFER_PIO_1:        TA = 0x05; TB = 0x0C; break;
51                 case XFER_PIO_0:
52                 default:                TA = 0x09; TB = 0x13; break;
53         }
54
55         if (speed < XFER_SW_DMA_0) {
56                 /*
57                  * preserve SYNC_INT / ERDDY_EN bits while clearing
58                  * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
59                  */
60                 AP &= ~0x3f;
61                 if (ide_pio_need_iordy(drive, speed - XFER_PIO_0))
62                         AP |= 0x20;     /* set IORDY_EN bit */
63                 if (drive->media == ide_disk)
64                         AP |= 0x10;     /* set Prefetch_EN bit */
65                 /* clear PB[4:0] bits of register B */
66                 BP &= ~0x1f;
67                 pci_write_config_byte(dev, drive_pci,     AP | TA);
68                 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
69         } else {
70                 /* clear MB[2:0] bits of register B */
71                 BP &= ~0xe0;
72                 /* clear MC[3:0] bits of register C */
73                 CP &= ~0x0f;
74                 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
75                 pci_write_config_byte(dev, drive_pci + 2, CP | TC);
76         }
77 }
78
79 static void pdc202xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
80 {
81         drive->dma_mode = drive->pio_mode;
82         pdc202xx_set_mode(hwif, drive);
83 }
84
85 static int pdc202xx_test_irq(ide_hwif_t *hwif)
86 {
87         struct pci_dev *dev     = to_pci_dev(hwif->dev);
88         unsigned long high_16   = pci_resource_start(dev, 4);
89         u8 sc1d                 = inb(high_16 + 0x1d);
90
91         if (hwif->channel) {
92                 /*
93                  * bit 7: error, bit 6: interrupting,
94                  * bit 5: FIFO full, bit 4: FIFO empty
95                  */
96                 return (sc1d & 0x40) ? 1 : 0;
97         } else  {
98                 /*
99                  * bit 3: error, bit 2: interrupting,
100                  * bit 1: FIFO full, bit 0: FIFO empty
101                  */
102                 return (sc1d & 0x04) ? 1 : 0;
103         }
104 }
105
106 static u8 pdc2026x_cable_detect(ide_hwif_t *hwif)
107 {
108         struct pci_dev *dev = to_pci_dev(hwif->dev);
109         u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10);
110
111         pci_read_config_word(dev, 0x50, &CIS);
112
113         return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
114 }
115
116 /*
117  * Set the control register to use the 66MHz system
118  * clock for UDMA 3/4/5 mode operation when necessary.
119  *
120  * FIXME: this register is shared by both channels, some locking is needed
121  *
122  * It may also be possible to leave the 66MHz clock on
123  * and readjust the timing parameters.
124  */
125 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
126 {
127         unsigned long clock_reg = hwif->extra_base + 0x01;
128         u8 clock = inb(clock_reg);
129
130         outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
131 }
132
133 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
134 {
135         unsigned long clock_reg = hwif->extra_base + 0x01;
136         u8 clock = inb(clock_reg);
137
138         outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
139 }
140
141 static void pdc2026x_init_hwif(ide_hwif_t *hwif)
142 {
143         pdc_old_disable_66MHz_clock(hwif);
144 }
145
146 static void pdc202xx_dma_start(ide_drive_t *drive)
147 {
148         if (drive->current_speed > XFER_UDMA_2)
149                 pdc_old_enable_66MHz_clock(drive->hwif);
150         if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) {
151                 ide_hwif_t *hwif        = drive->hwif;
152                 struct request *rq      = hwif->rq;
153                 unsigned long high_16   = hwif->extra_base - 16;
154                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
155                 u32 word_count  = 0;
156                 u8 clock = inb(high_16 + 0x11);
157
158                 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
159                 word_count = (blk_rq_sectors(rq) << 8);
160                 word_count = (rq_data_dir(rq) == READ) ?
161                                         word_count | 0x05000000 :
162                                         word_count | 0x06000000;
163                 outl(word_count, atapi_reg);
164         }
165         ide_dma_start(drive);
166 }
167
168 static int pdc202xx_dma_end(ide_drive_t *drive)
169 {
170         if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) {
171                 ide_hwif_t *hwif        = drive->hwif;
172                 unsigned long high_16   = hwif->extra_base - 16;
173                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
174                 u8 clock                = 0;
175
176                 outl(0, atapi_reg); /* zero out extra */
177                 clock = inb(high_16 + 0x11);
178                 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
179         }
180         if (drive->current_speed > XFER_UDMA_2)
181                 pdc_old_disable_66MHz_clock(drive->hwif);
182         return ide_dma_end(drive);
183 }
184
185 static int init_chipset_pdc202xx(struct pci_dev *dev)
186 {
187         unsigned long dmabase = pci_resource_start(dev, 4);
188         u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
189
190         if (dmabase == 0)
191                 goto out;
192
193         udma_speed_flag = inb(dmabase | 0x1f);
194         primary_mode    = inb(dmabase | 0x1a);
195         secondary_mode  = inb(dmabase | 0x1b);
196         printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
197                 "Primary %s Mode " \
198                 "Secondary %s Mode.\n", pci_name(dev),
199                 (udma_speed_flag & 1) ? "EN" : "DIS",
200                 (primary_mode & 1) ? "MASTER" : "PCI",
201                 (secondary_mode & 1) ? "MASTER" : "PCI" );
202
203         if (!(udma_speed_flag & 1)) {
204                 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
205                         pci_name(dev), udma_speed_flag,
206                         (udma_speed_flag|1));
207                 outb(udma_speed_flag | 1, dmabase | 0x1f);
208                 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
209         }
210 out:
211         return 0;
212 }
213
214 static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
215                                            const char *name)
216 {
217         if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
218                 u8 irq = 0, irq2 = 0;
219                 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
220                 /* 0xbc */
221                 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
222                 if (irq != irq2) {
223                         pci_write_config_byte(dev,
224                                 (PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
225                         printk(KERN_INFO "%s %s: PCI config space interrupt "
226                                 "mirror fixed\n", name, pci_name(dev));
227                 }
228         }
229 }
230
231 #define IDE_HFLAGS_PDC202XX \
232         (IDE_HFLAG_ERROR_STOPS_FIFO | \
233          IDE_HFLAG_OFF_BOARD)
234
235 static const struct ide_port_ops pdc20246_port_ops = {
236         .set_pio_mode           = pdc202xx_set_pio_mode,
237         .set_dma_mode           = pdc202xx_set_mode,
238         .test_irq               = pdc202xx_test_irq,
239 };
240
241 static const struct ide_port_ops pdc2026x_port_ops = {
242         .set_pio_mode           = pdc202xx_set_pio_mode,
243         .set_dma_mode           = pdc202xx_set_mode,
244         .test_irq               = pdc202xx_test_irq,
245         .cable_detect           = pdc2026x_cable_detect,
246 };
247
248 static const struct ide_dma_ops pdc2026x_dma_ops = {
249         .dma_host_set           = ide_dma_host_set,
250         .dma_setup              = ide_dma_setup,
251         .dma_start              = pdc202xx_dma_start,
252         .dma_end                = pdc202xx_dma_end,
253         .dma_test_irq           = ide_dma_test_irq,
254         .dma_lost_irq           = ide_dma_lost_irq,
255         .dma_timer_expiry       = ide_dma_sff_timer_expiry,
256         .dma_sff_read_status    = ide_dma_sff_read_status,
257 };
258
259 #define DECLARE_PDC2026X_DEV(udma, sectors) \
260         { \
261                 .name           = DRV_NAME, \
262                 .init_chipset   = init_chipset_pdc202xx, \
263                 .init_hwif      = pdc2026x_init_hwif, \
264                 .port_ops       = &pdc2026x_port_ops, \
265                 .dma_ops        = &pdc2026x_dma_ops, \
266                 .host_flags     = IDE_HFLAGS_PDC202XX, \
267                 .pio_mask       = ATA_PIO4, \
268                 .mwdma_mask     = ATA_MWDMA2, \
269                 .udma_mask      = udma, \
270                 .max_sectors    = sectors, \
271         }
272
273 static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
274         {       /* 0: PDC20246 */
275                 .name           = DRV_NAME,
276                 .init_chipset   = init_chipset_pdc202xx,
277                 .port_ops       = &pdc20246_port_ops,
278                 .dma_ops        = &sff_dma_ops,
279                 .host_flags     = IDE_HFLAGS_PDC202XX,
280                 .pio_mask       = ATA_PIO4,
281                 .mwdma_mask     = ATA_MWDMA2,
282                 .udma_mask      = ATA_UDMA2,
283         },
284
285         /* 1: PDC2026{2,3} */
286         DECLARE_PDC2026X_DEV(ATA_UDMA4, 0),
287         /* 2: PDC2026{5,7}: UDMA5, limit LBA48 requests to 256 sectors */
288         DECLARE_PDC2026X_DEV(ATA_UDMA5, 256),
289 };
290
291 /**
292  *      pdc202xx_init_one       -       called when a PDC202xx is found
293  *      @dev: the pdc202xx device
294  *      @id: the matching pci id
295  *
296  *      Called when the PCI registration layer (or the IDE initialization)
297  *      finds a device matching our IDE device tables.
298  */
299  
300 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
301 {
302         const struct ide_port_info *d;
303         u8 idx = id->driver_data;
304
305         d = &pdc202xx_chipsets[idx];
306
307         if (idx < 2)
308                 pdc202ata4_fixup_irq(dev, d->name);
309
310         if (dev->vendor == PCI_DEVICE_ID_PROMISE_20265) {
311                 struct pci_dev *bridge = dev->bus->self;
312
313                 if (bridge &&
314                     bridge->vendor == PCI_VENDOR_ID_INTEL &&
315                     (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
316                      bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
317                         printk(KERN_INFO DRV_NAME " %s: skipping Promise "
318                                 "PDC20265 attached to I2O RAID controller\n",
319                                 pci_name(dev));
320                         return -ENODEV;
321                 }
322         }
323
324         return ide_pci_init_one(dev, d, NULL);
325 }
326
327 static const struct pci_device_id pdc202xx_pci_tbl[] = {
328         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
329         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
330         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
331         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
332         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
333         { 0, },
334 };
335 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
336
337 static struct pci_driver pdc202xx_pci_driver = {
338         .name           = "Promise_Old_IDE",
339         .id_table       = pdc202xx_pci_tbl,
340         .probe          = pdc202xx_init_one,
341         .remove         = ide_pci_remove,
342         .suspend        = ide_pci_suspend,
343         .resume         = ide_pci_resume,
344 };
345
346 static int __init pdc202xx_ide_init(void)
347 {
348         return ide_pci_register_driver(&pdc202xx_pci_driver);
349 }
350
351 static void __exit pdc202xx_ide_exit(void)
352 {
353         pci_unregister_driver(&pdc202xx_pci_driver);
354 }
355
356 module_init(pdc202xx_ide_init);
357 module_exit(pdc202xx_ide_exit);
358
359 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Bartlomiej Zolnierkiewicz");
360 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
361 MODULE_LICENSE("GPL");