pdc202xx_old: remove no longer needed debugging code
[linux-2.6.git] / drivers / ide / pdc202xx_old.c
1 /*
2  *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
3  *  Copyright (C) 2006-2007, 2009       MontaVista Software, Inc.
4  *  Copyright (C) 2007                  Bartlomiej Zolnierkiewicz
5  *
6  *  Portions Copyright (C) 1999 Promise Technology, Inc.
7  *  Author: Frank Tiernan (frankt@promise.com)
8  *  Released under terms of General Public License
9  */
10
11 #include <linux/types.h>
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/delay.h>
15 #include <linux/blkdev.h>
16 #include <linux/pci.h>
17 #include <linux/init.h>
18 #include <linux/ide.h>
19
20 #include <asm/io.h>
21
22 #define DRV_NAME "pdc202xx_old"
23
24 static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
25
26 static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
27 {
28         ide_hwif_t *hwif        = drive->hwif;
29         struct pci_dev *dev     = to_pci_dev(hwif->dev);
30         u8 drive_pci            = 0x60 + (drive->dn << 2);
31
32         u8                      AP = 0, BP = 0, CP = 0;
33         u8                      TA = 0, TB = 0, TC = 0;
34
35         /*
36          * TODO: do this once per channel
37          */
38         if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
39                 pdc_old_disable_66MHz_clock(hwif);
40
41         pci_read_config_byte(dev, drive_pci,     &AP);
42         pci_read_config_byte(dev, drive_pci + 1, &BP);
43         pci_read_config_byte(dev, drive_pci + 2, &CP);
44
45         switch(speed) {
46                 case XFER_UDMA_5:
47                 case XFER_UDMA_4:       TB = 0x20; TC = 0x01; break;
48                 case XFER_UDMA_2:       TB = 0x20; TC = 0x01; break;
49                 case XFER_UDMA_3:
50                 case XFER_UDMA_1:       TB = 0x40; TC = 0x02; break;
51                 case XFER_UDMA_0:
52                 case XFER_MW_DMA_2:     TB = 0x60; TC = 0x03; break;
53                 case XFER_MW_DMA_1:     TB = 0x60; TC = 0x04; break;
54                 case XFER_MW_DMA_0:     TB = 0xE0; TC = 0x0F; break;
55                 case XFER_PIO_4:        TA = 0x01; TB = 0x04; break;
56                 case XFER_PIO_3:        TA = 0x02; TB = 0x06; break;
57                 case XFER_PIO_2:        TA = 0x03; TB = 0x08; break;
58                 case XFER_PIO_1:        TA = 0x05; TB = 0x0C; break;
59                 case XFER_PIO_0:
60                 default:                TA = 0x09; TB = 0x13; break;
61         }
62
63         if (speed < XFER_SW_DMA_0) {
64                 /*
65                  * preserve SYNC_INT / ERDDY_EN bits while clearing
66                  * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
67                  */
68                 AP &= ~0x3f;
69                 if (ide_pio_need_iordy(drive, speed - XFER_PIO_0))
70                         AP |= 0x20;     /* set IORDY_EN bit */
71                 if (drive->media == ide_disk)
72                         AP |= 0x10;     /* set Prefetch_EN bit */
73                 /* clear PB[4:0] bits of register B */
74                 BP &= ~0x1f;
75                 pci_write_config_byte(dev, drive_pci,     AP | TA);
76                 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
77         } else {
78                 /* clear MB[2:0] bits of register B */
79                 BP &= ~0xe0;
80                 /* clear MC[3:0] bits of register C */
81                 CP &= ~0x0f;
82                 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
83                 pci_write_config_byte(dev, drive_pci + 2, CP | TC);
84         }
85 }
86
87 static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
88 {
89         pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
90 }
91
92 static int pdc202xx_test_irq(ide_hwif_t *hwif)
93 {
94         struct pci_dev *dev     = to_pci_dev(hwif->dev);
95         unsigned long high_16   = pci_resource_start(dev, 4);
96         u8 sc1d                 = inb(high_16 + 0x1d);
97
98         if (hwif->channel) {
99                 /*
100                  * bit 7: error, bit 6: interrupting,
101                  * bit 5: FIFO full, bit 4: FIFO empty
102                  */
103                 return ((sc1d & 0x50) == 0x40) ? 1 : 0;
104         } else  {
105                 /*
106                  * bit 3: error, bit 2: interrupting,
107                  * bit 1: FIFO full, bit 0: FIFO empty
108                  */
109                 return ((sc1d & 0x05) == 0x04) ? 1 : 0;
110         }
111 }
112
113 static u8 pdc2026x_cable_detect(ide_hwif_t *hwif)
114 {
115         struct pci_dev *dev = to_pci_dev(hwif->dev);
116         u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10);
117
118         pci_read_config_word(dev, 0x50, &CIS);
119
120         return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
121 }
122
123 /*
124  * Set the control register to use the 66MHz system
125  * clock for UDMA 3/4/5 mode operation when necessary.
126  *
127  * FIXME: this register is shared by both channels, some locking is needed
128  *
129  * It may also be possible to leave the 66MHz clock on
130  * and readjust the timing parameters.
131  */
132 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
133 {
134         unsigned long clock_reg = hwif->extra_base + 0x01;
135         u8 clock = inb(clock_reg);
136
137         outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
138 }
139
140 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
141 {
142         unsigned long clock_reg = hwif->extra_base + 0x01;
143         u8 clock = inb(clock_reg);
144
145         outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
146 }
147
148 static void pdc202xx_dma_start(ide_drive_t *drive)
149 {
150         if (drive->current_speed > XFER_UDMA_2)
151                 pdc_old_enable_66MHz_clock(drive->hwif);
152         if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) {
153                 ide_hwif_t *hwif        = drive->hwif;
154                 struct request *rq      = hwif->rq;
155                 unsigned long high_16   = hwif->extra_base - 16;
156                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
157                 u32 word_count  = 0;
158                 u8 clock = inb(high_16 + 0x11);
159
160                 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
161                 word_count = (blk_rq_sectors(rq) << 8);
162                 word_count = (rq_data_dir(rq) == READ) ?
163                                         word_count | 0x05000000 :
164                                         word_count | 0x06000000;
165                 outl(word_count, atapi_reg);
166         }
167         ide_dma_start(drive);
168 }
169
170 static int pdc202xx_dma_end(ide_drive_t *drive)
171 {
172         if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) {
173                 ide_hwif_t *hwif        = drive->hwif;
174                 unsigned long high_16   = hwif->extra_base - 16;
175                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
176                 u8 clock                = 0;
177
178                 outl(0, atapi_reg); /* zero out extra */
179                 clock = inb(high_16 + 0x11);
180                 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
181         }
182         if (drive->current_speed > XFER_UDMA_2)
183                 pdc_old_disable_66MHz_clock(drive->hwif);
184         return ide_dma_end(drive);
185 }
186
187 static int init_chipset_pdc202xx(struct pci_dev *dev)
188 {
189         unsigned long dmabase = pci_resource_start(dev, 4);
190         u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
191
192         if (dmabase == 0)
193                 goto out;
194
195         udma_speed_flag = inb(dmabase | 0x1f);
196         primary_mode    = inb(dmabase | 0x1a);
197         secondary_mode  = inb(dmabase | 0x1b);
198         printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
199                 "Primary %s Mode " \
200                 "Secondary %s Mode.\n", pci_name(dev),
201                 (udma_speed_flag & 1) ? "EN" : "DIS",
202                 (primary_mode & 1) ? "MASTER" : "PCI",
203                 (secondary_mode & 1) ? "MASTER" : "PCI" );
204
205         if (!(udma_speed_flag & 1)) {
206                 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
207                         pci_name(dev), udma_speed_flag,
208                         (udma_speed_flag|1));
209                 outb(udma_speed_flag | 1, dmabase | 0x1f);
210                 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
211         }
212 out:
213         return 0;
214 }
215
216 static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
217                                            const char *name)
218 {
219         if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
220                 u8 irq = 0, irq2 = 0;
221                 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
222                 /* 0xbc */
223                 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
224                 if (irq != irq2) {
225                         pci_write_config_byte(dev,
226                                 (PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
227                         printk(KERN_INFO "%s %s: PCI config space interrupt "
228                                 "mirror fixed\n", name, pci_name(dev));
229                 }
230         }
231 }
232
233 #define IDE_HFLAGS_PDC202XX \
234         (IDE_HFLAG_ERROR_STOPS_FIFO | \
235          IDE_HFLAG_OFF_BOARD)
236
237 static const struct ide_port_ops pdc20246_port_ops = {
238         .set_pio_mode           = pdc202xx_set_pio_mode,
239         .set_dma_mode           = pdc202xx_set_mode,
240         .test_irq               = pdc202xx_test_irq,
241 };
242
243 static const struct ide_port_ops pdc2026x_port_ops = {
244         .set_pio_mode           = pdc202xx_set_pio_mode,
245         .set_dma_mode           = pdc202xx_set_mode,
246         .cable_detect           = pdc2026x_cable_detect,
247 };
248
249 static const struct ide_dma_ops pdc2026x_dma_ops = {
250         .dma_host_set           = ide_dma_host_set,
251         .dma_setup              = ide_dma_setup,
252         .dma_start              = pdc202xx_dma_start,
253         .dma_end                = pdc202xx_dma_end,
254         .dma_test_irq           = ide_dma_test_irq,
255         .dma_lost_irq           = ide_dma_lost_irq,
256         .dma_timer_expiry       = ide_dma_sff_timer_expiry,
257         .dma_sff_read_status    = ide_dma_sff_read_status,
258 };
259
260 #define DECLARE_PDC2026X_DEV(udma, sectors) \
261         { \
262                 .name           = DRV_NAME, \
263                 .init_chipset   = init_chipset_pdc202xx, \
264                 .port_ops       = &pdc2026x_port_ops, \
265                 .dma_ops        = &pdc2026x_dma_ops, \
266                 .host_flags     = IDE_HFLAGS_PDC202XX, \
267                 .pio_mask       = ATA_PIO4, \
268                 .mwdma_mask     = ATA_MWDMA2, \
269                 .udma_mask      = udma, \
270                 .max_sectors    = sectors, \
271         }
272
273 static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
274         {       /* 0: PDC20246 */
275                 .name           = DRV_NAME,
276                 .init_chipset   = init_chipset_pdc202xx,
277                 .port_ops       = &pdc20246_port_ops,
278                 .dma_ops        = &sff_dma_ops,
279                 .host_flags     = IDE_HFLAGS_PDC202XX,
280                 .pio_mask       = ATA_PIO4,
281                 .mwdma_mask     = ATA_MWDMA2,
282                 .udma_mask      = ATA_UDMA2,
283         },
284
285         /* 1: PDC2026{2,3} */
286         DECLARE_PDC2026X_DEV(ATA_UDMA4, 0),
287         /* 2: PDC2026{5,7}: UDMA5, limit LBA48 requests to 256 sectors */
288         DECLARE_PDC2026X_DEV(ATA_UDMA5, 256),
289 };
290
291 /**
292  *      pdc202xx_init_one       -       called when a PDC202xx is found
293  *      @dev: the pdc202xx device
294  *      @id: the matching pci id
295  *
296  *      Called when the PCI registration layer (or the IDE initialization)
297  *      finds a device matching our IDE device tables.
298  */
299  
300 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
301 {
302         const struct ide_port_info *d;
303         u8 idx = id->driver_data;
304
305         d = &pdc202xx_chipsets[idx];
306
307         if (idx < 2)
308                 pdc202ata4_fixup_irq(dev, d->name);
309
310         if (dev->vendor == PCI_DEVICE_ID_PROMISE_20265) {
311                 struct pci_dev *bridge = dev->bus->self;
312
313                 if (bridge &&
314                     bridge->vendor == PCI_VENDOR_ID_INTEL &&
315                     (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
316                      bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
317                         printk(KERN_INFO DRV_NAME " %s: skipping Promise "
318                                 "PDC20265 attached to I2O RAID controller\n",
319                                 pci_name(dev));
320                         return -ENODEV;
321                 }
322         }
323
324         return ide_pci_init_one(dev, d, NULL);
325 }
326
327 static const struct pci_device_id pdc202xx_pci_tbl[] = {
328         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
329         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
330         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
331         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
332         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
333         { 0, },
334 };
335 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
336
337 static struct pci_driver pdc202xx_pci_driver = {
338         .name           = "Promise_Old_IDE",
339         .id_table       = pdc202xx_pci_tbl,
340         .probe          = pdc202xx_init_one,
341         .remove         = ide_pci_remove,
342         .suspend        = ide_pci_suspend,
343         .resume         = ide_pci_resume,
344 };
345
346 static int __init pdc202xx_ide_init(void)
347 {
348         return ide_pci_register_driver(&pdc202xx_pci_driver);
349 }
350
351 static void __exit pdc202xx_ide_exit(void)
352 {
353         pci_unregister_driver(&pdc202xx_pci_driver);
354 }
355
356 module_init(pdc202xx_ide_init);
357 module_exit(pdc202xx_ide_exit);
358
359 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
360 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
361 MODULE_LICENSE("GPL");