[PATCH] ide: fix HPT3xx hotswap support
[linux-2.6.git] / drivers / ide / pci / hpt366.c
1 /*
2  * linux/drivers/ide/pci/hpt366.c               Version 0.36    April 25, 2003
3  *
4  * Copyright (C) 1999-2003              Andre Hedrick <andre@linux-ide.org>
5  * Portions Copyright (C) 2001          Sun Microsystems, Inc.
6  * Portions Copyright (C) 2003          Red Hat Inc
7  * Portions Copyright (C) 2005-2006     MontaVista Software, Inc.
8  *
9  * Thanks to HighPoint Technologies for their assistance, and hardware.
10  * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
11  * donation of an ABit BP6 mainboard, processor, and memory acellerated
12  * development and support.
13  *
14  *
15  * HighPoint has its own drivers (open source except for the RAID part)
16  * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
17  * This may be useful to anyone wanting to work on this driver, however  do not
18  * trust  them too much since the code tends to become less and less meaningful
19  * as the time passes... :-/
20  *
21  * Note that final HPT370 support was done by force extraction of GPL.
22  *
23  * - add function for getting/setting power status of drive
24  * - the HPT370's state machine can get confused. reset it before each dma 
25  *   xfer to prevent that from happening.
26  * - reset state engine whenever we get an error.
27  * - check for busmaster state at end of dma. 
28  * - use new highpoint timings.
29  * - detect bus speed using highpoint register.
30  * - use pll if we don't have a clock table. added a 66MHz table that's
31  *   just 2x the 33MHz table.
32  * - removed turnaround. NOTE: we never want to switch between pll and
33  *   pci clocks as the chip can glitch in those cases. the highpoint
34  *   approved workaround slows everything down too much to be useful. in
35  *   addition, we would have to serialize access to each chip.
36  *      Adrian Sun <a.sun@sun.com>
37  *
38  * add drive timings for 66MHz PCI bus,
39  * fix ATA Cable signal detection, fix incorrect /proc info
40  * add /proc display for per-drive PIO/DMA/UDMA mode and
41  * per-channel ATA-33/66 Cable detect.
42  *      Duncan Laurie <void@sun.com>
43  *
44  * fixup /proc output for multiple controllers
45  *      Tim Hockin <thockin@sun.com>
46  *
47  * On hpt366: 
48  * Reset the hpt366 on error, reset on dma
49  * Fix disabling Fast Interrupt hpt366.
50  *      Mike Waychison <crlf@sun.com>
51  *
52  * Added support for 372N clocking and clock switching. The 372N needs
53  * different clocks on read/write. This requires overloading rw_disk and
54  * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
55  * keeping me sane. 
56  *              Alan Cox <alan@redhat.com>
57  *
58  * - fix the clock turnaround code: it was writing to the wrong ports when
59  *   called for the secondary channel, caching the current clock mode per-
60  *   channel caused the cached register value to get out of sync with the
61  *   actual one, the channels weren't serialized, the turnaround shouldn't
62  *   be done on 66 MHz PCI bus
63  * - avoid calibrating PLL twice as the second time results in a wrong PCI
64  *   frequency and thus in the wrong timings for the secondary channel
65  * - disable UltraATA/133 for HPT372 by default (50 MHz DPLL clock do not
66  *   allow for this speed anyway)
67  * - add support for HPT302N and HPT371N clocking (the same as for HPT372N)
68  * - HPT371/N are single channel chips, so avoid touching the primary channel
69  *   which exists only virtually (there's no pins for it)
70  * - fix/remove bad/unused timing tables and use one set of tables for the whole
71  *   HPT37x chip family; save space by introducing the separate transfer mode
72  *   table in which the mode lookup is done
73  * - fix the hotswap code:  it caused RESET- to glitch when tristating the bus,
74  *   and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
75  *              <source@mvista.com>
76  *
77  */
78
79
80 #include <linux/types.h>
81 #include <linux/module.h>
82 #include <linux/kernel.h>
83 #include <linux/delay.h>
84 #include <linux/timer.h>
85 #include <linux/mm.h>
86 #include <linux/ioport.h>
87 #include <linux/blkdev.h>
88 #include <linux/hdreg.h>
89
90 #include <linux/interrupt.h>
91 #include <linux/pci.h>
92 #include <linux/init.h>
93 #include <linux/ide.h>
94
95 #include <asm/uaccess.h>
96 #include <asm/io.h>
97 #include <asm/irq.h>
98
99 /* various tuning parameters */
100 #define HPT_RESET_STATE_ENGINE
101 #undef  HPT_DELAY_INTERRUPT
102 #define HPT_SERIALIZE_IO        0
103
104 static const char *quirk_drives[] = {
105         "QUANTUM FIREBALLlct08 08",
106         "QUANTUM FIREBALLP KA6.4",
107         "QUANTUM FIREBALLP LM20.4",
108         "QUANTUM FIREBALLP LM20.5",
109         NULL
110 };
111
112 static const char *bad_ata100_5[] = {
113         "IBM-DTLA-307075",
114         "IBM-DTLA-307060",
115         "IBM-DTLA-307045",
116         "IBM-DTLA-307030",
117         "IBM-DTLA-307020",
118         "IBM-DTLA-307015",
119         "IBM-DTLA-305040",
120         "IBM-DTLA-305030",
121         "IBM-DTLA-305020",
122         "IC35L010AVER07-0",
123         "IC35L020AVER07-0",
124         "IC35L030AVER07-0",
125         "IC35L040AVER07-0",
126         "IC35L060AVER07-0",
127         "WDC AC310200R",
128         NULL
129 };
130
131 static const char *bad_ata66_4[] = {
132         "IBM-DTLA-307075",
133         "IBM-DTLA-307060",
134         "IBM-DTLA-307045",
135         "IBM-DTLA-307030",
136         "IBM-DTLA-307020",
137         "IBM-DTLA-307015",
138         "IBM-DTLA-305040",
139         "IBM-DTLA-305030",
140         "IBM-DTLA-305020",
141         "IC35L010AVER07-0",
142         "IC35L020AVER07-0",
143         "IC35L030AVER07-0",
144         "IC35L040AVER07-0",
145         "IC35L060AVER07-0",
146         "WDC AC310200R",
147         NULL
148 };
149
150 static const char *bad_ata66_3[] = {
151         "WDC AC310200R",
152         NULL
153 };
154
155 static const char *bad_ata33[] = {
156         "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
157         "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
158         "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
159         "Maxtor 90510D4",
160         "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
161         "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
162         "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
163         NULL
164 };
165
166 static u8 xfer_speeds[] = {
167         XFER_UDMA_6,
168         XFER_UDMA_5,
169         XFER_UDMA_4,
170         XFER_UDMA_3,
171         XFER_UDMA_2,
172         XFER_UDMA_1,
173         XFER_UDMA_0,
174
175         XFER_MW_DMA_2,
176         XFER_MW_DMA_1,
177         XFER_MW_DMA_0,
178
179         XFER_PIO_4,
180         XFER_PIO_3,
181         XFER_PIO_2,
182         XFER_PIO_1,
183         XFER_PIO_0
184 };
185
186 /* Key for bus clock timings
187  * 36x   37x
188  * bits  bits
189  * 0:3   0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
190  *              cycles = value + 1
191  * 4:7   4:8    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
192  *              cycles = value + 1
193  * 8:11  9:12   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
194  *              register access.
195  * 12:15 13:17  cmd_low_time. Active time of DIOW_/DIOR_ during task file
196  *              register access.
197  * 16:18 18:20  udma_cycle_time. Clock cycles for UDMA xfer.
198  * -     21     CLK frequency: 0=ATA clock, 1=dual ATA clock.
199  * 19:21 22:24  pre_high_time. Time to initialize the 1st cycle for PIO and
200  *              MW DMA xfer.
201  * 22:24 25:27  cmd_pre_high_time. Time to initialize the 1st PIO cycle for
202  *              task file register access.
203  * 28    28     UDMA enable.
204  * 29    29     DMA  enable.
205  * 30    30     PIO MST enable. If set, the chip is in bus master mode during
206  *              PIO xfer.
207  * 31    31     FIFO enable.
208  */
209
210 static u32 forty_base_hpt36x[] = {
211         /* XFER_UDMA_6 */       0x900fd943,
212         /* XFER_UDMA_5 */       0x900fd943,
213         /* XFER_UDMA_4 */       0x900fd943,
214         /* XFER_UDMA_3 */       0x900ad943,
215         /* XFER_UDMA_2 */       0x900bd943,
216         /* XFER_UDMA_1 */       0x9008d943,
217         /* XFER_UDMA_0 */       0x9008d943,
218
219         /* XFER_MW_DMA_2 */     0xa008d943,
220         /* XFER_MW_DMA_1 */     0xa010d955,
221         /* XFER_MW_DMA_0 */     0xa010d9fc,
222
223         /* XFER_PIO_4 */        0xc008d963,
224         /* XFER_PIO_3 */        0xc010d974,
225         /* XFER_PIO_2 */        0xc010d997,
226         /* XFER_PIO_1 */        0xc010d9c7,
227         /* XFER_PIO_0 */        0xc018d9d9
228 };
229
230 static u32 thirty_three_base_hpt36x[] = {
231         /* XFER_UDMA_6 */       0x90c9a731,
232         /* XFER_UDMA_5 */       0x90c9a731,
233         /* XFER_UDMA_4 */       0x90c9a731,
234         /* XFER_UDMA_3 */       0x90cfa731,
235         /* XFER_UDMA_2 */       0x90caa731,
236         /* XFER_UDMA_1 */       0x90cba731,
237         /* XFER_UDMA_0 */       0x90c8a731,
238
239         /* XFER_MW_DMA_2 */     0xa0c8a731,
240         /* XFER_MW_DMA_1 */     0xa0c8a732,     /* 0xa0c8a733 */
241         /* XFER_MW_DMA_0 */     0xa0c8a797,
242
243         /* XFER_PIO_4 */        0xc0c8a731,
244         /* XFER_PIO_3 */        0xc0c8a742,
245         /* XFER_PIO_2 */        0xc0d0a753,
246         /* XFER_PIO_1 */        0xc0d0a7a3,     /* 0xc0d0a793 */
247         /* XFER_PIO_0 */        0xc0d0a7aa      /* 0xc0d0a7a7 */
248 };
249
250 static u32 twenty_five_base_hpt36x[] = {
251         /* XFER_UDMA_6 */       0x90c98521,
252         /* XFER_UDMA_5 */       0x90c98521,
253         /* XFER_UDMA_4 */       0x90c98521,
254         /* XFER_UDMA_3 */       0x90cf8521,
255         /* XFER_UDMA_2 */       0x90cf8521,
256         /* XFER_UDMA_1 */       0x90cb8521,
257         /* XFER_UDMA_0 */       0x90cb8521,
258
259         /* XFER_MW_DMA_2 */     0xa0ca8521,
260         /* XFER_MW_DMA_1 */     0xa0ca8532,
261         /* XFER_MW_DMA_0 */     0xa0ca8575,
262
263         /* XFER_PIO_4 */        0xc0ca8521,
264         /* XFER_PIO_3 */        0xc0ca8532,
265         /* XFER_PIO_2 */        0xc0ca8542,
266         /* XFER_PIO_1 */        0xc0d08572,
267         /* XFER_PIO_0 */        0xc0d08585
268 };
269
270 static u32 thirty_three_base_hpt37x[] = {
271         /* XFER_UDMA_6 */       0x12446231,     /* 0x12646231 ?? */
272         /* XFER_UDMA_5 */       0x12446231,
273         /* XFER_UDMA_4 */       0x12446231,
274         /* XFER_UDMA_3 */       0x126c6231,
275         /* XFER_UDMA_2 */       0x12486231,
276         /* XFER_UDMA_1 */       0x124c6233,
277         /* XFER_UDMA_0 */       0x12506297,
278
279         /* XFER_MW_DMA_2 */     0x22406c31,
280         /* XFER_MW_DMA_1 */     0x22406c33,
281         /* XFER_MW_DMA_0 */     0x22406c97,
282
283         /* XFER_PIO_4 */        0x06414e31,
284         /* XFER_PIO_3 */        0x06414e42,
285         /* XFER_PIO_2 */        0x06414e53,
286         /* XFER_PIO_1 */        0x06814e93,
287         /* XFER_PIO_0 */        0x06814ea7
288 };
289
290 static u32 fifty_base_hpt37x[] = {
291         /* XFER_UDMA_6 */       0x12848242,
292         /* XFER_UDMA_5 */       0x12848242,
293         /* XFER_UDMA_4 */       0x12ac8242,
294         /* XFER_UDMA_3 */       0x128c8242,
295         /* XFER_UDMA_2 */       0x120c8242,
296         /* XFER_UDMA_1 */       0x12148254,
297         /* XFER_UDMA_0 */       0x121882ea,
298
299         /* XFER_MW_DMA_2 */     0x22808242,
300         /* XFER_MW_DMA_1 */     0x22808254,
301         /* XFER_MW_DMA_0 */     0x228082ea,
302
303         /* XFER_PIO_4 */        0x0a81f442,
304         /* XFER_PIO_3 */        0x0a81f443,
305         /* XFER_PIO_2 */        0x0a81f454,
306         /* XFER_PIO_1 */        0x0ac1f465,
307         /* XFER_PIO_0 */        0x0ac1f48a
308 };
309
310 static u32 sixty_six_base_hpt37x[] = {
311         /* XFER_UDMA_6 */       0x1c869c62,
312         /* XFER_UDMA_5 */       0x1cae9c62,     /* 0x1c8a9c62 */
313         /* XFER_UDMA_4 */       0x1c8a9c62,
314         /* XFER_UDMA_3 */       0x1c8e9c62,
315         /* XFER_UDMA_2 */       0x1c929c62,
316         /* XFER_UDMA_1 */       0x1c9a9c62,
317         /* XFER_UDMA_0 */       0x1c829c62,
318
319         /* XFER_MW_DMA_2 */     0x2c829c62,
320         /* XFER_MW_DMA_1 */     0x2c829c66,
321         /* XFER_MW_DMA_0 */     0x2c829d2e,
322
323         /* XFER_PIO_4 */        0x0c829c62,
324         /* XFER_PIO_3 */        0x0c829c84,
325         /* XFER_PIO_2 */        0x0c829ca6,
326         /* XFER_PIO_1 */        0x0d029d26,
327         /* XFER_PIO_0 */        0x0d029d5e
328 };
329
330 #define HPT366_DEBUG_DRIVE_INFO         0
331 #define HPT374_ALLOW_ATA133_6           0
332 #define HPT371_ALLOW_ATA133_6           0
333 #define HPT302_ALLOW_ATA133_6           0
334 #define HPT372_ALLOW_ATA133_6           0
335 #define HPT370_ALLOW_ATA100_5           1
336 #define HPT366_ALLOW_ATA66_4            1
337 #define HPT366_ALLOW_ATA66_3            1
338 #define HPT366_MAX_DEVS                 8
339
340 #define F_LOW_PCI_33    0x23
341 #define F_LOW_PCI_40    0x29
342 #define F_LOW_PCI_50    0x2d
343 #define F_LOW_PCI_66    0x42
344
345 /*
346  *      Hold all the highpoint quirks and revision information in one
347  *      place.
348  */
349
350 struct hpt_info
351 {
352         u8 max_mode;            /* Speeds allowed */
353         int revision;           /* Chipset revision */
354         int flags;              /* Chipset properties */
355 #define PLL_MODE        1
356 #define IS_3xxN         2
357 #define PCI_66MHZ       4
358                                 /* Speed table */
359         u32 *speed;
360 };
361
362 /*
363  *      This wants fixing so that we do everything not by classrev
364  *      (which breaks on the newest chips) but by creating an
365  *      enumeration of chip variants and using that
366  */
367
368 static __devinit u32 hpt_revision (struct pci_dev *dev)
369 {
370         u32 class_rev;
371         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
372         class_rev &= 0xff;
373
374         switch(dev->device) {
375                 /* Remap new 372N onto 372 */
376                 case PCI_DEVICE_ID_TTI_HPT372N:
377                         class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
378                 case PCI_DEVICE_ID_TTI_HPT374:
379                         class_rev = PCI_DEVICE_ID_TTI_HPT374; break;
380                 case PCI_DEVICE_ID_TTI_HPT371:
381                         class_rev = PCI_DEVICE_ID_TTI_HPT371; break;
382                 case PCI_DEVICE_ID_TTI_HPT302:
383                         class_rev = PCI_DEVICE_ID_TTI_HPT302; break;
384                 case PCI_DEVICE_ID_TTI_HPT372:
385                         class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
386                 default:
387                         break;
388         }
389         return class_rev;
390 }
391
392 static int check_in_drive_lists(ide_drive_t *drive, const char **list);
393
394 static u8 hpt3xx_ratemask (ide_drive_t *drive)
395 {
396         ide_hwif_t *hwif        = drive->hwif;
397         struct hpt_info *info   = ide_get_hwifdata(hwif);
398         u8 mode                 = 0;
399
400         /* FIXME: TODO - move this to set info->mode once at boot */
401
402         if (info->revision >= 8) {              /* HPT374 */
403                 mode = (HPT374_ALLOW_ATA133_6) ? 4 : 3;
404         } else if (info->revision >= 7) {       /* HPT371 */
405                 mode = (HPT371_ALLOW_ATA133_6) ? 4 : 3;
406         } else if (info->revision >= 6) {       /* HPT302 */
407                 mode = (HPT302_ALLOW_ATA133_6) ? 4 : 3;
408         } else if (info->revision >= 5) {       /* HPT372 */
409                 mode = (HPT372_ALLOW_ATA133_6) ? 4 : 3;
410         } else if (info->revision >= 4) {       /* HPT370A */
411                 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
412         } else if (info->revision >= 3) {       /* HPT370 */
413                 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
414                 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : mode;
415         } else {                                /* HPT366 and HPT368 */
416                 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : 2;
417         }
418         if (!eighty_ninty_three(drive) && mode)
419                 mode = min(mode, (u8)1);
420         return mode;
421 }
422
423 /*
424  *      Note for the future; the SATA hpt37x we must set
425  *      either PIO or UDMA modes 0,4,5
426  */
427  
428 static u8 hpt3xx_ratefilter (ide_drive_t *drive, u8 speed)
429 {
430         ide_hwif_t *hwif        = drive->hwif;
431         struct hpt_info *info   = ide_get_hwifdata(hwif);
432         u8 mode                 = hpt3xx_ratemask(drive);
433
434         if (drive->media != ide_disk)
435                 return min(speed, (u8)XFER_PIO_4);
436
437         switch(mode) {
438                 case 0x04:
439                         speed = min(speed, (u8)XFER_UDMA_6);
440                         break;
441                 case 0x03:
442                         speed = min(speed, (u8)XFER_UDMA_5);
443                         if (info->revision >= 5)
444                                 break;
445                         if (check_in_drive_lists(drive, bad_ata100_5))
446                                 speed = min(speed, (u8)XFER_UDMA_4);
447                         break;
448                 case 0x02:
449                         speed = min(speed, (u8)XFER_UDMA_4);
450         /*
451          * CHECK ME, Does this need to be set to 5 ??
452          */
453                         if (info->revision >= 3)
454                                 break;
455                         if ((check_in_drive_lists(drive, bad_ata66_4)) ||
456                             (!(HPT366_ALLOW_ATA66_4)))
457                                 speed = min(speed, (u8)XFER_UDMA_3);
458                         if ((check_in_drive_lists(drive, bad_ata66_3)) ||
459                             (!(HPT366_ALLOW_ATA66_3)))
460                                 speed = min(speed, (u8)XFER_UDMA_2);
461                         break;
462                 case 0x01:
463                         speed = min(speed, (u8)XFER_UDMA_2);
464         /*
465          * CHECK ME, Does this need to be set to 5 ??
466          */
467                         if (info->revision >= 3)
468                                 break;
469                         if (check_in_drive_lists(drive, bad_ata33))
470                                 speed = min(speed, (u8)XFER_MW_DMA_2);
471                         break;
472                 case 0x00:
473                 default:
474                         speed = min(speed, (u8)XFER_MW_DMA_2);
475                         break;
476         }
477         return speed;
478 }
479
480 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
481 {
482         struct hd_driveid *id = drive->id;
483
484         if (quirk_drives == list) {
485                 while (*list)
486                         if (strstr(id->model, *list++))
487                                 return 1;
488         } else {
489                 while (*list)
490                         if (!strcmp(*list++,id->model))
491                                 return 1;
492         }
493         return 0;
494 }
495
496 static u32 pci_bus_clock_list(u8 speed, u32 *chipset_table)
497 {
498         int i;
499
500         /*
501          * Lookup the transfer mode table to get the index into
502          * the timing table.
503          *
504          * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
505          */
506         for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
507                 if (xfer_speeds[i] == speed)
508                         break;
509         return chipset_table[i];
510 }
511
512 static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
513 {
514         ide_hwif_t *hwif        = drive->hwif;
515         struct pci_dev *dev     = hwif->pci_dev;
516         struct hpt_info *info   = ide_get_hwifdata(hwif);
517         u8 speed                = hpt3xx_ratefilter(drive, xferspeed);
518         u8 regtime              = (drive->select.b.unit & 0x01) ? 0x44 : 0x40;
519         u8 regfast              = (hwif->channel) ? 0x55 : 0x51;
520         u8 drive_fast           = 0;
521         u32 reg1 = 0, reg2      = 0;
522
523         /*
524          * Disable the "fast interrupt" prediction.
525          */
526         pci_read_config_byte(dev, regfast, &drive_fast);
527         if (drive_fast & 0x80)
528                 pci_write_config_byte(dev, regfast, drive_fast & ~0x80);
529
530         reg2 = pci_bus_clock_list(speed, info->speed);
531
532         /*
533          * Disable on-chip PIO FIFO/buffer
534          *  (to avoid problems handling I/O errors later)
535          */
536         pci_read_config_dword(dev, regtime, &reg1);
537         if (speed >= XFER_MW_DMA_0) {
538                 reg2 = (reg2 & ~0xc0000000) | (reg1 & 0xc0000000);
539         } else {
540                 reg2 = (reg2 & ~0x30070000) | (reg1 & 0x30070000);
541         }       
542         reg2 &= ~0x80000000;
543
544         pci_write_config_dword(dev, regtime, reg2);
545
546         return ide_config_drive_speed(drive, speed);
547 }
548
549 static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed)
550 {
551         ide_hwif_t *hwif        = drive->hwif;
552         struct pci_dev *dev = hwif->pci_dev;
553         struct hpt_info *info   = ide_get_hwifdata(hwif);
554         u8 speed        = hpt3xx_ratefilter(drive, xferspeed);
555         u8 regfast      = (drive->hwif->channel) ? 0x55 : 0x51;
556         u8 drive_pci    = 0x40 + (drive->dn * 4);
557         u8 new_fast     = 0, drive_fast = 0;
558         u32 list_conf   = 0, drive_conf = 0;
559         u32 conf_mask   = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
560
561         /*
562          * Disable the "fast interrupt" prediction.
563          * don't holdoff on interrupts. (== 0x01 despite what the docs say) 
564          */
565         pci_read_config_byte(dev, regfast, &drive_fast);
566         new_fast = drive_fast;
567         if (new_fast & 0x02)
568                 new_fast &= ~0x02;
569
570 #ifdef HPT_DELAY_INTERRUPT
571         if (new_fast & 0x01)
572                 new_fast &= ~0x01;
573 #else
574         if ((new_fast & 0x01) == 0)
575                 new_fast |= 0x01;
576 #endif
577         if (new_fast != drive_fast)
578                 pci_write_config_byte(dev, regfast, new_fast);
579
580         list_conf = pci_bus_clock_list(speed, info->speed);
581
582         pci_read_config_dword(dev, drive_pci, &drive_conf);
583         list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
584         
585         if (speed < XFER_MW_DMA_0)
586                 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
587         pci_write_config_dword(dev, drive_pci, list_conf);
588
589         return ide_config_drive_speed(drive, speed);
590 }
591
592 static int hpt372_tune_chipset(ide_drive_t *drive, u8 xferspeed)
593 {
594         ide_hwif_t *hwif        = drive->hwif;
595         struct pci_dev *dev     = hwif->pci_dev;
596         struct hpt_info *info   = ide_get_hwifdata(hwif);
597         u8 speed        = hpt3xx_ratefilter(drive, xferspeed);
598         u8 regfast      = (drive->hwif->channel) ? 0x55 : 0x51;
599         u8 drive_fast   = 0, drive_pci = 0x40 + (drive->dn * 4);
600         u32 list_conf   = 0, drive_conf = 0;
601         u32 conf_mask   = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
602
603         /*
604          * Disable the "fast interrupt" prediction.
605          * don't holdoff on interrupts. (== 0x01 despite what the docs say)
606          */
607         pci_read_config_byte(dev, regfast, &drive_fast);
608         drive_fast &= ~0x07;
609         pci_write_config_byte(dev, regfast, drive_fast);
610
611         list_conf = pci_bus_clock_list(speed, info->speed);
612         pci_read_config_dword(dev, drive_pci, &drive_conf);
613         list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
614         if (speed < XFER_MW_DMA_0)
615                 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
616         pci_write_config_dword(dev, drive_pci, list_conf);
617
618         return ide_config_drive_speed(drive, speed);
619 }
620
621 static int hpt3xx_tune_chipset (ide_drive_t *drive, u8 speed)
622 {
623         ide_hwif_t *hwif        = drive->hwif;
624         struct hpt_info *info   = ide_get_hwifdata(hwif);
625
626         if (info->revision >= 8)
627                 return hpt372_tune_chipset(drive, speed); /* not a typo */
628         else if (info->revision >= 5)
629                 return hpt372_tune_chipset(drive, speed);
630         else if (info->revision >= 3)
631                 return hpt370_tune_chipset(drive, speed);
632         else    /* hpt368: hpt_minimum_revision(dev, 2) */
633                 return hpt36x_tune_chipset(drive, speed);
634 }
635
636 static void hpt3xx_tune_drive (ide_drive_t *drive, u8 pio)
637 {
638         pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
639         (void) hpt3xx_tune_chipset(drive, (XFER_PIO_0 + pio));
640 }
641
642 /*
643  * This allows the configuration of ide_pci chipset registers
644  * for cards that learn about the drive's UDMA, DMA, PIO capabilities
645  * after the drive is reported by the OS.  Initially for designed for
646  * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
647  *
648  * check_in_drive_lists(drive, bad_ata66_4)
649  * check_in_drive_lists(drive, bad_ata66_3)
650  * check_in_drive_lists(drive, bad_ata33)
651  *
652  */
653 static int config_chipset_for_dma (ide_drive_t *drive)
654 {
655         u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
656         ide_hwif_t *hwif = drive->hwif;
657         struct hpt_info *info   = ide_get_hwifdata(hwif);
658
659         if (!speed)
660                 return 0;
661
662         /* If we don't have any timings we can't do a lot */
663         if (info->speed == NULL)
664                 return 0;
665
666         (void) hpt3xx_tune_chipset(drive, speed);
667         return ide_dma_enable(drive);
668 }
669
670 static int hpt3xx_quirkproc (ide_drive_t *drive)
671 {
672         return ((int) check_in_drive_lists(drive, quirk_drives));
673 }
674
675 static void hpt3xx_intrproc (ide_drive_t *drive)
676 {
677         ide_hwif_t *hwif = drive->hwif;
678
679         if (drive->quirk_list)
680                 return;
681         /* drives in the quirk_list may not like intr setups/cleanups */
682         hwif->OUTB(drive->ctl|2, IDE_CONTROL_REG);
683 }
684
685 static void hpt3xx_maskproc (ide_drive_t *drive, int mask)
686 {
687         ide_hwif_t *hwif = drive->hwif;
688         struct hpt_info *info = ide_get_hwifdata(hwif);
689         struct pci_dev *dev = hwif->pci_dev;
690
691         if (drive->quirk_list) {
692                 if (info->revision >= 3) {
693                         u8 reg5a = 0;
694                         pci_read_config_byte(dev, 0x5a, &reg5a);
695                         if (((reg5a & 0x10) >> 4) != mask)
696                                 pci_write_config_byte(dev, 0x5a, mask ? (reg5a | 0x10) : (reg5a & ~0x10));
697                 } else {
698                         if (mask) {
699                                 disable_irq(hwif->irq);
700                         } else {
701                                 enable_irq(hwif->irq);
702                         }
703                 }
704         } else {
705                 if (IDE_CONTROL_REG)
706                         hwif->OUTB(mask ? (drive->ctl | 2) :
707                                                  (drive->ctl & ~2),
708                                                  IDE_CONTROL_REG);
709         }
710 }
711
712 static int hpt366_config_drive_xfer_rate (ide_drive_t *drive)
713 {
714         ide_hwif_t *hwif        = drive->hwif;
715         struct hd_driveid *id   = drive->id;
716
717         drive->init_speed = 0;
718
719         if ((id->capability & 1) && drive->autodma) {
720
721                 if (ide_use_dma(drive)) {
722                         if (config_chipset_for_dma(drive))
723                                 return hwif->ide_dma_on(drive);
724                 }
725
726                 goto fast_ata_pio;
727
728         } else if ((id->capability & 8) || (id->field_valid & 2)) {
729 fast_ata_pio:
730                 hpt3xx_tune_drive(drive, 5);
731                 return hwif->ide_dma_off_quietly(drive);
732         }
733         /* IORDY not supported */
734         return 0;
735 }
736
737 /*
738  * This is specific to the HPT366 UDMA bios chipset
739  * by HighPoint|Triones Technologies, Inc.
740  */
741 static int hpt366_ide_dma_lostirq (ide_drive_t *drive)
742 {
743         struct pci_dev *dev     = HWIF(drive)->pci_dev;
744         u8 reg50h = 0, reg52h = 0, reg5ah = 0;
745
746         pci_read_config_byte(dev, 0x50, &reg50h);
747         pci_read_config_byte(dev, 0x52, &reg52h);
748         pci_read_config_byte(dev, 0x5a, &reg5ah);
749         printk("%s: (%s)  reg50h=0x%02x, reg52h=0x%02x, reg5ah=0x%02x\n",
750                 drive->name, __FUNCTION__, reg50h, reg52h, reg5ah);
751         if (reg5ah & 0x10)
752                 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
753         return __ide_dma_lostirq(drive);
754 }
755
756 static void hpt370_clear_engine (ide_drive_t *drive)
757 {
758         u8 regstate = HWIF(drive)->channel ? 0x54 : 0x50;
759         pci_write_config_byte(HWIF(drive)->pci_dev, regstate, 0x37);
760         udelay(10);
761 }
762
763 static void hpt370_ide_dma_start(ide_drive_t *drive)
764 {
765 #ifdef HPT_RESET_STATE_ENGINE
766         hpt370_clear_engine(drive);
767 #endif
768         ide_dma_start(drive);
769 }
770
771 static int hpt370_ide_dma_end (ide_drive_t *drive)
772 {
773         ide_hwif_t *hwif        = HWIF(drive);
774         u8 dma_stat             = hwif->INB(hwif->dma_status);
775
776         if (dma_stat & 0x01) {
777                 /* wait a little */
778                 udelay(20);
779                 dma_stat = hwif->INB(hwif->dma_status);
780         }
781         if ((dma_stat & 0x01) != 0) 
782                 /* fallthrough */
783                 (void) HWIF(drive)->ide_dma_timeout(drive);
784
785         return __ide_dma_end(drive);
786 }
787
788 static void hpt370_lostirq_timeout (ide_drive_t *drive)
789 {
790         ide_hwif_t *hwif        = HWIF(drive);
791         u8 bfifo = 0, reginfo   = hwif->channel ? 0x56 : 0x52;
792         u8 dma_stat = 0, dma_cmd = 0;
793
794         pci_read_config_byte(HWIF(drive)->pci_dev, reginfo, &bfifo);
795         printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo);
796         hpt370_clear_engine(drive);
797         /* get dma command mode */
798         dma_cmd = hwif->INB(hwif->dma_command);
799         /* stop dma */
800         hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
801         dma_stat = hwif->INB(hwif->dma_status);
802         /* clear errors */
803         hwif->OUTB(dma_stat | 0x6, hwif->dma_status);
804 }
805
806 static int hpt370_ide_dma_timeout (ide_drive_t *drive)
807 {
808         hpt370_lostirq_timeout(drive);
809         hpt370_clear_engine(drive);
810         return __ide_dma_timeout(drive);
811 }
812
813 static int hpt370_ide_dma_lostirq (ide_drive_t *drive)
814 {
815         hpt370_lostirq_timeout(drive);
816         hpt370_clear_engine(drive);
817         return __ide_dma_lostirq(drive);
818 }
819
820 /* returns 1 if DMA IRQ issued, 0 otherwise */
821 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
822 {
823         ide_hwif_t *hwif        = HWIF(drive);
824         u16 bfifo               = 0;
825         u8 reginfo              = hwif->channel ? 0x56 : 0x52;
826         u8 dma_stat;
827
828         pci_read_config_word(hwif->pci_dev, reginfo, &bfifo);
829         if (bfifo & 0x1FF) {
830 //              printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
831                 return 0;
832         }
833
834         dma_stat = hwif->INB(hwif->dma_status);
835         /* return 1 if INTR asserted */
836         if ((dma_stat & 4) == 4)
837                 return 1;
838
839         if (!drive->waiting_for_dma)
840                 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
841                                 drive->name, __FUNCTION__);
842         return 0;
843 }
844
845 static int hpt374_ide_dma_end (ide_drive_t *drive)
846 {
847         struct pci_dev *dev     = HWIF(drive)->pci_dev;
848         ide_hwif_t *hwif        = HWIF(drive);
849         u8 msc_stat = 0, mscreg = hwif->channel ? 0x54 : 0x50;
850         u8 bwsr_stat = 0, bwsr_mask = hwif->channel ? 0x02 : 0x01;
851
852         pci_read_config_byte(dev, 0x6a, &bwsr_stat);
853         pci_read_config_byte(dev, mscreg, &msc_stat);
854         if ((bwsr_stat & bwsr_mask) == bwsr_mask)
855                 pci_write_config_byte(dev, mscreg, msc_stat|0x30);
856         return __ide_dma_end(drive);
857 }
858
859 /**
860  *      hpt3xxn_set_clock       -       perform clock switching dance
861  *      @hwif: hwif to switch
862  *      @mode: clocking mode (0x21 for write, 0x23 otherwise)
863  *
864  *      Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
865  *      NOTE: avoid touching the disabled primary channel on HPT371N -- it
866  *      doesn't physically exist anyway...
867  */
868
869 static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
870 {
871         u8 mcr1, scr2 = hwif->INB(hwif->dma_master + 0x7b);
872
873         if ((scr2 & 0x7f) == mode)
874                 return;
875
876         /* MISC. control register 1 has the channel enable bit... */
877         mcr1 = hwif->INB(hwif->dma_master + 0x70);
878
879         /* Tristate the bus */
880         if (mcr1 & 0x04)
881                 hwif->OUTB(0x80, hwif->dma_master + 0x73);
882         hwif->OUTB(0x80, hwif->dma_master + 0x77);
883
884         /* Switch clock and reset channels */
885         hwif->OUTB(mode, hwif->dma_master + 0x7b);
886         hwif->OUTB(0xc0, hwif->dma_master + 0x79);
887
888         /* Reset state machines */
889         if (mcr1 & 0x04)
890                 hwif->OUTB(0x37, hwif->dma_master + 0x70);
891         hwif->OUTB(0x37, hwif->dma_master + 0x74);
892
893         /* Complete reset */
894         hwif->OUTB(0x00, hwif->dma_master + 0x79);
895
896         /* Reconnect channels to bus */
897         if (mcr1 & 0x04)
898                 hwif->OUTB(0x00, hwif->dma_master + 0x73);
899         hwif->OUTB(0x00, hwif->dma_master + 0x77);
900 }
901
902 /**
903  *      hpt3xxn_rw_disk         -       prepare for I/O
904  *      @drive: drive for command
905  *      @rq: block request structure
906  *
907  *      This is called when a disk I/O is issued to HPT3xxN.
908  *      We need it because of the clock switching.
909  */
910
911 static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
912 {
913         ide_hwif_t *hwif        = HWIF(drive);
914         u8 wantclock            = rq_data_dir(rq) ? 0x23 : 0x21;
915
916         hpt3xxn_set_clock(hwif, wantclock);
917 }
918
919 /* 
920  * Set/get power state for a drive.
921  *
922  * When we turn the power back on, we need to re-initialize things.
923  */
924 #define TRISTATE_BIT  0x8000
925
926 static int hpt3xx_busproc(ide_drive_t *drive, int state)
927 {
928         ide_hwif_t *hwif        = drive->hwif;
929         struct pci_dev *dev     = hwif->pci_dev;
930         u8  tristate, resetmask, bus_reg = 0;
931         u16 tri_reg = 0;
932
933         hwif->bus_state = state;
934
935         if (hwif->channel) { 
936                 /* secondary channel */
937                 tristate  = 0x56;
938                 resetmask = 0x80;
939         } else { 
940                 /* primary channel */
941                 tristate  = 0x52;
942                 resetmask = 0x40;
943         }
944
945         /* Grab the status. */
946         pci_read_config_word(dev, tristate, &tri_reg);
947         pci_read_config_byte(dev, 0x59, &bus_reg);
948
949         /*
950          * Set the state. We don't set it if we don't need to do so.
951          * Make sure that the drive knows that it has failed if it's off.
952          */
953         switch (state) {
954         case BUSSTATE_ON:
955                 if (!(bus_reg & resetmask))
956                         return 0;
957                 hwif->drives[0].failures = hwif->drives[1].failures = 0;
958
959                 pci_write_config_byte(dev, 0x59, bus_reg & ~resetmask);
960                 pci_write_config_word(dev, tristate, tri_reg & ~TRISTATE_BIT);
961                 return 0;
962         case BUSSTATE_OFF:
963                 if ((bus_reg & resetmask) && !(tri_reg & TRISTATE_BIT))
964                         return 0;
965                 tri_reg &= ~TRISTATE_BIT;
966                 break;
967         case BUSSTATE_TRISTATE:
968                 if ((bus_reg & resetmask) &&  (tri_reg & TRISTATE_BIT))
969                         return 0;
970                 tri_reg |= TRISTATE_BIT;
971                 break;
972         default:
973                 return -EINVAL;
974         }
975
976         hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
977         hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
978
979         pci_write_config_word(dev, tristate, tri_reg);
980         pci_write_config_byte(dev, 0x59, bus_reg | resetmask);
981         return 0;
982 }
983
984 static void __devinit hpt366_clocking(ide_hwif_t *hwif)
985 {
986         u32 reg1        = 0;
987         struct hpt_info *info = ide_get_hwifdata(hwif);
988
989         pci_read_config_dword(hwif->pci_dev, 0x40, &reg1);
990
991         /* detect bus speed by looking at control reg timing: */
992         switch((reg1 >> 8) & 7) {
993                 case 5:
994                         info->speed = forty_base_hpt36x;
995                         break;
996                 case 9:
997                         info->speed = twenty_five_base_hpt36x;
998                         break;
999                 case 7:
1000                 default:
1001                         info->speed = thirty_three_base_hpt36x;
1002                         break;
1003         }
1004 }
1005
1006 static void __devinit hpt37x_clocking(ide_hwif_t *hwif)
1007 {
1008         struct hpt_info *info = ide_get_hwifdata(hwif);
1009         struct pci_dev *dev = hwif->pci_dev;
1010         int adjust, i;
1011         u16 freq;
1012         u32 pll;
1013         u8 reg5bh = 0, mcr1 = 0;
1014         
1015         /*
1016          * default to pci clock. make sure MA15/16 are set to output
1017          * to prevent drives having problems with 40-pin cables. Needed
1018          * for some drives such as IBM-DTLA which will not enter ready
1019          * state on reset when PDIAG is a input.
1020          *
1021          * ToDo: should we set 0x21 when using PLL mode ?
1022          */
1023         pci_write_config_byte(dev, 0x5b, 0x23);
1024
1025         /*
1026          * set up the PLL. we need to adjust it so that it's stable. 
1027          * freq = Tpll * 192 / Tpci
1028          *
1029          * Todo. For non x86 should probably check the dword is
1030          * set to 0xABCDExxx indicating the BIOS saved f_CNT
1031          */
1032         pci_read_config_word(dev, 0x78, &freq);
1033         freq &= 0x1FF;
1034         
1035         /*
1036          * HPT3xxN chips use different PCI clock information.
1037          * Currently we always set up the PLL for them.
1038          */
1039
1040         if (info->flags & IS_3xxN) {
1041                 if(freq < 0x55)
1042                         pll = F_LOW_PCI_33;
1043                 else if(freq < 0x70)
1044                         pll = F_LOW_PCI_40;
1045                 else if(freq < 0x7F)
1046                         pll = F_LOW_PCI_50;
1047                 else
1048                         pll = F_LOW_PCI_66;
1049
1050                 printk(KERN_INFO "HPT3xxN detected, FREQ: %d, PLL: %d\n", freq, pll);
1051         }
1052         else
1053         {
1054                 if(freq < 0x9C)
1055                         pll = F_LOW_PCI_33;
1056                 else if(freq < 0xb0)
1057                         pll = F_LOW_PCI_40;
1058                 else if(freq <0xc8)
1059                         pll = F_LOW_PCI_50;
1060                 else
1061                         pll = F_LOW_PCI_66;
1062         
1063                 if (pll == F_LOW_PCI_33) {
1064                         info->speed = thirty_three_base_hpt37x;
1065                         printk(KERN_DEBUG "HPT37X: using 33MHz PCI clock\n");
1066                 } else if (pll == F_LOW_PCI_40) {
1067                         /* Unsupported */
1068                 } else if (pll == F_LOW_PCI_50) {
1069                         info->speed = fifty_base_hpt37x;
1070                         printk(KERN_DEBUG "HPT37X: using 50MHz PCI clock\n");
1071                 } else {
1072                         info->speed = sixty_six_base_hpt37x;
1073                         printk(KERN_DEBUG "HPT37X: using 66MHz PCI clock\n");
1074                 }
1075         }
1076
1077         if (pll == F_LOW_PCI_66)
1078                 info->flags |= PCI_66MHZ;
1079
1080         /*
1081          * only try the pll if we don't have a table for the clock
1082          * speed that we're running at. NOTE: the internal PLL will
1083          * result in slow reads when using a 33MHz PCI clock. we also
1084          * don't like to use the PLL because it will cause glitches
1085          * on PRST/SRST when the HPT state engine gets reset.
1086          *
1087          * ToDo: Use 66MHz PLL when ATA133 devices are present on a
1088          * 372 device so we can get ATA133 support
1089          */
1090         if (info->speed)
1091                 goto init_hpt37X_done;
1092
1093         info->flags |= PLL_MODE;
1094         
1095         /*
1096          * FIXME: make this work correctly, esp with 372N as per
1097          * reference driver code.
1098          *
1099          * adjust PLL based upon PCI clock, enable it, and wait for
1100          * stabilization.
1101          */
1102         adjust = 0;
1103         freq = (pll < F_LOW_PCI_50) ? 2 : 4;
1104         while (adjust++ < 6) {
1105                 pci_write_config_dword(dev, 0x5c, (freq + pll) << 16 |
1106                                        pll | 0x100);
1107
1108                 /* wait for clock stabilization */
1109                 for (i = 0; i < 0x50000; i++) {
1110                         pci_read_config_byte(dev, 0x5b, &reg5bh);
1111                         if (reg5bh & 0x80) {
1112                                 /* spin looking for the clock to destabilize */
1113                                 for (i = 0; i < 0x1000; ++i) {
1114                                         pci_read_config_byte(dev, 0x5b, 
1115                                                              &reg5bh);
1116                                         if ((reg5bh & 0x80) == 0)
1117                                                 goto pll_recal;
1118                                 }
1119                                 pci_read_config_dword(dev, 0x5c, &pll);
1120                                 pci_write_config_dword(dev, 0x5c, 
1121                                                        pll & ~0x100);
1122                                 pci_write_config_byte(dev, 0x5b, 0x21);
1123
1124                                 info->speed = fifty_base_hpt37x;
1125                                 printk("HPT37X: using 50MHz internal PLL\n");
1126                                 goto init_hpt37X_done;
1127                         }
1128                 }
1129 pll_recal:
1130                 if (adjust & 1)
1131                         pll -= (adjust >> 1);
1132                 else
1133                         pll += (adjust >> 1);
1134         } 
1135
1136 init_hpt37X_done:
1137         if (!info->speed)
1138                 printk(KERN_ERR "HPT37x%s: unknown bus timing [%d %d].\n",
1139                        (info->flags & IS_3xxN) ? "N" : "", pll, freq);
1140         /*
1141          * Reset the state engines.
1142          * NOTE: avoid accidentally enabling the primary channel on HPT371N.
1143          */
1144         pci_read_config_byte(dev, 0x50, &mcr1);
1145         if (mcr1 & 0x04)
1146                 pci_write_config_byte(dev, 0x50, 0x37);
1147         pci_write_config_byte(dev, 0x54, 0x37);
1148         udelay(100);
1149 }
1150
1151 static int __devinit init_hpt37x(struct pci_dev *dev)
1152 {
1153         u8 reg5ah;
1154
1155         pci_read_config_byte(dev, 0x5a, &reg5ah);
1156         /* interrupt force enable */
1157         pci_write_config_byte(dev, 0x5a, (reg5ah & ~0x10));
1158         return 0;
1159 }
1160
1161 static int __devinit init_hpt366(struct pci_dev *dev)
1162 {
1163         u32 reg1        = 0;
1164         u8 drive_fast   = 0;
1165
1166         /*
1167          * Disable the "fast interrupt" prediction.
1168          */
1169         pci_read_config_byte(dev, 0x51, &drive_fast);
1170         if (drive_fast & 0x80)
1171                 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
1172         pci_read_config_dword(dev, 0x40, &reg1);
1173                                                                         
1174         return 0;
1175 }
1176
1177 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
1178 {
1179         int ret = 0;
1180
1181         /*
1182          * FIXME: Not portable. Also, why do we enable the ROM in the first place?
1183          * We don't seem to be using it.
1184          */
1185         if (dev->resource[PCI_ROM_RESOURCE].start)
1186                 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
1187                         dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1188
1189         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1190         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1191         pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1192         pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1193
1194         if (hpt_revision(dev) >= 3)
1195                 ret = init_hpt37x(dev);
1196         else
1197                 ret = init_hpt366(dev);
1198
1199         if (ret)
1200                 return ret;
1201
1202         return dev->irq;
1203 }
1204
1205 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1206 {
1207         struct pci_dev *dev             = hwif->pci_dev;
1208         struct hpt_info *info           = ide_get_hwifdata(hwif);
1209         u8 ata66 = 0, regmask           = (hwif->channel) ? 0x01 : 0x02;
1210         int serialize                   = HPT_SERIALIZE_IO;
1211         
1212         hwif->tuneproc                  = &hpt3xx_tune_drive;
1213         hwif->speedproc                 = &hpt3xx_tune_chipset;
1214         hwif->quirkproc                 = &hpt3xx_quirkproc;
1215         hwif->intrproc                  = &hpt3xx_intrproc;
1216         hwif->maskproc                  = &hpt3xx_maskproc;
1217         
1218         /*
1219          * HPT3xxN chips have some complications:
1220          *
1221          * - on 33 MHz PCI we must clock switch
1222          * - on 66 MHz PCI we must NOT use the PCI clock
1223          */
1224         if ((info->flags & (IS_3xxN | PCI_66MHZ)) == IS_3xxN) {
1225                 /*
1226                  * Clock is shared between the channels,
1227                  * so we'll have to serialize them... :-(
1228                  */
1229                 serialize = 1;
1230                 hwif->rw_disk = &hpt3xxn_rw_disk;
1231         }
1232
1233         /*
1234          * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1235          * address lines to access an external eeprom.  To read valid
1236          * cable detect state the pins must be enabled as inputs.
1237          */
1238         if (info->revision >= 8 && (PCI_FUNC(dev->devfn) & 1)) {
1239                 /*
1240                  * HPT374 PCI function 1
1241                  * - set bit 15 of reg 0x52 to enable TCBLID as input
1242                  * - set bit 15 of reg 0x56 to enable FCBLID as input
1243                  */
1244                 u16 mcr3, mcr6;
1245                 pci_read_config_word(dev, 0x52, &mcr3);
1246                 pci_read_config_word(dev, 0x56, &mcr6);
1247                 pci_write_config_word(dev, 0x52, mcr3 | 0x8000);
1248                 pci_write_config_word(dev, 0x56, mcr6 | 0x8000);
1249                 /* now read cable id register */
1250                 pci_read_config_byte(dev, 0x5a, &ata66);
1251                 pci_write_config_word(dev, 0x52, mcr3);
1252                 pci_write_config_word(dev, 0x56, mcr6);
1253         } else if (info->revision >= 3) {
1254                 /*
1255                  * HPT370/372 and 374 pcifn 0
1256                  * - clear bit 0 of 0x5b to enable P/SCBLID as inputs
1257                  */
1258                 u8 scr2;
1259                 pci_read_config_byte(dev, 0x5b, &scr2);
1260                 pci_write_config_byte(dev, 0x5b, scr2 & ~1);
1261                 /* now read cable id register */
1262                 pci_read_config_byte(dev, 0x5a, &ata66);
1263                 pci_write_config_byte(dev, 0x5b, scr2);
1264         } else {
1265                 pci_read_config_byte(dev, 0x5a, &ata66);
1266         }
1267
1268 #ifdef DEBUG
1269         printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n",
1270                 ata66, (ata66 & regmask) ? "33" : "66",
1271                 PCI_FUNC(hwif->pci_dev->devfn));
1272 #endif /* DEBUG */
1273
1274         /* Serialize access to this device */
1275         if (serialize && hwif->mate)
1276                 hwif->serialized = hwif->mate->serialized = 1;
1277
1278         /*
1279          * Set up ioctl for power status.
1280          * NOTE:  power affects both drives on each channel.
1281          */
1282         hwif->busproc = &hpt3xx_busproc;
1283
1284         if (!hwif->dma_base) {
1285                 hwif->drives[0].autotune = 1;
1286                 hwif->drives[1].autotune = 1;
1287                 return;
1288         }
1289
1290         hwif->ultra_mask = 0x7f;
1291         hwif->mwdma_mask = 0x07;
1292
1293         if (!(hwif->udma_four))
1294                 hwif->udma_four = ((ata66 & regmask) ? 0 : 1);
1295         hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1296
1297         if (info->revision >= 8) {
1298                 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1299                 hwif->ide_dma_end = &hpt374_ide_dma_end;
1300         } else if (info->revision >= 5) {
1301                 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1302                 hwif->ide_dma_end = &hpt374_ide_dma_end;
1303         } else if (info->revision >= 3) {
1304                 hwif->dma_start = &hpt370_ide_dma_start;
1305                 hwif->ide_dma_end = &hpt370_ide_dma_end;
1306                 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
1307                 hwif->ide_dma_lostirq = &hpt370_ide_dma_lostirq;
1308         } else if (info->revision >= 2)
1309                 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1310         else
1311                 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1312
1313         if (!noautodma)
1314                 hwif->autodma = 1;
1315         hwif->drives[0].autodma = hwif->autodma;
1316         hwif->drives[1].autodma = hwif->autodma;
1317 }
1318
1319 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1320 {
1321         struct hpt_info *info   = ide_get_hwifdata(hwif);
1322         u8 masterdma    = 0, slavedma = 0;
1323         u8 dma_new      = 0, dma_old = 0;
1324         u8 primary      = hwif->channel ? 0x4b : 0x43;
1325         u8 secondary    = hwif->channel ? 0x4f : 0x47;
1326         unsigned long flags;
1327
1328         if (!dmabase)
1329                 return;
1330                 
1331         if(info->speed == NULL) {
1332                 printk(KERN_WARNING "hpt366: no known IDE timings, disabling DMA.\n");
1333                 return;
1334         }
1335
1336         dma_old = hwif->INB(dmabase+2);
1337
1338         local_irq_save(flags);
1339
1340         dma_new = dma_old;
1341         pci_read_config_byte(hwif->pci_dev, primary, &masterdma);
1342         pci_read_config_byte(hwif->pci_dev, secondary, &slavedma);
1343
1344         if (masterdma & 0x30)   dma_new |= 0x20;
1345         if (slavedma & 0x30)    dma_new |= 0x40;
1346         if (dma_new != dma_old)
1347                 hwif->OUTB(dma_new, dmabase+2);
1348
1349         local_irq_restore(flags);
1350
1351         ide_setup_dma(hwif, dmabase, 8);
1352 }
1353
1354 /*
1355  *      We "borrow" this hook in order to set the data structures
1356  *      up early enough before dma or init_hwif calls are made.
1357  */
1358
1359 static void __devinit init_iops_hpt366(ide_hwif_t *hwif)
1360 {
1361         struct hpt_info *info   = kzalloc(sizeof(struct hpt_info), GFP_KERNEL);
1362         struct pci_dev  *dev    = hwif->pci_dev;
1363         u16 did                 = dev->device;
1364         u8  rid                 = 0;
1365
1366         if(info == NULL) {
1367                 printk(KERN_WARNING "hpt366: out of memory.\n");
1368                 return;
1369         }
1370         ide_set_hwifdata(hwif, info);
1371
1372         /* Avoid doing the same thing twice. */
1373         if (hwif->channel && hwif->mate) {
1374                 memcpy(info, ide_get_hwifdata(hwif->mate), sizeof(struct hpt_info));
1375                 return;
1376         }
1377
1378         pci_read_config_byte(dev, PCI_CLASS_REVISION, &rid);
1379
1380         if (( did == PCI_DEVICE_ID_TTI_HPT366  && rid == 6) ||
1381             ((did == PCI_DEVICE_ID_TTI_HPT372  ||
1382               did == PCI_DEVICE_ID_TTI_HPT302  ||
1383               did == PCI_DEVICE_ID_TTI_HPT371) && rid > 1) ||
1384               did == PCI_DEVICE_ID_TTI_HPT372N)
1385                 info->flags |= IS_3xxN;
1386
1387         info->revision = hpt_revision(dev);
1388
1389         if (info->revision >= 3)
1390                 hpt37x_clocking(hwif);
1391         else
1392                 hpt366_clocking(hwif);
1393 }
1394
1395 static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1396 {
1397         struct pci_dev *findev = NULL;
1398
1399         if (PCI_FUNC(dev->devfn) & 1)
1400                 return -ENODEV;
1401
1402         while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1403                 if ((findev->vendor == dev->vendor) &&
1404                     (findev->device == dev->device) &&
1405                     ((findev->devfn - dev->devfn) == 1) &&
1406                     (PCI_FUNC(findev->devfn) & 1)) {
1407                         if (findev->irq != dev->irq) {
1408                                 /* FIXME: we need a core pci_set_interrupt() */
1409                                 findev->irq = dev->irq;
1410                                 printk(KERN_WARNING "%s: pci-config space interrupt "
1411                                         "fixed.\n", d->name);
1412                         }
1413                         return ide_setup_pci_devices(dev, findev, d);
1414                 }
1415         }
1416         return ide_setup_pci_device(dev, d);
1417 }
1418
1419 static int __devinit init_setup_hpt37x(struct pci_dev *dev, ide_pci_device_t *d)
1420 {
1421         return ide_setup_pci_device(dev, d);
1422 }
1423
1424 static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
1425 {
1426         u8 mcr1 = 0;
1427
1428         /*
1429          * HPT371 chips physically have only one channel, the secondary one,
1430          * but the primary channel registers do exist!  Go figure...
1431          * So,  we manually disable the non-existing channel here
1432          * (if the BIOS hasn't done this already).
1433          */
1434         pci_read_config_byte(dev, 0x50, &mcr1);
1435         if (mcr1 & 0x04)
1436                 pci_write_config_byte(dev, 0x50, (mcr1 & ~0x04));
1437
1438         return ide_setup_pci_device(dev, d);
1439 }
1440
1441 static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1442 {
1443         struct pci_dev *findev = NULL;
1444         u8 pin1 = 0, pin2 = 0;
1445         unsigned int class_rev;
1446         char *chipset_names[] = {"HPT366", "HPT366",  "HPT368",
1447                                  "HPT370", "HPT370A", "HPT372",
1448                                  "HPT372N" };
1449
1450         if (PCI_FUNC(dev->devfn) & 1)
1451                 return -ENODEV;
1452
1453         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1454         class_rev &= 0xff;
1455
1456         if(dev->device == PCI_DEVICE_ID_TTI_HPT372N)
1457                 class_rev = 6;
1458                 
1459         if(class_rev <= 6)
1460                 d->name = chipset_names[class_rev];
1461
1462         switch(class_rev) {
1463                 case 6:
1464                 case 5:
1465                 case 4:
1466                 case 3:
1467                         goto init_single;
1468                 default:
1469                         break;
1470         }
1471
1472         d->channels = 1;
1473
1474         pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1475         while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1476                 if ((findev->vendor == dev->vendor) &&
1477                     (findev->device == dev->device) &&
1478                     ((findev->devfn - dev->devfn) == 1) &&
1479                     (PCI_FUNC(findev->devfn) & 1)) {
1480                         pci_read_config_byte(findev, PCI_INTERRUPT_PIN, &pin2);
1481                         if ((pin1 != pin2) && (dev->irq == findev->irq)) {
1482                                 d->bootable = ON_BOARD;
1483                                 printk("%s: onboard version of chipset, "
1484                                         "pin1=%d pin2=%d\n", d->name,
1485                                         pin1, pin2);
1486                         }
1487                         return ide_setup_pci_devices(dev, findev, d);
1488                 }
1489         }
1490 init_single:
1491         return ide_setup_pci_device(dev, d);
1492 }
1493
1494 static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1495         {       /* 0 */
1496                 .name           = "HPT366",
1497                 .init_setup     = init_setup_hpt366,
1498                 .init_chipset   = init_chipset_hpt366,
1499                 .init_iops      = init_iops_hpt366,
1500                 .init_hwif      = init_hwif_hpt366,
1501                 .init_dma       = init_dma_hpt366,
1502                 .channels       = 2,
1503                 .autodma        = AUTODMA,
1504                 .bootable       = OFF_BOARD,
1505                 .extra          = 240
1506         },{     /* 1 */
1507                 .name           = "HPT372A",
1508                 .init_setup     = init_setup_hpt37x,
1509                 .init_chipset   = init_chipset_hpt366,
1510                 .init_iops      = init_iops_hpt366,
1511                 .init_hwif      = init_hwif_hpt366,
1512                 .init_dma       = init_dma_hpt366,
1513                 .channels       = 2,
1514                 .autodma        = AUTODMA,
1515                 .bootable       = OFF_BOARD,
1516         },{     /* 2 */
1517                 .name           = "HPT302",
1518                 .init_setup     = init_setup_hpt37x,
1519                 .init_chipset   = init_chipset_hpt366,
1520                 .init_iops      = init_iops_hpt366,
1521                 .init_hwif      = init_hwif_hpt366,
1522                 .init_dma       = init_dma_hpt366,
1523                 .channels       = 2,
1524                 .autodma        = AUTODMA,
1525                 .bootable       = OFF_BOARD,
1526         },{     /* 3 */
1527                 .name           = "HPT371",
1528                 .init_setup     = init_setup_hpt371,
1529                 .init_chipset   = init_chipset_hpt366,
1530                 .init_iops      = init_iops_hpt366,
1531                 .init_hwif      = init_hwif_hpt366,
1532                 .init_dma       = init_dma_hpt366,
1533                 .channels       = 2,
1534                 .autodma        = AUTODMA,
1535                 .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1536                 .bootable       = OFF_BOARD,
1537         },{     /* 4 */
1538                 .name           = "HPT374",
1539                 .init_setup     = init_setup_hpt374,
1540                 .init_chipset   = init_chipset_hpt366,
1541                 .init_iops      = init_iops_hpt366,
1542                 .init_hwif      = init_hwif_hpt366,
1543                 .init_dma       = init_dma_hpt366,
1544                 .channels       = 2,    /* 4 */
1545                 .autodma        = AUTODMA,
1546                 .bootable       = OFF_BOARD,
1547         },{     /* 5 */
1548                 .name           = "HPT372N",
1549                 .init_setup     = init_setup_hpt37x,
1550                 .init_chipset   = init_chipset_hpt366,
1551                 .init_iops      = init_iops_hpt366,
1552                 .init_hwif      = init_hwif_hpt366,
1553                 .init_dma       = init_dma_hpt366,
1554                 .channels       = 2,    /* 4 */
1555                 .autodma        = AUTODMA,
1556                 .bootable       = OFF_BOARD,
1557         }
1558 };
1559
1560 /**
1561  *      hpt366_init_one -       called when an HPT366 is found
1562  *      @dev: the hpt366 device
1563  *      @id: the matching pci id
1564  *
1565  *      Called when the PCI registration layer (or the IDE initialization)
1566  *      finds a device matching our IDE device tables.
1567  */
1568  
1569 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1570 {
1571         ide_pci_device_t *d = &hpt366_chipsets[id->driver_data];
1572
1573         return d->init_setup(dev, d);
1574 }
1575
1576 static struct pci_device_id hpt366_pci_tbl[] = {
1577         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1578         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1579         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1580         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1581         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1582         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1583         { 0, },
1584 };
1585 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1586
1587 static struct pci_driver driver = {
1588         .name           = "HPT366_IDE",
1589         .id_table       = hpt366_pci_tbl,
1590         .probe          = hpt366_init_one,
1591 };
1592
1593 static int hpt366_ide_init(void)
1594 {
1595         return ide_pci_register_driver(&driver);
1596 }
1597
1598 module_init(hpt366_ide_init);
1599
1600 MODULE_AUTHOR("Andre Hedrick");
1601 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1602 MODULE_LICENSE("GPL");