ide: add ide_use_fast_pio() helper (v3)
[linux-2.6.git] / drivers / ide / pci / aec62xx.c
1 /*
2  * linux/drivers/ide/pci/aec62xx.c              Version 0.11    March 27, 2002
3  *
4  * Copyright (C) 1999-2002      Andre Hedrick <andre@linux-ide.org>
5  *
6  */
7
8 #include <linux/module.h>
9 #include <linux/types.h>
10 #include <linux/pci.h>
11 #include <linux/delay.h>
12 #include <linux/hdreg.h>
13 #include <linux/ide.h>
14 #include <linux/init.h>
15
16 #include <asm/io.h>
17
18 struct chipset_bus_clock_list_entry {
19         u8 xfer_speed;
20         u8 chipset_settings;
21         u8 ultra_settings;
22 };
23
24 static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
25         {       XFER_UDMA_6,    0x31,   0x07    },
26         {       XFER_UDMA_5,    0x31,   0x06    },
27         {       XFER_UDMA_4,    0x31,   0x05    },
28         {       XFER_UDMA_3,    0x31,   0x04    },
29         {       XFER_UDMA_2,    0x31,   0x03    },
30         {       XFER_UDMA_1,    0x31,   0x02    },
31         {       XFER_UDMA_0,    0x31,   0x01    },
32
33         {       XFER_MW_DMA_2,  0x31,   0x00    },
34         {       XFER_MW_DMA_1,  0x31,   0x00    },
35         {       XFER_MW_DMA_0,  0x0a,   0x00    },
36         {       XFER_PIO_4,     0x31,   0x00    },
37         {       XFER_PIO_3,     0x33,   0x00    },
38         {       XFER_PIO_2,     0x08,   0x00    },
39         {       XFER_PIO_1,     0x0a,   0x00    },
40         {       XFER_PIO_0,     0x00,   0x00    },
41         {       0,              0x00,   0x00    }
42 };
43
44 static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
45         {       XFER_UDMA_6,    0x41,   0x06    },
46         {       XFER_UDMA_5,    0x41,   0x05    },
47         {       XFER_UDMA_4,    0x41,   0x04    },
48         {       XFER_UDMA_3,    0x41,   0x03    },
49         {       XFER_UDMA_2,    0x41,   0x02    },
50         {       XFER_UDMA_1,    0x41,   0x01    },
51         {       XFER_UDMA_0,    0x41,   0x01    },
52
53         {       XFER_MW_DMA_2,  0x41,   0x00    },
54         {       XFER_MW_DMA_1,  0x42,   0x00    },
55         {       XFER_MW_DMA_0,  0x7a,   0x00    },
56         {       XFER_PIO_4,     0x41,   0x00    },
57         {       XFER_PIO_3,     0x43,   0x00    },
58         {       XFER_PIO_2,     0x78,   0x00    },
59         {       XFER_PIO_1,     0x7a,   0x00    },
60         {       XFER_PIO_0,     0x70,   0x00    },
61         {       0,              0x00,   0x00    }
62 };
63
64 #define BUSCLOCK(D)     \
65         ((struct chipset_bus_clock_list_entry *) pci_get_drvdata((D)))
66
67
68 /*
69  * TO DO: active tuning and correction of cards without a bios.
70  */
71 static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
72 {
73         for ( ; chipset_table->xfer_speed ; chipset_table++)
74                 if (chipset_table->xfer_speed == speed) {
75                         return chipset_table->chipset_settings;
76                 }
77         return chipset_table->chipset_settings;
78 }
79
80 static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
81 {
82         for ( ; chipset_table->xfer_speed ; chipset_table++)
83                 if (chipset_table->xfer_speed == speed) {
84                         return chipset_table->ultra_settings;
85                 }
86         return chipset_table->ultra_settings;
87 }
88
89 static u8 aec62xx_ratemask (ide_drive_t *drive)
90 {
91         ide_hwif_t *hwif        = HWIF(drive);
92         u8 mode;
93
94         switch(hwif->pci_dev->device) {
95                 case PCI_DEVICE_ID_ARTOP_ATP865:
96                 case PCI_DEVICE_ID_ARTOP_ATP865R:
97                         mode = (hwif->INB(((hwif->channel) ?
98                                         hwif->mate->dma_status :
99                                         hwif->dma_status)) & 0x10) ? 4 : 3;
100                         break;
101                 case PCI_DEVICE_ID_ARTOP_ATP860:
102                 case PCI_DEVICE_ID_ARTOP_ATP860R:
103                         mode = 2;
104                         break;
105                 case PCI_DEVICE_ID_ARTOP_ATP850UF:
106                 default:
107                         return 1;
108         }
109
110         if (!eighty_ninty_three(drive))
111                 mode = min(mode, (u8)1);
112         return mode;
113 }
114
115 static int aec6210_tune_chipset (ide_drive_t *drive, u8 xferspeed)
116 {
117         ide_hwif_t *hwif        = HWIF(drive);
118         struct pci_dev *dev     = hwif->pci_dev;
119         u16 d_conf              = 0;
120         u8 speed        = ide_rate_filter(aec62xx_ratemask(drive), xferspeed);
121         u8 ultra = 0, ultra_conf = 0;
122         u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
123         unsigned long flags;
124
125         local_irq_save(flags);
126         /* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */
127         pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
128         tmp0 = pci_bus_clock_list(speed, BUSCLOCK(dev));
129         d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf);
130         pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);
131
132         tmp1 = 0x00;
133         tmp2 = 0x00;
134         pci_read_config_byte(dev, 0x54, &ultra);
135         tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn))));
136         ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
137         tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn))));
138         pci_write_config_byte(dev, 0x54, tmp2);
139         local_irq_restore(flags);
140         return(ide_config_drive_speed(drive, speed));
141 }
142
143 static int aec6260_tune_chipset (ide_drive_t *drive, u8 xferspeed)
144 {
145         ide_hwif_t *hwif        = HWIF(drive);
146         struct pci_dev *dev     = hwif->pci_dev;
147         u8 speed        = ide_rate_filter(aec62xx_ratemask(drive), xferspeed);
148         u8 unit         = (drive->select.b.unit & 0x01);
149         u8 tmp1 = 0, tmp2 = 0;
150         u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
151         unsigned long flags;
152
153         local_irq_save(flags);
154         /* high 4-bits: Active, low 4-bits: Recovery */
155         pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf);
156         drive_conf = pci_bus_clock_list(speed, BUSCLOCK(dev));
157         pci_write_config_byte(dev, 0x40|drive->dn, drive_conf);
158
159         pci_read_config_byte(dev, (0x44|hwif->channel), &ultra);
160         tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit))));
161         ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
162         tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit))));
163         pci_write_config_byte(dev, (0x44|hwif->channel), tmp2);
164         local_irq_restore(flags);
165         return(ide_config_drive_speed(drive, speed));
166 }
167
168 static int aec62xx_tune_chipset (ide_drive_t *drive, u8 speed)
169 {
170         switch (HWIF(drive)->pci_dev->device) {
171                 case PCI_DEVICE_ID_ARTOP_ATP865:
172                 case PCI_DEVICE_ID_ARTOP_ATP865R:
173                 case PCI_DEVICE_ID_ARTOP_ATP860:
174                 case PCI_DEVICE_ID_ARTOP_ATP860R:
175                         return ((int) aec6260_tune_chipset(drive, speed));
176                 case PCI_DEVICE_ID_ARTOP_ATP850UF:
177                         return ((int) aec6210_tune_chipset(drive, speed));
178                 default:
179                         return -1;
180         }
181 }
182
183 static int config_chipset_for_dma (ide_drive_t *drive)
184 {
185         u8 speed = ide_dma_speed(drive, aec62xx_ratemask(drive));       
186
187         if (!(speed))
188                 return 0;
189
190         (void) aec62xx_tune_chipset(drive, speed);
191         return ide_dma_enable(drive);
192 }
193
194 static void aec62xx_tune_drive (ide_drive_t *drive, u8 pio)
195 {
196         u8 speed = 0;
197         u8 new_pio = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
198
199         switch(pio) {
200                 case 5:         speed = new_pio; break;
201                 case 4:         speed = XFER_PIO_4; break;
202                 case 3:         speed = XFER_PIO_3; break;
203                 case 2:         speed = XFER_PIO_2; break;
204                 case 1:         speed = XFER_PIO_1; break;
205                 default:        speed = XFER_PIO_0; break;
206         }
207         (void) aec62xx_tune_chipset(drive, speed);
208 }
209
210 static int aec62xx_config_drive_xfer_rate (ide_drive_t *drive)
211 {
212         ide_hwif_t *hwif        = HWIF(drive);
213
214         if (ide_use_dma(drive) && config_chipset_for_dma(drive))
215                 return hwif->ide_dma_on(drive);
216
217         if (ide_use_fast_pio(drive)) {
218                 aec62xx_tune_drive(drive, 5);
219                 return hwif->ide_dma_off_quietly(drive);
220         }
221         /* IORDY not supported */
222         return 0;
223 }
224
225 static int aec62xx_irq_timeout (ide_drive_t *drive)
226 {
227         ide_hwif_t *hwif        = HWIF(drive);
228         struct pci_dev *dev     = hwif->pci_dev;
229
230         switch(dev->device) {
231                 case PCI_DEVICE_ID_ARTOP_ATP860:
232                 case PCI_DEVICE_ID_ARTOP_ATP860R:
233                 case PCI_DEVICE_ID_ARTOP_ATP865:
234                 case PCI_DEVICE_ID_ARTOP_ATP865R:
235                         printk(" AEC62XX time out ");
236                 default:
237                         break;
238         }
239         return 0;
240 }
241
242 static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const char *name)
243 {
244         int bus_speed = system_bus_clock();
245
246         if (dev->resource[PCI_ROM_RESOURCE].start) {
247                 pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
248                 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
249                         (unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
250         }
251
252         if (bus_speed <= 33)
253                 pci_set_drvdata(dev, (void *) aec6xxx_33_base);
254         else
255                 pci_set_drvdata(dev, (void *) aec6xxx_34_base);
256
257         /* These are necessary to get AEC6280 Macintosh cards to work */
258         if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) ||
259             (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) {
260                 u8 reg49h = 0, reg4ah = 0;
261                 /* Clear reset and test bits.  */
262                 pci_read_config_byte(dev, 0x49, &reg49h);
263                 pci_write_config_byte(dev, 0x49, reg49h & ~0x30);
264                 /* Enable chip interrupt output.  */
265                 pci_read_config_byte(dev, 0x4a, &reg4ah);
266                 pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01);
267                 /* Enable burst mode. */
268                 pci_read_config_byte(dev, 0x4a, &reg4ah);
269                 pci_write_config_byte(dev, 0x4a, reg4ah | 0x80);
270         }
271
272         return dev->irq;
273 }
274
275 static void __devinit init_hwif_aec62xx(ide_hwif_t *hwif)
276 {
277         hwif->autodma = 0;
278         hwif->tuneproc = &aec62xx_tune_drive;
279         hwif->speedproc = &aec62xx_tune_chipset;
280
281         if (hwif->pci_dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF)
282                 hwif->serialized = hwif->channel;
283
284         if (hwif->mate)
285                 hwif->mate->serialized = hwif->serialized;
286
287         if (!hwif->dma_base) {
288                 hwif->drives[0].autotune = 1;
289                 hwif->drives[1].autotune = 1;
290                 return;
291         }
292
293         hwif->ultra_mask = 0x7f;
294         hwif->mwdma_mask = 0x07;
295         hwif->swdma_mask = 0x07;
296
297         hwif->ide_dma_check     = &aec62xx_config_drive_xfer_rate;
298         hwif->ide_dma_lostirq   = &aec62xx_irq_timeout;
299         hwif->ide_dma_timeout   = &aec62xx_irq_timeout;
300         if (!noautodma)
301                 hwif->autodma = 1;
302         hwif->drives[0].autodma = hwif->autodma;
303         hwif->drives[1].autodma = hwif->autodma;
304 }
305
306 static void __devinit init_dma_aec62xx(ide_hwif_t *hwif, unsigned long dmabase)
307 {
308         struct pci_dev *dev     = hwif->pci_dev;
309
310         if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
311                 u8 reg54h = 0;
312                 unsigned long flags;
313
314                 spin_lock_irqsave(&ide_lock, flags);
315                 pci_read_config_byte(dev, 0x54, &reg54h);
316                 pci_write_config_byte(dev, 0x54, reg54h & ~(hwif->channel ? 0xF0 : 0x0F));
317                 spin_unlock_irqrestore(&ide_lock, flags);
318         } else {
319                 u8 ata66        = 0;
320                 pci_read_config_byte(hwif->pci_dev, 0x49, &ata66);
321                 if (!(hwif->udma_four))
322                         hwif->udma_four = (ata66&(hwif->channel?0x02:0x01))?0:1;
323         }
324
325         ide_setup_dma(hwif, dmabase, 8);
326 }
327
328 static int __devinit init_setup_aec62xx(struct pci_dev *dev, ide_pci_device_t *d)
329 {
330         return ide_setup_pci_device(dev, d);
331 }
332
333 static int __devinit init_setup_aec6x80(struct pci_dev *dev, ide_pci_device_t *d)
334 {
335         unsigned long bar4reg = pci_resource_start(dev, 4);
336
337         if (inb(bar4reg+2) & 0x10) {
338                 strcpy(d->name, "AEC6880");
339                 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)
340                         strcpy(d->name, "AEC6880R");
341         } else {
342                 strcpy(d->name, "AEC6280");
343                 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)
344                         strcpy(d->name, "AEC6280R");
345         }
346
347         return ide_setup_pci_device(dev, d);
348 }
349
350 static ide_pci_device_t aec62xx_chipsets[] __devinitdata = {
351         {       /* 0 */
352                 .name           = "AEC6210",
353                 .init_setup     = init_setup_aec62xx,
354                 .init_chipset   = init_chipset_aec62xx,
355                 .init_hwif      = init_hwif_aec62xx,
356                 .init_dma       = init_dma_aec62xx,
357                 .channels       = 2,
358                 .autodma        = AUTODMA,
359                 .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
360                 .bootable       = OFF_BOARD,
361         },{     /* 1 */
362                 .name           = "AEC6260",
363                 .init_setup     = init_setup_aec62xx,
364                 .init_chipset   = init_chipset_aec62xx,
365                 .init_hwif      = init_hwif_aec62xx,
366                 .init_dma       = init_dma_aec62xx,
367                 .channels       = 2,
368                 .autodma        = NOAUTODMA,
369                 .bootable       = OFF_BOARD,
370         },{     /* 2 */
371                 .name           = "AEC6260R",
372                 .init_setup     = init_setup_aec62xx,
373                 .init_chipset   = init_chipset_aec62xx,
374                 .init_hwif      = init_hwif_aec62xx,
375                 .init_dma       = init_dma_aec62xx,
376                 .channels       = 2,
377                 .autodma        = AUTODMA,
378                 .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
379                 .bootable       = NEVER_BOARD,
380         },{     /* 3 */
381                 .name           = "AEC6X80",
382                 .init_setup     = init_setup_aec6x80,
383                 .init_chipset   = init_chipset_aec62xx,
384                 .init_hwif      = init_hwif_aec62xx,
385                 .init_dma       = init_dma_aec62xx,
386                 .channels       = 2,
387                 .autodma        = AUTODMA,
388                 .bootable       = OFF_BOARD,
389         },{     /* 4 */
390                 .name           = "AEC6X80R",
391                 .init_setup     = init_setup_aec6x80,
392                 .init_chipset   = init_chipset_aec62xx,
393                 .init_hwif      = init_hwif_aec62xx,
394                 .init_dma       = init_dma_aec62xx,
395                 .channels       = 2,
396                 .autodma        = AUTODMA,
397                 .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
398                 .bootable       = OFF_BOARD,
399         }
400 };
401
402 /**
403  *      aec62xx_init_one        -       called when a AEC is found
404  *      @dev: the aec62xx device
405  *      @id: the matching pci id
406  *
407  *      Called when the PCI registration layer (or the IDE initialization)
408  *      finds a device matching our IDE device tables.
409  */
410  
411 static int __devinit aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
412 {
413         ide_pci_device_t *d = &aec62xx_chipsets[id->driver_data];
414
415         return d->init_setup(dev, d);
416 }
417
418 static struct pci_device_id aec62xx_pci_tbl[] = {
419         { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
420         { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860,   PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
421         { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R,  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
422         { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865,   PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
423         { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R,  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
424         { 0, },
425 };
426 MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);
427
428 static struct pci_driver driver = {
429         .name           = "AEC62xx_IDE",
430         .id_table       = aec62xx_pci_tbl,
431         .probe          = aec62xx_init_one,
432 };
433
434 static int __init aec62xx_ide_init(void)
435 {
436         return ide_pci_register_driver(&driver);
437 }
438
439 module_init(aec62xx_ide_init);
440
441 MODULE_AUTHOR("Andre Hedrick");
442 MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
443 MODULE_LICENSE("GPL");