c319f61631276c289549a9fbb38014e521010772
[linux-2.6.git] / drivers / ide / mips / au1xxx-ide.c
1 /*
2  * linux/drivers/ide/mips/au1xxx-ide.c  version 01.30.00        Aug. 02 2005
3  *
4  * BRIEF MODULE DESCRIPTION
5  * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
6  *
7  * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
8  *
9  * This program is free software; you can redistribute it and/or modify it under
10  * the terms of the GNU General Public License as published by the Free Software
11  * Foundation; either version 2 of the License, or (at your option) any later
12  * version.
13  *
14  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
15  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
16  * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
17  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
18  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
19  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
20  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
21  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
22  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
23  * POSSIBILITY OF SUCH DAMAGE.
24  *
25  * You should have received a copy of the GNU General Public License along with
26  * this program; if not, write to the Free Software Foundation, Inc.,
27  * 675 Mass Ave, Cambridge, MA 02139, USA.
28  *
29  * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
30  *       Interface and Linux Device Driver" Application Note.
31  */
32 #include <linux/types.h>
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/delay.h>
36 #include <linux/platform_device.h>
37
38 #include <linux/init.h>
39 #include <linux/ide.h>
40 #include <linux/sysdev.h>
41
42 #include <linux/dma-mapping.h>
43
44 #include "ide-timing.h"
45
46 #include <asm/io.h>
47 #include <asm/mach-au1x00/au1xxx.h>
48 #include <asm/mach-au1x00/au1xxx_dbdma.h>
49
50 #include <asm/mach-au1x00/au1xxx_ide.h>
51
52 #define DRV_NAME        "au1200-ide"
53 #define DRV_VERSION     "1.0"
54 #define DRV_AUTHOR      "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>"
55
56 /* enable the burstmode in the dbdma */
57 #define IDE_AU1XXX_BURSTMODE    1
58
59 static _auide_hwif auide_hwif;
60 static int dbdma_init_done;
61
62 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
63
64 void auide_insw(unsigned long port, void *addr, u32 count)
65 {
66         _auide_hwif *ahwif = &auide_hwif;
67         chan_tab_t *ctp;
68         au1x_ddma_desc_t *dp;
69
70         if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1, 
71                            DDMA_FLAGS_NOIE)) {
72                 printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
73                 return;
74         }
75         ctp = *((chan_tab_t **)ahwif->rx_chan);
76         dp = ctp->cur_ptr;
77         while (dp->dscr_cmd0 & DSCR_CMD0_V)
78                 ;
79         ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
80 }
81
82 void auide_outsw(unsigned long port, void *addr, u32 count)
83 {
84         _auide_hwif *ahwif = &auide_hwif;
85         chan_tab_t *ctp;
86         au1x_ddma_desc_t *dp;
87
88         if(!put_source_flags(ahwif->tx_chan, (void*)addr,
89                              count << 1, DDMA_FLAGS_NOIE)) {
90                 printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
91                 return;
92         }
93         ctp = *((chan_tab_t **)ahwif->tx_chan);
94         dp = ctp->cur_ptr;
95         while (dp->dscr_cmd0 & DSCR_CMD0_V)
96                 ;
97         ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
98 }
99
100 #endif
101
102 static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio)
103 {
104         int mem_sttime;
105         int mem_stcfg;
106
107         if (ide_config_drive_speed(drive, pio + XFER_PIO_0))
108                 return;
109
110         mem_sttime = 0;
111         mem_stcfg  = au_readl(MEM_STCFG2);
112
113         /* set pio mode! */
114         switch(pio) {
115         case 0:
116                 mem_sttime = SBC_IDE_TIMING(PIO0);
117
118                 /* set configuration for RCS2# */
119                 mem_stcfg |= TS_MASK;
120                 mem_stcfg &= ~TCSOE_MASK;
121                 mem_stcfg &= ~TOECS_MASK;
122                 mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS;
123                 break;
124
125         case 1:
126                 mem_sttime = SBC_IDE_TIMING(PIO1);
127
128                 /* set configuration for RCS2# */
129                 mem_stcfg |= TS_MASK;
130                 mem_stcfg &= ~TCSOE_MASK;
131                 mem_stcfg &= ~TOECS_MASK;
132                 mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS;
133                 break;
134
135         case 2:
136                 mem_sttime = SBC_IDE_TIMING(PIO2);
137
138                 /* set configuration for RCS2# */
139                 mem_stcfg &= ~TS_MASK;
140                 mem_stcfg &= ~TCSOE_MASK;
141                 mem_stcfg &= ~TOECS_MASK;
142                 mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS;
143                 break;
144
145         case 3:
146                 mem_sttime = SBC_IDE_TIMING(PIO3);
147
148                 /* set configuration for RCS2# */
149                 mem_stcfg &= ~TS_MASK;
150                 mem_stcfg &= ~TCSOE_MASK;
151                 mem_stcfg &= ~TOECS_MASK;
152                 mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS;
153
154                 break;
155
156         case 4:
157                 mem_sttime = SBC_IDE_TIMING(PIO4);
158
159                 /* set configuration for RCS2# */
160                 mem_stcfg &= ~TS_MASK;
161                 mem_stcfg &= ~TCSOE_MASK;
162                 mem_stcfg &= ~TOECS_MASK;
163                 mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS;
164                 break;
165         }
166
167         au_writel(mem_sttime,MEM_STTIME2);
168         au_writel(mem_stcfg,MEM_STCFG2);
169 }
170
171 static int auide_tune_chipset(ide_drive_t *drive, const u8 speed)
172 {
173         int mem_sttime;
174         int mem_stcfg;
175
176         mem_sttime = 0;
177         mem_stcfg  = au_readl(MEM_STCFG2);
178
179         switch(speed) {
180 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
181         case XFER_MW_DMA_2:
182                 mem_sttime = SBC_IDE_TIMING(MDMA2);
183
184                 /* set configuration for RCS2# */
185                 mem_stcfg &= ~TS_MASK;
186                 mem_stcfg &= ~TCSOE_MASK;
187                 mem_stcfg &= ~TOECS_MASK;
188                 mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS;
189
190                 break;
191         case XFER_MW_DMA_1:
192                 mem_sttime = SBC_IDE_TIMING(MDMA1);
193
194                 /* set configuration for RCS2# */
195                 mem_stcfg &= ~TS_MASK;
196                 mem_stcfg &= ~TCSOE_MASK;
197                 mem_stcfg &= ~TOECS_MASK;
198                 mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS;
199
200                 break;
201         case XFER_MW_DMA_0:
202                 mem_sttime = SBC_IDE_TIMING(MDMA0);
203
204                 /* set configuration for RCS2# */
205                 mem_stcfg |= TS_MASK;
206                 mem_stcfg &= ~TCSOE_MASK;
207                 mem_stcfg &= ~TOECS_MASK;
208                 mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS;
209
210                 break;
211 #endif
212         default:
213                 return 1;
214         }
215
216         if (ide_config_drive_speed(drive, speed))
217                 return 1;
218
219         au_writel(mem_sttime,MEM_STTIME2);
220         au_writel(mem_stcfg,MEM_STCFG2);
221
222         return 0;
223 }
224
225 /*
226  * Multi-Word DMA + DbDMA functions
227  */
228
229 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
230
231 static int auide_build_sglist(ide_drive_t *drive,  struct request *rq)
232 {
233         ide_hwif_t *hwif = drive->hwif;
234         _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
235         struct scatterlist *sg = hwif->sg_table;
236
237         ide_map_sg(drive, rq);
238
239         if (rq_data_dir(rq) == READ)
240                 hwif->sg_dma_direction = DMA_FROM_DEVICE;
241         else
242                 hwif->sg_dma_direction = DMA_TO_DEVICE;
243
244         return dma_map_sg(ahwif->dev, sg, hwif->sg_nents,
245                           hwif->sg_dma_direction);
246 }
247
248 static int auide_build_dmatable(ide_drive_t *drive)
249 {
250         int i, iswrite, count = 0;
251         ide_hwif_t *hwif = HWIF(drive);
252
253         struct request *rq = HWGROUP(drive)->rq;
254
255         _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
256         struct scatterlist *sg;
257
258         iswrite = (rq_data_dir(rq) == WRITE);
259         /* Save for interrupt context */
260         ahwif->drive = drive;
261
262         /* Build sglist */
263         hwif->sg_nents = i = auide_build_sglist(drive, rq);
264
265         if (!i)
266                 return 0;
267
268         /* fill the descriptors */
269         sg = hwif->sg_table;
270         while (i && sg_dma_len(sg)) {
271                 u32 cur_addr;
272                 u32 cur_len;
273
274                 cur_addr = sg_dma_address(sg);
275                 cur_len = sg_dma_len(sg);
276
277                 while (cur_len) {
278                         u32 flags = DDMA_FLAGS_NOIE;
279                         unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
280
281                         if (++count >= PRD_ENTRIES) {
282                                 printk(KERN_WARNING "%s: DMA table too small\n",
283                                        drive->name);
284                                 goto use_pio_instead;
285                         }
286
287                         /* Lets enable intr for the last descriptor only */
288                         if (1==i)
289                                 flags = DDMA_FLAGS_IE;
290                         else
291                                 flags = DDMA_FLAGS_NOIE;
292
293                         if (iswrite) {
294                                 if(!put_source_flags(ahwif->tx_chan, 
295                                                      (void*)(page_address(sg->page) 
296                                                              + sg->offset), 
297                                                      tc, flags)) { 
298                                         printk(KERN_ERR "%s failed %d\n", 
299                                                __FUNCTION__, __LINE__);
300                                 }
301                         } else 
302                         {
303                                 if(!put_dest_flags(ahwif->rx_chan, 
304                                                    (void*)(page_address(sg->page) 
305                                                            + sg->offset), 
306                                                    tc, flags)) { 
307                                         printk(KERN_ERR "%s failed %d\n", 
308                                                __FUNCTION__, __LINE__);
309                                 }
310                         }
311
312                         cur_addr += tc;
313                         cur_len -= tc;
314                 }
315                 sg++;
316                 i--;
317         }
318
319         if (count)
320                 return 1;
321
322  use_pio_instead:
323         dma_unmap_sg(ahwif->dev,
324                      hwif->sg_table,
325                      hwif->sg_nents,
326                      hwif->sg_dma_direction);
327
328         return 0; /* revert to PIO for this request */
329 }
330
331 static int auide_dma_end(ide_drive_t *drive)
332 {
333         ide_hwif_t *hwif = HWIF(drive);
334         _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
335
336         if (hwif->sg_nents) {
337                 dma_unmap_sg(ahwif->dev, hwif->sg_table, hwif->sg_nents,
338                              hwif->sg_dma_direction);
339                 hwif->sg_nents = 0;
340         }
341
342         return 0;
343 }
344
345 static void auide_dma_start(ide_drive_t *drive )
346 {
347 }
348
349
350 static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command)
351 {
352         /* issue cmd to drive */
353         ide_execute_command(drive, command, &ide_dma_intr,
354                             (2*WAIT_CMD), NULL);
355 }
356
357 static int auide_dma_setup(ide_drive_t *drive)
358 {               
359         struct request *rq = HWGROUP(drive)->rq;
360
361         if (!auide_build_dmatable(drive)) {
362                 ide_map_sg(drive, rq);
363                 return 1;
364         }
365
366         drive->waiting_for_dma = 1;
367         return 0;
368 }
369
370 static int auide_dma_check(ide_drive_t *drive)
371 {
372         u8 speed = ide_max_dma_mode(drive);
373
374         if( dbdma_init_done == 0 ){
375                 auide_hwif.white_list = ide_in_drive_list(drive->id,
376                                                           dma_white_list);
377                 auide_hwif.black_list = ide_in_drive_list(drive->id,
378                                                           dma_black_list);
379                 auide_hwif.drive = drive;
380                 auide_ddma_init(&auide_hwif);
381                 dbdma_init_done = 1;
382         }
383
384         /* Is the drive in our DMA black list? */
385
386         if ( auide_hwif.black_list ) {
387                 drive->using_dma = 0;
388
389                 /* Borrowed the warning message from ide-dma.c */
390
391                 printk(KERN_WARNING "%s: Disabling DMA for %s (blacklisted)\n",
392                        drive->name, drive->id->model);         
393         }
394         else
395                 drive->using_dma = 1;
396
397         if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
398                 return 0;
399
400         return -1;
401 }
402
403 static int auide_dma_test_irq(ide_drive_t *drive)
404 {       
405         if (drive->waiting_for_dma == 0)
406                 printk(KERN_WARNING "%s: ide_dma_test_irq \
407                                      called while not waiting\n", drive->name);
408
409         /* If dbdma didn't execute the STOP command yet, the
410          * active bit is still set
411          */
412         drive->waiting_for_dma++;
413         if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
414                 printk(KERN_WARNING "%s: timeout waiting for ddma to \
415                                      complete\n", drive->name);
416                 return 1;
417         }
418         udelay(10);
419         return 0;
420 }
421
422 static void auide_dma_host_on(ide_drive_t *drive)
423 {
424 }
425
426 static int auide_dma_on(ide_drive_t *drive)
427 {
428         drive->using_dma = 1;
429
430         return 0;
431 }
432
433 static void auide_dma_host_off(ide_drive_t *drive)
434 {
435 }
436
437 static void auide_dma_off_quietly(ide_drive_t *drive)
438 {
439         drive->using_dma = 0;
440 }
441
442 static void auide_dma_lost_irq(ide_drive_t *drive)
443 {
444         printk(KERN_ERR "%s: IRQ lost\n", drive->name);
445 }
446
447 static void auide_ddma_tx_callback(int irq, void *param)
448 {
449         _auide_hwif *ahwif = (_auide_hwif*)param;
450         ahwif->drive->waiting_for_dma = 0;
451 }
452
453 static void auide_ddma_rx_callback(int irq, void *param)
454 {
455         _auide_hwif *ahwif = (_auide_hwif*)param;
456         ahwif->drive->waiting_for_dma = 0;
457 }
458
459 #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
460
461 static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags)
462 {
463         dev->dev_id          = dev_id;
464         dev->dev_physaddr    = (u32)AU1XXX_ATA_PHYS_ADDR;
465         dev->dev_intlevel    = 0;
466         dev->dev_intpolarity = 0;
467         dev->dev_tsize       = tsize;
468         dev->dev_devwidth    = devwidth;
469         dev->dev_flags       = flags;
470 }
471   
472 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
473
474 static void auide_dma_timeout(ide_drive_t *drive)
475 {
476         ide_hwif_t *hwif = HWIF(drive);
477
478         printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
479
480         if (hwif->ide_dma_test_irq(drive))
481                 return;
482
483         hwif->ide_dma_end(drive);
484 }
485                                         
486
487 static int auide_ddma_init(_auide_hwif *auide) {
488         
489         dbdev_tab_t source_dev_tab, target_dev_tab;
490         u32 dev_id, tsize, devwidth, flags;
491         ide_hwif_t *hwif = auide->hwif;
492
493         dev_id   = AU1XXX_ATA_DDMA_REQ;
494
495         if (auide->white_list || auide->black_list) {
496                 tsize    = 8;
497                 devwidth = 32;
498         }
499         else { 
500                 tsize    = 1;
501                 devwidth = 16;
502                 
503                 printk(KERN_ERR "au1xxx-ide: %s is not on ide driver whitelist.\n",auide_hwif.drive->id->model);
504                 printk(KERN_ERR "            please read 'Documentation/mips/AU1xxx_IDE.README'");
505         }
506
507 #ifdef IDE_AU1XXX_BURSTMODE 
508         flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
509 #else
510         flags = DEV_FLAGS_SYNC;
511 #endif
512
513         /* setup dev_tab for tx channel */
514         auide_init_dbdma_dev( &source_dev_tab,
515                               dev_id,
516                               tsize, devwidth, DEV_FLAGS_OUT | flags);
517         auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
518
519         auide_init_dbdma_dev( &source_dev_tab,
520                               dev_id,
521                               tsize, devwidth, DEV_FLAGS_IN | flags);
522         auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
523         
524         /* We also need to add a target device for the DMA */
525         auide_init_dbdma_dev( &target_dev_tab,
526                               (u32)DSCR_CMD0_ALWAYS,
527                               tsize, devwidth, DEV_FLAGS_ANYUSE);
528         auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab); 
529  
530         /* Get a channel for TX */
531         auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
532                                                  auide->tx_dev_id,
533                                                  auide_ddma_tx_callback,
534                                                  (void*)auide);
535  
536         /* Get a channel for RX */
537         auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
538                                                  auide->target_dev_id,
539                                                  auide_ddma_rx_callback,
540                                                  (void*)auide);
541
542         auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
543                                                              NUM_DESCRIPTORS);
544         auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
545                                                              NUM_DESCRIPTORS);
546  
547         hwif->dmatable_cpu = dma_alloc_coherent(auide->dev,
548                                                 PRD_ENTRIES * PRD_BYTES,        /* 1 Page */
549                                                 &hwif->dmatable_dma, GFP_KERNEL);
550         
551         au1xxx_dbdma_start( auide->tx_chan );
552         au1xxx_dbdma_start( auide->rx_chan );
553  
554         return 0;
555
556 #else
557  
558 static int auide_ddma_init( _auide_hwif *auide )
559 {
560         dbdev_tab_t source_dev_tab;
561         int flags;
562
563 #ifdef IDE_AU1XXX_BURSTMODE 
564         flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
565 #else
566         flags = DEV_FLAGS_SYNC;
567 #endif
568
569         /* setup dev_tab for tx channel */
570         auide_init_dbdma_dev( &source_dev_tab,
571                               (u32)DSCR_CMD0_ALWAYS,
572                               8, 32, DEV_FLAGS_OUT | flags);
573         auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
574
575         auide_init_dbdma_dev( &source_dev_tab,
576                               (u32)DSCR_CMD0_ALWAYS,
577                               8, 32, DEV_FLAGS_IN | flags);
578         auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
579         
580         /* Get a channel for TX */
581         auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
582                                                  auide->tx_dev_id,
583                                                  NULL,
584                                                  (void*)auide);
585  
586         /* Get a channel for RX */
587         auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
588                                                  DSCR_CMD0_ALWAYS,
589                                                  NULL,
590                                                  (void*)auide);
591  
592         auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
593                                                              NUM_DESCRIPTORS);
594         auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
595                                                              NUM_DESCRIPTORS);
596  
597         au1xxx_dbdma_start( auide->tx_chan );
598         au1xxx_dbdma_start( auide->rx_chan );
599         
600         return 0;
601 }
602 #endif
603
604 static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif)
605 {
606         int i;
607         unsigned long *ata_regs = hw->io_ports;
608
609         /* FIXME? */
610         for (i = 0; i < IDE_CONTROL_OFFSET; i++) {
611                 *ata_regs++ = ahwif->regbase + (i << AU1XXX_ATA_REG_OFFSET);
612         }
613
614         /* set the Alternative Status register */
615         *ata_regs = ahwif->regbase + (14 << AU1XXX_ATA_REG_OFFSET);
616 }
617
618 static int au_ide_probe(struct device *dev)
619 {
620         struct platform_device *pdev = to_platform_device(dev);
621         _auide_hwif *ahwif = &auide_hwif;
622         ide_hwif_t *hwif;
623         struct resource *res;
624         hw_regs_t *hw;
625         int ret = 0;
626
627 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
628         char *mode = "MWDMA2";
629 #elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
630         char *mode = "PIO+DDMA(offload)";
631 #endif
632
633         memset(&auide_hwif, 0, sizeof(_auide_hwif));
634         auide_hwif.dev                  = 0;
635
636         ahwif->dev = dev;
637         ahwif->irq = platform_get_irq(pdev, 0);
638
639         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
640
641         if (res == NULL) {
642                 pr_debug("%s %d: no base address\n", DRV_NAME, pdev->id);
643                 ret = -ENODEV;
644                 goto out;
645         }
646         if (ahwif->irq < 0) {
647                 pr_debug("%s %d: no IRQ\n", DRV_NAME, pdev->id);
648                 ret = -ENODEV;
649                 goto out;
650         }
651
652         if (!request_mem_region (res->start, res->end-res->start, pdev->name)) {
653                 pr_debug("%s: request_mem_region failed\n", DRV_NAME);
654                 ret =  -EBUSY;
655                 goto out;
656         }
657
658         ahwif->regbase = (u32)ioremap(res->start, res->end-res->start);
659         if (ahwif->regbase == 0) {
660                 ret = -ENOMEM;
661                 goto out;
662         }
663
664         /* FIXME:  This might possibly break PCMCIA IDE devices */
665
666         hwif                            = &ide_hwifs[pdev->id];
667         hw                              = &hwif->hw;
668         hwif->irq = hw->irq             = ahwif->irq;
669         hwif->chipset                   = ide_au1xxx;
670
671         auide_setup_ports(hw, ahwif);
672         memcpy(hwif->io_ports, hw->io_ports, sizeof(hwif->io_ports));
673
674         hwif->ultra_mask                = 0x0;  /* Disable Ultra DMA */
675 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
676         hwif->mwdma_mask                = 0x07; /* Multimode-2 DMA  */
677         hwif->swdma_mask                = 0x00;
678 #else
679         hwif->mwdma_mask                = 0x0;
680         hwif->swdma_mask                = 0x0;
681 #endif
682
683         hwif->pio_mask = ATA_PIO4;
684
685         hwif->noprobe = 0;
686         hwif->drives[0].unmask          = 1;
687         hwif->drives[1].unmask          = 1;
688
689         /* hold should be on in all cases */
690         hwif->hold                      = 1;
691
692         hwif->mmio  = 1;
693
694         /* If the user has selected DDMA assisted copies,
695            then set up a few local I/O function entry points 
696         */
697
698 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA      
699         hwif->INSW                      = auide_insw;
700         hwif->OUTSW                     = auide_outsw;
701 #endif
702
703         hwif->set_pio_mode              = &au1xxx_set_pio_mode;
704         hwif->speedproc                 = &auide_tune_chipset;
705
706 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
707         hwif->dma_off_quietly           = &auide_dma_off_quietly;
708         hwif->dma_timeout               = &auide_dma_timeout;
709
710         hwif->ide_dma_check             = &auide_dma_check;
711         hwif->dma_exec_cmd              = &auide_dma_exec_cmd;
712         hwif->dma_start                 = &auide_dma_start;
713         hwif->ide_dma_end               = &auide_dma_end;
714         hwif->dma_setup                 = &auide_dma_setup;
715         hwif->ide_dma_test_irq          = &auide_dma_test_irq;
716         hwif->dma_host_off              = &auide_dma_host_off;
717         hwif->dma_host_on               = &auide_dma_host_on;
718         hwif->dma_lost_irq              = &auide_dma_lost_irq;
719         hwif->ide_dma_on                = &auide_dma_on;
720
721         hwif->autodma                   = 1;
722         hwif->drives[0].autodma         = hwif->autodma;
723         hwif->drives[1].autodma         = hwif->autodma;
724         hwif->atapi_dma                 = 1;
725
726 #else /* !CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
727         hwif->autodma                   = 0;
728         hwif->channel                   = 0;
729         hwif->hold                      = 1;
730         hwif->select_data               = 0;    /* no chipset-specific code */
731         hwif->config_data               = 0;    /* no chipset-specific code */
732
733         hwif->drives[0].autodma         = 0;
734         hwif->drives[0].autotune        = 1;    /* 1=autotune, 2=noautotune, 0=default */
735 #endif
736         hwif->drives[0].no_io_32bit     = 1;   
737
738         auide_hwif.hwif                 = hwif;
739         hwif->hwif_data                 = &auide_hwif;
740
741 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA           
742         auide_ddma_init(&auide_hwif);
743         dbdma_init_done = 1;
744 #endif
745
746         probe_hwif_init(hwif);
747
748         ide_proc_register_port(hwif);
749
750         dev_set_drvdata(dev, hwif);
751
752         printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode );
753
754  out:
755         return ret;
756 }
757
758 static int au_ide_remove(struct device *dev)
759 {
760         struct platform_device *pdev = to_platform_device(dev);
761         struct resource *res;
762         ide_hwif_t *hwif = dev_get_drvdata(dev);
763         _auide_hwif *ahwif = &auide_hwif;
764
765         ide_unregister(hwif - ide_hwifs);
766
767         iounmap((void *)ahwif->regbase);
768
769         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
770         release_mem_region(res->start, res->end - res->start);
771
772         return 0;
773 }
774
775 static struct device_driver au1200_ide_driver = {
776         .name           = "au1200-ide",
777         .bus            = &platform_bus_type,
778         .probe          = au_ide_probe,
779         .remove         = au_ide_remove,
780 };
781
782 static int __init au_ide_init(void)
783 {
784         return driver_register(&au1200_ide_driver);
785 }
786
787 static void __exit au_ide_exit(void)
788 {
789         driver_unregister(&au1200_ide_driver);
790 }
791
792 MODULE_LICENSE("GPL");
793 MODULE_DESCRIPTION("AU1200 IDE driver");
794
795 module_init(au_ide_init);
796 module_exit(au_ide_exit);