ide: add ->dma_timer_expiry method and remove ->dma_exec_cmd one (v2)
[linux-2.6.git] / drivers / ide / au1xxx-ide.c
1 /*
2  * BRIEF MODULE DESCRIPTION
3  * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
4  *
5  * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
6  *
7  * This program is free software; you can redistribute it and/or modify it under
8  * the terms of the GNU General Public License as published by the Free Software
9  * Foundation; either version 2 of the License, or (at your option) any later
10  * version.
11  *
12  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
13  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
14  * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
15  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
16  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
17  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
18  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
19  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
20  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
21  * POSSIBILITY OF SUCH DAMAGE.
22  *
23  * You should have received a copy of the GNU General Public License along with
24  * this program; if not, write to the Free Software Foundation, Inc.,
25  * 675 Mass Ave, Cambridge, MA 02139, USA.
26  *
27  * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
28  *       Interface and Linux Device Driver" Application Note.
29  */
30 #include <linux/types.h>
31 #include <linux/module.h>
32 #include <linux/kernel.h>
33 #include <linux/delay.h>
34 #include <linux/platform_device.h>
35 #include <linux/init.h>
36 #include <linux/ide.h>
37 #include <linux/scatterlist.h>
38
39 #include <asm/mach-au1x00/au1xxx.h>
40 #include <asm/mach-au1x00/au1xxx_dbdma.h>
41 #include <asm/mach-au1x00/au1xxx_ide.h>
42
43 #define DRV_NAME        "au1200-ide"
44 #define DRV_AUTHOR      "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>"
45
46 /* enable the burstmode in the dbdma */
47 #define IDE_AU1XXX_BURSTMODE    1
48
49 static _auide_hwif auide_hwif;
50
51 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
52
53 void auide_insw(unsigned long port, void *addr, u32 count)
54 {
55         _auide_hwif *ahwif = &auide_hwif;
56         chan_tab_t *ctp;
57         au1x_ddma_desc_t *dp;
58
59         if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1, 
60                            DDMA_FLAGS_NOIE)) {
61                 printk(KERN_ERR "%s failed %d\n", __func__, __LINE__);
62                 return;
63         }
64         ctp = *((chan_tab_t **)ahwif->rx_chan);
65         dp = ctp->cur_ptr;
66         while (dp->dscr_cmd0 & DSCR_CMD0_V)
67                 ;
68         ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
69 }
70
71 void auide_outsw(unsigned long port, void *addr, u32 count)
72 {
73         _auide_hwif *ahwif = &auide_hwif;
74         chan_tab_t *ctp;
75         au1x_ddma_desc_t *dp;
76
77         if(!put_source_flags(ahwif->tx_chan, (void*)addr,
78                              count << 1, DDMA_FLAGS_NOIE)) {
79                 printk(KERN_ERR "%s failed %d\n", __func__, __LINE__);
80                 return;
81         }
82         ctp = *((chan_tab_t **)ahwif->tx_chan);
83         dp = ctp->cur_ptr;
84         while (dp->dscr_cmd0 & DSCR_CMD0_V)
85                 ;
86         ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
87 }
88
89 static void au1xxx_input_data(ide_drive_t *drive, struct ide_cmd *cmd,
90                               void *buf, unsigned int len)
91 {
92         auide_insw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
93 }
94
95 static void au1xxx_output_data(ide_drive_t *drive, struct ide_cmd *cmd,
96                                void *buf, unsigned int len)
97 {
98         auide_outsw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
99 }
100 #endif
101
102 static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio)
103 {
104         int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
105
106         /* set pio mode! */
107         switch(pio) {
108         case 0:
109                 mem_sttime = SBC_IDE_TIMING(PIO0);
110
111                 /* set configuration for RCS2# */
112                 mem_stcfg |= TS_MASK;
113                 mem_stcfg &= ~TCSOE_MASK;
114                 mem_stcfg &= ~TOECS_MASK;
115                 mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS;
116                 break;
117
118         case 1:
119                 mem_sttime = SBC_IDE_TIMING(PIO1);
120
121                 /* set configuration for RCS2# */
122                 mem_stcfg |= TS_MASK;
123                 mem_stcfg &= ~TCSOE_MASK;
124                 mem_stcfg &= ~TOECS_MASK;
125                 mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS;
126                 break;
127
128         case 2:
129                 mem_sttime = SBC_IDE_TIMING(PIO2);
130
131                 /* set configuration for RCS2# */
132                 mem_stcfg &= ~TS_MASK;
133                 mem_stcfg &= ~TCSOE_MASK;
134                 mem_stcfg &= ~TOECS_MASK;
135                 mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS;
136                 break;
137
138         case 3:
139                 mem_sttime = SBC_IDE_TIMING(PIO3);
140
141                 /* set configuration for RCS2# */
142                 mem_stcfg &= ~TS_MASK;
143                 mem_stcfg &= ~TCSOE_MASK;
144                 mem_stcfg &= ~TOECS_MASK;
145                 mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS;
146
147                 break;
148
149         case 4:
150                 mem_sttime = SBC_IDE_TIMING(PIO4);
151
152                 /* set configuration for RCS2# */
153                 mem_stcfg &= ~TS_MASK;
154                 mem_stcfg &= ~TCSOE_MASK;
155                 mem_stcfg &= ~TOECS_MASK;
156                 mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS;
157                 break;
158         }
159
160         au_writel(mem_sttime,MEM_STTIME2);
161         au_writel(mem_stcfg,MEM_STCFG2);
162 }
163
164 static void auide_set_dma_mode(ide_drive_t *drive, const u8 speed)
165 {
166         int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
167
168         switch(speed) {
169 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
170         case XFER_MW_DMA_2:
171                 mem_sttime = SBC_IDE_TIMING(MDMA2);
172
173                 /* set configuration for RCS2# */
174                 mem_stcfg &= ~TS_MASK;
175                 mem_stcfg &= ~TCSOE_MASK;
176                 mem_stcfg &= ~TOECS_MASK;
177                 mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS;
178
179                 break;
180         case XFER_MW_DMA_1:
181                 mem_sttime = SBC_IDE_TIMING(MDMA1);
182
183                 /* set configuration for RCS2# */
184                 mem_stcfg &= ~TS_MASK;
185                 mem_stcfg &= ~TCSOE_MASK;
186                 mem_stcfg &= ~TOECS_MASK;
187                 mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS;
188
189                 break;
190         case XFER_MW_DMA_0:
191                 mem_sttime = SBC_IDE_TIMING(MDMA0);
192
193                 /* set configuration for RCS2# */
194                 mem_stcfg |= TS_MASK;
195                 mem_stcfg &= ~TCSOE_MASK;
196                 mem_stcfg &= ~TOECS_MASK;
197                 mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS;
198
199                 break;
200 #endif
201         }
202
203         au_writel(mem_sttime,MEM_STTIME2);
204         au_writel(mem_stcfg,MEM_STCFG2);
205 }
206
207 /*
208  * Multi-Word DMA + DbDMA functions
209  */
210
211 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
212 static int auide_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd)
213 {
214         ide_hwif_t *hwif = drive->hwif;
215         _auide_hwif *ahwif = &auide_hwif;
216         struct scatterlist *sg;
217         int i = cmd->sg_nents, count = 0;
218         int iswrite = !!(cmd->tf_flags & IDE_TFLAG_WRITE);
219
220         /* Save for interrupt context */
221         ahwif->drive = drive;
222
223         /* fill the descriptors */
224         sg = hwif->sg_table;
225         while (i && sg_dma_len(sg)) {
226                 u32 cur_addr;
227                 u32 cur_len;
228
229                 cur_addr = sg_dma_address(sg);
230                 cur_len = sg_dma_len(sg);
231
232                 while (cur_len) {
233                         u32 flags = DDMA_FLAGS_NOIE;
234                         unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
235
236                         if (++count >= PRD_ENTRIES) {
237                                 printk(KERN_WARNING "%s: DMA table too small\n",
238                                        drive->name);
239                                 goto use_pio_instead;
240                         }
241
242                         /* Lets enable intr for the last descriptor only */
243                         if (1==i)
244                                 flags = DDMA_FLAGS_IE;
245                         else
246                                 flags = DDMA_FLAGS_NOIE;
247
248                         if (iswrite) {
249                                 if(!put_source_flags(ahwif->tx_chan, 
250                                                      (void*) sg_virt(sg),
251                                                      tc, flags)) { 
252                                         printk(KERN_ERR "%s failed %d\n", 
253                                                __func__, __LINE__);
254                                 }
255                         } else 
256                         {
257                                 if(!put_dest_flags(ahwif->rx_chan, 
258                                                    (void*) sg_virt(sg),
259                                                    tc, flags)) { 
260                                         printk(KERN_ERR "%s failed %d\n", 
261                                                __func__, __LINE__);
262                                 }
263                         }
264
265                         cur_addr += tc;
266                         cur_len -= tc;
267                 }
268                 sg = sg_next(sg);
269                 i--;
270         }
271
272         if (count)
273                 return 1;
274
275  use_pio_instead:
276         ide_destroy_dmatable(drive);
277
278         return 0; /* revert to PIO for this request */
279 }
280
281 static int auide_dma_end(ide_drive_t *drive)
282 {
283         ide_destroy_dmatable(drive);
284
285         return 0;
286 }
287
288 static void auide_dma_start(ide_drive_t *drive )
289 {
290 }
291
292
293 static int auide_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
294 {
295         if (auide_build_dmatable(drive, cmd) == 0) {
296                 ide_map_sg(drive, cmd);
297                 return 1;
298         }
299
300         drive->waiting_for_dma = 1;
301         return 0;
302 }
303
304 static int auide_dma_test_irq(ide_drive_t *drive)
305 {
306         /* If dbdma didn't execute the STOP command yet, the
307          * active bit is still set
308          */
309         drive->waiting_for_dma++;
310         if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
311                 printk(KERN_WARNING "%s: timeout waiting for ddma to \
312                                      complete\n", drive->name);
313                 return 1;
314         }
315         udelay(10);
316         return 0;
317 }
318
319 static void auide_dma_host_set(ide_drive_t *drive, int on)
320 {
321 }
322
323 static void auide_ddma_tx_callback(int irq, void *param)
324 {
325         _auide_hwif *ahwif = (_auide_hwif*)param;
326         ahwif->drive->waiting_for_dma = 0;
327 }
328
329 static void auide_ddma_rx_callback(int irq, void *param)
330 {
331         _auide_hwif *ahwif = (_auide_hwif*)param;
332         ahwif->drive->waiting_for_dma = 0;
333 }
334
335 #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
336
337 static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags)
338 {
339         dev->dev_id          = dev_id;
340         dev->dev_physaddr    = (u32)IDE_PHYS_ADDR;
341         dev->dev_intlevel    = 0;
342         dev->dev_intpolarity = 0;
343         dev->dev_tsize       = tsize;
344         dev->dev_devwidth    = devwidth;
345         dev->dev_flags       = flags;
346 }
347
348 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
349 static const struct ide_dma_ops au1xxx_dma_ops = {
350         .dma_host_set           = auide_dma_host_set,
351         .dma_setup              = auide_dma_setup,
352         .dma_start              = auide_dma_start,
353         .dma_end                = auide_dma_end,
354         .dma_test_irq           = auide_dma_test_irq,
355         .dma_lost_irq           = ide_dma_lost_irq,
356         .dma_timeout            = ide_dma_timeout,
357 };
358
359 static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
360 {
361         _auide_hwif *auide = &auide_hwif;
362         dbdev_tab_t source_dev_tab, target_dev_tab;
363         u32 dev_id, tsize, devwidth, flags;
364
365         dev_id   = IDE_DDMA_REQ;
366
367         tsize    =  8; /*  1 */
368         devwidth = 32; /* 16 */
369
370 #ifdef IDE_AU1XXX_BURSTMODE 
371         flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
372 #else
373         flags = DEV_FLAGS_SYNC;
374 #endif
375
376         /* setup dev_tab for tx channel */
377         auide_init_dbdma_dev( &source_dev_tab,
378                               dev_id,
379                               tsize, devwidth, DEV_FLAGS_OUT | flags);
380         auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
381
382         auide_init_dbdma_dev( &source_dev_tab,
383                               dev_id,
384                               tsize, devwidth, DEV_FLAGS_IN | flags);
385         auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
386         
387         /* We also need to add a target device for the DMA */
388         auide_init_dbdma_dev( &target_dev_tab,
389                               (u32)DSCR_CMD0_ALWAYS,
390                               tsize, devwidth, DEV_FLAGS_ANYUSE);
391         auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab); 
392  
393         /* Get a channel for TX */
394         auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
395                                                  auide->tx_dev_id,
396                                                  auide_ddma_tx_callback,
397                                                  (void*)auide);
398  
399         /* Get a channel for RX */
400         auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
401                                                  auide->target_dev_id,
402                                                  auide_ddma_rx_callback,
403                                                  (void*)auide);
404
405         auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
406                                                              NUM_DESCRIPTORS);
407         auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
408                                                              NUM_DESCRIPTORS);
409
410         /* FIXME: check return value */
411         (void)ide_allocate_dma_engine(hwif);
412         
413         au1xxx_dbdma_start( auide->tx_chan );
414         au1xxx_dbdma_start( auide->rx_chan );
415  
416         return 0;
417
418 #else
419 static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
420 {
421         _auide_hwif *auide = &auide_hwif;
422         dbdev_tab_t source_dev_tab;
423         int flags;
424
425 #ifdef IDE_AU1XXX_BURSTMODE 
426         flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
427 #else
428         flags = DEV_FLAGS_SYNC;
429 #endif
430
431         /* setup dev_tab for tx channel */
432         auide_init_dbdma_dev( &source_dev_tab,
433                               (u32)DSCR_CMD0_ALWAYS,
434                               8, 32, DEV_FLAGS_OUT | flags);
435         auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
436
437         auide_init_dbdma_dev( &source_dev_tab,
438                               (u32)DSCR_CMD0_ALWAYS,
439                               8, 32, DEV_FLAGS_IN | flags);
440         auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
441         
442         /* Get a channel for TX */
443         auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
444                                                  auide->tx_dev_id,
445                                                  NULL,
446                                                  (void*)auide);
447  
448         /* Get a channel for RX */
449         auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
450                                                  DSCR_CMD0_ALWAYS,
451                                                  NULL,
452                                                  (void*)auide);
453  
454         auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
455                                                              NUM_DESCRIPTORS);
456         auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
457                                                              NUM_DESCRIPTORS);
458  
459         au1xxx_dbdma_start( auide->tx_chan );
460         au1xxx_dbdma_start( auide->rx_chan );
461         
462         return 0;
463 }
464 #endif
465
466 static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif)
467 {
468         int i;
469         unsigned long *ata_regs = hw->io_ports_array;
470
471         /* FIXME? */
472         for (i = 0; i < 8; i++)
473                 *ata_regs++ = ahwif->regbase + (i << IDE_REG_SHIFT);
474
475         /* set the Alternative Status register */
476         *ata_regs = ahwif->regbase + (14 << IDE_REG_SHIFT);
477 }
478
479 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
480 static const struct ide_tp_ops au1xxx_tp_ops = {
481         .exec_command           = ide_exec_command,
482         .read_status            = ide_read_status,
483         .read_altstatus         = ide_read_altstatus,
484
485         .set_irq                = ide_set_irq,
486
487         .tf_load                = ide_tf_load,
488         .tf_read                = ide_tf_read,
489
490         .input_data             = au1xxx_input_data,
491         .output_data            = au1xxx_output_data,
492 };
493 #endif
494
495 static const struct ide_port_ops au1xxx_port_ops = {
496         .set_pio_mode           = au1xxx_set_pio_mode,
497         .set_dma_mode           = auide_set_dma_mode,
498 };
499
500 static const struct ide_port_info au1xxx_port_info = {
501         .init_dma               = auide_ddma_init,
502 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
503         .tp_ops                 = &au1xxx_tp_ops,
504 #endif
505         .port_ops               = &au1xxx_port_ops,
506 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
507         .dma_ops                = &au1xxx_dma_ops,
508 #endif
509         .host_flags             = IDE_HFLAG_POST_SET_MODE |
510                                   IDE_HFLAG_NO_IO_32BIT |
511                                   IDE_HFLAG_UNMASK_IRQS,
512         .pio_mask               = ATA_PIO4,
513 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
514         .mwdma_mask             = ATA_MWDMA2,
515 #endif
516 };
517
518 static int au_ide_probe(struct platform_device *dev)
519 {
520         _auide_hwif *ahwif = &auide_hwif;
521         struct resource *res;
522         struct ide_host *host;
523         int ret = 0;
524         hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
525
526 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
527         char *mode = "MWDMA2";
528 #elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
529         char *mode = "PIO+DDMA(offload)";
530 #endif
531
532         memset(&auide_hwif, 0, sizeof(_auide_hwif));
533         ahwif->irq = platform_get_irq(dev, 0);
534
535         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
536
537         if (res == NULL) {
538                 pr_debug("%s %d: no base address\n", DRV_NAME, dev->id);
539                 ret = -ENODEV;
540                 goto out;
541         }
542         if (ahwif->irq < 0) {
543                 pr_debug("%s %d: no IRQ\n", DRV_NAME, dev->id);
544                 ret = -ENODEV;
545                 goto out;
546         }
547
548         if (!request_mem_region(res->start, res->end - res->start + 1,
549                                 dev->name)) {
550                 pr_debug("%s: request_mem_region failed\n", DRV_NAME);
551                 ret =  -EBUSY;
552                 goto out;
553         }
554
555         ahwif->regbase = (u32)ioremap(res->start, res->end - res->start + 1);
556         if (ahwif->regbase == 0) {
557                 ret = -ENOMEM;
558                 goto out;
559         }
560
561         memset(&hw, 0, sizeof(hw));
562         auide_setup_ports(&hw, ahwif);
563         hw.irq = ahwif->irq;
564         hw.dev = &dev->dev;
565         hw.chipset = ide_au1xxx;
566
567         ret = ide_host_add(&au1xxx_port_info, hws, &host);
568         if (ret)
569                 goto out;
570
571         auide_hwif.hwif = host->ports[0];
572
573         platform_set_drvdata(dev, host);
574
575         printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode );
576
577  out:
578         return ret;
579 }
580
581 static int au_ide_remove(struct platform_device *dev)
582 {
583         struct resource *res;
584         struct ide_host *host = platform_get_drvdata(dev);
585         _auide_hwif *ahwif = &auide_hwif;
586
587         ide_host_remove(host);
588
589         iounmap((void *)ahwif->regbase);
590
591         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
592         release_mem_region(res->start, res->end - res->start + 1);
593
594         return 0;
595 }
596
597 static struct platform_driver au1200_ide_driver = {
598         .driver = {
599                 .name           = "au1200-ide",
600                 .owner          = THIS_MODULE,
601         },
602         .probe          = au_ide_probe,
603         .remove         = au_ide_remove,
604 };
605
606 static int __init au_ide_init(void)
607 {
608         return platform_driver_register(&au1200_ide_driver);
609 }
610
611 static void __exit au_ide_exit(void)
612 {
613         platform_driver_unregister(&au1200_ide_driver);
614 }
615
616 MODULE_LICENSE("GPL");
617 MODULE_DESCRIPTION("AU1200 IDE driver");
618
619 module_init(au_ide_init);
620 module_exit(au_ide_exit);