58485d6cb0267f7f1a82b5f2b0849a9d3002a05d
[linux-2.6.git] / drivers / ide / au1xxx-ide.c
1 /*
2  * BRIEF MODULE DESCRIPTION
3  * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
4  *
5  * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
6  *
7  * This program is free software; you can redistribute it and/or modify it under
8  * the terms of the GNU General Public License as published by the Free Software
9  * Foundation; either version 2 of the License, or (at your option) any later
10  * version.
11  *
12  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
13  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
14  * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
15  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
16  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
17  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
18  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
19  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
20  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
21  * POSSIBILITY OF SUCH DAMAGE.
22  *
23  * You should have received a copy of the GNU General Public License along with
24  * this program; if not, write to the Free Software Foundation, Inc.,
25  * 675 Mass Ave, Cambridge, MA 02139, USA.
26  *
27  * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
28  *       Interface and Linux Device Driver" Application Note.
29  */
30 #include <linux/types.h>
31 #include <linux/module.h>
32 #include <linux/kernel.h>
33 #include <linux/delay.h>
34 #include <linux/platform_device.h>
35 #include <linux/init.h>
36 #include <linux/ide.h>
37 #include <linux/scatterlist.h>
38
39 #include <asm/mach-au1x00/au1xxx.h>
40 #include <asm/mach-au1x00/au1xxx_dbdma.h>
41 #include <asm/mach-au1x00/au1xxx_ide.h>
42
43 #define DRV_NAME        "au1200-ide"
44 #define DRV_AUTHOR      "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>"
45
46 /* enable the burstmode in the dbdma */
47 #define IDE_AU1XXX_BURSTMODE    1
48
49 static _auide_hwif auide_hwif;
50
51 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
52
53 void auide_insw(unsigned long port, void *addr, u32 count)
54 {
55         _auide_hwif *ahwif = &auide_hwif;
56         chan_tab_t *ctp;
57         au1x_ddma_desc_t *dp;
58
59         if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1, 
60                            DDMA_FLAGS_NOIE)) {
61                 printk(KERN_ERR "%s failed %d\n", __func__, __LINE__);
62                 return;
63         }
64         ctp = *((chan_tab_t **)ahwif->rx_chan);
65         dp = ctp->cur_ptr;
66         while (dp->dscr_cmd0 & DSCR_CMD0_V)
67                 ;
68         ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
69 }
70
71 void auide_outsw(unsigned long port, void *addr, u32 count)
72 {
73         _auide_hwif *ahwif = &auide_hwif;
74         chan_tab_t *ctp;
75         au1x_ddma_desc_t *dp;
76
77         if(!put_source_flags(ahwif->tx_chan, (void*)addr,
78                              count << 1, DDMA_FLAGS_NOIE)) {
79                 printk(KERN_ERR "%s failed %d\n", __func__, __LINE__);
80                 return;
81         }
82         ctp = *((chan_tab_t **)ahwif->tx_chan);
83         dp = ctp->cur_ptr;
84         while (dp->dscr_cmd0 & DSCR_CMD0_V)
85                 ;
86         ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
87 }
88
89 static void au1xxx_input_data(ide_drive_t *drive, struct ide_cmd *cmd,
90                               void *buf, unsigned int len)
91 {
92         auide_insw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
93 }
94
95 static void au1xxx_output_data(ide_drive_t *drive, struct ide_cmd *cmd,
96                                void *buf, unsigned int len)
97 {
98         auide_outsw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
99 }
100 #endif
101
102 static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio)
103 {
104         int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
105
106         /* set pio mode! */
107         switch(pio) {
108         case 0:
109                 mem_sttime = SBC_IDE_TIMING(PIO0);
110
111                 /* set configuration for RCS2# */
112                 mem_stcfg |= TS_MASK;
113                 mem_stcfg &= ~TCSOE_MASK;
114                 mem_stcfg &= ~TOECS_MASK;
115                 mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS;
116                 break;
117
118         case 1:
119                 mem_sttime = SBC_IDE_TIMING(PIO1);
120
121                 /* set configuration for RCS2# */
122                 mem_stcfg |= TS_MASK;
123                 mem_stcfg &= ~TCSOE_MASK;
124                 mem_stcfg &= ~TOECS_MASK;
125                 mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS;
126                 break;
127
128         case 2:
129                 mem_sttime = SBC_IDE_TIMING(PIO2);
130
131                 /* set configuration for RCS2# */
132                 mem_stcfg &= ~TS_MASK;
133                 mem_stcfg &= ~TCSOE_MASK;
134                 mem_stcfg &= ~TOECS_MASK;
135                 mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS;
136                 break;
137
138         case 3:
139                 mem_sttime = SBC_IDE_TIMING(PIO3);
140
141                 /* set configuration for RCS2# */
142                 mem_stcfg &= ~TS_MASK;
143                 mem_stcfg &= ~TCSOE_MASK;
144                 mem_stcfg &= ~TOECS_MASK;
145                 mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS;
146
147                 break;
148
149         case 4:
150                 mem_sttime = SBC_IDE_TIMING(PIO4);
151
152                 /* set configuration for RCS2# */
153                 mem_stcfg &= ~TS_MASK;
154                 mem_stcfg &= ~TCSOE_MASK;
155                 mem_stcfg &= ~TOECS_MASK;
156                 mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS;
157                 break;
158         }
159
160         au_writel(mem_sttime,MEM_STTIME2);
161         au_writel(mem_stcfg,MEM_STCFG2);
162 }
163
164 static void auide_set_dma_mode(ide_drive_t *drive, const u8 speed)
165 {
166         int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
167
168         switch(speed) {
169 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
170         case XFER_MW_DMA_2:
171                 mem_sttime = SBC_IDE_TIMING(MDMA2);
172
173                 /* set configuration for RCS2# */
174                 mem_stcfg &= ~TS_MASK;
175                 mem_stcfg &= ~TCSOE_MASK;
176                 mem_stcfg &= ~TOECS_MASK;
177                 mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS;
178
179                 break;
180         case XFER_MW_DMA_1:
181                 mem_sttime = SBC_IDE_TIMING(MDMA1);
182
183                 /* set configuration for RCS2# */
184                 mem_stcfg &= ~TS_MASK;
185                 mem_stcfg &= ~TCSOE_MASK;
186                 mem_stcfg &= ~TOECS_MASK;
187                 mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS;
188
189                 break;
190         case XFER_MW_DMA_0:
191                 mem_sttime = SBC_IDE_TIMING(MDMA0);
192
193                 /* set configuration for RCS2# */
194                 mem_stcfg |= TS_MASK;
195                 mem_stcfg &= ~TCSOE_MASK;
196                 mem_stcfg &= ~TOECS_MASK;
197                 mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS;
198
199                 break;
200 #endif
201         }
202
203         au_writel(mem_sttime,MEM_STTIME2);
204         au_writel(mem_stcfg,MEM_STCFG2);
205 }
206
207 /*
208  * Multi-Word DMA + DbDMA functions
209  */
210
211 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
212 static int auide_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd)
213 {
214         ide_hwif_t *hwif = drive->hwif;
215         _auide_hwif *ahwif = &auide_hwif;
216         struct scatterlist *sg;
217         int i = cmd->sg_nents, count = 0;
218         int iswrite = !!(cmd->tf_flags & IDE_TFLAG_WRITE);
219
220         /* Save for interrupt context */
221         ahwif->drive = drive;
222
223         /* fill the descriptors */
224         sg = hwif->sg_table;
225         while (i && sg_dma_len(sg)) {
226                 u32 cur_addr;
227                 u32 cur_len;
228
229                 cur_addr = sg_dma_address(sg);
230                 cur_len = sg_dma_len(sg);
231
232                 while (cur_len) {
233                         u32 flags = DDMA_FLAGS_NOIE;
234                         unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
235
236                         if (++count >= PRD_ENTRIES) {
237                                 printk(KERN_WARNING "%s: DMA table too small\n",
238                                        drive->name);
239                                 goto use_pio_instead;
240                         }
241
242                         /* Lets enable intr for the last descriptor only */
243                         if (1==i)
244                                 flags = DDMA_FLAGS_IE;
245                         else
246                                 flags = DDMA_FLAGS_NOIE;
247
248                         if (iswrite) {
249                                 if(!put_source_flags(ahwif->tx_chan, 
250                                                      (void*) sg_virt(sg),
251                                                      tc, flags)) { 
252                                         printk(KERN_ERR "%s failed %d\n", 
253                                                __func__, __LINE__);
254                                 }
255                         } else 
256                         {
257                                 if(!put_dest_flags(ahwif->rx_chan, 
258                                                    (void*) sg_virt(sg),
259                                                    tc, flags)) { 
260                                         printk(KERN_ERR "%s failed %d\n", 
261                                                __func__, __LINE__);
262                                 }
263                         }
264
265                         cur_addr += tc;
266                         cur_len -= tc;
267                 }
268                 sg = sg_next(sg);
269                 i--;
270         }
271
272         if (count)
273                 return 1;
274
275  use_pio_instead:
276         ide_destroy_dmatable(drive);
277
278         return 0; /* revert to PIO for this request */
279 }
280
281 static int auide_dma_end(ide_drive_t *drive)
282 {
283         ide_destroy_dmatable(drive);
284
285         return 0;
286 }
287
288 static void auide_dma_start(ide_drive_t *drive )
289 {
290 }
291
292
293 static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command)
294 {
295         /* issue cmd to drive */
296         ide_execute_command(drive, command, &ide_dma_intr,
297                             (2*WAIT_CMD), NULL);
298 }
299
300 static int auide_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
301 {
302         if (auide_build_dmatable(drive, cmd) == 0) {
303                 ide_map_sg(drive, cmd);
304                 return 1;
305         }
306
307         drive->waiting_for_dma = 1;
308         return 0;
309 }
310
311 static int auide_dma_test_irq(ide_drive_t *drive)
312 {
313         /* If dbdma didn't execute the STOP command yet, the
314          * active bit is still set
315          */
316         drive->waiting_for_dma++;
317         if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
318                 printk(KERN_WARNING "%s: timeout waiting for ddma to \
319                                      complete\n", drive->name);
320                 return 1;
321         }
322         udelay(10);
323         return 0;
324 }
325
326 static void auide_dma_host_set(ide_drive_t *drive, int on)
327 {
328 }
329
330 static void auide_ddma_tx_callback(int irq, void *param)
331 {
332         _auide_hwif *ahwif = (_auide_hwif*)param;
333         ahwif->drive->waiting_for_dma = 0;
334 }
335
336 static void auide_ddma_rx_callback(int irq, void *param)
337 {
338         _auide_hwif *ahwif = (_auide_hwif*)param;
339         ahwif->drive->waiting_for_dma = 0;
340 }
341
342 #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
343
344 static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags)
345 {
346         dev->dev_id          = dev_id;
347         dev->dev_physaddr    = (u32)IDE_PHYS_ADDR;
348         dev->dev_intlevel    = 0;
349         dev->dev_intpolarity = 0;
350         dev->dev_tsize       = tsize;
351         dev->dev_devwidth    = devwidth;
352         dev->dev_flags       = flags;
353 }
354
355 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
356 static const struct ide_dma_ops au1xxx_dma_ops = {
357         .dma_host_set           = auide_dma_host_set,
358         .dma_setup              = auide_dma_setup,
359         .dma_exec_cmd           = auide_dma_exec_cmd,
360         .dma_start              = auide_dma_start,
361         .dma_end                = auide_dma_end,
362         .dma_test_irq           = auide_dma_test_irq,
363         .dma_lost_irq           = ide_dma_lost_irq,
364         .dma_timeout            = ide_dma_timeout,
365 };
366
367 static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
368 {
369         _auide_hwif *auide = &auide_hwif;
370         dbdev_tab_t source_dev_tab, target_dev_tab;
371         u32 dev_id, tsize, devwidth, flags;
372
373         dev_id   = IDE_DDMA_REQ;
374
375         tsize    =  8; /*  1 */
376         devwidth = 32; /* 16 */
377
378 #ifdef IDE_AU1XXX_BURSTMODE 
379         flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
380 #else
381         flags = DEV_FLAGS_SYNC;
382 #endif
383
384         /* setup dev_tab for tx channel */
385         auide_init_dbdma_dev( &source_dev_tab,
386                               dev_id,
387                               tsize, devwidth, DEV_FLAGS_OUT | flags);
388         auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
389
390         auide_init_dbdma_dev( &source_dev_tab,
391                               dev_id,
392                               tsize, devwidth, DEV_FLAGS_IN | flags);
393         auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
394         
395         /* We also need to add a target device for the DMA */
396         auide_init_dbdma_dev( &target_dev_tab,
397                               (u32)DSCR_CMD0_ALWAYS,
398                               tsize, devwidth, DEV_FLAGS_ANYUSE);
399         auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab); 
400  
401         /* Get a channel for TX */
402         auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
403                                                  auide->tx_dev_id,
404                                                  auide_ddma_tx_callback,
405                                                  (void*)auide);
406  
407         /* Get a channel for RX */
408         auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
409                                                  auide->target_dev_id,
410                                                  auide_ddma_rx_callback,
411                                                  (void*)auide);
412
413         auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
414                                                              NUM_DESCRIPTORS);
415         auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
416                                                              NUM_DESCRIPTORS);
417
418         /* FIXME: check return value */
419         (void)ide_allocate_dma_engine(hwif);
420         
421         au1xxx_dbdma_start( auide->tx_chan );
422         au1xxx_dbdma_start( auide->rx_chan );
423  
424         return 0;
425
426 #else
427 static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
428 {
429         _auide_hwif *auide = &auide_hwif;
430         dbdev_tab_t source_dev_tab;
431         int flags;
432
433 #ifdef IDE_AU1XXX_BURSTMODE 
434         flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
435 #else
436         flags = DEV_FLAGS_SYNC;
437 #endif
438
439         /* setup dev_tab for tx channel */
440         auide_init_dbdma_dev( &source_dev_tab,
441                               (u32)DSCR_CMD0_ALWAYS,
442                               8, 32, DEV_FLAGS_OUT | flags);
443         auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
444
445         auide_init_dbdma_dev( &source_dev_tab,
446                               (u32)DSCR_CMD0_ALWAYS,
447                               8, 32, DEV_FLAGS_IN | flags);
448         auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
449         
450         /* Get a channel for TX */
451         auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
452                                                  auide->tx_dev_id,
453                                                  NULL,
454                                                  (void*)auide);
455  
456         /* Get a channel for RX */
457         auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
458                                                  DSCR_CMD0_ALWAYS,
459                                                  NULL,
460                                                  (void*)auide);
461  
462         auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
463                                                              NUM_DESCRIPTORS);
464         auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
465                                                              NUM_DESCRIPTORS);
466  
467         au1xxx_dbdma_start( auide->tx_chan );
468         au1xxx_dbdma_start( auide->rx_chan );
469         
470         return 0;
471 }
472 #endif
473
474 static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif)
475 {
476         int i;
477         unsigned long *ata_regs = hw->io_ports_array;
478
479         /* FIXME? */
480         for (i = 0; i < 8; i++)
481                 *ata_regs++ = ahwif->regbase + (i << IDE_REG_SHIFT);
482
483         /* set the Alternative Status register */
484         *ata_regs = ahwif->regbase + (14 << IDE_REG_SHIFT);
485 }
486
487 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
488 static const struct ide_tp_ops au1xxx_tp_ops = {
489         .exec_command           = ide_exec_command,
490         .read_status            = ide_read_status,
491         .read_altstatus         = ide_read_altstatus,
492
493         .set_irq                = ide_set_irq,
494
495         .tf_load                = ide_tf_load,
496         .tf_read                = ide_tf_read,
497
498         .input_data             = au1xxx_input_data,
499         .output_data            = au1xxx_output_data,
500 };
501 #endif
502
503 static const struct ide_port_ops au1xxx_port_ops = {
504         .set_pio_mode           = au1xxx_set_pio_mode,
505         .set_dma_mode           = auide_set_dma_mode,
506 };
507
508 static const struct ide_port_info au1xxx_port_info = {
509         .init_dma               = auide_ddma_init,
510 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
511         .tp_ops                 = &au1xxx_tp_ops,
512 #endif
513         .port_ops               = &au1xxx_port_ops,
514 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
515         .dma_ops                = &au1xxx_dma_ops,
516 #endif
517         .host_flags             = IDE_HFLAG_POST_SET_MODE |
518                                   IDE_HFLAG_NO_IO_32BIT |
519                                   IDE_HFLAG_UNMASK_IRQS,
520         .pio_mask               = ATA_PIO4,
521 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
522         .mwdma_mask             = ATA_MWDMA2,
523 #endif
524 };
525
526 static int au_ide_probe(struct platform_device *dev)
527 {
528         _auide_hwif *ahwif = &auide_hwif;
529         struct resource *res;
530         struct ide_host *host;
531         int ret = 0;
532         hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
533
534 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
535         char *mode = "MWDMA2";
536 #elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
537         char *mode = "PIO+DDMA(offload)";
538 #endif
539
540         memset(&auide_hwif, 0, sizeof(_auide_hwif));
541         ahwif->irq = platform_get_irq(dev, 0);
542
543         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
544
545         if (res == NULL) {
546                 pr_debug("%s %d: no base address\n", DRV_NAME, dev->id);
547                 ret = -ENODEV;
548                 goto out;
549         }
550         if (ahwif->irq < 0) {
551                 pr_debug("%s %d: no IRQ\n", DRV_NAME, dev->id);
552                 ret = -ENODEV;
553                 goto out;
554         }
555
556         if (!request_mem_region(res->start, res->end - res->start + 1,
557                                 dev->name)) {
558                 pr_debug("%s: request_mem_region failed\n", DRV_NAME);
559                 ret =  -EBUSY;
560                 goto out;
561         }
562
563         ahwif->regbase = (u32)ioremap(res->start, res->end - res->start + 1);
564         if (ahwif->regbase == 0) {
565                 ret = -ENOMEM;
566                 goto out;
567         }
568
569         memset(&hw, 0, sizeof(hw));
570         auide_setup_ports(&hw, ahwif);
571         hw.irq = ahwif->irq;
572         hw.dev = &dev->dev;
573         hw.chipset = ide_au1xxx;
574
575         ret = ide_host_add(&au1xxx_port_info, hws, &host);
576         if (ret)
577                 goto out;
578
579         auide_hwif.hwif = host->ports[0];
580
581         platform_set_drvdata(dev, host);
582
583         printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode );
584
585  out:
586         return ret;
587 }
588
589 static int au_ide_remove(struct platform_device *dev)
590 {
591         struct resource *res;
592         struct ide_host *host = platform_get_drvdata(dev);
593         _auide_hwif *ahwif = &auide_hwif;
594
595         ide_host_remove(host);
596
597         iounmap((void *)ahwif->regbase);
598
599         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
600         release_mem_region(res->start, res->end - res->start + 1);
601
602         return 0;
603 }
604
605 static struct platform_driver au1200_ide_driver = {
606         .driver = {
607                 .name           = "au1200-ide",
608                 .owner          = THIS_MODULE,
609         },
610         .probe          = au_ide_probe,
611         .remove         = au_ide_remove,
612 };
613
614 static int __init au_ide_init(void)
615 {
616         return platform_driver_register(&au1200_ide_driver);
617 }
618
619 static void __exit au_ide_exit(void)
620 {
621         platform_driver_unregister(&au1200_ide_driver);
622 }
623
624 MODULE_LICENSE("GPL");
625 MODULE_DESCRIPTION("AU1200 IDE driver");
626
627 module_init(au_ide_init);
628 module_exit(au_ide_exit);