ide: move ide_config_drive_speed() calls to upper layers (take 2)
[linux-2.6.git] / drivers / ide / arm / icside.c
1 /*
2  * linux/drivers/ide/arm/icside.c
3  *
4  * Copyright (c) 1996-2004 Russell King.
5  *
6  * Please note that this platform does not support 32-bit IDE IO.
7  */
8
9 #include <linux/string.h>
10 #include <linux/module.h>
11 #include <linux/ioport.h>
12 #include <linux/slab.h>
13 #include <linux/blkdev.h>
14 #include <linux/errno.h>
15 #include <linux/hdreg.h>
16 #include <linux/ide.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/device.h>
19 #include <linux/init.h>
20 #include <linux/scatterlist.h>
21 #include <linux/io.h>
22
23 #include <asm/dma.h>
24 #include <asm/ecard.h>
25
26 #define ICS_IDENT_OFFSET                0x2280
27
28 #define ICS_ARCIN_V5_INTRSTAT           0x0000
29 #define ICS_ARCIN_V5_INTROFFSET         0x0004
30 #define ICS_ARCIN_V5_IDEOFFSET          0x2800
31 #define ICS_ARCIN_V5_IDEALTOFFSET       0x2b80
32 #define ICS_ARCIN_V5_IDESTEPPING        6
33
34 #define ICS_ARCIN_V6_IDEOFFSET_1        0x2000
35 #define ICS_ARCIN_V6_INTROFFSET_1       0x2200
36 #define ICS_ARCIN_V6_INTRSTAT_1         0x2290
37 #define ICS_ARCIN_V6_IDEALTOFFSET_1     0x2380
38 #define ICS_ARCIN_V6_IDEOFFSET_2        0x3000
39 #define ICS_ARCIN_V6_INTROFFSET_2       0x3200
40 #define ICS_ARCIN_V6_INTRSTAT_2         0x3290
41 #define ICS_ARCIN_V6_IDEALTOFFSET_2     0x3380
42 #define ICS_ARCIN_V6_IDESTEPPING        6
43
44 struct cardinfo {
45         unsigned int dataoffset;
46         unsigned int ctrloffset;
47         unsigned int stepping;
48 };
49
50 static struct cardinfo icside_cardinfo_v5 = {
51         .dataoffset     = ICS_ARCIN_V5_IDEOFFSET,
52         .ctrloffset     = ICS_ARCIN_V5_IDEALTOFFSET,
53         .stepping       = ICS_ARCIN_V5_IDESTEPPING,
54 };
55
56 static struct cardinfo icside_cardinfo_v6_1 = {
57         .dataoffset     = ICS_ARCIN_V6_IDEOFFSET_1,
58         .ctrloffset     = ICS_ARCIN_V6_IDEALTOFFSET_1,
59         .stepping       = ICS_ARCIN_V6_IDESTEPPING,
60 };
61
62 static struct cardinfo icside_cardinfo_v6_2 = {
63         .dataoffset     = ICS_ARCIN_V6_IDEOFFSET_2,
64         .ctrloffset     = ICS_ARCIN_V6_IDEALTOFFSET_2,
65         .stepping       = ICS_ARCIN_V6_IDESTEPPING,
66 };
67
68 struct icside_state {
69         unsigned int channel;
70         unsigned int enabled;
71         void __iomem *irq_port;
72         void __iomem *ioc_base;
73         unsigned int type;
74         /* parent device... until the IDE core gets one of its own */
75         struct device *dev;
76         ide_hwif_t *hwif[2];
77 };
78
79 #define ICS_TYPE_A3IN   0
80 #define ICS_TYPE_A3USER 1
81 #define ICS_TYPE_V6     3
82 #define ICS_TYPE_V5     15
83 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
84
85 /* ---------------- Version 5 PCB Support Functions --------------------- */
86 /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
87  * Purpose  : enable interrupts from card
88  */
89 static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
90 {
91         struct icside_state *state = ec->irq_data;
92
93         writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
94 }
95
96 /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
97  * Purpose  : disable interrupts from card
98  */
99 static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
100 {
101         struct icside_state *state = ec->irq_data;
102
103         readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
104 }
105
106 static const expansioncard_ops_t icside_ops_arcin_v5 = {
107         .irqenable      = icside_irqenable_arcin_v5,
108         .irqdisable     = icside_irqdisable_arcin_v5,
109 };
110
111
112 /* ---------------- Version 6 PCB Support Functions --------------------- */
113 /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
114  * Purpose  : enable interrupts from card
115  */
116 static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
117 {
118         struct icside_state *state = ec->irq_data;
119         void __iomem *base = state->irq_port;
120
121         state->enabled = 1;
122
123         switch (state->channel) {
124         case 0:
125                 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
126                 readb(base + ICS_ARCIN_V6_INTROFFSET_2);
127                 break;
128         case 1:
129                 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
130                 readb(base + ICS_ARCIN_V6_INTROFFSET_1);
131                 break;
132         }
133 }
134
135 /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
136  * Purpose  : disable interrupts from card
137  */
138 static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
139 {
140         struct icside_state *state = ec->irq_data;
141
142         state->enabled = 0;
143
144         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
145         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
146 }
147
148 /* Prototype: icside_irqprobe(struct expansion_card *ec)
149  * Purpose  : detect an active interrupt from card
150  */
151 static int icside_irqpending_arcin_v6(struct expansion_card *ec)
152 {
153         struct icside_state *state = ec->irq_data;
154
155         return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
156                readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
157 }
158
159 static const expansioncard_ops_t icside_ops_arcin_v6 = {
160         .irqenable      = icside_irqenable_arcin_v6,
161         .irqdisable     = icside_irqdisable_arcin_v6,
162         .irqpending     = icside_irqpending_arcin_v6,
163 };
164
165 /*
166  * Handle routing of interrupts.  This is called before
167  * we write the command to the drive.
168  */
169 static void icside_maskproc(ide_drive_t *drive, int mask)
170 {
171         ide_hwif_t *hwif = HWIF(drive);
172         struct icside_state *state = hwif->hwif_data;
173         unsigned long flags;
174
175         local_irq_save(flags);
176
177         state->channel = hwif->channel;
178
179         if (state->enabled && !mask) {
180                 switch (hwif->channel) {
181                 case 0:
182                         writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
183                         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
184                         break;
185                 case 1:
186                         writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
187                         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
188                         break;
189                 }
190         } else {
191                 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
192                 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
193         }
194
195         local_irq_restore(flags);
196 }
197
198 #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
199 /*
200  * SG-DMA support.
201  *
202  * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
203  * There is only one DMA controller per card, which means that only
204  * one drive can be accessed at one time.  NOTE! We do not enforce that
205  * here, but we rely on the main IDE driver spotting that both
206  * interfaces use the same IRQ, which should guarantee this.
207  */
208
209 static void icside_build_sglist(ide_drive_t *drive, struct request *rq)
210 {
211         ide_hwif_t *hwif = drive->hwif;
212         struct icside_state *state = hwif->hwif_data;
213         struct scatterlist *sg = hwif->sg_table;
214
215         ide_map_sg(drive, rq);
216
217         if (rq_data_dir(rq) == READ)
218                 hwif->sg_dma_direction = DMA_FROM_DEVICE;
219         else
220                 hwif->sg_dma_direction = DMA_TO_DEVICE;
221
222         hwif->sg_nents = dma_map_sg(state->dev, sg, hwif->sg_nents,
223                                     hwif->sg_dma_direction);
224 }
225
226 /*
227  * Configure the IOMD to give the appropriate timings for the transfer
228  * mode being requested.  We take the advice of the ATA standards, and
229  * calculate the cycle time based on the transfer mode, and the EIDE
230  * MW DMA specs that the drive provides in the IDENTIFY command.
231  *
232  * We have the following IOMD DMA modes to choose from:
233  *
234  *      Type    Active          Recovery        Cycle
235  *      A       250 (250)       312 (550)       562 (800)
236  *      B       187             250             437
237  *      C       125 (125)       125 (375)       250 (500)
238  *      D       62              125             187
239  *
240  * (figures in brackets are actual measured timings)
241  *
242  * However, we also need to take care of the read/write active and
243  * recovery timings:
244  *
245  *                      Read    Write
246  *      Mode    Active  -- Recovery --  Cycle   IOMD type
247  *      MW0     215     50      215     480     A
248  *      MW1     80      50      50      150     C
249  *      MW2     70      25      25      120     C
250  */
251 static void icside_set_dma_mode(ide_drive_t *drive, const u8 xfer_mode)
252 {
253         int cycle_time, use_dma_info = 0;
254
255         switch (xfer_mode) {
256         case XFER_MW_DMA_2:
257                 cycle_time = 250;
258                 use_dma_info = 1;
259                 break;
260
261         case XFER_MW_DMA_1:
262                 cycle_time = 250;
263                 use_dma_info = 1;
264                 break;
265
266         case XFER_MW_DMA_0:
267                 cycle_time = 480;
268                 break;
269
270         case XFER_SW_DMA_2:
271         case XFER_SW_DMA_1:
272         case XFER_SW_DMA_0:
273                 cycle_time = 480;
274                 break;
275         default:
276                 return;
277         }
278
279         /*
280          * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
281          * take care to note the values in the ID...
282          */
283         if (use_dma_info && drive->id->eide_dma_time > cycle_time)
284                 cycle_time = drive->id->eide_dma_time;
285
286         drive->drive_data = cycle_time;
287
288         printk("%s: %s selected (peak %dMB/s)\n", drive->name,
289                 ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data);
290 }
291
292 static void icside_dma_host_off(ide_drive_t *drive)
293 {
294 }
295
296 static void icside_dma_off_quietly(ide_drive_t *drive)
297 {
298         drive->using_dma = 0;
299 }
300
301 static void icside_dma_host_on(ide_drive_t *drive)
302 {
303 }
304
305 static int icside_dma_on(ide_drive_t *drive)
306 {
307         drive->using_dma = 1;
308
309         return 0;
310 }
311
312 static int icside_dma_check(ide_drive_t *drive)
313 {
314         if (ide_tune_dma(drive))
315                 return 0;
316
317         return -1;
318 }
319
320 static int icside_dma_end(ide_drive_t *drive)
321 {
322         ide_hwif_t *hwif = HWIF(drive);
323         struct icside_state *state = hwif->hwif_data;
324
325         drive->waiting_for_dma = 0;
326
327         disable_dma(hwif->hw.dma);
328
329         /* Teardown mappings after DMA has completed. */
330         dma_unmap_sg(state->dev, hwif->sg_table, hwif->sg_nents,
331                      hwif->sg_dma_direction);
332
333         return get_dma_residue(hwif->hw.dma) != 0;
334 }
335
336 static void icside_dma_start(ide_drive_t *drive)
337 {
338         ide_hwif_t *hwif = HWIF(drive);
339
340         /* We can not enable DMA on both channels simultaneously. */
341         BUG_ON(dma_channel_active(hwif->hw.dma));
342         enable_dma(hwif->hw.dma);
343 }
344
345 static int icside_dma_setup(ide_drive_t *drive)
346 {
347         ide_hwif_t *hwif = HWIF(drive);
348         struct request *rq = hwif->hwgroup->rq;
349         unsigned int dma_mode;
350
351         if (rq_data_dir(rq))
352                 dma_mode = DMA_MODE_WRITE;
353         else
354                 dma_mode = DMA_MODE_READ;
355
356         /*
357          * We can not enable DMA on both channels.
358          */
359         BUG_ON(dma_channel_active(hwif->hw.dma));
360
361         icside_build_sglist(drive, rq);
362
363         /*
364          * Ensure that we have the right interrupt routed.
365          */
366         icside_maskproc(drive, 0);
367
368         /*
369          * Route the DMA signals to the correct interface.
370          */
371         writeb(hwif->select_data, hwif->config_data);
372
373         /*
374          * Select the correct timing for this drive.
375          */
376         set_dma_speed(hwif->hw.dma, drive->drive_data);
377
378         /*
379          * Tell the DMA engine about the SG table and
380          * data direction.
381          */
382         set_dma_sg(hwif->hw.dma, hwif->sg_table, hwif->sg_nents);
383         set_dma_mode(hwif->hw.dma, dma_mode);
384
385         drive->waiting_for_dma = 1;
386
387         return 0;
388 }
389
390 static void icside_dma_exec_cmd(ide_drive_t *drive, u8 cmd)
391 {
392         /* issue cmd to drive */
393         ide_execute_command(drive, cmd, ide_dma_intr, 2 * WAIT_CMD, NULL);
394 }
395
396 static int icside_dma_test_irq(ide_drive_t *drive)
397 {
398         ide_hwif_t *hwif = HWIF(drive);
399         struct icside_state *state = hwif->hwif_data;
400
401         return readb(state->irq_port +
402                      (hwif->channel ?
403                         ICS_ARCIN_V6_INTRSTAT_2 :
404                         ICS_ARCIN_V6_INTRSTAT_1)) & 1;
405 }
406
407 static void icside_dma_timeout(ide_drive_t *drive)
408 {
409         printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
410
411         if (icside_dma_test_irq(drive))
412                 return;
413
414         ide_dump_status(drive, "DMA timeout", HWIF(drive)->INB(IDE_STATUS_REG));
415
416         icside_dma_end(drive);
417 }
418
419 static void icside_dma_lost_irq(ide_drive_t *drive)
420 {
421         printk(KERN_ERR "%s: IRQ lost\n", drive->name);
422 }
423
424 static void icside_dma_init(ide_hwif_t *hwif)
425 {
426         printk("    %s: SG-DMA", hwif->name);
427
428         hwif->atapi_dma         = 1;
429         hwif->mwdma_mask        = 7; /* MW0..2 */
430         hwif->swdma_mask        = 7; /* SW0..2 */
431
432         hwif->dmatable_cpu      = NULL;
433         hwif->dmatable_dma      = 0;
434         hwif->set_dma_mode      = icside_set_dma_mode;
435         hwif->autodma           = 1;
436
437         hwif->ide_dma_check     = icside_dma_check;
438         hwif->dma_host_off      = icside_dma_host_off;
439         hwif->dma_off_quietly   = icside_dma_off_quietly;
440         hwif->dma_host_on       = icside_dma_host_on;
441         hwif->ide_dma_on        = icside_dma_on;
442         hwif->dma_setup         = icside_dma_setup;
443         hwif->dma_exec_cmd      = icside_dma_exec_cmd;
444         hwif->dma_start         = icside_dma_start;
445         hwif->ide_dma_end       = icside_dma_end;
446         hwif->ide_dma_test_irq  = icside_dma_test_irq;
447         hwif->dma_timeout       = icside_dma_timeout;
448         hwif->dma_lost_irq      = icside_dma_lost_irq;
449
450         hwif->drives[0].autodma = hwif->autodma;
451         hwif->drives[1].autodma = hwif->autodma;
452
453         printk(" capable%s\n", hwif->autodma ? ", auto-enable" : "");
454 }
455 #else
456 #define icside_dma_init(hwif)   (0)
457 #endif
458
459 static ide_hwif_t *icside_find_hwif(unsigned long dataport)
460 {
461         ide_hwif_t *hwif;
462         int index;
463
464         for (index = 0; index < MAX_HWIFS; ++index) {
465                 hwif = &ide_hwifs[index];
466                 if (hwif->io_ports[IDE_DATA_OFFSET] == dataport)
467                         goto found;
468         }
469
470         for (index = 0; index < MAX_HWIFS; ++index) {
471                 hwif = &ide_hwifs[index];
472                 if (!hwif->io_ports[IDE_DATA_OFFSET])
473                         goto found;
474         }
475
476         hwif = NULL;
477 found:
478         return hwif;
479 }
480
481 static ide_hwif_t *
482 icside_setup(void __iomem *base, struct cardinfo *info, struct expansion_card *ec)
483 {
484         unsigned long port = (unsigned long)base + info->dataoffset;
485         ide_hwif_t *hwif;
486
487         hwif = icside_find_hwif(port);
488         if (hwif) {
489                 int i;
490
491                 memset(&hwif->hw, 0, sizeof(hw_regs_t));
492
493                 /*
494                  * Ensure we're using MMIO
495                  */
496                 default_hwif_mmiops(hwif);
497                 hwif->mmio = 1;
498
499                 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
500                         hwif->hw.io_ports[i] = port;
501                         hwif->io_ports[i] = port;
502                         port += 1 << info->stepping;
503                 }
504                 hwif->hw.io_ports[IDE_CONTROL_OFFSET] = (unsigned long)base + info->ctrloffset;
505                 hwif->io_ports[IDE_CONTROL_OFFSET] = (unsigned long)base + info->ctrloffset;
506                 hwif->hw.irq  = ec->irq;
507                 hwif->irq     = ec->irq;
508                 hwif->noprobe = 0;
509                 hwif->chipset = ide_acorn;
510                 hwif->gendev.parent = &ec->dev;
511         }
512
513         return hwif;
514 }
515
516 static int __init
517 icside_register_v5(struct icside_state *state, struct expansion_card *ec)
518 {
519         ide_hwif_t *hwif;
520         void __iomem *base;
521
522         base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0);
523         if (!base)
524                 return -ENOMEM;
525
526         state->irq_port = base;
527
528         ec->irqaddr  = base + ICS_ARCIN_V5_INTRSTAT;
529         ec->irqmask  = 1;
530
531         ecard_setirq(ec, &icside_ops_arcin_v5, state);
532
533         /*
534          * Be on the safe side - disable interrupts
535          */
536         icside_irqdisable_arcin_v5(ec, 0);
537
538         hwif = icside_setup(base, &icside_cardinfo_v5, ec);
539         if (!hwif)
540                 return -ENODEV;
541
542         state->hwif[0] = hwif;
543
544         probe_hwif_init(hwif);
545
546         ide_proc_register_port(hwif);
547
548         return 0;
549 }
550
551 static int __init
552 icside_register_v6(struct icside_state *state, struct expansion_card *ec)
553 {
554         ide_hwif_t *hwif, *mate;
555         void __iomem *ioc_base, *easi_base;
556         unsigned int sel = 0;
557         int ret;
558
559         ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
560         if (!ioc_base) {
561                 ret = -ENOMEM;
562                 goto out;
563         }
564
565         easi_base = ioc_base;
566
567         if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
568                 easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
569                 if (!easi_base) {
570                         ret = -ENOMEM;
571                         goto out;
572                 }
573
574                 /*
575                  * Enable access to the EASI region.
576                  */
577                 sel = 1 << 5;
578         }
579
580         writeb(sel, ioc_base);
581
582         ecard_setirq(ec, &icside_ops_arcin_v6, state);
583
584         state->irq_port   = easi_base;
585         state->ioc_base   = ioc_base;
586
587         /*
588          * Be on the safe side - disable interrupts
589          */
590         icside_irqdisable_arcin_v6(ec, 0);
591
592         /*
593          * Find and register the interfaces.
594          */
595         hwif = icside_setup(easi_base, &icside_cardinfo_v6_1, ec);
596         mate = icside_setup(easi_base, &icside_cardinfo_v6_2, ec);
597
598         if (!hwif || !mate) {
599                 ret = -ENODEV;
600                 goto out;
601         }
602
603         state->hwif[0]    = hwif;
604         state->hwif[1]    = mate;
605
606         hwif->maskproc    = icside_maskproc;
607         hwif->channel     = 0;
608         hwif->hwif_data   = state;
609         hwif->mate        = mate;
610         hwif->serialized  = 1;
611         hwif->config_data = (unsigned long)ioc_base;
612         hwif->select_data = sel;
613         hwif->hw.dma      = ec->dma;
614
615         mate->maskproc    = icside_maskproc;
616         mate->channel     = 1;
617         mate->hwif_data   = state;
618         mate->mate        = hwif;
619         mate->serialized  = 1;
620         mate->config_data = (unsigned long)ioc_base;
621         mate->select_data = sel | 1;
622         mate->hw.dma      = ec->dma;
623
624         if (ec->dma != NO_DMA && !request_dma(ec->dma, hwif->name)) {
625                 icside_dma_init(hwif);
626                 icside_dma_init(mate);
627         }
628
629         probe_hwif_init(hwif);
630         probe_hwif_init(mate);
631
632         ide_proc_register_port(hwif);
633         ide_proc_register_port(mate);
634
635         return 0;
636
637  out:
638         return ret;
639 }
640
641 static int __devinit
642 icside_probe(struct expansion_card *ec, const struct ecard_id *id)
643 {
644         struct icside_state *state;
645         void __iomem *idmem;
646         int ret;
647
648         ret = ecard_request_resources(ec);
649         if (ret)
650                 goto out;
651
652         state = kzalloc(sizeof(struct icside_state), GFP_KERNEL);
653         if (!state) {
654                 ret = -ENOMEM;
655                 goto release;
656         }
657
658         state->type     = ICS_TYPE_NOTYPE;
659         state->dev      = &ec->dev;
660
661         idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
662         if (idmem) {
663                 unsigned int type;
664
665                 type = readb(idmem + ICS_IDENT_OFFSET) & 1;
666                 type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
667                 type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
668                 type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
669                 ecardm_iounmap(ec, idmem);
670
671                 state->type = type;
672         }
673
674         switch (state->type) {
675         case ICS_TYPE_A3IN:
676                 dev_warn(&ec->dev, "A3IN unsupported\n");
677                 ret = -ENODEV;
678                 break;
679
680         case ICS_TYPE_A3USER:
681                 dev_warn(&ec->dev, "A3USER unsupported\n");
682                 ret = -ENODEV;
683                 break;
684
685         case ICS_TYPE_V5:
686                 ret = icside_register_v5(state, ec);
687                 break;
688
689         case ICS_TYPE_V6:
690                 ret = icside_register_v6(state, ec);
691                 break;
692
693         default:
694                 dev_warn(&ec->dev, "unknown interface type\n");
695                 ret = -ENODEV;
696                 break;
697         }
698
699         if (ret == 0) {
700                 ecard_set_drvdata(ec, state);
701                 goto out;
702         }
703
704         kfree(state);
705  release:
706         ecard_release_resources(ec);
707  out:
708         return ret;
709 }
710
711 static void __devexit icside_remove(struct expansion_card *ec)
712 {
713         struct icside_state *state = ecard_get_drvdata(ec);
714
715         switch (state->type) {
716         case ICS_TYPE_V5:
717                 /* FIXME: tell IDE to stop using the interface */
718
719                 /* Disable interrupts */
720                 icside_irqdisable_arcin_v5(ec, 0);
721                 break;
722
723         case ICS_TYPE_V6:
724                 /* FIXME: tell IDE to stop using the interface */
725                 if (ec->dma != NO_DMA)
726                         free_dma(ec->dma);
727
728                 /* Disable interrupts */
729                 icside_irqdisable_arcin_v6(ec, 0);
730
731                 /* Reset the ROM pointer/EASI selection */
732                 writeb(0, state->ioc_base);
733                 break;
734         }
735
736         ecard_set_drvdata(ec, NULL);
737
738         kfree(state);
739         ecard_release_resources(ec);
740 }
741
742 static void icside_shutdown(struct expansion_card *ec)
743 {
744         struct icside_state *state = ecard_get_drvdata(ec);
745         unsigned long flags;
746
747         /*
748          * Disable interrupts from this card.  We need to do
749          * this before disabling EASI since we may be accessing
750          * this register via that region.
751          */
752         local_irq_save(flags);
753         ec->ops->irqdisable(ec, 0);
754         local_irq_restore(flags);
755
756         /*
757          * Reset the ROM pointer so that we can read the ROM
758          * after a soft reboot.  This also disables access to
759          * the IDE taskfile via the EASI region.
760          */
761         if (state->ioc_base)
762                 writeb(0, state->ioc_base);
763 }
764
765 static const struct ecard_id icside_ids[] = {
766         { MANU_ICS,  PROD_ICS_IDE  },
767         { MANU_ICS2, PROD_ICS2_IDE },
768         { 0xffff, 0xffff }
769 };
770
771 static struct ecard_driver icside_driver = {
772         .probe          = icside_probe,
773         .remove         = __devexit_p(icside_remove),
774         .shutdown       = icside_shutdown,
775         .id_table       = icside_ids,
776         .drv = {
777                 .name   = "icside",
778         },
779 };
780
781 static int __init icside_init(void)
782 {
783         return ecard_register_driver(&icside_driver);
784 }
785
786 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
787 MODULE_LICENSE("GPL");
788 MODULE_DESCRIPTION("ICS IDE driver");
789
790 module_init(icside_init);