i2c: tegra: use of_match_ptr() for match_table initialization
[linux-2.6.git] / drivers / i2c / busses / i2c-tegra.c
1 /*
2  * drivers/i2c/busses/i2c-tegra.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Colin Cross <ccross@android.com>
6  *
7  * Copyright (C) 2010-2012 NVIDIA Corporation
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 /*#define DEBUG           1*/
21 /*#define VERBOSE_DEBUG   1*/
22
23 #include <linux/kernel.h>
24 #include <linux/init.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/err.h>
28 #include <linux/i2c.h>
29 #include <linux/io.h>
30 #include <linux/interrupt.h>
31 #include <linux/delay.h>
32 #include <linux/slab.h>
33 #include <linux/i2c-tegra.h>
34 #include <linux/of_i2c.h>
35 #include <linux/spinlock.h>
36
37 #include <asm/unaligned.h>
38
39 #include <mach/clk.h>
40 #include <mach/pinmux.h>
41
42 #define TEGRA_I2C_TIMEOUT                       (msecs_to_jiffies(1000))
43 #define TEGRA_I2C_RETRIES                       3
44 #define BYTES_PER_FIFO_WORD                     4
45
46 #define I2C_CNFG                                0x000
47 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT             12
48 #define I2C_CNFG_PACKET_MODE_EN                 (1<<10)
49 #define I2C_CNFG_NEW_MASTER_FSM                 (1<<11)
50 #define I2C_STATUS                              0x01C
51 #define I2C_STATUS_BUSY                         (1<<8)
52 #define I2C_SL_CNFG                             0x020
53 #define I2C_SL_CNFG_NACK                        (1<<1)
54 #define I2C_SL_CNFG_NEWSL                       (1<<2)
55 #define I2C_SL_ADDR1                            0x02c
56 #define I2C_SL_ADDR2                            0x030
57 #define I2C_TX_FIFO                             0x050
58 #define I2C_RX_FIFO                             0x054
59 #define I2C_PACKET_TRANSFER_STATUS              0x058
60 #define I2C_FIFO_CONTROL                        0x05c
61 #define I2C_FIFO_CONTROL_TX_FLUSH               (1<<1)
62 #define I2C_FIFO_CONTROL_RX_FLUSH               (1<<0)
63 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT          5
64 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT          2
65 #define I2C_FIFO_STATUS                         0x060
66 #define I2C_FIFO_STATUS_TX_MASK                 0xF0
67 #define I2C_FIFO_STATUS_TX_SHIFT                4
68 #define I2C_FIFO_STATUS_RX_MASK                 0x0F
69 #define I2C_FIFO_STATUS_RX_SHIFT                0
70 #define I2C_INT_MASK                            0x064
71 #define I2C_INT_STATUS                          0x068
72 #define I2C_INT_PACKET_XFER_COMPLETE            (1<<7)
73 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE       (1<<6)
74 #define I2C_INT_TX_FIFO_OVERFLOW                (1<<5)
75 #define I2C_INT_RX_FIFO_UNDERFLOW               (1<<4)
76 #define I2C_INT_NO_ACK                          (1<<3)
77 #define I2C_INT_ARBITRATION_LOST                (1<<2)
78 #define I2C_INT_TX_FIFO_DATA_REQ                (1<<1)
79 #define I2C_INT_RX_FIFO_DATA_REQ                (1<<0)
80 #define I2C_CLK_DIVISOR                         0x06c
81
82 #define DVC_CTRL_REG1                           0x000
83 #define DVC_CTRL_REG1_INTR_EN                   (1<<10)
84 #define DVC_CTRL_REG2                           0x004
85 #define DVC_CTRL_REG3                           0x008
86 #define DVC_CTRL_REG3_SW_PROG                   (1<<26)
87 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN          (1<<30)
88 #define DVC_STATUS                              0x00c
89 #define DVC_STATUS_I2C_DONE_INTR                (1<<30)
90
91 #define I2C_ERR_NONE                            0x00
92 #define I2C_ERR_NO_ACK                          0x01
93 #define I2C_ERR_ARBITRATION_LOST                0x02
94 #define I2C_ERR_UNKNOWN_INTERRUPT               0x04
95 #define I2C_ERR_UNEXPECTED_STATUS               0x08
96
97 #define PACKET_HEADER0_HEADER_SIZE_SHIFT        28
98 #define PACKET_HEADER0_PACKET_ID_SHIFT          16
99 #define PACKET_HEADER0_CONT_ID_SHIFT            12
100 #define PACKET_HEADER0_PROTOCOL_I2C             (1<<4)
101
102 #define I2C_HEADER_HIGHSPEED_MODE               (1<<22)
103 #define I2C_HEADER_CONT_ON_NAK                  (1<<21)
104 #define I2C_HEADER_SEND_START_BYTE              (1<<20)
105 #define I2C_HEADER_READ                         (1<<19)
106 #define I2C_HEADER_10BIT_ADDR                   (1<<18)
107 #define I2C_HEADER_IE_ENABLE                    (1<<17)
108 #define I2C_HEADER_REPEAT_START                 (1<<16)
109 #define I2C_HEADER_CONTINUE_XFER                (1<<15)
110 #define I2C_HEADER_MASTER_ADDR_SHIFT            12
111 #define I2C_HEADER_SLAVE_ADDR_SHIFT             1
112
113 #define SL_ADDR1(addr) (addr & 0xff)
114 #define SL_ADDR2(addr) ((addr >> 8) & 0xff)
115
116 /*
117  * msg_end_type: The bus control which need to be send at end of transfer.
118  * @MSG_END_STOP: Send stop pulse at end of transfer.
119  * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
120  * @MSG_END_CONTINUE: The following on message is coming and so do not send
121  *              stop or repeat start.
122  */
123
124 enum msg_end_type {
125         MSG_END_STOP,
126         MSG_END_REPEAT_START,
127         MSG_END_CONTINUE,
128 };
129
130 struct tegra_i2c_dev;
131
132 struct tegra_i2c_bus {
133         struct tegra_i2c_dev *dev;
134         const struct tegra_pingroup_config *mux;
135         int mux_len;
136         unsigned long bus_clk_rate;
137         struct i2c_adapter adapter;
138         int scl_gpio;
139         int sda_gpio;
140 };
141
142 /**
143  * struct tegra_i2c_dev - per device i2c context
144  * @dev: device reference for power management
145  * @adapter: core i2c layer adapter information
146  * @clk: clock reference for i2c controller
147  * @i2c_clk: clock reference for i2c bus
148  * @iomem: memory resource for registers
149  * @base: ioremapped registers cookie
150  * @cont_id: i2c controller id, used for for packet header
151  * @irq: irq number of transfer complete interrupt
152  * @is_dvc: identifies the DVC i2c controller, has a different register layout
153  * @msg_complete: transfer completion notifier
154  * @msg_err: error code for completed message
155  * @msg_buf: pointer to current message data
156  * @msg_buf_remaining: size of unsent data in the message buffer
157  * @msg_read: identifies read transfers
158  * @bus_clk_rate: current i2c bus clock rate
159  * @is_suspended: prevents i2c controller accesses after suspend is called
160  */
161 struct tegra_i2c_dev {
162         struct device *dev;
163         struct clk *div_clk;
164         struct clk *fast_clk;
165         struct resource *iomem;
166         struct rt_mutex dev_lock;
167         spinlock_t fifo_lock;
168         void __iomem *base;
169         int cont_id;
170         int irq;
171         bool irq_disabled;
172         int is_dvc;
173         bool is_slave;
174         struct completion msg_complete;
175         int msg_err;
176         u8 *msg_buf;
177         u32 packet_header;
178         u32 payload_size;
179         u32 io_header;
180         size_t msg_buf_remaining;
181         int msg_read;
182         struct i2c_msg *msgs;
183         int msg_add;
184         int msgs_num;
185         bool is_suspended;
186         int bus_count;
187         const struct tegra_pingroup_config *last_mux;
188         int last_mux_len;
189         unsigned long last_bus_clk_rate;
190         u16 slave_addr;
191         bool is_clkon_always;
192         bool is_high_speed_enable;
193         u16 hs_master_code;
194         int (*arb_recovery)(int scl_gpio, int sda_gpio);
195         struct tegra_i2c_bus busses[1];
196 };
197
198 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
199 {
200         writel(val, i2c_dev->base + reg);
201 }
202
203 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
204 {
205         return readl(i2c_dev->base + reg);
206 }
207
208 static void dvc_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
209 {
210         u32 int_mask = dvc_readl(i2c_dev, DVC_CTRL_REG3);
211         int_mask &= ~mask;
212         dvc_writel(i2c_dev, int_mask, DVC_CTRL_REG3);
213 }
214
215 static void dvc_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
216 {
217         u32 int_mask = dvc_readl(i2c_dev, DVC_CTRL_REG3);
218         int_mask |= mask;
219         dvc_writel(i2c_dev, int_mask, DVC_CTRL_REG3);
220 }
221
222 /*
223  * i2c_writel and i2c_readl will offset the register if necessary to talk
224  * to the I2C block inside the DVC block
225  */
226 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
227         unsigned long reg)
228 {
229         if (i2c_dev->is_dvc)
230                 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
231         return reg;
232 }
233
234 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
235         unsigned long reg)
236 {
237         writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
238 }
239
240 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
241 {
242         return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
243 }
244
245 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
246         unsigned long reg, int len)
247 {
248         writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
249 }
250
251 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
252         unsigned long reg, int len)
253 {
254         readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
255 }
256
257 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
258 {
259         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
260         int_mask &= ~mask;
261         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
262 }
263
264 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
265 {
266         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
267         int_mask |= mask;
268         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
269 }
270
271 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
272 {
273         unsigned long timeout = jiffies + HZ;
274         u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
275         val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
276         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
277
278         while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
279                 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
280                 if (time_after(jiffies, timeout)) {
281                         dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
282                         return -ETIMEDOUT;
283                 }
284                 msleep(1);
285         }
286         return 0;
287 }
288
289 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
290 {
291         u32 val;
292         int rx_fifo_avail;
293         u8 *buf = i2c_dev->msg_buf;
294         size_t buf_remaining = i2c_dev->msg_buf_remaining;
295         int words_to_transfer;
296
297         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
298         rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
299                 I2C_FIFO_STATUS_RX_SHIFT;
300
301         /* Rounds down to not include partial word at the end of buf */
302         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
303         if (words_to_transfer > rx_fifo_avail)
304                 words_to_transfer = rx_fifo_avail;
305
306         i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
307
308         buf += words_to_transfer * BYTES_PER_FIFO_WORD;
309         buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
310         rx_fifo_avail -= words_to_transfer;
311
312         /*
313          * If there is a partial word at the end of buf, handle it manually to
314          * prevent overwriting past the end of buf
315          */
316         if (rx_fifo_avail > 0 && buf_remaining > 0) {
317                 BUG_ON(buf_remaining > 3);
318                 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
319                 memcpy(buf, &val, buf_remaining);
320                 buf_remaining = 0;
321                 rx_fifo_avail--;
322         }
323
324         BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
325         i2c_dev->msg_buf_remaining = buf_remaining;
326         i2c_dev->msg_buf = buf;
327         return 0;
328 }
329
330 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
331 {
332         u32 val;
333         int tx_fifo_avail;
334         u8 *buf;
335         size_t buf_remaining;
336         int words_to_transfer;
337         unsigned long flags;
338
339         spin_lock_irqsave(&i2c_dev->fifo_lock, flags);
340         if (!i2c_dev->msg_buf_remaining) {
341                 spin_unlock_irqrestore(&i2c_dev->fifo_lock, flags);
342                 return 0;
343         }
344
345         buf = i2c_dev->msg_buf;
346         buf_remaining = i2c_dev->msg_buf_remaining;
347
348         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
349         tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
350                 I2C_FIFO_STATUS_TX_SHIFT;
351
352         /* Rounds down to not include partial word at the end of buf */
353         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
354
355         /* It's very common to have < 4 bytes, so optimize that case. */
356         if (words_to_transfer) {
357                 if (words_to_transfer > tx_fifo_avail)
358                         words_to_transfer = tx_fifo_avail;
359
360                 /*
361                  * Update state before writing to FIFO.  If this casues us
362                  * to finish writing all bytes (AKA buf_remaining goes to 0) we
363                  * have a potential for an interrupt (PACKET_XFER_COMPLETE is
364                  * not maskable).  We need to make sure that the isr sees
365                  * buf_remaining as 0 and doesn't call us back re-entrantly.
366                  */
367                 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
368                 tx_fifo_avail -= words_to_transfer;
369                 i2c_dev->msg_buf_remaining = buf_remaining;
370                 i2c_dev->msg_buf = buf +
371                         words_to_transfer * BYTES_PER_FIFO_WORD;
372                 barrier();
373
374                 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
375
376                 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
377         }
378
379         /*
380          * If there is a partial word at the end of buf, handle it manually to
381          * prevent reading past the end of buf, which could cross a page
382          * boundary and fault.
383          */
384         if (tx_fifo_avail > 0 && buf_remaining > 0) {
385                 if (buf_remaining > 3) {
386                         dev_err(i2c_dev->dev,
387                                 "Remaining buffer more than 3 %d\n",
388                                 buf_remaining);
389                         BUG();
390                 }
391                 memcpy(&val, buf, buf_remaining);
392
393                 /* Again update before writing to FIFO to make sure isr sees. */
394                 i2c_dev->msg_buf_remaining = 0;
395                 i2c_dev->msg_buf = NULL;
396                 barrier();
397
398                 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
399         }
400
401         spin_unlock_irqrestore(&i2c_dev->fifo_lock, flags);
402
403         return 0;
404 }
405
406 /*
407  * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
408  * block.  This block is identical to the rest of the I2C blocks, except that
409  * it only supports master mode, it has registers moved around, and it needs
410  * some extra init to get it into I2C mode.  The register moves are handled
411  * by i2c_readl and i2c_writel
412  */
413 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
414 {
415         u32 val = 0;
416         val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
417         val |= DVC_CTRL_REG3_SW_PROG;
418         dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
419
420         val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
421         val |= DVC_CTRL_REG1_INTR_EN;
422         dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
423 }
424
425 static void tegra_i2c_slave_init(struct tegra_i2c_dev *i2c_dev)
426 {
427         u32 val = I2C_SL_CNFG_NEWSL | I2C_SL_CNFG_NACK;
428
429         i2c_writel(i2c_dev, val, I2C_SL_CNFG);
430
431         if (i2c_dev->slave_addr) {
432                 u16 addr = i2c_dev->slave_addr;
433
434                 i2c_writel(i2c_dev, SL_ADDR1(addr), I2C_SL_ADDR1);
435                 i2c_writel(i2c_dev, SL_ADDR2(addr), I2C_SL_ADDR2);
436         }
437 }
438
439 static inline int tegra_i2c_clock_enable(struct tegra_i2c_dev *i2c_dev)
440 {
441         int ret;
442         ret = clk_enable(i2c_dev->fast_clk);
443         if (ret < 0) {
444                 dev_err(i2c_dev->dev,
445                         "Error in enabling fast clock err %d\n", ret);
446                 return ret;
447         }
448         ret = clk_enable(i2c_dev->div_clk);
449         if (ret < 0) {
450                 dev_err(i2c_dev->dev,
451                         "Error in enabling div clock err %d\n", ret);
452                 clk_disable(i2c_dev->fast_clk);
453         }
454         return ret;
455 }
456
457 static inline void tegra_i2c_clock_disable(struct tegra_i2c_dev *i2c_dev)
458 {
459         clk_disable(i2c_dev->div_clk);
460         clk_disable(i2c_dev->fast_clk);
461 }
462
463 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
464 {
465         u32 val;
466         int err = 0;
467
468         if (!i2c_dev->is_clkon_always)
469                 tegra_i2c_clock_enable(i2c_dev);
470
471         /* Interrupt generated before sending stop signal so
472         * wait for some time so that stop signal can be send proerly */
473         mdelay(1);
474
475         tegra_periph_reset_assert(i2c_dev->div_clk);
476         udelay(2);
477         tegra_periph_reset_deassert(i2c_dev->div_clk);
478
479         if (i2c_dev->is_dvc)
480                 tegra_dvc_init(i2c_dev);
481
482         val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
483                 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
484         i2c_writel(i2c_dev, val, I2C_CNFG);
485         i2c_writel(i2c_dev, 0, I2C_INT_MASK);
486         clk_set_rate(i2c_dev->div_clk, i2c_dev->last_bus_clk_rate * 8);
487         i2c_writel(i2c_dev, 0x3, I2C_CLK_DIVISOR);
488
489         if (!i2c_dev->is_dvc) {
490                 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
491                 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
492                 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
493                 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
494                 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
495
496         }
497
498         val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
499                 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
500         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
501
502         if (i2c_dev->is_slave)
503                 tegra_i2c_slave_init(i2c_dev);
504
505         if (tegra_i2c_flush_fifos(i2c_dev))
506                 err = -ETIMEDOUT;
507
508         if (!i2c_dev->is_clkon_always)
509                 tegra_i2c_clock_disable(i2c_dev);
510
511         if (i2c_dev->irq_disabled) {
512                 i2c_dev->irq_disabled = 0;
513                 enable_irq(i2c_dev->irq);
514         }
515
516         return err;
517 }
518
519 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
520 {
521         u32 status;
522         const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST | I2C_INT_TX_FIFO_OVERFLOW;
523         struct tegra_i2c_dev *i2c_dev = dev_id;
524
525         status = i2c_readl(i2c_dev, I2C_INT_STATUS);
526
527         if (status == 0) {
528                 dev_warn(i2c_dev->dev, "unknown interrupt Add 0x%02x\n",
529                                                 i2c_dev->msg_add);
530                 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
531
532                 if (!i2c_dev->irq_disabled) {
533                         disable_irq_nosync(i2c_dev->irq);
534                         i2c_dev->irq_disabled = 1;
535                 }
536
537                 goto err;
538         }
539
540         if (unlikely(status & status_err)) {
541                 dev_warn(i2c_dev->dev, "I2c error status 0x%08x\n", status);
542                 if (status & I2C_INT_NO_ACK) {
543                         i2c_dev->msg_err |= I2C_ERR_NO_ACK;
544                         dev_warn(i2c_dev->dev, "no acknowledge from address"
545                                         " 0x%x\n", i2c_dev->msg_add);
546                         dev_warn(i2c_dev->dev, "Packet status 0x%08x\n",
547                                 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS));
548                 }
549
550                 if (status & I2C_INT_ARBITRATION_LOST) {
551                         i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
552                         dev_warn(i2c_dev->dev, "arbitration lost during "
553                                 " communicate to add 0x%x\n", i2c_dev->msg_add);
554                         dev_warn(i2c_dev->dev, "Packet status 0x%08x\n",
555                                 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS));
556                 }
557
558                 if (status & I2C_INT_TX_FIFO_OVERFLOW) {
559                         i2c_dev->msg_err |= I2C_INT_TX_FIFO_OVERFLOW;
560                         dev_warn(i2c_dev->dev, "Tx fifo overflow during "
561                                 " communicate to add 0x%x\n", i2c_dev->msg_add);
562                         dev_warn(i2c_dev->dev, "Packet status 0x%08x\n",
563                                 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS));
564                 }
565                 goto err;
566         }
567
568         if (unlikely((i2c_readl(i2c_dev, I2C_STATUS) & I2C_STATUS_BUSY)
569                                 && (status == I2C_INT_TX_FIFO_DATA_REQ)
570                                 && i2c_dev->msg_read
571                                 && i2c_dev->msg_buf_remaining)) {
572                 dev_warn(i2c_dev->dev, "unexpected status\n");
573                 i2c_dev->msg_err |= I2C_ERR_UNEXPECTED_STATUS;
574
575                 if (!i2c_dev->irq_disabled) {
576                         disable_irq_nosync(i2c_dev->irq);
577                         i2c_dev->irq_disabled = 1;
578                 }
579
580                 goto err;
581         }
582
583         if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
584                 if (i2c_dev->msg_buf_remaining)
585                         tegra_i2c_empty_rx_fifo(i2c_dev);
586                 else
587                         BUG();
588         }
589
590         if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
591                 if (i2c_dev->msg_buf_remaining)
592                         tegra_i2c_fill_tx_fifo(i2c_dev);
593                 else
594                         tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
595         }
596
597         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
598         i2c_readl(i2c_dev, I2C_INT_STATUS);
599
600         if (i2c_dev->is_dvc) {
601                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
602                 dvc_readl(i2c_dev, DVC_STATUS);
603         }
604
605         if (status & I2C_INT_PACKET_XFER_COMPLETE) {
606                 BUG_ON(i2c_dev->msg_buf_remaining);
607                 complete(&i2c_dev->msg_complete);
608         }
609
610         return IRQ_HANDLED;
611
612 err:
613         dev_dbg(i2c_dev->dev, "reg: 0x%08x 0x%08x 0x%08x 0x%08x\n",
614                  i2c_readl(i2c_dev, I2C_CNFG), i2c_readl(i2c_dev, I2C_STATUS),
615                  i2c_readl(i2c_dev, I2C_INT_STATUS),
616                  i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS));
617
618         dev_dbg(i2c_dev->dev, "packet: 0x%08x %u 0x%08x\n",
619                  i2c_dev->packet_header, i2c_dev->payload_size,
620                  i2c_dev->io_header);
621
622         if (i2c_dev->msgs) {
623                 struct i2c_msg *msgs = i2c_dev->msgs;
624                 int i;
625
626                 for (i = 0; i < i2c_dev->msgs_num; i++)
627                         dev_dbg(i2c_dev->dev,
628                                  "msgs[%d] %c, addr=0x%04x, len=%d\n",
629                                  i, (msgs[i].flags & I2C_M_RD) ? 'R' : 'W',
630                                  msgs[i].addr, msgs[i].len);
631         }
632
633         /* An error occurred, mask all interrupts */
634         tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
635                 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
636                 I2C_INT_RX_FIFO_DATA_REQ | I2C_INT_TX_FIFO_OVERFLOW);
637
638         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
639         i2c_readl(i2c_dev, I2C_INT_STATUS);
640
641         /* An error occured, mask dvc interrupt */
642         if (i2c_dev->is_dvc)
643                 dvc_i2c_mask_irq(i2c_dev, DVC_CTRL_REG3_I2C_DONE_INTR_EN);
644
645         if (i2c_dev->is_dvc) {
646                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
647                 dvc_readl(i2c_dev, DVC_STATUS);
648         }
649
650         complete(&i2c_dev->msg_complete);
651         return IRQ_HANDLED;
652 }
653
654 static int tegra_i2c_xfer_msg(struct tegra_i2c_bus *i2c_bus,
655         struct i2c_msg *msg, enum msg_end_type end_state)
656 {
657         struct tegra_i2c_dev *i2c_dev = i2c_bus->dev;
658         u32 int_mask;
659         int ret;
660         int arb_stat;
661
662         if (msg->len == 0)
663                 return -EINVAL;
664
665         tegra_i2c_flush_fifos(i2c_dev);
666
667         /* Toggle the direction flag if rev dir is selected */
668         if (msg->flags & I2C_M_REV_DIR_ADDR)
669                 msg->flags ^= I2C_M_RD;
670
671         i2c_dev->msg_buf = msg->buf;
672         i2c_dev->msg_buf_remaining = msg->len;
673         i2c_dev->msg_err = I2C_ERR_NONE;
674         i2c_dev->msg_read = (msg->flags & I2C_M_RD);
675         INIT_COMPLETION(i2c_dev->msg_complete);
676         i2c_dev->msg_add = msg->addr;
677
678         i2c_dev->packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
679                         PACKET_HEADER0_PROTOCOL_I2C |
680                         (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
681                         (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
682         i2c_writel(i2c_dev, i2c_dev->packet_header, I2C_TX_FIFO);
683
684         i2c_dev->payload_size = msg->len - 1;
685         i2c_writel(i2c_dev, i2c_dev->payload_size, I2C_TX_FIFO);
686
687         i2c_dev->io_header = I2C_HEADER_IE_ENABLE;
688         if (end_state == MSG_END_CONTINUE)
689                 i2c_dev->io_header |= I2C_HEADER_CONTINUE_XFER;
690         else if (end_state == MSG_END_REPEAT_START)
691                 i2c_dev->io_header |= I2C_HEADER_REPEAT_START;
692
693         if (msg->flags & I2C_M_TEN) {
694                 i2c_dev->io_header |= msg->addr;
695                 i2c_dev->io_header |= I2C_HEADER_10BIT_ADDR;
696         } else {
697                 i2c_dev->io_header |= (msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT);
698         }
699         if (msg->flags & I2C_M_IGNORE_NAK)
700                 i2c_dev->io_header |= I2C_HEADER_CONT_ON_NAK;
701         if (msg->flags & I2C_M_RD)
702                 i2c_dev->io_header |= I2C_HEADER_READ;
703         if (i2c_dev->is_high_speed_enable) {
704                 i2c_dev->io_header |= I2C_HEADER_HIGHSPEED_MODE;
705                 i2c_dev->io_header |= ((i2c_dev->hs_master_code & 0x7) <<  I2C_HEADER_MASTER_ADDR_SHIFT);
706         }
707         i2c_writel(i2c_dev, i2c_dev->io_header, I2C_TX_FIFO);
708
709         if (!(msg->flags & I2C_M_RD))
710                 tegra_i2c_fill_tx_fifo(i2c_dev);
711
712         if (i2c_dev->is_dvc)
713                 dvc_i2c_unmask_irq(i2c_dev, DVC_CTRL_REG3_I2C_DONE_INTR_EN);
714
715         int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST | I2C_INT_TX_FIFO_OVERFLOW;
716         if (msg->flags & I2C_M_RD)
717                 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
718         else if (i2c_dev->msg_buf_remaining)
719                 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
720         tegra_i2c_unmask_irq(i2c_dev, int_mask);
721         dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
722                 i2c_readl(i2c_dev, I2C_INT_MASK));
723
724         ret = wait_for_completion_timeout(&i2c_dev->msg_complete,
725                                         TEGRA_I2C_TIMEOUT);
726         tegra_i2c_mask_irq(i2c_dev, int_mask);
727
728         if (i2c_dev->is_dvc)
729                 dvc_i2c_mask_irq(i2c_dev, DVC_CTRL_REG3_I2C_DONE_INTR_EN);
730
731         /* Restore the message flag */
732         if (msg->flags & I2C_M_REV_DIR_ADDR)
733                 msg->flags ^= I2C_M_RD;
734
735         if (WARN_ON(ret == 0)) {
736                 dev_err(i2c_dev->dev,
737                         "i2c transfer timed out, addr 0x%04x, data 0x%02x\n",
738                         msg->addr, msg->buf[0]);
739
740                 tegra_i2c_init(i2c_dev);
741                 return -ETIMEDOUT;
742         }
743
744         dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n",
745                 ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
746
747         if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
748                 return 0;
749
750         /* Arbitration Lost occurs, Start recovery */
751         if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) {
752                 if (i2c_dev->arb_recovery) {
753                         arb_stat = i2c_dev->arb_recovery(i2c_bus->scl_gpio, i2c_bus->sda_gpio);
754                         if (!arb_stat)
755                                 return -EAGAIN;
756                 }
757         }
758
759         tegra_i2c_init(i2c_dev);
760
761         if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
762                 if (msg->flags & I2C_M_IGNORE_NAK)
763                         return 0;
764                 return -EREMOTEIO;
765         }
766
767         if (i2c_dev->msg_err & I2C_ERR_UNEXPECTED_STATUS)
768                 return -EAGAIN;
769
770         return -EIO;
771 }
772
773 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
774         int num)
775 {
776         struct tegra_i2c_bus *i2c_bus = i2c_get_adapdata(adap);
777         struct tegra_i2c_dev *i2c_dev = i2c_bus->dev;
778         int i;
779         int ret = 0;
780
781         rt_mutex_lock(&i2c_dev->dev_lock);
782
783         if (i2c_dev->is_suspended) {
784                 rt_mutex_unlock(&i2c_dev->dev_lock);
785                 return -EBUSY;
786         }
787
788         if (i2c_dev->last_mux != i2c_bus->mux) {
789                 tegra_pinmux_set_safe_pinmux_table(i2c_dev->last_mux,
790                         i2c_dev->last_mux_len);
791                 tegra_pinmux_config_pinmux_table(i2c_bus->mux,
792                         i2c_bus->mux_len);
793                 i2c_dev->last_mux = i2c_bus->mux;
794                 i2c_dev->last_mux_len = i2c_bus->mux_len;
795         }
796
797         if (i2c_dev->last_bus_clk_rate != i2c_bus->bus_clk_rate) {
798                 clk_set_rate(i2c_dev->div_clk, i2c_bus->bus_clk_rate * 8);
799                 i2c_dev->last_bus_clk_rate = i2c_bus->bus_clk_rate;
800         }
801
802         i2c_dev->msgs = msgs;
803         i2c_dev->msgs_num = num;
804
805         if (!i2c_dev->is_clkon_always)
806                 tegra_i2c_clock_enable(i2c_dev);
807
808         for (i = 0; i < num; i++) {
809                 enum msg_end_type end_type = MSG_END_STOP;
810                 if (i < (num - 1)) {
811                         if (msgs[i + 1].flags & I2C_M_NOSTART)
812                                 end_type = MSG_END_CONTINUE;
813                         else
814                                 end_type = MSG_END_REPEAT_START;
815                 }
816                 ret = tegra_i2c_xfer_msg(i2c_bus, &msgs[i], end_type);
817                 if (ret)
818                         break;
819         }
820
821         if (!i2c_dev->is_clkon_always)
822                 tegra_i2c_clock_disable(i2c_dev);
823
824         rt_mutex_unlock(&i2c_dev->dev_lock);
825
826         i2c_dev->msgs = NULL;
827         i2c_dev->msgs_num = 0;
828
829         return ret ?: i;
830 }
831
832 static u32 tegra_i2c_func(struct i2c_adapter *adap)
833 {
834         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR |
835                         I2C_FUNC_PROTOCOL_MANGLING;
836 }
837
838 static const struct i2c_algorithm tegra_i2c_algo = {
839         .master_xfer    = tegra_i2c_xfer,
840         .functionality  = tegra_i2c_func,
841 };
842
843 static int tegra_i2c_probe(struct platform_device *pdev)
844 {
845         struct tegra_i2c_dev *i2c_dev;
846         struct tegra_i2c_platform_data *plat = pdev->dev.platform_data;
847         struct resource *res;
848         struct resource *iomem;
849         struct clk *div_clk;
850         struct clk *fast_clk = NULL;
851         const unsigned int *prop;
852         void *base;
853         int irq;
854         int nbus;
855         int i = 0;
856         int ret = 0;
857
858         if (!plat) {
859                 dev_err(&pdev->dev, "no platform data?\n");
860                 return -ENODEV;
861         }
862
863         if (plat->bus_count <= 0 || plat->adapter_nr < 0) {
864                 dev_err(&pdev->dev, "invalid platform data?\n");
865                 return -ENODEV;
866         }
867
868         WARN_ON(plat->bus_count > TEGRA_I2C_MAX_BUS);
869         nbus = min(TEGRA_I2C_MAX_BUS, plat->bus_count);
870
871         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
872         if (!res) {
873                 dev_err(&pdev->dev, "no mem resource\n");
874                 return -EINVAL;
875         }
876         iomem = request_mem_region(res->start, resource_size(res), pdev->name);
877         if (!iomem) {
878                 dev_err(&pdev->dev, "I2C region already claimed\n");
879                 return -EBUSY;
880         }
881
882         base = ioremap(iomem->start, resource_size(iomem));
883         if (!base) {
884                 dev_err(&pdev->dev, "Cannot ioremap I2C region\n");
885                 return -ENOMEM;
886         }
887
888         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
889         if (!res) {
890                 dev_err(&pdev->dev, "no irq resource\n");
891                 ret = -EINVAL;
892                 goto err_iounmap;
893         }
894         irq = res->start;
895
896         div_clk = clk_get(&pdev->dev, "i2c-div");
897         if (IS_ERR(div_clk)) {
898                 dev_err(&pdev->dev, "missing controller clock");
899                 ret = PTR_ERR(div_clk);
900                 goto err_release_region;
901         }
902
903         fast_clk = clk_get(&pdev->dev, "i2c-fast");
904         if (IS_ERR(fast_clk)) {
905                 dev_err(&pdev->dev, "missing controller fast clock");
906                 ret = PTR_ERR(fast_clk);
907                 goto fast_clk_err;
908         }
909
910         i2c_dev = kzalloc(sizeof(struct tegra_i2c_dev) +
911                           (nbus-1) * sizeof(struct tegra_i2c_bus), GFP_KERNEL);
912         if (!i2c_dev) {
913                 ret = -ENOMEM;
914                 goto err_clk_put;
915         }
916
917         i2c_dev->base = base;
918         i2c_dev->div_clk = div_clk;
919         i2c_dev->fast_clk = fast_clk;
920         i2c_dev->iomem = iomem;
921         i2c_dev->irq = irq;
922         i2c_dev->cont_id = pdev->id;
923         i2c_dev->dev = &pdev->dev;
924         i2c_dev->is_clkon_always = plat->is_clkon_always;
925
926         i2c_dev->last_bus_clk_rate = 100000; /* default clock rate */
927         if (plat) {
928                 i2c_dev->last_bus_clk_rate = plat->bus_clk_rate[0];
929
930         } else if (i2c_dev->dev->of_node) {    /* if there is a device tree node ... */
931                 /* TODO: DAN: this doesn't work for DT */
932                 prop = of_get_property(i2c_dev->dev->of_node,
933                                 "clock-frequency", NULL);
934                 if (prop)
935                         i2c_dev->last_bus_clk_rate = be32_to_cpup(prop);
936         }
937
938         i2c_dev->is_high_speed_enable = plat->is_high_speed_enable;
939         i2c_dev->last_bus_clk_rate = plat->bus_clk_rate[0] ?: 100000;
940         i2c_dev->msgs = NULL;
941         i2c_dev->msgs_num = 0;
942         rt_mutex_init(&i2c_dev->dev_lock);
943         spin_lock_init(&i2c_dev->fifo_lock);
944
945         i2c_dev->slave_addr = plat->slave_addr;
946         i2c_dev->hs_master_code = plat->hs_master_code;
947         i2c_dev->is_dvc = plat->is_dvc;
948         i2c_dev->arb_recovery = plat->arb_recovery;
949         init_completion(&i2c_dev->msg_complete);
950
951         if (irq == INT_I2C || irq == INT_I2C2 || irq == INT_I2C3)
952                 i2c_dev->is_slave = true;
953
954         platform_set_drvdata(pdev, i2c_dev);
955
956         if (i2c_dev->is_clkon_always)
957                 tegra_i2c_clock_enable(i2c_dev);
958
959         ret = tegra_i2c_init(i2c_dev);
960         if (ret) {
961                 dev_err(&pdev->dev, "Failed to initialize i2c controller");
962                 goto err_free;
963         }
964
965         ret = request_irq(i2c_dev->irq, tegra_i2c_isr, 0, pdev->name, i2c_dev);
966         if (ret) {
967                 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
968                 goto err_free;
969         }
970
971
972         for (i = 0; i < nbus; i++) {
973                 struct tegra_i2c_bus *i2c_bus = &i2c_dev->busses[i];
974
975                 i2c_bus->dev = i2c_dev;
976                 i2c_bus->mux = plat->bus_mux[i];
977                 i2c_bus->mux_len = plat->bus_mux_len[i];
978                 i2c_bus->bus_clk_rate = plat->bus_clk_rate[i] ?: 100000;
979
980                 i2c_bus->scl_gpio = plat->scl_gpio[i];
981                 i2c_bus->sda_gpio = plat->sda_gpio[i];
982
983                 i2c_bus->adapter.dev.of_node = pdev->dev.of_node;
984                 i2c_bus->adapter.algo = &tegra_i2c_algo;
985                 i2c_set_adapdata(&i2c_bus->adapter, i2c_bus);
986                 i2c_bus->adapter.owner = THIS_MODULE;
987                 i2c_bus->adapter.class = I2C_CLASS_HWMON;
988                 strlcpy(i2c_bus->adapter.name, "Tegra I2C adapter",
989                         sizeof(i2c_bus->adapter.name));
990                 i2c_bus->adapter.dev.parent = &pdev->dev;
991                 i2c_bus->adapter.nr = plat->adapter_nr + i;
992
993                 if (plat->retries)
994                         i2c_bus->adapter.retries = plat->retries;
995                 else
996                         i2c_bus->adapter.retries = TEGRA_I2C_RETRIES;
997
998                 if (plat->timeout)
999                         i2c_bus->adapter.timeout = plat->timeout;
1000
1001                 ret = i2c_add_numbered_adapter(&i2c_bus->adapter);
1002                 if (ret) {
1003                         dev_err(&pdev->dev, "Failed to add I2C adapter\n");
1004                         goto err_del_bus;
1005                 }
1006                 of_i2c_register_devices(&i2c_bus->adapter);
1007
1008                 i2c_dev->bus_count++;
1009         }
1010
1011         return 0;
1012
1013 err_del_bus:
1014         while (i2c_dev->bus_count--)
1015                 i2c_del_adapter(&i2c_dev->busses[i2c_dev->bus_count].adapter);
1016         free_irq(i2c_dev->irq, i2c_dev);
1017 err_free:
1018         kfree(i2c_dev);
1019 err_clk_put:
1020         clk_put(fast_clk);
1021 fast_clk_err:
1022         clk_put(div_clk);
1023 err_release_region:
1024         release_mem_region(iomem->start, resource_size(iomem));
1025 err_iounmap:
1026         iounmap(base);
1027         return ret;
1028 }
1029
1030 static int tegra_i2c_remove(struct platform_device *pdev)
1031 {
1032         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1033         while (i2c_dev->bus_count--)
1034                 i2c_del_adapter(&i2c_dev->busses[i2c_dev->bus_count].adapter);
1035
1036         if (i2c_dev->is_clkon_always)
1037                 tegra_i2c_clock_disable(i2c_dev);
1038
1039         free_irq(i2c_dev->irq, i2c_dev);
1040         clk_put(i2c_dev->div_clk);
1041         clk_put(i2c_dev->fast_clk);
1042         release_mem_region(i2c_dev->iomem->start,
1043                 resource_size(i2c_dev->iomem));
1044         iounmap(i2c_dev->base);
1045         kfree(i2c_dev);
1046         return 0;
1047 }
1048
1049 #ifdef CONFIG_PM
1050 static int tegra_i2c_suspend_noirq(struct device *dev)
1051 {
1052         struct platform_device *pdev = to_platform_device(dev);
1053         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1054
1055         rt_mutex_lock(&i2c_dev->dev_lock);
1056
1057         i2c_dev->is_suspended = true;
1058         if (i2c_dev->is_clkon_always)
1059                 tegra_i2c_clock_disable(i2c_dev);
1060
1061         rt_mutex_unlock(&i2c_dev->dev_lock);
1062
1063         return 0;
1064 }
1065
1066 static int tegra_i2c_resume_noirq(struct device *dev)
1067 {
1068         struct platform_device *pdev = to_platform_device(dev);
1069         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1070         int ret;
1071
1072         rt_mutex_lock(&i2c_dev->dev_lock);
1073
1074         if (i2c_dev->is_clkon_always)
1075                 tegra_i2c_clock_enable(i2c_dev);
1076
1077         ret = tegra_i2c_init(i2c_dev);
1078
1079         if (ret) {
1080                 rt_mutex_unlock(&i2c_dev->dev_lock);
1081                 return ret;
1082         }
1083
1084         i2c_dev->is_suspended = false;
1085
1086         rt_mutex_unlock(&i2c_dev->dev_lock);
1087
1088         return 0;
1089 }
1090
1091 static const struct dev_pm_ops tegra_i2c_dev_pm_ops = {
1092         .suspend_noirq = tegra_i2c_suspend_noirq,
1093         .resume_noirq = tegra_i2c_resume_noirq,
1094 };
1095 #define TEGRA_I2C_DEV_PM_OPS (&tegra_i2c_dev_pm_ops)
1096 #else
1097 #define TEGRA_I2C_DEV_PM_OPS NULL
1098 #endif
1099
1100 #if defined(CONFIG_OF)
1101 /* Match table for of_platform binding */
1102 static const struct of_device_id tegra_i2c_of_match[] __devinitconst = {
1103         { .compatible = "nvidia,tegra20-i2c", },
1104         {},
1105 };
1106 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
1107 #endif
1108
1109 static struct platform_driver tegra_i2c_driver = {
1110         .probe   = tegra_i2c_probe,
1111         .remove  = tegra_i2c_remove,
1112         .driver  = {
1113                 .name  = "tegra-i2c",
1114                 .owner = THIS_MODULE,
1115                 .of_match_table = of_match_ptr(tegra_i2c_of_match),
1116                 .pm    = TEGRA_I2C_DEV_PM_OPS,
1117         },
1118 };
1119
1120 static int __init tegra_i2c_init_driver(void)
1121 {
1122         return platform_driver_register(&tegra_i2c_driver);
1123 }
1124
1125 static void __exit tegra_i2c_exit_driver(void)
1126 {
1127         platform_driver_unregister(&tegra_i2c_driver);
1128 }
1129
1130 subsys_initcall(tegra_i2c_init_driver);
1131 module_exit(tegra_i2c_exit_driver);
1132
1133 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
1134 MODULE_AUTHOR("Colin Cross");
1135 MODULE_LICENSE("GPL v2");