i2c: tegra: Add debug prints for i2c timed out case
[linux-2.6.git] / drivers / i2c / busses / i2c-tegra.c
1 /*
2  * drivers/i2c/busses/i2c-tegra.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Colin Cross <ccross@android.com>
6  *
7  * Copyright (C) 2010-2013 NVIDIA CORPORATION. All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 /*#define DEBUG           1*/
21 /*#define VERBOSE_DEBUG   1*/
22
23 #include <linux/kernel.h>
24 #include <linux/init.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/err.h>
28 #include <linux/i2c.h>
29 #include <linux/io.h>
30 #include <linux/interrupt.h>
31 #include <linux/delay.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/slab.h>
34 #include <linux/i2c-tegra.h>
35 #include <linux/of_device.h>
36 #include <linux/of_i2c.h>
37 #include <linux/module.h>
38 #include <linux/spinlock.h>
39
40 #include <asm/unaligned.h>
41
42 #include <mach/clk.h>
43 #include <mach/pinmux.h>
44
45 #define TEGRA_I2C_TIMEOUT                       (msecs_to_jiffies(1000))
46 #define TEGRA_I2C_RETRIES                       3
47 #define BYTES_PER_FIFO_WORD                     4
48
49 #define I2C_CNFG                                0x000
50 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT             12
51 #define I2C_CNFG_PACKET_MODE_EN                 (1<<10)
52 #define I2C_CNFG_NEW_MASTER_FSM                 (1<<11)
53 #define I2C_STATUS                              0x01C
54 #define I2C_STATUS_BUSY                         (1<<8)
55 #define I2C_SL_CNFG                             0x020
56 #define I2C_SL_CNFG_NACK                        (1<<1)
57 #define I2C_SL_CNFG_NEWSL                       (1<<2)
58 #define I2C_SL_ADDR1                            0x02c
59 #define I2C_SL_ADDR2                            0x030
60 #define I2C_TX_FIFO                             0x050
61 #define I2C_RX_FIFO                             0x054
62 #define I2C_PACKET_TRANSFER_STATUS              0x058
63 #define I2C_FIFO_CONTROL                        0x05c
64 #define I2C_FIFO_CONTROL_TX_FLUSH               (1<<1)
65 #define I2C_FIFO_CONTROL_RX_FLUSH               (1<<0)
66 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT          5
67 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT          2
68 #define I2C_FIFO_STATUS                         0x060
69 #define I2C_FIFO_STATUS_TX_MASK                 0xF0
70 #define I2C_FIFO_STATUS_TX_SHIFT                4
71 #define I2C_FIFO_STATUS_RX_MASK                 0x0F
72 #define I2C_FIFO_STATUS_RX_SHIFT                0
73 #define I2C_INT_MASK                            0x064
74 #define I2C_INT_STATUS                          0x068
75 #define I2C_INT_BUS_CLEAR_DONE          (1<<11)
76 #define I2C_INT_PACKET_XFER_COMPLETE            (1<<7)
77 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE       (1<<6)
78 #define I2C_INT_TX_FIFO_OVERFLOW                (1<<5)
79 #define I2C_INT_RX_FIFO_UNDERFLOW               (1<<4)
80 #define I2C_INT_NO_ACK                          (1<<3)
81 #define I2C_INT_ARBITRATION_LOST                (1<<2)
82 #define I2C_INT_TX_FIFO_DATA_REQ                (1<<1)
83 #define I2C_INT_RX_FIFO_DATA_REQ                (1<<0)
84
85 #define I2C_CLK_DIVISOR                         0x06c
86 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT     16
87 #define I2C_CLK_MULTIPLIER_STD_FAST_MODE        8
88
89 #define DVC_CTRL_REG1                           0x000
90 #define DVC_CTRL_REG1_INTR_EN                   (1<<10)
91 #define DVC_CTRL_REG2                           0x004
92 #define DVC_CTRL_REG3                           0x008
93 #define DVC_CTRL_REG3_SW_PROG                   (1<<26)
94 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN          (1<<30)
95 #define DVC_STATUS                              0x00c
96 #define DVC_STATUS_I2C_DONE_INTR                (1<<30)
97
98 #define I2C_ERR_NONE                            0x00
99 #define I2C_ERR_NO_ACK                          0x01
100 #define I2C_ERR_ARBITRATION_LOST                0x02
101 #define I2C_ERR_UNKNOWN_INTERRUPT               0x04
102 #define I2C_ERR_UNEXPECTED_STATUS               0x08
103
104 #define PACKET_HEADER0_HEADER_SIZE_SHIFT        28
105 #define PACKET_HEADER0_PACKET_ID_SHIFT          16
106 #define PACKET_HEADER0_CONT_ID_SHIFT            12
107 #define PACKET_HEADER0_PROTOCOL_I2C             (1<<4)
108
109 #define I2C_HEADER_HIGHSPEED_MODE               (1<<22)
110 #define I2C_HEADER_CONT_ON_NAK                  (1<<21)
111 #define I2C_HEADER_SEND_START_BYTE              (1<<20)
112 #define I2C_HEADER_READ                         (1<<19)
113 #define I2C_HEADER_10BIT_ADDR                   (1<<18)
114 #define I2C_HEADER_IE_ENABLE                    (1<<17)
115 #define I2C_HEADER_REPEAT_START                 (1<<16)
116 #define I2C_HEADER_CONTINUE_XFER                (1<<15)
117 #define I2C_HEADER_MASTER_ADDR_SHIFT            12
118 #define I2C_HEADER_SLAVE_ADDR_SHIFT             1
119
120 #define I2C_BUS_CLEAR_CNFG                              0x084
121 #define I2C_BC_SCLK_THRESHOLD                           (9<<16)
122 #define I2C_BC_STOP_COND                                (1<<2)
123 #define I2C_BC_TERMINATE                                (1<<1)
124 #define I2C_BC_ENABLE                                   (1<<0)
125
126 #define I2C_BUS_CLEAR_STATUS                            0x088
127 #define I2C_BC_STATUS                                   (1<<0)
128
129 #define SL_ADDR1(addr) (addr & 0xff)
130 #define SL_ADDR2(addr) ((addr >> 8) & 0xff)
131
132 /*
133  * msg_end_type: The bus control which need to be send at end of transfer.
134  * @MSG_END_STOP: Send stop pulse at end of transfer.
135  * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
136  * @MSG_END_CONTINUE: The following on message is coming and so do not send
137  *              stop or repeat start.
138  */
139
140 enum msg_end_type {
141         MSG_END_STOP,
142         MSG_END_REPEAT_START,
143         MSG_END_CONTINUE,
144 };
145
146 struct tegra_i2c_chipdata {
147         bool timeout_irq_occurs_before_bus_inactive;
148         bool has_xfer_complete_interrupt;
149         bool has_hw_arb_support;
150         bool has_fast_clock;
151         bool has_clk_divisor_std_fast_mode;
152         bool has_continue_xfer_support;
153         u16 clk_divisor_std_fast_mode;
154         u16 clk_divisor_hs_mode;
155         int clk_multiplier_hs_mode;
156 };
157
158 struct tegra_i2c_dev;
159
160 struct tegra_i2c_bus {
161         struct tegra_i2c_dev *dev;
162         const struct tegra_pingroup_config *mux;
163         int mux_len;
164         unsigned long bus_clk_rate;
165         struct i2c_adapter adapter;
166         int scl_gpio;
167         int sda_gpio;
168 };
169
170 /**
171  * struct tegra_i2c_dev - per device i2c context
172  * @dev: device reference for power management
173  * @adapter: core i2c layer adapter information
174  * @clk: clock reference for i2c controller
175  * @i2c_clk: clock reference for i2c bus
176  * @base: ioremapped registers cookie
177  * @cont_id: i2c controller id, used for for packet header
178  * @irq: irq number of transfer complete interrupt
179  * @is_dvc: identifies the DVC i2c controller, has a different register layout
180  * @msg_complete: transfer completion notifier
181  * @msg_err: error code for completed message
182  * @msg_buf: pointer to current message data
183  * @msg_buf_remaining: size of unsent data in the message buffer
184  * @msg_read: identifies read transfers
185  * @bus_clk_rate: current i2c bus clock rate
186  * @is_suspended: prevents i2c controller accesses after suspend is called
187  */
188 struct tegra_i2c_dev {
189         struct device *dev;
190         struct clk *div_clk;
191         struct clk *fast_clk;
192         struct rt_mutex dev_lock;
193         spinlock_t fifo_lock;
194         void __iomem *base;
195         int cont_id;
196         int irq;
197         bool irq_disabled;
198         int is_dvc;
199         struct completion msg_complete;
200         int msg_err;
201         int next_msg_err;
202         u8 *msg_buf;
203         u8 *next_msg_buf;
204         u32 packet_header;
205         u32 next_packet_header;
206         u32 payload_size;
207         u32 next_payload_size;
208         u32 io_header;
209         u32 next_io_header;
210         size_t msg_buf_remaining;
211         size_t next_msg_buf_remaining;
212         int msg_read;
213         int next_msg_read;
214         struct i2c_msg *msgs;
215         int msg_add;
216         int next_msg_add;
217         int msgs_num;
218         bool is_suspended;
219         int bus_count;
220         const struct tegra_pingroup_config *last_mux;
221         int last_mux_len;
222         unsigned long last_bus_clk_rate;
223         u16 slave_addr;
224         bool is_clkon_always;
225         bool is_high_speed_enable;
226         u16 hs_master_code;
227         bool use_single_xfer_complete;
228         int (*arb_recovery)(int scl_gpio, int sda_gpio);
229         struct tegra_i2c_chipdata *chipdata;
230         struct tegra_i2c_bus busses[1];
231 };
232
233 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
234 {
235         writel(val, i2c_dev->base + reg);
236 }
237
238 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
239 {
240         return readl(i2c_dev->base + reg);
241 }
242
243 static void dvc_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
244 {
245         u32 int_mask = dvc_readl(i2c_dev, DVC_CTRL_REG3);
246         int_mask &= ~mask;
247         dvc_writel(i2c_dev, int_mask, DVC_CTRL_REG3);
248 }
249
250 static void dvc_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
251 {
252         u32 int_mask = dvc_readl(i2c_dev, DVC_CTRL_REG3);
253         int_mask |= mask;
254         dvc_writel(i2c_dev, int_mask, DVC_CTRL_REG3);
255 }
256
257 /*
258  * i2c_writel and i2c_readl will offset the register if necessary to talk
259  * to the I2C block inside the DVC block
260  */
261 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
262         unsigned long reg)
263 {
264         if (i2c_dev->is_dvc)
265                 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
266         return reg;
267 }
268
269 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
270         unsigned long reg)
271 {
272         writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
273
274         /* Read back register to make sure that register writes completed */
275         if (reg != I2C_TX_FIFO)
276                 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
277 }
278
279 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
280 {
281         return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
282 }
283
284 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
285         unsigned long reg, int len)
286 {
287         writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
288 }
289
290 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
291         unsigned long reg, int len)
292 {
293         readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
294 }
295
296 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
297 {
298         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
299         int_mask &= ~mask;
300         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
301 }
302
303 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
304 {
305         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
306         int_mask |= mask;
307         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
308 }
309
310 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
311 {
312         unsigned long timeout = jiffies + HZ;
313         u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
314         val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
315         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
316
317         while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
318                 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
319                 if (time_after(jiffies, timeout)) {
320                         dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
321                         return -ETIMEDOUT;
322                 }
323                 msleep(1);
324         }
325         return 0;
326 }
327
328 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
329 {
330         u32 val;
331         int rx_fifo_avail;
332         u8 *buf = i2c_dev->msg_buf;
333         size_t buf_remaining = i2c_dev->msg_buf_remaining;
334         int words_to_transfer;
335
336         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
337         rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
338                 I2C_FIFO_STATUS_RX_SHIFT;
339
340         /* Rounds down to not include partial word at the end of buf */
341         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
342         if (words_to_transfer > rx_fifo_avail)
343                 words_to_transfer = rx_fifo_avail;
344
345         i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
346
347         buf += words_to_transfer * BYTES_PER_FIFO_WORD;
348         buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
349         rx_fifo_avail -= words_to_transfer;
350
351         /*
352          * If there is a partial word at the end of buf, handle it manually to
353          * prevent overwriting past the end of buf
354          */
355         if (rx_fifo_avail > 0 && buf_remaining > 0) {
356                 BUG_ON(buf_remaining > 3);
357                 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
358                 memcpy(buf, &val, buf_remaining);
359                 buf_remaining = 0;
360                 rx_fifo_avail--;
361         }
362
363         BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
364         i2c_dev->msg_buf_remaining = buf_remaining;
365         i2c_dev->msg_buf = buf;
366         return 0;
367 }
368
369 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
370 {
371         u32 val;
372         int tx_fifo_avail;
373         u8 *buf;
374         size_t buf_remaining;
375         int words_to_transfer;
376
377         if (!i2c_dev->msg_buf_remaining)
378                 return 0;
379         buf = i2c_dev->msg_buf;
380         buf_remaining = i2c_dev->msg_buf_remaining;
381
382         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
383         tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
384                 I2C_FIFO_STATUS_TX_SHIFT;
385
386         /* Rounds down to not include partial word at the end of buf */
387         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
388
389         /* It's very common to have < 4 bytes, so optimize that case. */
390         if (words_to_transfer) {
391                 if (words_to_transfer > tx_fifo_avail)
392                         words_to_transfer = tx_fifo_avail;
393
394                 /*
395                  * Update state before writing to FIFO.  If this casues us
396                  * to finish writing all bytes (AKA buf_remaining goes to 0) we
397                  * have a potential for an interrupt (PACKET_XFER_COMPLETE is
398                  * not maskable).  We need to make sure that the isr sees
399                  * buf_remaining as 0 and doesn't call us back re-entrantly.
400                  */
401                 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
402                 tx_fifo_avail -= words_to_transfer;
403                 i2c_dev->msg_buf_remaining = buf_remaining;
404                 i2c_dev->msg_buf = buf +
405                         words_to_transfer * BYTES_PER_FIFO_WORD;
406                 barrier();
407
408                 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
409
410                 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
411         }
412
413         /*
414          * If there is a partial word at the end of buf, handle it manually to
415          * prevent reading past the end of buf, which could cross a page
416          * boundary and fault.
417          */
418         if (tx_fifo_avail > 0 && buf_remaining > 0) {
419                 if (buf_remaining > 3) {
420                         dev_err(i2c_dev->dev,
421                                 "Remaining buffer more than 3 %d\n",
422                                 buf_remaining);
423                         BUG();
424                 }
425                 memcpy(&val, buf, buf_remaining);
426
427                 /* Again update before writing to FIFO to make sure isr sees. */
428                 i2c_dev->msg_buf_remaining = 0;
429                 i2c_dev->msg_buf = NULL;
430                 barrier();
431
432                 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
433         }
434
435         return 0;
436 }
437
438 /*
439  * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
440  * block.  This block is identical to the rest of the I2C blocks, except that
441  * it only supports master mode, it has registers moved around, and it needs
442  * some extra init to get it into I2C mode.  The register moves are handled
443  * by i2c_readl and i2c_writel
444  */
445 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
446 {
447         u32 val = 0;
448         val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
449         val |= DVC_CTRL_REG3_SW_PROG;
450         dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
451
452         val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
453         val |= DVC_CTRL_REG1_INTR_EN;
454         dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
455 }
456
457 static void tegra_i2c_slave_init(struct tegra_i2c_dev *i2c_dev)
458 {
459         u32 val = I2C_SL_CNFG_NEWSL | I2C_SL_CNFG_NACK;
460
461         i2c_writel(i2c_dev, val, I2C_SL_CNFG);
462
463         if (i2c_dev->slave_addr) {
464                 u16 addr = i2c_dev->slave_addr;
465
466                 i2c_writel(i2c_dev, SL_ADDR1(addr), I2C_SL_ADDR1);
467                 i2c_writel(i2c_dev, SL_ADDR2(addr), I2C_SL_ADDR2);
468         }
469 }
470
471 static inline int tegra_i2c_clock_enable(struct tegra_i2c_dev *i2c_dev)
472 {
473         int ret;
474         if (i2c_dev->chipdata->has_fast_clock) {
475                 ret = clk_prepare_enable(i2c_dev->fast_clk);
476                 if (ret < 0) {
477                         dev_err(i2c_dev->dev,
478                                 "Error in enabling fast clock err %d\n", ret);
479                         return ret;
480                 }
481         }
482         ret = clk_prepare_enable(i2c_dev->div_clk);
483         if (ret < 0) {
484                 dev_err(i2c_dev->dev,
485                         "Error in enabling div clock err %d\n", ret);
486                 clk_disable_unprepare(i2c_dev->fast_clk);
487         }
488         return ret;
489 }
490
491 static inline void tegra_i2c_clock_disable(struct tegra_i2c_dev *i2c_dev)
492 {
493         clk_disable_unprepare(i2c_dev->div_clk);
494         if (i2c_dev->chipdata->has_fast_clock)
495                 clk_disable_unprepare(i2c_dev->fast_clk);
496 }
497
498 static void tegra_i2c_set_clk_rate(struct tegra_i2c_dev *i2c_dev)
499 {
500         u32 clk_multiplier;
501         if (i2c_dev->is_high_speed_enable)
502                 clk_multiplier = i2c_dev->chipdata->clk_multiplier_hs_mode
503                         * (i2c_dev->chipdata->clk_divisor_hs_mode + 1);
504         else
505                 clk_multiplier = I2C_CLK_MULTIPLIER_STD_FAST_MODE
506                 * (i2c_dev->chipdata->clk_divisor_std_fast_mode + 1);
507
508         clk_set_rate(i2c_dev->div_clk, i2c_dev->last_bus_clk_rate
509                                                         * clk_multiplier);
510 }
511
512 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
513 {
514         u32 val;
515         int err = 0;
516         u32 clk_divisor = 0;
517
518         tegra_i2c_clock_enable(i2c_dev);
519
520         tegra_periph_reset_assert(i2c_dev->div_clk);
521         udelay(2);
522         tegra_periph_reset_deassert(i2c_dev->div_clk);
523
524         if (i2c_dev->is_dvc)
525                 tegra_dvc_init(i2c_dev);
526
527         val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
528                 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
529         i2c_writel(i2c_dev, val, I2C_CNFG);
530         i2c_writel(i2c_dev, 0, I2C_INT_MASK);
531
532         tegra_i2c_set_clk_rate(i2c_dev);
533
534         clk_divisor |= i2c_dev->chipdata->clk_divisor_hs_mode;
535         if (i2c_dev->chipdata->has_clk_divisor_std_fast_mode)
536                 clk_divisor |= i2c_dev->chipdata->clk_divisor_std_fast_mode
537                                 << I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
538         i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
539
540         if (!i2c_dev->is_dvc) {
541                 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
542                 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
543                 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
544                 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
545                 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
546
547         }
548
549         val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
550                 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
551         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
552
553         if (!i2c_dev->is_dvc)
554                 tegra_i2c_slave_init(i2c_dev);
555
556         if (tegra_i2c_flush_fifos(i2c_dev))
557                 err = -ETIMEDOUT;
558
559         tegra_i2c_clock_disable(i2c_dev);
560
561         if (i2c_dev->irq_disabled) {
562                 i2c_dev->irq_disabled = 0;
563                 enable_irq(i2c_dev->irq);
564         }
565
566         return err;
567 }
568 static int tegra_i2c_copy_next_to_current(struct tegra_i2c_dev *i2c_dev)
569 {
570         i2c_dev->msg_buf = i2c_dev->next_msg_buf;
571         i2c_dev->msg_buf_remaining = i2c_dev->next_msg_buf_remaining;
572         i2c_dev->msg_err = i2c_dev->next_msg_err;
573         i2c_dev->msg_read = i2c_dev->next_msg_read;
574         i2c_dev->msg_add = i2c_dev->next_msg_add;
575         i2c_dev->packet_header = i2c_dev->next_packet_header;
576         i2c_dev->io_header = i2c_dev->next_io_header;
577         i2c_dev->payload_size = i2c_dev->next_payload_size;
578
579         return 0;
580 }
581
582 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
583 {
584         u32 status;
585         unsigned long flags = 0;
586
587         const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST
588                                         | I2C_INT_TX_FIFO_OVERFLOW;
589         struct tegra_i2c_dev *i2c_dev = dev_id;
590         u32 mask;
591
592         status = i2c_readl(i2c_dev, I2C_INT_STATUS);
593
594         if (status == 0) {
595                 dev_warn(i2c_dev->dev, "unknown interrupt Add 0x%02x\n",
596                                                 i2c_dev->msg_add);
597                 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
598
599                 if (!i2c_dev->irq_disabled) {
600                         disable_irq_nosync(i2c_dev->irq);
601                         i2c_dev->irq_disabled = 1;
602                 }
603                 goto err;
604         }
605
606         if (unlikely(status & status_err)) {
607                 dev_dbg(i2c_dev->dev, "I2c error status 0x%08x\n", status);
608                 if (status & I2C_INT_NO_ACK) {
609                         i2c_dev->msg_err |= I2C_ERR_NO_ACK;
610                         dev_warn(i2c_dev->dev, "no acknowledge from address"
611                                         " 0x%x\n", i2c_dev->msg_add);
612                         dev_dbg(i2c_dev->dev, "Packet status 0x%08x\n",
613                                 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS));
614                 }
615
616                 if (status & I2C_INT_ARBITRATION_LOST) {
617                         i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
618                         dev_warn(i2c_dev->dev, "arbitration lost during "
619                                 " communicate to add 0x%x\n", i2c_dev->msg_add);
620                         dev_dbg(i2c_dev->dev, "Packet status 0x%08x\n",
621                                 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS));
622                 }
623
624                 if (status & I2C_INT_TX_FIFO_OVERFLOW) {
625                         i2c_dev->msg_err |= I2C_INT_TX_FIFO_OVERFLOW;
626                         dev_warn(i2c_dev->dev, "Tx fifo overflow during "
627                                 " communicate to add 0x%x\n", i2c_dev->msg_add);
628                         dev_dbg(i2c_dev->dev, "Packet status 0x%08x\n",
629                                 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS));
630                 }
631                 goto err;
632         }
633
634         if (i2c_dev->chipdata->has_hw_arb_support &&
635                         (status & I2C_INT_BUS_CLEAR_DONE))
636                 goto err;
637
638         if (unlikely((i2c_readl(i2c_dev, I2C_STATUS) & I2C_STATUS_BUSY)
639                                 && (status == I2C_INT_TX_FIFO_DATA_REQ)
640                                 && i2c_dev->msg_read
641                                 && i2c_dev->msg_buf_remaining)) {
642                 dev_warn(i2c_dev->dev, "unexpected status\n");
643                 i2c_dev->msg_err |= I2C_ERR_UNEXPECTED_STATUS;
644
645                 if (!i2c_dev->irq_disabled) {
646                         disable_irq_nosync(i2c_dev->irq);
647                         i2c_dev->irq_disabled = 1;
648                 }
649
650                 goto err;
651         }
652
653         if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
654                 if (i2c_dev->msg_buf_remaining)
655                         tegra_i2c_empty_rx_fifo(i2c_dev);
656                 else
657                         BUG();
658         }
659
660         if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
661                 if (i2c_dev->msg_buf_remaining) {
662
663                         if (!i2c_dev->chipdata->has_xfer_complete_interrupt)
664                                 spin_lock_irqsave(&i2c_dev->fifo_lock, flags);
665
666                         tegra_i2c_fill_tx_fifo(i2c_dev);
667
668                         if (!i2c_dev->chipdata->has_xfer_complete_interrupt)
669                                 spin_unlock_irqrestore(&i2c_dev->fifo_lock, flags);
670
671                 }
672                 else
673                         tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
674         }
675
676         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
677
678         if (i2c_dev->is_dvc)
679                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
680
681         if (status & I2C_INT_ALL_PACKETS_XFER_COMPLETE) {
682                 BUG_ON(i2c_dev->msg_buf_remaining);
683                 complete(&i2c_dev->msg_complete);
684         } else if ((status & I2C_INT_PACKET_XFER_COMPLETE)
685                                 && i2c_dev->use_single_xfer_complete) {
686                 BUG_ON(i2c_dev->msg_buf_remaining);
687                 complete(&i2c_dev->msg_complete);
688         }
689
690         return IRQ_HANDLED;
691
692 err:
693         dev_dbg(i2c_dev->dev, "reg: 0x%08x 0x%08x 0x%08x 0x%08x\n",
694                  i2c_readl(i2c_dev, I2C_CNFG), i2c_readl(i2c_dev, I2C_STATUS),
695                  i2c_readl(i2c_dev, I2C_INT_STATUS),
696                  i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS));
697
698         dev_dbg(i2c_dev->dev, "packet: 0x%08x %u 0x%08x\n",
699                  i2c_dev->packet_header, i2c_dev->payload_size,
700                  i2c_dev->io_header);
701
702         if (i2c_dev->msgs) {
703                 struct i2c_msg *msgs = i2c_dev->msgs;
704                 int i;
705
706                 for (i = 0; i < i2c_dev->msgs_num; i++)
707                         dev_dbg(i2c_dev->dev,
708                                  "msgs[%d] %c, addr=0x%04x, len=%d\n",
709                                  i, (msgs[i].flags & I2C_M_RD) ? 'R' : 'W',
710                                  msgs[i].addr, msgs[i].len);
711         }
712
713         mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
714                 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
715                 I2C_INT_RX_FIFO_DATA_REQ | I2C_INT_TX_FIFO_OVERFLOW;
716
717         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
718
719         if (i2c_dev->chipdata->has_xfer_complete_interrupt)
720                 mask |= I2C_INT_ALL_PACKETS_XFER_COMPLETE;
721
722         if (!(i2c_dev->use_single_xfer_complete &&
723                         i2c_dev->chipdata->has_xfer_complete_interrupt))
724                 mask |= I2C_INT_ALL_PACKETS_XFER_COMPLETE;
725
726         if (i2c_dev->chipdata->has_hw_arb_support)
727                 mask |= I2C_INT_BUS_CLEAR_DONE;
728
729         /* An error occurred, mask all interrupts */
730         tegra_i2c_mask_irq(i2c_dev, mask);
731
732         /* An error occured, mask dvc interrupt */
733         if (i2c_dev->is_dvc)
734                 dvc_i2c_mask_irq(i2c_dev, DVC_CTRL_REG3_I2C_DONE_INTR_EN);
735
736         if (i2c_dev->is_dvc)
737                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
738
739         complete(&i2c_dev->msg_complete);
740
741         return IRQ_HANDLED;
742 }
743
744 static int tegra_i2c_send_next_read_msg_pkt_header(struct tegra_i2c_dev *i2c_dev, struct i2c_msg *next_msg, enum msg_end_type end_state)
745 {
746         i2c_dev->next_msg_buf = next_msg->buf;
747         i2c_dev->next_msg_buf_remaining = next_msg->len;
748         i2c_dev->next_msg_err = I2C_ERR_NONE;
749         i2c_dev->next_msg_read = 1;
750         i2c_dev->next_msg_add = next_msg->addr;
751         i2c_dev->next_packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
752                         PACKET_HEADER0_PROTOCOL_I2C |
753                         (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
754                         (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
755
756         i2c_writel(i2c_dev, i2c_dev->next_packet_header, I2C_TX_FIFO);
757
758         i2c_dev->next_payload_size = next_msg->len - 1;
759         i2c_writel(i2c_dev, i2c_dev->next_payload_size, I2C_TX_FIFO);
760
761         i2c_dev->next_io_header = I2C_HEADER_IE_ENABLE;
762
763         if (end_state == MSG_END_CONTINUE)
764                 i2c_dev->next_io_header |= I2C_HEADER_CONTINUE_XFER;
765         else if (end_state == MSG_END_REPEAT_START)
766                 i2c_dev->next_io_header |= I2C_HEADER_REPEAT_START;
767
768         if (next_msg->flags & I2C_M_TEN) {
769                 i2c_dev->next_io_header |= next_msg->addr;
770                 i2c_dev->next_io_header |= I2C_HEADER_10BIT_ADDR;
771         } else {
772                 i2c_dev->next_io_header |= (next_msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT);
773         }
774         if (next_msg->flags & I2C_M_IGNORE_NAK)
775                 i2c_dev->next_io_header |= I2C_HEADER_CONT_ON_NAK;
776
777         i2c_dev->next_io_header |= I2C_HEADER_READ;
778
779         if (i2c_dev->is_high_speed_enable) {
780                 i2c_dev->next_io_header |= I2C_HEADER_HIGHSPEED_MODE;
781                 i2c_dev->next_io_header |= ((i2c_dev->hs_master_code & 0x7)
782                                         <<  I2C_HEADER_MASTER_ADDR_SHIFT);
783         }
784         i2c_writel(i2c_dev, i2c_dev->next_io_header, I2C_TX_FIFO);
785
786         return 0;
787 }
788
789 static int tegra_i2c_xfer_msg(struct tegra_i2c_bus *i2c_bus,
790         struct i2c_msg *msg, enum msg_end_type end_state, struct i2c_msg *next_msg, enum msg_end_type next_msg_end_state)
791 {
792         struct tegra_i2c_dev *i2c_dev = i2c_bus->dev;
793         u32 int_mask;
794         int ret;
795         unsigned long flags = 0;
796
797         if (msg->len == 0)
798                 return -EINVAL;
799
800         tegra_i2c_flush_fifos(i2c_dev);
801
802
803         i2c_dev->msg_buf = msg->buf;
804         i2c_dev->msg_buf_remaining = msg->len;
805         i2c_dev->msg_err = I2C_ERR_NONE;
806         i2c_dev->msg_read = (msg->flags & I2C_M_RD);
807         INIT_COMPLETION(i2c_dev->msg_complete);
808
809         if (!i2c_dev->chipdata->has_xfer_complete_interrupt)
810                 spin_lock_irqsave(&i2c_dev->fifo_lock, flags);
811
812         i2c_dev->msg_add = msg->addr;
813
814         i2c_dev->packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
815                         PACKET_HEADER0_PROTOCOL_I2C |
816                         (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
817                         (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
818         i2c_writel(i2c_dev, i2c_dev->packet_header, I2C_TX_FIFO);
819
820         i2c_dev->payload_size = msg->len - 1;
821         i2c_writel(i2c_dev, i2c_dev->payload_size, I2C_TX_FIFO);
822
823         i2c_dev->use_single_xfer_complete = true;
824         i2c_dev->io_header = 0;
825         if (next_msg == NULL)
826                 i2c_dev->io_header = I2C_HEADER_IE_ENABLE;
827
828         if (end_state == MSG_END_CONTINUE)
829                 i2c_dev->io_header |= I2C_HEADER_CONTINUE_XFER;
830         else if (end_state == MSG_END_REPEAT_START)
831                 i2c_dev->io_header |= I2C_HEADER_REPEAT_START;
832
833         if (msg->flags & I2C_M_TEN) {
834                 i2c_dev->io_header |= msg->addr;
835                 i2c_dev->io_header |= I2C_HEADER_10BIT_ADDR;
836         } else {
837                 i2c_dev->io_header |= (msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT);
838         }
839         if (msg->flags & I2C_M_IGNORE_NAK)
840                 i2c_dev->io_header |= I2C_HEADER_CONT_ON_NAK;
841         if (msg->flags & I2C_M_RD)
842                 i2c_dev->io_header |= I2C_HEADER_READ;
843         if (i2c_dev->is_high_speed_enable) {
844                 i2c_dev->io_header |= I2C_HEADER_HIGHSPEED_MODE;
845                 i2c_dev->io_header |= ((i2c_dev->hs_master_code & 0x7)
846                                         <<  I2C_HEADER_MASTER_ADDR_SHIFT);
847         }
848         i2c_writel(i2c_dev, i2c_dev->io_header, I2C_TX_FIFO);
849
850         if (!(msg->flags & I2C_M_RD))
851                 tegra_i2c_fill_tx_fifo(i2c_dev);
852
853         if (i2c_dev->is_dvc)
854                 dvc_i2c_unmask_irq(i2c_dev, DVC_CTRL_REG3_I2C_DONE_INTR_EN);
855
856         int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST
857                                         | I2C_INT_TX_FIFO_OVERFLOW;
858         if (i2c_dev->chipdata->has_xfer_complete_interrupt)
859                 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
860
861         if (i2c_dev->chipdata->has_xfer_complete_interrupt)
862                 int_mask |= I2C_INT_ALL_PACKETS_XFER_COMPLETE;
863
864         if (msg->flags & I2C_M_RD)
865                 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
866         else if (i2c_dev->msg_buf_remaining)
867                 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
868
869         if (next_msg != NULL) {
870                 tegra_i2c_send_next_read_msg_pkt_header(i2c_dev, next_msg,
871                                                         next_msg_end_state);
872                 tegra_i2c_copy_next_to_current(i2c_dev);
873                 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
874                 i2c_dev->use_single_xfer_complete = false;
875         }
876
877         if (!(i2c_dev->use_single_xfer_complete &&
878                         i2c_dev->chipdata->has_xfer_complete_interrupt))
879                 int_mask |= I2C_INT_ALL_PACKETS_XFER_COMPLETE;
880
881         if (!i2c_dev->chipdata->has_xfer_complete_interrupt)
882                 spin_unlock_irqrestore(&i2c_dev->fifo_lock, flags);
883
884         tegra_i2c_unmask_irq(i2c_dev, int_mask);
885
886         dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
887                 i2c_readl(i2c_dev, I2C_INT_MASK));
888
889         ret = wait_for_completion_timeout(&i2c_dev->msg_complete,
890                                         TEGRA_I2C_TIMEOUT);
891         if (ret == 0) {
892
893                 dev_err(i2c_dev->dev, "--- register dump for debugging ----\n");
894                 dev_err(i2c_dev->dev, "I2C_CNFG - 0x%x\n", i2c_readl(i2c_dev, I2C_CNFG));
895                 dev_err(i2c_dev->dev, "I2C_PACKET_TRANSFER_STATUS - 0x%x\n", i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS));
896                 dev_err(i2c_dev->dev, "I2C_FIFO_CONTROL - 0x%x\n", i2c_readl(i2c_dev, I2C_FIFO_CONTROL));
897                 dev_err(i2c_dev->dev, "I2C_FIFO_STATUS - 0x%x\n", i2c_readl(i2c_dev, I2C_FIFO_STATUS));
898                 dev_err(i2c_dev->dev, "I2C_INT_MASK - 0x%x\n", i2c_readl(i2c_dev, I2C_INT_MASK));
899                 dev_err(i2c_dev->dev, "I2C_INT_STATUS - 0x%x\n", i2c_readl(i2c_dev, I2C_INT_STATUS));
900
901                 dev_err(i2c_dev->dev, "msg->len - %d\n", msg->len);
902                 dev_err(i2c_dev->dev, "is_msg_write - %d\n", !(msg->flags & I2C_M_RD));
903                 if (next_msg != NULL) {
904                         dev_err(i2c_dev->dev, "next_msg->len - %d\n", next_msg->len);
905                         dev_err(i2c_dev->dev, "is_next_msg_write - %d\n", !(next_msg->flags & I2C_M_RD));
906                 }
907                 dev_err(i2c_dev->dev, "buf_remaining - %d\n", i2c_dev->msg_buf_remaining);
908
909
910         }
911
912         tegra_i2c_mask_irq(i2c_dev, int_mask);
913
914         if (i2c_dev->is_dvc)
915                 dvc_i2c_mask_irq(i2c_dev, DVC_CTRL_REG3_I2C_DONE_INTR_EN);
916
917         if (WARN_ON(ret == 0)) {
918                 dev_err(i2c_dev->dev,
919                         "i2c transfer timed out, addr 0x%04x, data 0x%02x\n",
920                         msg->addr, msg->buf[0]);
921
922                 tegra_i2c_init(i2c_dev);
923                 return -ETIMEDOUT;
924         }
925
926         dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n",
927                 ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
928
929         if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
930                 return 0;
931
932         if ((i2c_dev->chipdata->timeout_irq_occurs_before_bus_inactive) &&
933                 (i2c_dev->msg_err == I2C_ERR_NO_ACK)) {
934                 /*
935                 * In NACK error condition resetting of I2C controller happens
936                 * before STOP condition is properly completed by I2C controller,
937                 * so wait for 2 clock cycle to complete STOP condition.
938                 */
939                 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->last_bus_clk_rate));
940         }
941
942         /*
943          * NACK interrupt is generated before the I2C controller generates the
944          * STOP condition on the bus. So wait for 2 clock periods before resetting
945          * the controller so that STOP condition has been delivered properly.
946          */
947         if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
948                 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->last_bus_clk_rate));
949
950         tegra_i2c_init(i2c_dev);
951
952         /* Arbitration Lost occurs, Start recovery */
953         if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) {
954                 if (i2c_dev->chipdata->has_hw_arb_support) {
955                         INIT_COMPLETION(i2c_dev->msg_complete);
956                         i2c_writel(i2c_dev, I2C_BC_ENABLE
957                                         | I2C_BC_SCLK_THRESHOLD
958                                         | I2C_BC_STOP_COND
959                                         | I2C_BC_TERMINATE
960                                         , I2C_BUS_CLEAR_CNFG);
961                         tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLEAR_DONE);
962
963                         wait_for_completion_timeout(&i2c_dev->msg_complete,
964                                 TEGRA_I2C_TIMEOUT);
965
966                         if (!(i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS) & I2C_BC_STATUS))
967                                 dev_warn(i2c_dev->dev, "Un-recovered Arbitration lost\n");
968                         else
969                                 dev_warn(i2c_dev->dev, "Recovered Arbitration lost\n");
970
971                 } else if (i2c_dev->arb_recovery)
972                         i2c_dev->arb_recovery(i2c_bus->scl_gpio,
973                                                         i2c_bus->sda_gpio);
974                 return -EAGAIN;
975         }
976
977         if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
978                 if (msg->flags & I2C_M_IGNORE_NAK)
979                         return 0;
980                 return -EREMOTEIO;
981         }
982
983         if (i2c_dev->msg_err & I2C_ERR_UNEXPECTED_STATUS)
984                 return -EAGAIN;
985
986         return -EIO;
987 }
988
989 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
990         int num)
991 {
992         struct tegra_i2c_bus *i2c_bus = i2c_get_adapdata(adap);
993         struct tegra_i2c_dev *i2c_dev = i2c_bus->dev;
994         int i;
995         int ret = 0;
996         bool continue_xfer = i2c_dev->chipdata->has_continue_xfer_support;
997
998         rt_mutex_lock(&i2c_dev->dev_lock);
999
1000         if (i2c_dev->is_suspended) {
1001                 rt_mutex_unlock(&i2c_dev->dev_lock);
1002                 return -EBUSY;
1003         }
1004
1005         /* Support I2C_M_NOSTART only if HW support continue xfer. */
1006         for (i = 0; i < num - 1; i++) {
1007                         if ((msgs[i + 1].flags & I2C_M_NOSTART) && !continue_xfer) {
1008                         dev_err(i2c_dev->dev, "mesg %d have illegal flag\n", i + 1);
1009                         rt_mutex_unlock(&i2c_dev->dev_lock);
1010                         return -EINVAL;
1011                 }
1012         }
1013
1014         if (i2c_dev->last_mux != i2c_bus->mux) {
1015                 tegra_pinmux_set_safe_pinmux_table(i2c_dev->last_mux,
1016                         i2c_dev->last_mux_len);
1017                 tegra_pinmux_config_pinmux_table(i2c_bus->mux,
1018                         i2c_bus->mux_len);
1019                 i2c_dev->last_mux = i2c_bus->mux;
1020                 i2c_dev->last_mux_len = i2c_bus->mux_len;
1021         }
1022
1023         if (i2c_dev->last_bus_clk_rate != i2c_bus->bus_clk_rate) {
1024                 tegra_i2c_set_clk_rate(i2c_dev);
1025                 i2c_dev->last_bus_clk_rate = i2c_bus->bus_clk_rate;
1026         }
1027
1028         i2c_dev->msgs = msgs;
1029         i2c_dev->msgs_num = num;
1030
1031         pm_runtime_get_sync(&adap->dev);
1032         tegra_i2c_clock_enable(i2c_dev);
1033
1034         for (i = 0; i < num; i++) {
1035                 enum msg_end_type end_type = MSG_END_STOP;
1036                 enum msg_end_type next_msg_end_type = MSG_END_STOP;
1037
1038                 if (i < (num - 1)) {
1039                         if (msgs[i + 1].flags & I2C_M_NOSTART)
1040                                 end_type = MSG_END_CONTINUE;
1041                         else
1042                                 end_type = MSG_END_REPEAT_START;
1043                         if (i < num - 2) {
1044                                 if (msgs[i + 2].flags & I2C_M_NOSTART)
1045                                         next_msg_end_type = MSG_END_CONTINUE;
1046                                 else
1047                                         next_msg_end_type = MSG_END_REPEAT_START;
1048                         }
1049                         if ((!(msgs[i].flags & I2C_M_RD)) && (msgs[i].len <= 8) && (msgs[i+1].flags & I2C_M_RD)
1050                                         && (next_msg_end_type != MSG_END_CONTINUE) && (end_type == MSG_END_REPEAT_START)) {
1051                                 ret = tegra_i2c_xfer_msg(i2c_bus, &msgs[i], end_type, &msgs[i+1], next_msg_end_type);
1052                                 if (ret)
1053                                         break;
1054                                 i++;
1055                         } else {
1056                                 ret = tegra_i2c_xfer_msg(i2c_bus, &msgs[i], end_type, NULL, next_msg_end_type);
1057                                 if (ret)
1058                                         break;
1059                         }
1060                 } else {
1061                         ret = tegra_i2c_xfer_msg(i2c_bus, &msgs[i], end_type, NULL, next_msg_end_type);
1062                         if (ret)
1063                                 break;
1064                 }
1065         }
1066
1067         tegra_i2c_clock_disable(i2c_dev);
1068         pm_runtime_put(&adap->dev);
1069
1070         rt_mutex_unlock(&i2c_dev->dev_lock);
1071
1072         i2c_dev->msgs = NULL;
1073         i2c_dev->msgs_num = 0;
1074
1075         return ret ?: i;
1076 }
1077
1078 static u32 tegra_i2c_func(struct i2c_adapter *adap)
1079 {
1080         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR |
1081                         I2C_FUNC_PROTOCOL_MANGLING;
1082 }
1083
1084 static const struct i2c_algorithm tegra_i2c_algo = {
1085         .master_xfer    = tegra_i2c_xfer,
1086         .functionality  = tegra_i2c_func,
1087 };
1088
1089 static struct tegra_i2c_chipdata tegra20_i2c_chipdata = {
1090         .timeout_irq_occurs_before_bus_inactive = true,
1091         .has_xfer_complete_interrupt = false,
1092         .has_hw_arb_support = false,
1093         .has_fast_clock = true,
1094         .has_clk_divisor_std_fast_mode = false,
1095         .clk_divisor_std_fast_mode = 0,
1096         .clk_divisor_hs_mode = 3,
1097         .clk_multiplier_hs_mode = 12,
1098 };
1099
1100 static struct tegra_i2c_chipdata tegra11_i2c_chipdata = {
1101         .timeout_irq_occurs_before_bus_inactive = false,
1102         .has_xfer_complete_interrupt = true,
1103         .has_hw_arb_support = true,
1104         .has_fast_clock = false,
1105         .has_clk_divisor_std_fast_mode = true,
1106         .clk_divisor_std_fast_mode = 0x19,
1107         .clk_divisor_hs_mode = 1,
1108         .clk_multiplier_hs_mode = 3,
1109 };
1110
1111 /* Match table for of_platform binding */
1112 static const struct of_device_id tegra_i2c_of_match[] __devinitconst = {
1113         { .compatible = "nvidia,tegra114-i2c", .data = &tegra11_i2c_chipdata, },
1114         { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_chipdata, },
1115         { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_chipdata, },
1116         {},
1117 };
1118 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
1119
1120 static struct platform_device_id tegra_i2c_devtype[] = {
1121         {
1122                 .name = "tegra-i2c",
1123                 .driver_data = (unsigned long)&tegra20_i2c_chipdata,
1124         },
1125         {
1126                 .name = "tegra11-i2c",
1127                 .driver_data = (unsigned long)&tegra11_i2c_chipdata,
1128         }
1129 };
1130
1131 static int __devinit tegra_i2c_probe(struct platform_device *pdev)
1132 {
1133         struct tegra_i2c_dev *i2c_dev;
1134         struct tegra_i2c_platform_data *plat = pdev->dev.platform_data;
1135         struct resource *res;
1136         struct clk *div_clk;
1137         struct clk *fast_clk = NULL;
1138         const unsigned int *prop;
1139         void __iomem *base;
1140         int irq;
1141         int nbus;
1142         int i = 0;
1143         int ret = 0;
1144         struct tegra_i2c_chipdata *chip_data = NULL;
1145         const struct of_device_id *match;
1146
1147         match = of_match_device(of_match_ptr(tegra_i2c_of_match), &pdev->dev);
1148         if (match)
1149                 chip_data = match->data;
1150         else
1151                 chip_data = (struct tegra_i2c_chipdata *)pdev->id_entry->driver_data;
1152
1153         if (!plat || !chip_data) {
1154                 dev_err(&pdev->dev, "no platform/chip data?\n");
1155                 return -ENODEV;
1156         }
1157
1158 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1159         chip_data->has_continue_xfer_support = true;
1160 #endif
1161
1162         if (plat->bus_count <= 0 || plat->adapter_nr < 0) {
1163                 dev_err(&pdev->dev, "invalid platform data?\n");
1164                 return -ENODEV;
1165         }
1166
1167         WARN_ON(plat->bus_count > TEGRA_I2C_MAX_BUS);
1168         nbus = min(TEGRA_I2C_MAX_BUS, plat->bus_count);
1169
1170         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1171         if (!res) {
1172                 dev_err(&pdev->dev, "no mem resource\n");
1173                 return -EINVAL;
1174         }
1175
1176         base = devm_request_and_ioremap(&pdev->dev, res);
1177         if (!base) {
1178                 dev_err(&pdev->dev, "Cannot request/ioremap I2C registers\n");
1179                 return -EADDRNOTAVAIL;
1180         }
1181
1182         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1183         if (!res) {
1184                 dev_err(&pdev->dev, "no irq resource\n");
1185                 return -EINVAL;
1186         }
1187         irq = res->start;
1188
1189         i2c_dev = devm_kzalloc(&pdev->dev, sizeof(struct tegra_i2c_dev) +
1190                           (nbus-1) * sizeof(struct tegra_i2c_bus), GFP_KERNEL);
1191         if (!i2c_dev) {
1192                 dev_err(&pdev->dev, "Could not allocate struct tegra_i2c_dev");
1193                 return -ENOMEM;
1194         }
1195
1196         i2c_dev->chipdata = chip_data;
1197
1198         if (!i2c_dev->chipdata) {
1199                 dev_err(&pdev->dev, "Error: Chip data is not valid\n");
1200                 return -ENOMEM;
1201         }
1202
1203         div_clk = devm_clk_get(&pdev->dev, "div-clk");
1204         if (IS_ERR(div_clk)) {
1205                 dev_err(&pdev->dev, "missing controller clock");
1206                 return PTR_ERR(div_clk);
1207         }
1208
1209         if (i2c_dev->chipdata->has_fast_clock) {
1210                 fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
1211                 if (IS_ERR(fast_clk)) {
1212                         dev_err(&pdev->dev, "missing controller fast clock");
1213                         return PTR_ERR(fast_clk);
1214                 }
1215         }
1216
1217         i2c_dev->base = base;
1218         i2c_dev->div_clk = div_clk;
1219         if (i2c_dev->chipdata->has_fast_clock)
1220                 i2c_dev->fast_clk = fast_clk;
1221         i2c_dev->irq = irq;
1222         i2c_dev->cont_id = pdev->id;
1223         i2c_dev->dev = &pdev->dev;
1224         i2c_dev->is_clkon_always = plat->is_clkon_always;
1225
1226         i2c_dev->last_bus_clk_rate = 100000; /* default clock rate */
1227         if (plat) {
1228                 i2c_dev->last_bus_clk_rate = plat->bus_clk_rate[0];
1229
1230         } else if (i2c_dev->dev->of_node) {    /* if there is a device tree node ... */
1231                 /* TODO: DAN: this doesn't work for DT */
1232                 prop = of_get_property(i2c_dev->dev->of_node,
1233                                 "clock-frequency", NULL);
1234                 if (prop)
1235                         i2c_dev->last_bus_clk_rate = be32_to_cpup(prop);
1236
1237                 /* FIXME! Populate the Tegra30 and then support M_NOSTART */
1238                 i2c_dev->chipdata->has_continue_xfer_support = false;
1239         }
1240
1241         i2c_dev->is_high_speed_enable = plat->is_high_speed_enable;
1242         i2c_dev->last_bus_clk_rate = plat->bus_clk_rate[0] ?: 100000;
1243         i2c_dev->msgs = NULL;
1244         i2c_dev->msgs_num = 0;
1245         rt_mutex_init(&i2c_dev->dev_lock);
1246
1247         if (pdev->dev.of_node)
1248                 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
1249                                                 "nvidia,tegra20-i2c-dvc");
1250         else
1251                 i2c_dev->is_dvc = plat->is_dvc;
1252         i2c_dev->slave_addr = plat->slave_addr;
1253         i2c_dev->hs_master_code = plat->hs_master_code;
1254         i2c_dev->is_dvc = plat->is_dvc;
1255         init_completion(&i2c_dev->msg_complete);
1256
1257         if (!i2c_dev->chipdata->has_xfer_complete_interrupt)
1258                 spin_lock_init(&i2c_dev->fifo_lock);
1259
1260         if (!i2c_dev->chipdata->has_hw_arb_support)
1261                 i2c_dev->arb_recovery = plat->arb_recovery;
1262
1263         platform_set_drvdata(pdev, i2c_dev);
1264
1265         if (i2c_dev->is_clkon_always)
1266                 tegra_i2c_clock_enable(i2c_dev);
1267
1268         ret = tegra_i2c_init(i2c_dev);
1269         if (ret) {
1270                 dev_err(&pdev->dev, "Failed to initialize i2c controller");
1271                 return ret;
1272         }
1273
1274         ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
1275                         tegra_i2c_isr, IRQF_NO_SUSPEND,
1276                         dev_name(&pdev->dev), i2c_dev);
1277         if (ret) {
1278                 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
1279                 return ret;
1280         }
1281
1282         pm_runtime_enable(&pdev->dev);
1283
1284         for (i = 0; i < nbus; i++) {
1285                 struct tegra_i2c_bus *i2c_bus = &i2c_dev->busses[i];
1286
1287                 i2c_bus->dev = i2c_dev;
1288                 i2c_bus->mux = plat->bus_mux[i];
1289                 i2c_bus->mux_len = plat->bus_mux_len[i];
1290                 i2c_bus->bus_clk_rate = plat->bus_clk_rate[i] ?: 100000;
1291
1292                 if (i2c_dev->arb_recovery) {
1293                         i2c_bus->scl_gpio = plat->scl_gpio[i];
1294                         i2c_bus->sda_gpio = plat->sda_gpio[i];
1295                 }
1296                 i2c_bus->adapter.dev.of_node = pdev->dev.of_node;
1297                 i2c_bus->adapter.algo = &tegra_i2c_algo;
1298                 i2c_set_adapdata(&i2c_bus->adapter, i2c_bus);
1299                 i2c_bus->adapter.owner = THIS_MODULE;
1300                 i2c_bus->adapter.class = I2C_CLASS_HWMON;
1301                 strlcpy(i2c_bus->adapter.name, "Tegra I2C adapter",
1302                         sizeof(i2c_bus->adapter.name));
1303                 i2c_bus->adapter.dev.parent = &pdev->dev;
1304                 i2c_bus->adapter.nr = plat->adapter_nr + i;
1305
1306                 if (plat->retries)
1307                         i2c_bus->adapter.retries = plat->retries;
1308                 else
1309                         i2c_bus->adapter.retries = TEGRA_I2C_RETRIES;
1310
1311                 if (plat->timeout)
1312                         i2c_bus->adapter.timeout = plat->timeout;
1313
1314                 ret = i2c_add_numbered_adapter(&i2c_bus->adapter);
1315                 if (ret) {
1316                         dev_err(&pdev->dev, "Failed to add I2C adapter\n");
1317                         goto err_del_bus;
1318                 }
1319
1320                 of_i2c_register_devices(&i2c_bus->adapter);
1321                 pm_runtime_enable(&i2c_bus->adapter.dev);
1322
1323                 i2c_dev->bus_count++;
1324         }
1325
1326
1327         return 0;
1328
1329 err_del_bus:
1330         while (i2c_dev->bus_count--)
1331                 i2c_del_adapter(&i2c_dev->busses[i2c_dev->bus_count].adapter);
1332         return ret;
1333 }
1334
1335 static int __devexit tegra_i2c_remove(struct platform_device *pdev)
1336 {
1337         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1338
1339         while (i2c_dev->bus_count--) {
1340                 i2c_del_adapter(&i2c_dev->busses[i2c_dev->bus_count].adapter);
1341                 pm_runtime_disable(&i2c_dev->busses[i2c_dev->bus_count].adapter.dev);
1342         }
1343
1344         if (i2c_dev->is_clkon_always)
1345                 tegra_i2c_clock_disable(i2c_dev);
1346
1347         pm_runtime_disable(&pdev->dev);
1348         return 0;
1349 }
1350
1351 #ifdef CONFIG_PM_SLEEP
1352 static int tegra_i2c_suspend_noirq(struct device *dev)
1353 {
1354         struct platform_device *pdev = to_platform_device(dev);
1355         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1356
1357         rt_mutex_lock(&i2c_dev->dev_lock);
1358
1359         i2c_dev->is_suspended = true;
1360         if (i2c_dev->is_clkon_always)
1361                 tegra_i2c_clock_disable(i2c_dev);
1362
1363         rt_mutex_unlock(&i2c_dev->dev_lock);
1364
1365         return 0;
1366 }
1367
1368 static int tegra_i2c_resume_noirq(struct device *dev)
1369 {
1370         struct platform_device *pdev = to_platform_device(dev);
1371         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1372         int ret;
1373
1374         rt_mutex_lock(&i2c_dev->dev_lock);
1375
1376         if (i2c_dev->is_clkon_always)
1377                 tegra_i2c_clock_enable(i2c_dev);
1378
1379         ret = tegra_i2c_init(i2c_dev);
1380
1381         if (ret) {
1382                 rt_mutex_unlock(&i2c_dev->dev_lock);
1383                 return ret;
1384         }
1385
1386         i2c_dev->is_suspended = false;
1387
1388         rt_mutex_unlock(&i2c_dev->dev_lock);
1389
1390         return 0;
1391 }
1392
1393 static const struct dev_pm_ops tegra_i2c_pm = {
1394         .suspend_noirq = tegra_i2c_suspend_noirq,
1395         .resume_noirq = tegra_i2c_resume_noirq,
1396 };
1397 #define TEGRA_I2C_PM    (&tegra_i2c_pm)
1398 #else
1399 #define TEGRA_I2C_PM    NULL
1400 #endif
1401
1402 static struct platform_driver tegra_i2c_driver = {
1403         .probe   = tegra_i2c_probe,
1404         .remove  = __devexit_p(tegra_i2c_remove),
1405         .id_table = tegra_i2c_devtype,
1406         .driver  = {
1407                 .name  = "tegra-i2c",
1408                 .owner = THIS_MODULE,
1409                 .of_match_table = of_match_ptr(tegra_i2c_of_match),
1410                 .pm    = TEGRA_I2C_PM,
1411         },
1412 };
1413
1414 static int __init tegra_i2c_init_driver(void)
1415 {
1416         return platform_driver_register(&tegra_i2c_driver);
1417 }
1418
1419 static void __exit tegra_i2c_exit_driver(void)
1420 {
1421         platform_driver_unregister(&tegra_i2c_driver);
1422 }
1423
1424 subsys_initcall(tegra_i2c_init_driver);
1425 module_exit(tegra_i2c_exit_driver);
1426
1427 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
1428 MODULE_AUTHOR("Colin Cross");
1429 MODULE_LICENSE("GPL v2");