i2c: tegra: rename fast clock and div clock
[linux-2.6.git] / drivers / i2c / busses / i2c-tegra.c
1 /*
2  * drivers/i2c/busses/i2c-tegra.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Colin Cross <ccross@android.com>
6  *
7  * Copyright (C) 2010-2012 NVIDIA Corporation
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 /*#define DEBUG           1*/
21 /*#define VERBOSE_DEBUG   1*/
22
23 #include <linux/kernel.h>
24 #include <linux/init.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/err.h>
28 #include <linux/i2c.h>
29 #include <linux/io.h>
30 #include <linux/interrupt.h>
31 #include <linux/delay.h>
32 #include <linux/slab.h>
33 #include <linux/i2c-tegra.h>
34 #include <linux/of_i2c.h>
35 #include <linux/spinlock.h>
36
37 #include <asm/unaligned.h>
38
39 #include <mach/clk.h>
40 #include <mach/pinmux.h>
41
42 #define TEGRA_I2C_TIMEOUT                       (msecs_to_jiffies(1000))
43 #define TEGRA_I2C_RETRIES                       3
44 #define BYTES_PER_FIFO_WORD                     4
45
46 #define I2C_CNFG                                0x000
47 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT             12
48 #define I2C_CNFG_PACKET_MODE_EN                 (1<<10)
49 #define I2C_CNFG_NEW_MASTER_FSM                 (1<<11)
50 #define I2C_STATUS                              0x01C
51 #define I2C_STATUS_BUSY                         (1<<8)
52 #define I2C_SL_CNFG                             0x020
53 #define I2C_SL_CNFG_NACK                        (1<<1)
54 #define I2C_SL_CNFG_NEWSL                       (1<<2)
55 #define I2C_SL_ADDR1                            0x02c
56 #define I2C_SL_ADDR2                            0x030
57 #define I2C_TX_FIFO                             0x050
58 #define I2C_RX_FIFO                             0x054
59 #define I2C_PACKET_TRANSFER_STATUS              0x058
60 #define I2C_FIFO_CONTROL                        0x05c
61 #define I2C_FIFO_CONTROL_TX_FLUSH               (1<<1)
62 #define I2C_FIFO_CONTROL_RX_FLUSH               (1<<0)
63 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT          5
64 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT          2
65 #define I2C_FIFO_STATUS                         0x060
66 #define I2C_FIFO_STATUS_TX_MASK                 0xF0
67 #define I2C_FIFO_STATUS_TX_SHIFT                4
68 #define I2C_FIFO_STATUS_RX_MASK                 0x0F
69 #define I2C_FIFO_STATUS_RX_SHIFT                0
70 #define I2C_INT_MASK                            0x064
71 #define I2C_INT_STATUS                          0x068
72 #define I2C_INT_PACKET_XFER_COMPLETE            (1<<7)
73 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE       (1<<6)
74 #define I2C_INT_TX_FIFO_OVERFLOW                (1<<5)
75 #define I2C_INT_RX_FIFO_UNDERFLOW               (1<<4)
76 #define I2C_INT_NO_ACK                          (1<<3)
77 #define I2C_INT_ARBITRATION_LOST                (1<<2)
78 #define I2C_INT_TX_FIFO_DATA_REQ                (1<<1)
79 #define I2C_INT_RX_FIFO_DATA_REQ                (1<<0)
80 #define I2C_CLK_DIVISOR                         0x06c
81
82 #define DVC_CTRL_REG1                           0x000
83 #define DVC_CTRL_REG1_INTR_EN                   (1<<10)
84 #define DVC_CTRL_REG2                           0x004
85 #define DVC_CTRL_REG3                           0x008
86 #define DVC_CTRL_REG3_SW_PROG                   (1<<26)
87 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN          (1<<30)
88 #define DVC_STATUS                              0x00c
89 #define DVC_STATUS_I2C_DONE_INTR                (1<<30)
90
91 #define I2C_ERR_NONE                            0x00
92 #define I2C_ERR_NO_ACK                          0x01
93 #define I2C_ERR_ARBITRATION_LOST                0x02
94 #define I2C_ERR_UNKNOWN_INTERRUPT               0x04
95 #define I2C_ERR_UNEXPECTED_STATUS               0x08
96
97 #define PACKET_HEADER0_HEADER_SIZE_SHIFT        28
98 #define PACKET_HEADER0_PACKET_ID_SHIFT          16
99 #define PACKET_HEADER0_CONT_ID_SHIFT            12
100 #define PACKET_HEADER0_PROTOCOL_I2C             (1<<4)
101
102 #define I2C_HEADER_HIGHSPEED_MODE               (1<<22)
103 #define I2C_HEADER_CONT_ON_NAK                  (1<<21)
104 #define I2C_HEADER_SEND_START_BYTE              (1<<20)
105 #define I2C_HEADER_READ                         (1<<19)
106 #define I2C_HEADER_10BIT_ADDR                   (1<<18)
107 #define I2C_HEADER_IE_ENABLE                    (1<<17)
108 #define I2C_HEADER_REPEAT_START                 (1<<16)
109 #define I2C_HEADER_CONTINUE_XFER                (1<<15)
110 #define I2C_HEADER_MASTER_ADDR_SHIFT            12
111 #define I2C_HEADER_SLAVE_ADDR_SHIFT             1
112
113 #define SL_ADDR1(addr) (addr & 0xff)
114 #define SL_ADDR2(addr) ((addr >> 8) & 0xff)
115
116 /*
117  * msg_end_type: The bus control which need to be send at end of transfer.
118  * @MSG_END_STOP: Send stop pulse at end of transfer.
119  * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
120  * @MSG_END_CONTINUE: The following on message is coming and so do not send
121  *              stop or repeat start.
122  */
123
124 enum msg_end_type {
125         MSG_END_STOP,
126         MSG_END_REPEAT_START,
127         MSG_END_CONTINUE,
128 };
129
130 struct tegra_i2c_dev;
131
132 /**
133  * struct tegra_i2c_hw_feature : Different HW support on Tegra
134  * @has_continue_xfer_support: Continue transfer supports.
135  */
136
137 struct tegra_i2c_hw_feature {
138         bool has_continue_xfer_support;
139 };
140
141 struct tegra_i2c_bus {
142         struct tegra_i2c_dev *dev;
143         const struct tegra_pingroup_config *mux;
144         int mux_len;
145         unsigned long bus_clk_rate;
146         struct i2c_adapter adapter;
147         int scl_gpio;
148         int sda_gpio;
149 };
150
151 /**
152  * struct tegra_i2c_dev - per device i2c context
153  * @dev: device reference for power management
154  * @hw: Tegra i2c hw feature.
155  * @adapter: core i2c layer adapter information
156  * @div_clk: clock reference for div clock of i2c controller.
157  * @fast_clk: clock reference for fast clock of i2c controller.
158  * @base: ioremapped registers cookie
159  * @cont_id: i2c controller id, used for for packet header
160  * @irq: irq number of transfer complete interrupt
161  * @is_dvc: identifies the DVC i2c controller, has a different register layout
162  * @msg_complete: transfer completion notifier
163  * @msg_err: error code for completed message
164  * @msg_buf: pointer to current message data
165  * @msg_buf_remaining: size of unsent data in the message buffer
166  * @msg_read: identifies read transfers
167  * @bus_clk_rate: current i2c bus clock rate
168  * @is_suspended: prevents i2c controller accesses after suspend is called
169  */
170 struct tegra_i2c_dev {
171         struct device *dev;
172         struct tegra_i2c_hw_feature *hw;
173         struct clk *div_clk;
174         struct clk *fast_clk;
175         struct rt_mutex dev_lock;
176         spinlock_t fifo_lock;
177         void __iomem *base;
178         int cont_id;
179         int irq;
180         bool irq_disabled;
181         int is_dvc;
182         struct completion msg_complete;
183         int msg_err;
184         u8 *msg_buf;
185         u32 packet_header;
186         u32 payload_size;
187         u32 io_header;
188         size_t msg_buf_remaining;
189         int msg_read;
190         struct i2c_msg *msgs;
191         int msg_add;
192         int msgs_num;
193         bool is_suspended;
194         int bus_count;
195         const struct tegra_pingroup_config *last_mux;
196         int last_mux_len;
197         unsigned long last_bus_clk_rate;
198         u16 slave_addr;
199         bool is_clkon_always;
200         bool is_high_speed_enable;
201         u16 hs_master_code;
202         int (*arb_recovery)(int scl_gpio, int sda_gpio);
203         struct tegra_i2c_bus busses[1];
204 };
205
206 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
207 {
208         writel(val, i2c_dev->base + reg);
209 }
210
211 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
212 {
213         return readl(i2c_dev->base + reg);
214 }
215
216 static void dvc_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
217 {
218         u32 int_mask = dvc_readl(i2c_dev, DVC_CTRL_REG3);
219         int_mask &= ~mask;
220         dvc_writel(i2c_dev, int_mask, DVC_CTRL_REG3);
221 }
222
223 static void dvc_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
224 {
225         u32 int_mask = dvc_readl(i2c_dev, DVC_CTRL_REG3);
226         int_mask |= mask;
227         dvc_writel(i2c_dev, int_mask, DVC_CTRL_REG3);
228 }
229
230 /*
231  * i2c_writel and i2c_readl will offset the register if necessary to talk
232  * to the I2C block inside the DVC block
233  */
234 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
235         unsigned long reg)
236 {
237         if (i2c_dev->is_dvc)
238                 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
239         return reg;
240 }
241
242 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
243         unsigned long reg)
244 {
245         writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
246
247         /* Read back register to make sure that register writes completed */
248         if (reg != I2C_TX_FIFO)
249                 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
250 }
251
252 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
253 {
254         return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
255 }
256
257 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
258         unsigned long reg, int len)
259 {
260         writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
261 }
262
263 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
264         unsigned long reg, int len)
265 {
266         readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
267 }
268
269 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
270 {
271         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
272         int_mask &= ~mask;
273         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
274 }
275
276 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
277 {
278         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
279         int_mask |= mask;
280         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
281 }
282
283 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
284 {
285         unsigned long timeout = jiffies + HZ;
286         u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
287         val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
288         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
289
290         while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
291                 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
292                 if (time_after(jiffies, timeout)) {
293                         dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
294                         return -ETIMEDOUT;
295                 }
296                 msleep(1);
297         }
298         return 0;
299 }
300
301 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
302 {
303         u32 val;
304         int rx_fifo_avail;
305         u8 *buf = i2c_dev->msg_buf;
306         size_t buf_remaining = i2c_dev->msg_buf_remaining;
307         int words_to_transfer;
308
309         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
310         rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
311                 I2C_FIFO_STATUS_RX_SHIFT;
312
313         /* Rounds down to not include partial word at the end of buf */
314         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
315         if (words_to_transfer > rx_fifo_avail)
316                 words_to_transfer = rx_fifo_avail;
317
318         i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
319
320         buf += words_to_transfer * BYTES_PER_FIFO_WORD;
321         buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
322         rx_fifo_avail -= words_to_transfer;
323
324         /*
325          * If there is a partial word at the end of buf, handle it manually to
326          * prevent overwriting past the end of buf
327          */
328         if (rx_fifo_avail > 0 && buf_remaining > 0) {
329                 BUG_ON(buf_remaining > 3);
330                 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
331                 memcpy(buf, &val, buf_remaining);
332                 buf_remaining = 0;
333                 rx_fifo_avail--;
334         }
335
336         BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
337         i2c_dev->msg_buf_remaining = buf_remaining;
338         i2c_dev->msg_buf = buf;
339         return 0;
340 }
341
342 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
343 {
344         u32 val;
345         int tx_fifo_avail;
346         u8 *buf;
347         size_t buf_remaining;
348         int words_to_transfer;
349         unsigned long flags;
350
351         spin_lock_irqsave(&i2c_dev->fifo_lock, flags);
352         if (!i2c_dev->msg_buf_remaining) {
353                 spin_unlock_irqrestore(&i2c_dev->fifo_lock, flags);
354                 return 0;
355         }
356
357         buf = i2c_dev->msg_buf;
358         buf_remaining = i2c_dev->msg_buf_remaining;
359
360         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
361         tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
362                 I2C_FIFO_STATUS_TX_SHIFT;
363
364         /* Rounds down to not include partial word at the end of buf */
365         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
366
367         /* It's very common to have < 4 bytes, so optimize that case. */
368         if (words_to_transfer) {
369                 if (words_to_transfer > tx_fifo_avail)
370                         words_to_transfer = tx_fifo_avail;
371
372                 /*
373                  * Update state before writing to FIFO.  If this casues us
374                  * to finish writing all bytes (AKA buf_remaining goes to 0) we
375                  * have a potential for an interrupt (PACKET_XFER_COMPLETE is
376                  * not maskable).  We need to make sure that the isr sees
377                  * buf_remaining as 0 and doesn't call us back re-entrantly.
378                  */
379                 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
380                 tx_fifo_avail -= words_to_transfer;
381                 i2c_dev->msg_buf_remaining = buf_remaining;
382                 i2c_dev->msg_buf = buf +
383                         words_to_transfer * BYTES_PER_FIFO_WORD;
384                 barrier();
385
386                 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
387
388                 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
389         }
390
391         /*
392          * If there is a partial word at the end of buf, handle it manually to
393          * prevent reading past the end of buf, which could cross a page
394          * boundary and fault.
395          */
396         if (tx_fifo_avail > 0 && buf_remaining > 0) {
397                 if (buf_remaining > 3) {
398                         dev_err(i2c_dev->dev,
399                                 "Remaining buffer more than 3 %d\n",
400                                 buf_remaining);
401                         BUG();
402                 }
403                 memcpy(&val, buf, buf_remaining);
404
405                 /* Again update before writing to FIFO to make sure isr sees. */
406                 i2c_dev->msg_buf_remaining = 0;
407                 i2c_dev->msg_buf = NULL;
408                 barrier();
409
410                 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
411         }
412
413         spin_unlock_irqrestore(&i2c_dev->fifo_lock, flags);
414
415         return 0;
416 }
417
418 /*
419  * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
420  * block.  This block is identical to the rest of the I2C blocks, except that
421  * it only supports master mode, it has registers moved around, and it needs
422  * some extra init to get it into I2C mode.  The register moves are handled
423  * by i2c_readl and i2c_writel
424  */
425 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
426 {
427         u32 val = 0;
428         val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
429         val |= DVC_CTRL_REG3_SW_PROG;
430         dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
431
432         val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
433         val |= DVC_CTRL_REG1_INTR_EN;
434         dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
435 }
436
437 static void tegra_i2c_slave_init(struct tegra_i2c_dev *i2c_dev)
438 {
439         u32 val = I2C_SL_CNFG_NEWSL | I2C_SL_CNFG_NACK;
440
441         i2c_writel(i2c_dev, val, I2C_SL_CNFG);
442
443         if (i2c_dev->slave_addr) {
444                 u16 addr = i2c_dev->slave_addr;
445
446                 i2c_writel(i2c_dev, SL_ADDR1(addr), I2C_SL_ADDR1);
447                 i2c_writel(i2c_dev, SL_ADDR2(addr), I2C_SL_ADDR2);
448         }
449 }
450
451 static inline int tegra_i2c_clock_enable(struct tegra_i2c_dev *i2c_dev)
452 {
453         int ret;
454         ret = clk_enable(i2c_dev->fast_clk);
455         if (ret < 0) {
456                 dev_err(i2c_dev->dev,
457                         "Enabling fast clk failed, err %d\n", ret);
458                 return ret;
459         }
460         ret = clk_enable(i2c_dev->div_clk);
461         if (ret < 0) {
462                 dev_err(i2c_dev->dev,
463                         "Enabling div clk failed, err %d\n", ret);
464                 clk_disable(i2c_dev->fast_clk);
465         }
466         return ret;
467 }
468
469 static inline void tegra_i2c_clock_disable(struct tegra_i2c_dev *i2c_dev)
470 {
471         clk_disable(i2c_dev->div_clk);
472         clk_disable(i2c_dev->fast_clk);
473 }
474
475 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
476 {
477         u32 val;
478         int err = 0;
479
480         tegra_i2c_clock_enable(i2c_dev);
481
482         tegra_periph_reset_assert(i2c_dev->div_clk);
483         udelay(2);
484         tegra_periph_reset_deassert(i2c_dev->div_clk);
485
486         if (i2c_dev->is_dvc)
487                 tegra_dvc_init(i2c_dev);
488
489         val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
490                 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
491         i2c_writel(i2c_dev, val, I2C_CNFG);
492         i2c_writel(i2c_dev, 0, I2C_INT_MASK);
493         clk_set_rate(i2c_dev->div_clk, i2c_dev->last_bus_clk_rate * 8);
494         i2c_writel(i2c_dev, 0x3, I2C_CLK_DIVISOR);
495
496         if (!i2c_dev->is_dvc) {
497                 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
498                 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
499                 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
500                 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
501                 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
502
503         }
504
505         val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
506                 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
507         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
508
509         if (!i2c_dev->is_dvc)
510                 tegra_i2c_slave_init(i2c_dev);
511
512         if (tegra_i2c_flush_fifos(i2c_dev))
513                 err = -ETIMEDOUT;
514
515         tegra_i2c_clock_disable(i2c_dev);
516
517         if (i2c_dev->irq_disabled) {
518                 i2c_dev->irq_disabled = 0;
519                 enable_irq(i2c_dev->irq);
520         }
521
522         return err;
523 }
524
525 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
526 {
527         u32 status;
528         const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST | I2C_INT_TX_FIFO_OVERFLOW;
529         struct tegra_i2c_dev *i2c_dev = dev_id;
530
531         status = i2c_readl(i2c_dev, I2C_INT_STATUS);
532
533         if (status == 0) {
534                 dev_warn(i2c_dev->dev, "unknown interrupt Add 0x%02x\n",
535                                                 i2c_dev->msg_add);
536                 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
537
538                 if (!i2c_dev->irq_disabled) {
539                         disable_irq_nosync(i2c_dev->irq);
540                         i2c_dev->irq_disabled = 1;
541                 }
542
543                 goto err;
544         }
545
546         if (unlikely(status & status_err)) {
547                 dev_warn(i2c_dev->dev, "I2c error status 0x%08x\n", status);
548                 if (status & I2C_INT_NO_ACK) {
549                         i2c_dev->msg_err |= I2C_ERR_NO_ACK;
550                         dev_warn(i2c_dev->dev, "no acknowledge from address"
551                                         " 0x%x\n", i2c_dev->msg_add);
552                         dev_warn(i2c_dev->dev, "Packet status 0x%08x\n",
553                                 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS));
554                 }
555
556                 if (status & I2C_INT_ARBITRATION_LOST) {
557                         i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
558                         dev_warn(i2c_dev->dev, "arbitration lost during "
559                                 " communicate to add 0x%x\n", i2c_dev->msg_add);
560                         dev_warn(i2c_dev->dev, "Packet status 0x%08x\n",
561                                 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS));
562                 }
563
564                 if (status & I2C_INT_TX_FIFO_OVERFLOW) {
565                         i2c_dev->msg_err |= I2C_INT_TX_FIFO_OVERFLOW;
566                         dev_warn(i2c_dev->dev, "Tx fifo overflow during "
567                                 " communicate to add 0x%x\n", i2c_dev->msg_add);
568                         dev_warn(i2c_dev->dev, "Packet status 0x%08x\n",
569                                 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS));
570                 }
571                 goto err;
572         }
573
574         if (unlikely((i2c_readl(i2c_dev, I2C_STATUS) & I2C_STATUS_BUSY)
575                                 && (status == I2C_INT_TX_FIFO_DATA_REQ)
576                                 && i2c_dev->msg_read
577                                 && i2c_dev->msg_buf_remaining)) {
578                 dev_warn(i2c_dev->dev, "unexpected status\n");
579                 i2c_dev->msg_err |= I2C_ERR_UNEXPECTED_STATUS;
580
581                 if (!i2c_dev->irq_disabled) {
582                         disable_irq_nosync(i2c_dev->irq);
583                         i2c_dev->irq_disabled = 1;
584                 }
585
586                 goto err;
587         }
588
589         if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
590                 if (i2c_dev->msg_buf_remaining)
591                         tegra_i2c_empty_rx_fifo(i2c_dev);
592                 else
593                         BUG();
594         }
595
596         if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
597                 if (i2c_dev->msg_buf_remaining)
598                         tegra_i2c_fill_tx_fifo(i2c_dev);
599                 else
600                         tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
601         }
602
603         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
604
605         if (i2c_dev->is_dvc)
606                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
607
608         if (status & I2C_INT_PACKET_XFER_COMPLETE) {
609                 BUG_ON(i2c_dev->msg_buf_remaining);
610                 complete(&i2c_dev->msg_complete);
611         }
612
613         return IRQ_HANDLED;
614
615 err:
616         dev_dbg(i2c_dev->dev, "reg: 0x%08x 0x%08x 0x%08x 0x%08x\n",
617                  i2c_readl(i2c_dev, I2C_CNFG), i2c_readl(i2c_dev, I2C_STATUS),
618                  i2c_readl(i2c_dev, I2C_INT_STATUS),
619                  i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS));
620
621         dev_dbg(i2c_dev->dev, "packet: 0x%08x %u 0x%08x\n",
622                  i2c_dev->packet_header, i2c_dev->payload_size,
623                  i2c_dev->io_header);
624
625         if (i2c_dev->msgs) {
626                 struct i2c_msg *msgs = i2c_dev->msgs;
627                 int i;
628
629                 for (i = 0; i < i2c_dev->msgs_num; i++)
630                         dev_dbg(i2c_dev->dev,
631                                  "msgs[%d] %c, addr=0x%04x, len=%d\n",
632                                  i, (msgs[i].flags & I2C_M_RD) ? 'R' : 'W',
633                                  msgs[i].addr, msgs[i].len);
634         }
635
636         /* An error occurred, mask all interrupts */
637         tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
638                 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
639                 I2C_INT_RX_FIFO_DATA_REQ | I2C_INT_TX_FIFO_OVERFLOW);
640
641         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
642
643         /* An error occured, mask dvc interrupt */
644         if (i2c_dev->is_dvc)
645                 dvc_i2c_mask_irq(i2c_dev, DVC_CTRL_REG3_I2C_DONE_INTR_EN);
646
647         if (i2c_dev->is_dvc)
648                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
649
650         complete(&i2c_dev->msg_complete);
651         return IRQ_HANDLED;
652 }
653
654 static int tegra_i2c_xfer_msg(struct tegra_i2c_bus *i2c_bus,
655         struct i2c_msg *msg, enum msg_end_type end_state)
656 {
657         struct tegra_i2c_dev *i2c_dev = i2c_bus->dev;
658         u32 int_mask;
659         int ret;
660         int arb_stat;
661
662         if (msg->len == 0)
663                 return -EINVAL;
664
665         tegra_i2c_flush_fifos(i2c_dev);
666
667         i2c_dev->msg_buf = msg->buf;
668         i2c_dev->msg_buf_remaining = msg->len;
669         i2c_dev->msg_err = I2C_ERR_NONE;
670         i2c_dev->msg_read = (msg->flags & I2C_M_RD);
671         INIT_COMPLETION(i2c_dev->msg_complete);
672         i2c_dev->msg_add = msg->addr;
673
674         i2c_dev->packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
675                         PACKET_HEADER0_PROTOCOL_I2C |
676                         (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
677                         (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
678         i2c_writel(i2c_dev, i2c_dev->packet_header, I2C_TX_FIFO);
679
680         i2c_dev->payload_size = msg->len - 1;
681         i2c_writel(i2c_dev, i2c_dev->payload_size, I2C_TX_FIFO);
682
683         i2c_dev->io_header = I2C_HEADER_IE_ENABLE;
684         if (end_state == MSG_END_CONTINUE)
685                 i2c_dev->io_header |= I2C_HEADER_CONTINUE_XFER;
686         else if (end_state == MSG_END_REPEAT_START)
687                 i2c_dev->io_header |= I2C_HEADER_REPEAT_START;
688
689         if (msg->flags & I2C_M_TEN) {
690                 i2c_dev->io_header |= msg->addr;
691                 i2c_dev->io_header |= I2C_HEADER_10BIT_ADDR;
692         } else {
693                 i2c_dev->io_header |= (msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT);
694         }
695         if (msg->flags & I2C_M_IGNORE_NAK)
696                 i2c_dev->io_header |= I2C_HEADER_CONT_ON_NAK;
697         if (msg->flags & I2C_M_RD)
698                 i2c_dev->io_header |= I2C_HEADER_READ;
699         if (i2c_dev->is_high_speed_enable) {
700                 i2c_dev->io_header |= I2C_HEADER_HIGHSPEED_MODE;
701                 i2c_dev->io_header |= ((i2c_dev->hs_master_code & 0x7) <<  I2C_HEADER_MASTER_ADDR_SHIFT);
702         }
703         i2c_writel(i2c_dev, i2c_dev->io_header, I2C_TX_FIFO);
704
705         if (!(msg->flags & I2C_M_RD))
706                 tegra_i2c_fill_tx_fifo(i2c_dev);
707
708         if (i2c_dev->is_dvc)
709                 dvc_i2c_unmask_irq(i2c_dev, DVC_CTRL_REG3_I2C_DONE_INTR_EN);
710
711         int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST | I2C_INT_TX_FIFO_OVERFLOW;
712         if (msg->flags & I2C_M_RD)
713                 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
714         else if (i2c_dev->msg_buf_remaining)
715                 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
716         tegra_i2c_unmask_irq(i2c_dev, int_mask);
717         dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
718                 i2c_readl(i2c_dev, I2C_INT_MASK));
719
720         ret = wait_for_completion_timeout(&i2c_dev->msg_complete,
721                                         TEGRA_I2C_TIMEOUT);
722         tegra_i2c_mask_irq(i2c_dev, int_mask);
723
724         if (i2c_dev->is_dvc)
725                 dvc_i2c_mask_irq(i2c_dev, DVC_CTRL_REG3_I2C_DONE_INTR_EN);
726
727         if (WARN_ON(ret == 0)) {
728                 dev_err(i2c_dev->dev,
729                         "i2c transfer timed out, addr 0x%04x, data 0x%02x\n",
730                         msg->addr, msg->buf[0]);
731
732                 tegra_i2c_init(i2c_dev);
733                 return -ETIMEDOUT;
734         }
735
736         dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n",
737                 ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
738
739         if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
740                 return 0;
741
742         /* Arbitration Lost occurs, Start recovery */
743         if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) {
744                 if (i2c_dev->arb_recovery) {
745                         arb_stat = i2c_dev->arb_recovery(i2c_bus->scl_gpio, i2c_bus->sda_gpio);
746                         if (!arb_stat)
747                                 return -EAGAIN;
748                 }
749         }
750
751         /*
752          * NACK interrupt is generated before the I2C controller generates the
753          * STOP condition on the bus. So wait for 2 clock periods before resetting
754          * the controller so that STOP condition has been delivered properly.
755          */
756         if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
757                 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->last_bus_clk_rate));
758
759         tegra_i2c_init(i2c_dev);
760
761         if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
762                 if (msg->flags & I2C_M_IGNORE_NAK)
763                         return 0;
764                 return -EREMOTEIO;
765         }
766
767         if (i2c_dev->msg_err & I2C_ERR_UNEXPECTED_STATUS)
768                 return -EAGAIN;
769
770         return -EIO;
771 }
772
773 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
774         int num)
775 {
776         struct tegra_i2c_bus *i2c_bus = i2c_get_adapdata(adap);
777         struct tegra_i2c_dev *i2c_dev = i2c_bus->dev;
778         int i;
779         int ret = 0;
780
781         rt_mutex_lock(&i2c_dev->dev_lock);
782
783         if (i2c_dev->is_suspended) {
784                 rt_mutex_unlock(&i2c_dev->dev_lock);
785                 return -EBUSY;
786         }
787
788         /* Support I2C_M_NOSTART only if HW support continue xfer. */
789         for (i = 0; i < num - 1; i++) {
790                         if ((msgs[i + 1].flags & I2C_M_NOSTART) &&
791                         !i2c_dev->hw->has_continue_xfer_support) {
792                         dev_err(i2c_dev->dev,
793                                 "mesg %d have illegal flag\n", i + 1);
794                         rt_mutex_unlock(&i2c_dev->dev_lock);
795                         return -EINVAL;
796                 }
797         }
798
799         if (i2c_dev->last_mux != i2c_bus->mux) {
800                 tegra_pinmux_set_safe_pinmux_table(i2c_dev->last_mux,
801                         i2c_dev->last_mux_len);
802                 tegra_pinmux_config_pinmux_table(i2c_bus->mux,
803                         i2c_bus->mux_len);
804                 i2c_dev->last_mux = i2c_bus->mux;
805                 i2c_dev->last_mux_len = i2c_bus->mux_len;
806         }
807
808         if (i2c_dev->last_bus_clk_rate != i2c_bus->bus_clk_rate) {
809                 clk_set_rate(i2c_dev->div_clk, i2c_bus->bus_clk_rate * 8);
810                 i2c_dev->last_bus_clk_rate = i2c_bus->bus_clk_rate;
811         }
812
813         i2c_dev->msgs = msgs;
814         i2c_dev->msgs_num = num;
815
816         tegra_i2c_clock_enable(i2c_dev);
817
818         for (i = 0; i < num; i++) {
819                 enum msg_end_type end_type = MSG_END_STOP;
820                 if (i < (num - 1)) {
821                         if (msgs[i + 1].flags & I2C_M_NOSTART)
822                                 end_type = MSG_END_CONTINUE;
823                         else
824                                 end_type = MSG_END_REPEAT_START;
825                 }
826                 ret = tegra_i2c_xfer_msg(i2c_bus, &msgs[i], end_type);
827                 if (ret)
828                         break;
829         }
830
831         tegra_i2c_clock_disable(i2c_dev);
832
833         rt_mutex_unlock(&i2c_dev->dev_lock);
834
835         i2c_dev->msgs = NULL;
836         i2c_dev->msgs_num = 0;
837
838         return ret ?: i;
839 }
840
841 static u32 tegra_i2c_func(struct i2c_adapter *adap)
842 {
843         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR |
844                         I2C_FUNC_PROTOCOL_MANGLING;
845 }
846
847 static const struct i2c_algorithm tegra_i2c_algo = {
848         .master_xfer    = tegra_i2c_xfer,
849         .functionality  = tegra_i2c_func,
850 };
851
852 static struct tegra_i2c_hw_feature tegra20_i2c_hw = {
853         .has_continue_xfer_support = false,
854 };
855
856 static struct tegra_i2c_hw_feature tegra30_i2c_hw = {
857         .has_continue_xfer_support = true,
858 };
859
860 #if defined(CONFIG_OF)
861 /* Match table for of_platform binding */
862 static const struct of_device_id tegra_i2c_of_match[] __devinitconst = {
863         { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
864         {},
865 };
866 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
867 #endif
868
869 static int __devinit tegra_i2c_probe(struct platform_device *pdev)
870 {
871         struct tegra_i2c_dev *i2c_dev;
872         struct tegra_i2c_platform_data *plat = pdev->dev.platform_data;
873         struct resource *res;
874         struct clk *div_clk;
875         struct clk *fast_clk = NULL;
876         const unsigned int *prop;
877         void __iomem *base;
878         int irq;
879         int nbus;
880         int i = 0;
881         int ret = 0;
882
883         if (!plat) {
884                 dev_err(&pdev->dev, "no platform data?\n");
885                 return -ENODEV;
886         }
887
888         if (plat->bus_count <= 0 || plat->adapter_nr < 0) {
889                 dev_err(&pdev->dev, "invalid platform data?\n");
890                 return -ENODEV;
891         }
892
893         WARN_ON(plat->bus_count > TEGRA_I2C_MAX_BUS);
894         nbus = min(TEGRA_I2C_MAX_BUS, plat->bus_count);
895
896         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
897         if (!res) {
898                 dev_err(&pdev->dev, "no mem resource\n");
899                 return -EINVAL;
900         }
901
902         base = devm_request_and_ioremap(&pdev->dev, res);
903         if (!base) {
904                 dev_err(&pdev->dev, "Cannot request/ioremap I2C registers\n");
905                 return -EADDRNOTAVAIL;
906         }
907
908         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
909         if (!res) {
910                 dev_err(&pdev->dev, "no irq resource\n");
911                 return -EINVAL;
912         }
913         irq = res->start;
914
915         div_clk = devm_clk_get(&pdev->dev, "div-clk");
916         if (IS_ERR(div_clk)) {
917                 dev_err(&pdev->dev, "missing controller clock");
918                 return PTR_ERR(div_clk);
919         }
920
921         fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
922         if (IS_ERR(fast_clk)) {
923                 dev_err(&pdev->dev, "missing controller fast clock");
924                 return PTR_ERR(fast_clk);
925         }
926
927         i2c_dev = devm_kzalloc(&pdev->dev, sizeof(struct tegra_i2c_dev) +
928                           (nbus-1) * sizeof(struct tegra_i2c_bus), GFP_KERNEL);
929         if (!i2c_dev) {
930                 dev_err(&pdev->dev, "Could not allocate struct tegra_i2c_dev");
931                 return -ENOMEM;
932         }
933
934         i2c_dev->base = base;
935         i2c_dev->div_clk = div_clk;
936         i2c_dev->fast_clk = fast_clk;
937         i2c_dev->irq = irq;
938         i2c_dev->cont_id = pdev->id;
939         i2c_dev->dev = &pdev->dev;
940         i2c_dev->is_clkon_always = plat->is_clkon_always;
941
942
943 #ifdef ARCH_TEGRA_2x_SOC
944         i2c_dev->hw = &tegra20_i2c_hw;
945 #else
946         i2c_dev->hw = &tegra30_i2c_hw;
947 #endif
948
949         i2c_dev->last_bus_clk_rate = 100000; /* default clock rate */
950         if (plat) {
951                 i2c_dev->last_bus_clk_rate = plat->bus_clk_rate[0];
952
953         } else if (i2c_dev->dev->of_node) {    /* if there is a device tree node ... */
954                 /* TODO: DAN: this doesn't work for DT */
955                 prop = of_get_property(i2c_dev->dev->of_node,
956                                 "clock-frequency", NULL);
957                 if (prop)
958                         i2c_dev->last_bus_clk_rate = be32_to_cpup(prop);
959
960                 /* FIXME! Populate the Tegra30 and then support M_NOSTART */
961                 i2c_dev->hw = &tegra20_i2c_hw;
962         }
963
964         i2c_dev->is_high_speed_enable = plat->is_high_speed_enable;
965         i2c_dev->last_bus_clk_rate = plat->bus_clk_rate[0] ?: 100000;
966         i2c_dev->msgs = NULL;
967         i2c_dev->msgs_num = 0;
968         rt_mutex_init(&i2c_dev->dev_lock);
969         spin_lock_init(&i2c_dev->fifo_lock);
970
971         i2c_dev->slave_addr = plat->slave_addr;
972         i2c_dev->hs_master_code = plat->hs_master_code;
973         i2c_dev->is_dvc = plat->is_dvc;
974         i2c_dev->arb_recovery = plat->arb_recovery;
975         init_completion(&i2c_dev->msg_complete);
976
977         platform_set_drvdata(pdev, i2c_dev);
978
979         if (i2c_dev->is_clkon_always)
980                 tegra_i2c_clock_enable(i2c_dev);
981
982         ret = tegra_i2c_init(i2c_dev);
983         if (ret) {
984                 dev_err(&pdev->dev, "Failed to initialize i2c controller");
985                 return ret;
986         }
987
988         ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
989                         tegra_i2c_isr, 0, pdev->name, i2c_dev);
990         if (ret) {
991                 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
992                 return ret;
993         }
994
995
996         for (i = 0; i < nbus; i++) {
997                 struct tegra_i2c_bus *i2c_bus = &i2c_dev->busses[i];
998
999                 i2c_bus->dev = i2c_dev;
1000                 i2c_bus->mux = plat->bus_mux[i];
1001                 i2c_bus->mux_len = plat->bus_mux_len[i];
1002                 i2c_bus->bus_clk_rate = plat->bus_clk_rate[i] ?: 100000;
1003
1004                 i2c_bus->scl_gpio = plat->scl_gpio[i];
1005                 i2c_bus->sda_gpio = plat->sda_gpio[i];
1006
1007                 i2c_bus->adapter.dev.of_node = pdev->dev.of_node;
1008                 i2c_bus->adapter.algo = &tegra_i2c_algo;
1009                 i2c_set_adapdata(&i2c_bus->adapter, i2c_bus);
1010                 i2c_bus->adapter.owner = THIS_MODULE;
1011                 i2c_bus->adapter.class = I2C_CLASS_HWMON;
1012                 strlcpy(i2c_bus->adapter.name, "Tegra I2C adapter",
1013                         sizeof(i2c_bus->adapter.name));
1014                 i2c_bus->adapter.dev.parent = &pdev->dev;
1015                 i2c_bus->adapter.nr = plat->adapter_nr + i;
1016
1017                 if (plat->retries)
1018                         i2c_bus->adapter.retries = plat->retries;
1019                 else
1020                         i2c_bus->adapter.retries = TEGRA_I2C_RETRIES;
1021
1022                 if (plat->timeout)
1023                         i2c_bus->adapter.timeout = plat->timeout;
1024
1025                 ret = i2c_add_numbered_adapter(&i2c_bus->adapter);
1026                 if (ret) {
1027                         dev_err(&pdev->dev, "Failed to add I2C adapter\n");
1028                         goto err_del_bus;
1029                 }
1030                 of_i2c_register_devices(&i2c_bus->adapter);
1031
1032                 i2c_dev->bus_count++;
1033         }
1034
1035         return 0;
1036
1037 err_del_bus:
1038         while (i2c_dev->bus_count--)
1039                 i2c_del_adapter(&i2c_dev->busses[i2c_dev->bus_count].adapter);
1040         return ret;
1041 }
1042
1043 static int __devexit tegra_i2c_remove(struct platform_device *pdev)
1044 {
1045         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1046
1047         while (i2c_dev->bus_count--)
1048                 i2c_del_adapter(&i2c_dev->busses[i2c_dev->bus_count].adapter);
1049
1050         if (i2c_dev->is_clkon_always)
1051                 tegra_i2c_clock_disable(i2c_dev);
1052         return 0;
1053 }
1054
1055 #ifdef CONFIG_PM_SLEEP
1056 static int tegra_i2c_suspend_noirq(struct device *dev)
1057 {
1058         struct platform_device *pdev = to_platform_device(dev);
1059         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1060
1061         rt_mutex_lock(&i2c_dev->dev_lock);
1062
1063         i2c_dev->is_suspended = true;
1064         if (i2c_dev->is_clkon_always)
1065                 tegra_i2c_clock_disable(i2c_dev);
1066
1067         rt_mutex_unlock(&i2c_dev->dev_lock);
1068
1069         return 0;
1070 }
1071
1072 static int tegra_i2c_resume_noirq(struct device *dev)
1073 {
1074         struct platform_device *pdev = to_platform_device(dev);
1075         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1076         int ret;
1077
1078         rt_mutex_lock(&i2c_dev->dev_lock);
1079
1080         if (i2c_dev->is_clkon_always)
1081                 tegra_i2c_clock_enable(i2c_dev);
1082
1083         ret = tegra_i2c_init(i2c_dev);
1084
1085         if (ret) {
1086                 rt_mutex_unlock(&i2c_dev->dev_lock);
1087                 return ret;
1088         }
1089
1090         i2c_dev->is_suspended = false;
1091
1092         rt_mutex_unlock(&i2c_dev->dev_lock);
1093
1094         return 0;
1095 }
1096
1097 static const struct dev_pm_ops tegra_i2c_pm = {
1098         .suspend_noirq = tegra_i2c_suspend_noirq,
1099         .resume_noirq = tegra_i2c_resume_noirq,
1100 };
1101 #define TEGRA_I2C_PM    (&tegra_i2c_pm)
1102 #else
1103 #define TEGRA_I2C_PM    NULL
1104 #endif
1105
1106 static struct platform_driver tegra_i2c_driver = {
1107         .probe   = tegra_i2c_probe,
1108         .remove  = __devexit_p(tegra_i2c_remove),
1109         .driver  = {
1110                 .name  = "tegra-i2c",
1111                 .owner = THIS_MODULE,
1112                 .of_match_table = of_match_ptr(tegra_i2c_of_match),
1113                 .pm    = TEGRA_I2C_PM,
1114         },
1115 };
1116
1117 static int __init tegra_i2c_init_driver(void)
1118 {
1119         return platform_driver_register(&tegra_i2c_driver);
1120 }
1121
1122 static void __exit tegra_i2c_exit_driver(void)
1123 {
1124         platform_driver_unregister(&tegra_i2c_driver);
1125 }
1126
1127 subsys_initcall(tegra_i2c_init_driver);
1128 module_exit(tegra_i2c_exit_driver);
1129
1130 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
1131 MODULE_AUTHOR("Colin Cross");
1132 MODULE_LICENSE("GPL v2");