Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[linux-2.6.git] / drivers / i2c / busses / i2c-sh_mobile.c
1 /*
2  * SuperH Mobile I2C Controller
3  *
4  * Copyright (C) 2008 Magnus Damm
5  *
6  * Portions of the code based on out-of-tree driver i2c-sh7343.c
7  * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
21  */
22
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/platform_device.h>
28 #include <linux/interrupt.h>
29 #include <linux/i2c.h>
30 #include <linux/err.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/clk.h>
33 #include <linux/io.h>
34 #include <linux/slab.h>
35
36 /* Transmit operation:                                                      */
37 /*                                                                          */
38 /* 0 byte transmit                                                          */
39 /* BUS:     S     A8     ACK   P                                            */
40 /* IRQ:       DTE   WAIT                                                    */
41 /* ICIC:                                                                    */
42 /* ICCR: 0x94 0x90                                                          */
43 /* ICDR:      A8                                                            */
44 /*                                                                          */
45 /* 1 byte transmit                                                          */
46 /* BUS:     S     A8     ACK   D8(1)   ACK   P                              */
47 /* IRQ:       DTE   WAIT         WAIT                                       */
48 /* ICIC:      -DTE                                                          */
49 /* ICCR: 0x94       0x90                                                    */
50 /* ICDR:      A8    D8(1)                                                   */
51 /*                                                                          */
52 /* 2 byte transmit                                                          */
53 /* BUS:     S     A8     ACK   D8(1)   ACK   D8(2)   ACK   P                */
54 /* IRQ:       DTE   WAIT         WAIT          WAIT                         */
55 /* ICIC:      -DTE                                                          */
56 /* ICCR: 0x94                    0x90                                       */
57 /* ICDR:      A8    D8(1)        D8(2)                                      */
58 /*                                                                          */
59 /* 3 bytes or more, +---------+ gets repeated                               */
60 /*                                                                          */
61 /*                                                                          */
62 /* Receive operation:                                                       */
63 /*                                                                          */
64 /* 0 byte receive - not supported since slave may hold SDA low              */
65 /*                                                                          */
66 /* 1 byte receive       [TX] | [RX]                                         */
67 /* BUS:     S     A8     ACK | D8(1)   ACK   P                              */
68 /* IRQ:       DTE   WAIT     |   WAIT     DTE                               */
69 /* ICIC:      -DTE           |   +DTE                                       */
70 /* ICCR: 0x94       0x81     |   0xc0                                       */
71 /* ICDR:      A8             |            D8(1)                             */
72 /*                                                                          */
73 /* 2 byte receive        [TX]| [RX]                                         */
74 /* BUS:     S     A8     ACK | D8(1)   ACK   D8(2)   ACK   P                */
75 /* IRQ:       DTE   WAIT     |   WAIT          WAIT     DTE                 */
76 /* ICIC:      -DTE           |                 +DTE                         */
77 /* ICCR: 0x94       0x81     |                 0xc0                         */
78 /* ICDR:      A8             |                 D8(1)    D8(2)               */
79 /*                                                                          */
80 /* 3 byte receive       [TX] | [RX]                                         */
81 /* BUS:     S     A8     ACK | D8(1)   ACK   D8(2)   ACK   D8(3)   ACK    P */
82 /* IRQ:       DTE   WAIT     |   WAIT          WAIT         WAIT      DTE   */
83 /* ICIC:      -DTE           |                              +DTE            */
84 /* ICCR: 0x94       0x81     |                              0xc0            */
85 /* ICDR:      A8             |                 D8(1)        D8(2)     D8(3) */
86 /*                                                                          */
87 /* 4 bytes or more, this part is repeated    +---------+                    */
88 /*                                                                          */
89 /*                                                                          */
90 /* Interrupt order and BUSY flag                                            */
91 /*     ___                                                 _                */
92 /* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/                 */
93 /* SCL      \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/                   */
94 /*                                                                          */
95 /*        S   D7  D6  D5  D4  D3  D2  D1  D0              P                 */
96 /*                                           ___                            */
97 /* WAIT IRQ ________________________________/   \___________                */
98 /* TACK IRQ ____________________________________/   \_______                */
99 /* DTE  IRQ __________________________________________/   \_                */
100 /* AL   IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX                */
101 /*         _______________________________________________                  */
102 /* BUSY __/                                               \_                */
103 /*                                                                          */
104
105 enum sh_mobile_i2c_op {
106         OP_START = 0,
107         OP_TX_FIRST,
108         OP_TX,
109         OP_TX_STOP,
110         OP_TX_TO_RX,
111         OP_RX,
112         OP_RX_STOP,
113         OP_RX_STOP_DATA,
114 };
115
116 struct sh_mobile_i2c_data {
117         struct device *dev;
118         void __iomem *reg;
119         struct i2c_adapter adap;
120
121         struct clk *clk;
122         u_int8_t icic;
123         u_int8_t iccl;
124         u_int8_t icch;
125         u_int8_t flags;
126
127         spinlock_t lock;
128         wait_queue_head_t wait;
129         struct i2c_msg *msg;
130         int pos;
131         int sr;
132 };
133
134 #define IIC_FLAG_HAS_ICIC67     (1 << 0)
135
136 #define NORMAL_SPEED            100000 /* FAST_SPEED 400000 */
137
138 /* Register offsets */
139 #define ICDR                    0x00
140 #define ICCR                    0x04
141 #define ICSR                    0x08
142 #define ICIC                    0x0c
143 #define ICCL                    0x10
144 #define ICCH                    0x14
145
146 /* Register bits */
147 #define ICCR_ICE                0x80
148 #define ICCR_RACK               0x40
149 #define ICCR_TRS                0x10
150 #define ICCR_BBSY               0x04
151 #define ICCR_SCP                0x01
152
153 #define ICSR_SCLM               0x80
154 #define ICSR_SDAM               0x40
155 #define SW_DONE                 0x20
156 #define ICSR_BUSY               0x10
157 #define ICSR_AL                 0x08
158 #define ICSR_TACK               0x04
159 #define ICSR_WAIT               0x02
160 #define ICSR_DTE                0x01
161
162 #define ICIC_ICCLB8             0x80
163 #define ICIC_ICCHB8             0x40
164 #define ICIC_ALE                0x08
165 #define ICIC_TACKE              0x04
166 #define ICIC_WAITE              0x02
167 #define ICIC_DTEE               0x01
168
169 static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
170 {
171         if (offs == ICIC)
172                 data |= pd->icic;
173
174         iowrite8(data, pd->reg + offs);
175 }
176
177 static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs)
178 {
179         return ioread8(pd->reg + offs);
180 }
181
182 static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
183                         unsigned char set, unsigned char clr)
184 {
185         iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
186 }
187
188 static void activate_ch(struct sh_mobile_i2c_data *pd)
189 {
190         unsigned long i2c_clk;
191         u_int32_t num;
192         u_int32_t denom;
193         u_int32_t tmp;
194
195         /* Wake up device and enable clock */
196         pm_runtime_get_sync(pd->dev);
197         clk_enable(pd->clk);
198
199         /* Get clock rate after clock is enabled */
200         i2c_clk = clk_get_rate(pd->clk);
201
202         /* Calculate the value for iccl. From the data sheet:
203          * iccl = (p clock / transfer rate) * (L / (L + H))
204          * where L and H are the SCL low/high ratio (5/4 in this case).
205          * We also round off the result.
206          */
207         num = i2c_clk * 5;
208         denom = NORMAL_SPEED * 9;
209         tmp = num * 10 / denom;
210         if (tmp % 10 >= 5)
211                 pd->iccl = (u_int8_t)((num/denom) + 1);
212         else
213                 pd->iccl = (u_int8_t)(num/denom);
214
215         /* one more bit of ICCL in ICIC */
216         if (pd->flags & IIC_FLAG_HAS_ICIC67) {
217                 if ((num/denom) > 0xff)
218                         pd->icic |= ICIC_ICCLB8;
219                 else
220                         pd->icic &= ~ICIC_ICCLB8;
221         }
222
223         /* Calculate the value for icch. From the data sheet:
224            icch = (p clock / transfer rate) * (H / (L + H)) */
225         num = i2c_clk * 4;
226         tmp = num * 10 / denom;
227         if (tmp % 10 >= 5)
228                 pd->icch = (u_int8_t)((num/denom) + 1);
229         else
230                 pd->icch = (u_int8_t)(num/denom);
231
232         /* one more bit of ICCH in ICIC */
233         if (pd->flags & IIC_FLAG_HAS_ICIC67) {
234                 if ((num/denom) > 0xff)
235                         pd->icic |= ICIC_ICCHB8;
236                 else
237                         pd->icic &= ~ICIC_ICCHB8;
238         }
239
240         /* Enable channel and configure rx ack */
241         iic_set_clr(pd, ICCR, ICCR_ICE, 0);
242
243         /* Mask all interrupts */
244         iic_wr(pd, ICIC, 0);
245
246         /* Set the clock */
247         iic_wr(pd, ICCL, pd->iccl);
248         iic_wr(pd, ICCH, pd->icch);
249 }
250
251 static void deactivate_ch(struct sh_mobile_i2c_data *pd)
252 {
253         /* Clear/disable interrupts */
254         iic_wr(pd, ICSR, 0);
255         iic_wr(pd, ICIC, 0);
256
257         /* Disable channel */
258         iic_set_clr(pd, ICCR, 0, ICCR_ICE);
259
260         /* Disable clock and mark device as idle */
261         clk_disable(pd->clk);
262         pm_runtime_put_sync(pd->dev);
263 }
264
265 static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
266                             enum sh_mobile_i2c_op op, unsigned char data)
267 {
268         unsigned char ret = 0;
269         unsigned long flags;
270
271         dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data);
272
273         spin_lock_irqsave(&pd->lock, flags);
274
275         switch (op) {
276         case OP_START: /* issue start and trigger DTE interrupt */
277                 iic_wr(pd, ICCR, 0x94);
278                 break;
279         case OP_TX_FIRST: /* disable DTE interrupt and write data */
280                 iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
281                 iic_wr(pd, ICDR, data);
282                 break;
283         case OP_TX: /* write data */
284                 iic_wr(pd, ICDR, data);
285                 break;
286         case OP_TX_STOP: /* write data and issue a stop afterwards */
287                 iic_wr(pd, ICDR, data);
288                 iic_wr(pd, ICCR, 0x90);
289                 break;
290         case OP_TX_TO_RX: /* select read mode */
291                 iic_wr(pd, ICCR, 0x81);
292                 break;
293         case OP_RX: /* just read data */
294                 ret = iic_rd(pd, ICDR);
295                 break;
296         case OP_RX_STOP: /* enable DTE interrupt, issue stop */
297                 iic_wr(pd, ICIC,
298                        ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
299                 iic_wr(pd, ICCR, 0xc0);
300                 break;
301         case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
302                 iic_wr(pd, ICIC,
303                        ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
304                 ret = iic_rd(pd, ICDR);
305                 iic_wr(pd, ICCR, 0xc0);
306                 break;
307         }
308
309         spin_unlock_irqrestore(&pd->lock, flags);
310
311         dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret);
312         return ret;
313 }
314
315 static int sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd)
316 {
317         if (pd->pos == -1)
318                 return 1;
319
320         return 0;
321 }
322
323 static int sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd)
324 {
325         if (pd->pos == (pd->msg->len - 1))
326                 return 1;
327
328         return 0;
329 }
330
331 static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd,
332                                    unsigned char *buf)
333 {
334         switch (pd->pos) {
335         case -1:
336                 *buf = (pd->msg->addr & 0x7f) << 1;
337                 *buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0;
338                 break;
339         default:
340                 *buf = pd->msg->buf[pd->pos];
341         }
342 }
343
344 static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
345 {
346         unsigned char data;
347
348         if (pd->pos == pd->msg->len)
349                 return 1;
350
351         sh_mobile_i2c_get_data(pd, &data);
352
353         if (sh_mobile_i2c_is_last_byte(pd))
354                 i2c_op(pd, OP_TX_STOP, data);
355         else if (sh_mobile_i2c_is_first_byte(pd))
356                 i2c_op(pd, OP_TX_FIRST, data);
357         else
358                 i2c_op(pd, OP_TX, data);
359
360         pd->pos++;
361         return 0;
362 }
363
364 static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
365 {
366         unsigned char data;
367         int real_pos;
368
369         do {
370                 if (pd->pos <= -1) {
371                         sh_mobile_i2c_get_data(pd, &data);
372
373                         if (sh_mobile_i2c_is_first_byte(pd))
374                                 i2c_op(pd, OP_TX_FIRST, data);
375                         else
376                                 i2c_op(pd, OP_TX, data);
377                         break;
378                 }
379
380                 if (pd->pos == 0) {
381                         i2c_op(pd, OP_TX_TO_RX, 0);
382                         break;
383                 }
384
385                 real_pos = pd->pos - 2;
386
387                 if (pd->pos == pd->msg->len) {
388                         if (real_pos < 0) {
389                                 i2c_op(pd, OP_RX_STOP, 0);
390                                 break;
391                         }
392                         data = i2c_op(pd, OP_RX_STOP_DATA, 0);
393                 } else
394                         data = i2c_op(pd, OP_RX, 0);
395
396                 if (real_pos >= 0)
397                         pd->msg->buf[real_pos] = data;
398         } while (0);
399
400         pd->pos++;
401         return pd->pos == (pd->msg->len + 2);
402 }
403
404 static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
405 {
406         struct platform_device *dev = dev_id;
407         struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
408         unsigned char sr;
409         int wakeup;
410
411         sr = iic_rd(pd, ICSR);
412         pd->sr |= sr; /* remember state */
413
414         dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
415                (pd->msg->flags & I2C_M_RD) ? "read" : "write",
416                pd->pos, pd->msg->len);
417
418         if (sr & (ICSR_AL | ICSR_TACK)) {
419                 /* don't interrupt transaction - continue to issue stop */
420                 iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
421                 wakeup = 0;
422         } else if (pd->msg->flags & I2C_M_RD)
423                 wakeup = sh_mobile_i2c_isr_rx(pd);
424         else
425                 wakeup = sh_mobile_i2c_isr_tx(pd);
426
427         if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
428                 iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
429
430         if (wakeup) {
431                 pd->sr |= SW_DONE;
432                 wake_up(&pd->wait);
433         }
434
435         return IRQ_HANDLED;
436 }
437
438 static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg)
439 {
440         if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) {
441                 dev_err(pd->dev, "Unsupported zero length i2c read\n");
442                 return -EIO;
443         }
444
445         /* Initialize channel registers */
446         iic_set_clr(pd, ICCR, 0, ICCR_ICE);
447
448         /* Enable channel and configure rx ack */
449         iic_set_clr(pd, ICCR, ICCR_ICE, 0);
450
451         /* Set the clock */
452         iic_wr(pd, ICCL, pd->iccl);
453         iic_wr(pd, ICCH, pd->icch);
454
455         pd->msg = usr_msg;
456         pd->pos = -1;
457         pd->sr = 0;
458
459         /* Enable all interrupts to begin with */
460         iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
461         return 0;
462 }
463
464 static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
465                               struct i2c_msg *msgs,
466                               int num)
467 {
468         struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
469         struct i2c_msg  *msg;
470         int err = 0;
471         u_int8_t val;
472         int i, k, retry_count;
473
474         activate_ch(pd);
475
476         /* Process all messages */
477         for (i = 0; i < num; i++) {
478                 msg = &msgs[i];
479
480                 err = start_ch(pd, msg);
481                 if (err)
482                         break;
483
484                 i2c_op(pd, OP_START, 0);
485
486                 /* The interrupt handler takes care of the rest... */
487                 k = wait_event_timeout(pd->wait,
488                                        pd->sr & (ICSR_TACK | SW_DONE),
489                                        5 * HZ);
490                 if (!k)
491                         dev_err(pd->dev, "Transfer request timed out\n");
492
493                 retry_count = 1000;
494 again:
495                 val = iic_rd(pd, ICSR);
496
497                 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
498
499                 /* the interrupt handler may wake us up before the
500                  * transfer is finished, so poll the hardware
501                  * until we're done.
502                  */
503                 if (val & ICSR_BUSY) {
504                         udelay(10);
505                         if (retry_count--)
506                                 goto again;
507
508                         err = -EIO;
509                         dev_err(pd->dev, "Polling timed out\n");
510                         break;
511                 }
512
513                 /* handle missing acknowledge and arbitration lost */
514                 if ((val | pd->sr) & (ICSR_TACK | ICSR_AL)) {
515                         err = -EIO;
516                         break;
517                 }
518         }
519
520         deactivate_ch(pd);
521
522         if (!err)
523                 err = num;
524         return err;
525 }
526
527 static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
528 {
529         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
530 }
531
532 static struct i2c_algorithm sh_mobile_i2c_algorithm = {
533         .functionality  = sh_mobile_i2c_func,
534         .master_xfer    = sh_mobile_i2c_xfer,
535 };
536
537 static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, int hook)
538 {
539         struct resource *res;
540         int ret = -ENXIO;
541         int n, k = 0;
542
543         while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
544                 for (n = res->start; hook && n <= res->end; n++) {
545                         if (request_irq(n, sh_mobile_i2c_isr, IRQF_DISABLED,
546                                         dev_name(&dev->dev), dev)) {
547                                 for (n--; n >= res->start; n--)
548                                         free_irq(n, dev);
549
550                                 goto rollback;
551                         }
552                 }
553                 k++;
554         }
555
556         if (hook)
557                 return k > 0 ? 0 : -ENOENT;
558
559         ret = 0;
560
561  rollback:
562         k--;
563
564         while (k >= 0) {
565                 res = platform_get_resource(dev, IORESOURCE_IRQ, k);
566                 for (n = res->start; n <= res->end; n++)
567                         free_irq(n, dev);
568
569                 k--;
570         }
571
572         return ret;
573 }
574
575 static int sh_mobile_i2c_probe(struct platform_device *dev)
576 {
577         struct sh_mobile_i2c_data *pd;
578         struct i2c_adapter *adap;
579         struct resource *res;
580         char clk_name[8];
581         int size;
582         int ret;
583
584         pd = kzalloc(sizeof(struct sh_mobile_i2c_data), GFP_KERNEL);
585         if (pd == NULL) {
586                 dev_err(&dev->dev, "cannot allocate private data\n");
587                 return -ENOMEM;
588         }
589
590         snprintf(clk_name, sizeof(clk_name), "i2c%d", dev->id);
591         pd->clk = clk_get(&dev->dev, clk_name);
592         if (IS_ERR(pd->clk)) {
593                 dev_err(&dev->dev, "cannot get clock \"%s\"\n", clk_name);
594                 ret = PTR_ERR(pd->clk);
595                 goto err;
596         }
597
598         ret = sh_mobile_i2c_hook_irqs(dev, 1);
599         if (ret) {
600                 dev_err(&dev->dev, "cannot request IRQ\n");
601                 goto err_clk;
602         }
603
604         pd->dev = &dev->dev;
605         platform_set_drvdata(dev, pd);
606
607         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
608         if (res == NULL) {
609                 dev_err(&dev->dev, "cannot find IO resource\n");
610                 ret = -ENOENT;
611                 goto err_irq;
612         }
613
614         size = resource_size(res);
615
616         pd->reg = ioremap(res->start, size);
617         if (pd->reg == NULL) {
618                 dev_err(&dev->dev, "cannot map IO\n");
619                 ret = -ENXIO;
620                 goto err_irq;
621         }
622
623         /* The IIC blocks on SH-Mobile ARM processors
624          * come with two new bits in ICIC.
625          */
626         if (size > 0x17)
627                 pd->flags |= IIC_FLAG_HAS_ICIC67;
628
629         /* Enable Runtime PM for this device.
630          *
631          * Also tell the Runtime PM core to ignore children
632          * for this device since it is valid for us to suspend
633          * this I2C master driver even though the slave devices
634          * on the I2C bus may not be suspended.
635          *
636          * The state of the I2C hardware bus is unaffected by
637          * the Runtime PM state.
638          */
639         pm_suspend_ignore_children(&dev->dev, true);
640         pm_runtime_enable(&dev->dev);
641
642         /* setup the private data */
643         adap = &pd->adap;
644         i2c_set_adapdata(adap, pd);
645
646         adap->owner = THIS_MODULE;
647         adap->algo = &sh_mobile_i2c_algorithm;
648         adap->dev.parent = &dev->dev;
649         adap->retries = 5;
650         adap->nr = dev->id;
651
652         strlcpy(adap->name, dev->name, sizeof(adap->name));
653
654         spin_lock_init(&pd->lock);
655         init_waitqueue_head(&pd->wait);
656
657         ret = i2c_add_numbered_adapter(adap);
658         if (ret < 0) {
659                 dev_err(&dev->dev, "cannot add numbered adapter\n");
660                 goto err_all;
661         }
662
663         return 0;
664
665  err_all:
666         iounmap(pd->reg);
667  err_irq:
668         sh_mobile_i2c_hook_irqs(dev, 0);
669  err_clk:
670         clk_put(pd->clk);
671  err:
672         kfree(pd);
673         return ret;
674 }
675
676 static int sh_mobile_i2c_remove(struct platform_device *dev)
677 {
678         struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
679
680         i2c_del_adapter(&pd->adap);
681         iounmap(pd->reg);
682         sh_mobile_i2c_hook_irqs(dev, 0);
683         clk_put(pd->clk);
684         pm_runtime_disable(&dev->dev);
685         kfree(pd);
686         return 0;
687 }
688
689 static int sh_mobile_i2c_runtime_nop(struct device *dev)
690 {
691         /* Runtime PM callback shared between ->runtime_suspend()
692          * and ->runtime_resume(). Simply returns success.
693          *
694          * This driver re-initializes all registers after
695          * pm_runtime_get_sync() anyway so there is no need
696          * to save and restore registers here.
697          */
698         return 0;
699 }
700
701 static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = {
702         .runtime_suspend = sh_mobile_i2c_runtime_nop,
703         .runtime_resume = sh_mobile_i2c_runtime_nop,
704 };
705
706 static struct platform_driver sh_mobile_i2c_driver = {
707         .driver         = {
708                 .name           = "i2c-sh_mobile",
709                 .owner          = THIS_MODULE,
710                 .pm             = &sh_mobile_i2c_dev_pm_ops,
711         },
712         .probe          = sh_mobile_i2c_probe,
713         .remove         = sh_mobile_i2c_remove,
714 };
715
716 static int __init sh_mobile_i2c_adap_init(void)
717 {
718         return platform_driver_register(&sh_mobile_i2c_driver);
719 }
720
721 static void __exit sh_mobile_i2c_adap_exit(void)
722 {
723         platform_driver_unregister(&sh_mobile_i2c_driver);
724 }
725
726 subsys_initcall(sh_mobile_i2c_adap_init);
727 module_exit(sh_mobile_i2c_adap_exit);
728
729 MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
730 MODULE_AUTHOR("Magnus Damm");
731 MODULE_LICENSE("GPL v2");