Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/hid
[linux-2.6.git] / drivers / i2c / busses / i2c-s3c2410.c
1 /* linux/drivers/i2c/busses/i2c-s3c2410.c
2  *
3  * Copyright (C) 2004,2005 Simtec Electronics
4  *      Ben Dooks <ben@simtec.co.uk>
5  *
6  * S3C2410 I2C Controller
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
21 */
22
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25
26 #include <linux/i2c.h>
27 #include <linux/i2c-id.h>
28 #include <linux/init.h>
29 #include <linux/time.h>
30 #include <linux/interrupt.h>
31 #include <linux/delay.h>
32 #include <linux/errno.h>
33 #include <linux/err.h>
34 #include <linux/platform_device.h>
35 #include <linux/clk.h>
36 #include <linux/cpufreq.h>
37
38 #include <mach/hardware.h>
39 #include <asm/irq.h>
40 #include <asm/io.h>
41
42 #include <mach/regs-gpio.h>
43 #include <plat/regs-iic.h>
44 #include <plat/iic.h>
45
46 /* i2c controller state */
47
48 enum s3c24xx_i2c_state {
49         STATE_IDLE,
50         STATE_START,
51         STATE_READ,
52         STATE_WRITE,
53         STATE_STOP
54 };
55
56 struct s3c24xx_i2c {
57         spinlock_t              lock;
58         wait_queue_head_t       wait;
59         unsigned int            suspended:1;
60
61         struct i2c_msg          *msg;
62         unsigned int            msg_num;
63         unsigned int            msg_idx;
64         unsigned int            msg_ptr;
65
66         unsigned int            tx_setup;
67
68         enum s3c24xx_i2c_state  state;
69         unsigned long           clkrate;
70
71         void __iomem            *regs;
72         struct clk              *clk;
73         struct device           *dev;
74         struct resource         *irq;
75         struct resource         *ioarea;
76         struct i2c_adapter      adap;
77
78 #ifdef CONFIG_CPU_FREQ
79         struct notifier_block   freq_transition;
80 #endif
81 };
82
83 /* default platform data to use if not supplied in the platform_device
84 */
85
86 static struct s3c2410_platform_i2c s3c24xx_i2c_default_platform = {
87         .flags          = 0,
88         .slave_addr     = 0x10,
89         .bus_freq       = 100*1000,
90         .max_freq       = 400*1000,
91         .sda_delay      = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
92 };
93
94 /* s3c24xx_i2c_is2440()
95  *
96  * return true is this is an s3c2440
97 */
98
99 static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c)
100 {
101         struct platform_device *pdev = to_platform_device(i2c->dev);
102
103         return !strcmp(pdev->name, "s3c2440-i2c");
104 }
105
106
107 /* s3c24xx_i2c_get_platformdata
108  *
109  * get the platform data associated with the given device, or return
110  * the default if there is none
111 */
112
113 static inline struct s3c2410_platform_i2c *s3c24xx_i2c_get_platformdata(struct device *dev)
114 {
115         if (dev->platform_data != NULL)
116                 return (struct s3c2410_platform_i2c *)dev->platform_data;
117
118         return &s3c24xx_i2c_default_platform;
119 }
120
121 /* s3c24xx_i2c_master_complete
122  *
123  * complete the message and wake up the caller, using the given return code,
124  * or zero to mean ok.
125 */
126
127 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
128 {
129         dev_dbg(i2c->dev, "master_complete %d\n", ret);
130
131         i2c->msg_ptr = 0;
132         i2c->msg = NULL;
133         i2c->msg_idx ++;
134         i2c->msg_num = 0;
135         if (ret)
136                 i2c->msg_idx = ret;
137
138         wake_up(&i2c->wait);
139 }
140
141 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
142 {
143         unsigned long tmp;
144         
145         tmp = readl(i2c->regs + S3C2410_IICCON);
146         writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
147
148 }
149
150 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
151 {
152         unsigned long tmp;
153         
154         tmp = readl(i2c->regs + S3C2410_IICCON);
155         writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
156
157 }
158
159 /* irq enable/disable functions */
160
161 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
162 {
163         unsigned long tmp;
164         
165         tmp = readl(i2c->regs + S3C2410_IICCON);
166         writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
167 }
168
169 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
170 {
171         unsigned long tmp;
172         
173         tmp = readl(i2c->regs + S3C2410_IICCON);
174         writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
175 }
176
177
178 /* s3c24xx_i2c_message_start
179  *
180  * put the start of a message onto the bus 
181 */
182
183 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c, 
184                                       struct i2c_msg *msg)
185 {
186         unsigned int addr = (msg->addr & 0x7f) << 1;
187         unsigned long stat;
188         unsigned long iiccon;
189
190         stat = 0;
191         stat |=  S3C2410_IICSTAT_TXRXEN;
192
193         if (msg->flags & I2C_M_RD) {
194                 stat |= S3C2410_IICSTAT_MASTER_RX;
195                 addr |= 1;
196         } else
197                 stat |= S3C2410_IICSTAT_MASTER_TX;
198
199         if (msg->flags & I2C_M_REV_DIR_ADDR)
200                 addr ^= 1;
201
202         // todo - check for wether ack wanted or not
203         s3c24xx_i2c_enable_ack(i2c);
204
205         iiccon = readl(i2c->regs + S3C2410_IICCON);
206         writel(stat, i2c->regs + S3C2410_IICSTAT);
207         
208         dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
209         writeb(addr, i2c->regs + S3C2410_IICDS);
210         
211         /* delay here to ensure the data byte has gotten onto the bus
212          * before the transaction is started */
213
214         ndelay(i2c->tx_setup);
215
216         dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
217         writel(iiccon, i2c->regs + S3C2410_IICCON);
218         
219         stat |=  S3C2410_IICSTAT_START;
220         writel(stat, i2c->regs + S3C2410_IICSTAT);
221 }
222
223 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
224 {
225         unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
226
227         dev_dbg(i2c->dev, "STOP\n");
228
229         /* stop the transfer */
230         iicstat &= ~ S3C2410_IICSTAT_START;
231         writel(iicstat, i2c->regs + S3C2410_IICSTAT);
232         
233         i2c->state = STATE_STOP;
234         
235         s3c24xx_i2c_master_complete(i2c, ret);
236         s3c24xx_i2c_disable_irq(i2c);
237 }
238
239 /* helper functions to determine the current state in the set of
240  * messages we are sending */
241
242 /* is_lastmsg()
243  *
244  * returns TRUE if the current message is the last in the set 
245 */
246
247 static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
248 {
249         return i2c->msg_idx >= (i2c->msg_num - 1);
250 }
251
252 /* is_msglast
253  *
254  * returns TRUE if we this is the last byte in the current message
255 */
256
257 static inline int is_msglast(struct s3c24xx_i2c *i2c)
258 {
259         return i2c->msg_ptr == i2c->msg->len-1;
260 }
261
262 /* is_msgend
263  *
264  * returns TRUE if we reached the end of the current message
265 */
266
267 static inline int is_msgend(struct s3c24xx_i2c *i2c)
268 {
269         return i2c->msg_ptr >= i2c->msg->len;
270 }
271
272 /* i2s_s3c_irq_nextbyte
273  *
274  * process an interrupt and work out what to do
275  */
276
277 static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
278 {
279         unsigned long tmp;
280         unsigned char byte;
281         int ret = 0;
282
283         switch (i2c->state) {
284
285         case STATE_IDLE:
286                 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
287                 goto out;
288                 break;
289
290         case STATE_STOP:
291                 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
292                 s3c24xx_i2c_disable_irq(i2c);           
293                 goto out_ack;
294
295         case STATE_START:
296                 /* last thing we did was send a start condition on the
297                  * bus, or started a new i2c message
298                  */
299                 
300                 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
301                     !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
302                         /* ack was not received... */
303
304                         dev_dbg(i2c->dev, "ack was not received\n");
305                         s3c24xx_i2c_stop(i2c, -ENXIO);
306                         goto out_ack;
307                 }
308
309                 if (i2c->msg->flags & I2C_M_RD)
310                         i2c->state = STATE_READ;
311                 else
312                         i2c->state = STATE_WRITE;
313
314                 /* terminate the transfer if there is nothing to do
315                  * as this is used by the i2c probe to find devices. */
316
317                 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
318                         s3c24xx_i2c_stop(i2c, 0);
319                         goto out_ack;
320                 }
321
322                 if (i2c->state == STATE_READ)
323                         goto prepare_read;
324
325                 /* fall through to the write state, as we will need to 
326                  * send a byte as well */
327
328         case STATE_WRITE:
329                 /* we are writing data to the device... check for the
330                  * end of the message, and if so, work out what to do
331                  */
332
333                 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
334                         if (iicstat & S3C2410_IICSTAT_LASTBIT) {
335                                 dev_dbg(i2c->dev, "WRITE: No Ack\n");
336
337                                 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
338                                 goto out_ack;
339                         }
340                 }
341
342         retry_write:
343
344                 if (!is_msgend(i2c)) {
345                         byte = i2c->msg->buf[i2c->msg_ptr++];
346                         writeb(byte, i2c->regs + S3C2410_IICDS);
347
348                         /* delay after writing the byte to allow the
349                          * data setup time on the bus, as writing the
350                          * data to the register causes the first bit
351                          * to appear on SDA, and SCL will change as
352                          * soon as the interrupt is acknowledged */
353
354                         ndelay(i2c->tx_setup);
355
356                 } else if (!is_lastmsg(i2c)) {
357                         /* we need to go to the next i2c message */
358
359                         dev_dbg(i2c->dev, "WRITE: Next Message\n");
360
361                         i2c->msg_ptr = 0;
362                         i2c->msg_idx ++;
363                         i2c->msg++;
364                         
365                         /* check to see if we need to do another message */
366                         if (i2c->msg->flags & I2C_M_NOSTART) {
367
368                                 if (i2c->msg->flags & I2C_M_RD) {
369                                         /* cannot do this, the controller
370                                          * forces us to send a new START
371                                          * when we change direction */
372
373                                         s3c24xx_i2c_stop(i2c, -EINVAL);
374                                 }
375
376                                 goto retry_write;
377                         } else {
378                         
379                                 /* send the new start */
380                                 s3c24xx_i2c_message_start(i2c, i2c->msg);
381                                 i2c->state = STATE_START;
382                         }
383
384                 } else {
385                         /* send stop */
386
387                         s3c24xx_i2c_stop(i2c, 0);
388                 }
389                 break;
390
391         case STATE_READ:
392                 /* we have a byte of data in the data register, do 
393                  * something with it, and then work out wether we are
394                  * going to do any more read/write
395                  */
396
397                 byte = readb(i2c->regs + S3C2410_IICDS);
398                 i2c->msg->buf[i2c->msg_ptr++] = byte;
399
400         prepare_read:
401                 if (is_msglast(i2c)) {
402                         /* last byte of buffer */
403
404                         if (is_lastmsg(i2c))
405                                 s3c24xx_i2c_disable_ack(i2c);
406                         
407                 } else if (is_msgend(i2c)) {
408                         /* ok, we've read the entire buffer, see if there
409                          * is anything else we need to do */
410
411                         if (is_lastmsg(i2c)) {
412                                 /* last message, send stop and complete */
413                                 dev_dbg(i2c->dev, "READ: Send Stop\n");
414
415                                 s3c24xx_i2c_stop(i2c, 0);
416                         } else {
417                                 /* go to the next transfer */
418                                 dev_dbg(i2c->dev, "READ: Next Transfer\n");
419
420                                 i2c->msg_ptr = 0;
421                                 i2c->msg_idx++;
422                                 i2c->msg++;
423                         }
424                 }
425
426                 break;
427         }
428
429         /* acknowlegde the IRQ and get back on with the work */
430
431  out_ack:
432         tmp = readl(i2c->regs + S3C2410_IICCON);        
433         tmp &= ~S3C2410_IICCON_IRQPEND;
434         writel(tmp, i2c->regs + S3C2410_IICCON);
435  out:
436         return ret;
437 }
438
439 /* s3c24xx_i2c_irq
440  *
441  * top level IRQ servicing routine
442 */
443
444 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
445 {
446         struct s3c24xx_i2c *i2c = dev_id;
447         unsigned long status;
448         unsigned long tmp;
449
450         status = readl(i2c->regs + S3C2410_IICSTAT);
451
452         if (status & S3C2410_IICSTAT_ARBITR) {
453                 // deal with arbitration loss
454                 dev_err(i2c->dev, "deal with arbitration loss\n");
455         }
456
457         if (i2c->state == STATE_IDLE) {
458                 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
459
460                 tmp = readl(i2c->regs + S3C2410_IICCON);        
461                 tmp &= ~S3C2410_IICCON_IRQPEND;
462                 writel(tmp, i2c->regs +  S3C2410_IICCON);
463                 goto out;
464         }
465         
466         /* pretty much this leaves us with the fact that we've
467          * transmitted or received whatever byte we last sent */
468
469         i2s_s3c_irq_nextbyte(i2c, status);
470
471  out:
472         return IRQ_HANDLED;
473 }
474
475
476 /* s3c24xx_i2c_set_master
477  *
478  * get the i2c bus for a master transaction
479 */
480
481 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
482 {
483         unsigned long iicstat;
484         int timeout = 400;
485
486         while (timeout-- > 0) {
487                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
488                 
489                 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
490                         return 0;
491
492                 msleep(1);
493         }
494
495         dev_dbg(i2c->dev, "timeout: GPEDAT is %08x\n",
496                 __raw_readl(S3C2410_GPEDAT));
497
498         return -ETIMEDOUT;
499 }
500
501 /* s3c24xx_i2c_doxfer
502  *
503  * this starts an i2c transfer
504 */
505
506 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, struct i2c_msg *msgs, int num)
507 {
508         unsigned long timeout;
509         int ret;
510
511         if (i2c->suspended)
512                 return -EIO;
513
514         ret = s3c24xx_i2c_set_master(i2c);
515         if (ret != 0) {
516                 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
517                 ret = -EAGAIN;
518                 goto out;
519         }
520
521         spin_lock_irq(&i2c->lock);
522
523         i2c->msg     = msgs;
524         i2c->msg_num = num;
525         i2c->msg_ptr = 0;
526         i2c->msg_idx = 0;
527         i2c->state   = STATE_START;
528
529         s3c24xx_i2c_enable_irq(i2c);
530         s3c24xx_i2c_message_start(i2c, msgs);
531         spin_unlock_irq(&i2c->lock);
532         
533         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
534
535         ret = i2c->msg_idx;
536
537         /* having these next two as dev_err() makes life very 
538          * noisy when doing an i2cdetect */
539
540         if (timeout == 0)
541                 dev_dbg(i2c->dev, "timeout\n");
542         else if (ret != num)
543                 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
544
545         /* ensure the stop has been through the bus */
546
547         msleep(1);
548
549  out:
550         return ret;
551 }
552
553 /* s3c24xx_i2c_xfer
554  *
555  * first port of call from the i2c bus code when an message needs
556  * transferring across the i2c bus.
557 */
558
559 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
560                         struct i2c_msg *msgs, int num)
561 {
562         struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
563         int retry;
564         int ret;
565
566         for (retry = 0; retry < adap->retries; retry++) {
567
568                 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
569
570                 if (ret != -EAGAIN)
571                         return ret;
572
573                 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
574
575                 udelay(100);
576         }
577
578         return -EREMOTEIO;
579 }
580
581 /* declare our i2c functionality */
582 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
583 {
584         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
585 }
586
587 /* i2c bus registration info */
588
589 static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
590         .master_xfer            = s3c24xx_i2c_xfer,
591         .functionality          = s3c24xx_i2c_func,
592 };
593
594 static struct s3c24xx_i2c s3c24xx_i2c = {
595         .lock           = __SPIN_LOCK_UNLOCKED(s3c24xx_i2c.lock),
596         .wait           = __WAIT_QUEUE_HEAD_INITIALIZER(s3c24xx_i2c.wait),
597         .tx_setup       = 50,
598         .adap           = {
599                 .name                   = "s3c2410-i2c",
600                 .owner                  = THIS_MODULE,
601                 .algo                   = &s3c24xx_i2c_algorithm,
602                 .retries                = 2,
603                 .class                  = I2C_CLASS_HWMON | I2C_CLASS_SPD,
604         },
605 };
606
607 /* s3c24xx_i2c_calcdivisor
608  *
609  * return the divisor settings for a given frequency
610 */
611
612 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
613                                    unsigned int *div1, unsigned int *divs)
614 {
615         unsigned int calc_divs = clkin / wanted;
616         unsigned int calc_div1;
617
618         if (calc_divs > (16*16))
619                 calc_div1 = 512;
620         else
621                 calc_div1 = 16;
622
623         calc_divs += calc_div1-1;
624         calc_divs /= calc_div1;
625
626         if (calc_divs == 0)
627                 calc_divs = 1;
628         if (calc_divs > 17)
629                 calc_divs = 17;
630
631         *divs = calc_divs;
632         *div1 = calc_div1;
633
634         return clkin / (calc_divs * calc_div1);
635 }
636
637 /* freq_acceptable
638  *
639  * test wether a frequency is within the acceptable range of error
640 */
641
642 static inline int freq_acceptable(unsigned int freq, unsigned int wanted)
643 {
644         int diff = freq - wanted;
645
646         return (diff >= -2 && diff <= 2);
647 }
648
649 /* s3c24xx_i2c_clockrate
650  *
651  * work out a divisor for the user requested frequency setting,
652  * either by the requested frequency, or scanning the acceptable
653  * range of frequencies until something is found
654 */
655
656 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
657 {
658         struct s3c2410_platform_i2c *pdata;
659         unsigned long clkin = clk_get_rate(i2c->clk);
660         unsigned int divs, div1;
661         u32 iiccon;
662         int freq;
663         int start, end;
664
665         i2c->clkrate = clkin;
666
667         pdata = s3c24xx_i2c_get_platformdata(i2c->adap.dev.parent);
668         clkin /= 1000;          /* clkin now in KHz */
669      
670         dev_dbg(i2c->dev, "pdata %p, freq %lu %lu..%lu\n",
671                  pdata, pdata->bus_freq, pdata->min_freq, pdata->max_freq);
672
673         if (pdata->bus_freq != 0) {
674                 freq = s3c24xx_i2c_calcdivisor(clkin, pdata->bus_freq/1000,
675                                                &div1, &divs);
676                 if (freq_acceptable(freq, pdata->bus_freq/1000))
677                         goto found;
678         }
679
680         /* ok, we may have to search for something suitable... */
681
682         start = (pdata->max_freq == 0) ? pdata->bus_freq : pdata->max_freq;
683         end = pdata->min_freq;
684
685         start /= 1000;
686         end /= 1000;
687
688         /* search loop... */
689
690         for (; start > end; start--) {
691                 freq = s3c24xx_i2c_calcdivisor(clkin, start, &div1, &divs);
692                 if (freq_acceptable(freq, start))
693                         goto found;
694         }
695
696         /* cannot find frequency spec */
697
698         return -EINVAL;
699
700  found:
701         *got = freq;
702
703         iiccon = readl(i2c->regs + S3C2410_IICCON);
704         iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
705         iiccon |= (divs-1);
706
707         if (div1 == 512)
708                 iiccon |= S3C2410_IICCON_TXDIV_512;
709
710         writel(iiccon, i2c->regs + S3C2410_IICCON);
711
712         return 0;
713 }
714
715 #ifdef CONFIG_CPU_FREQ
716
717 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
718
719 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
720                                           unsigned long val, void *data)
721 {
722         struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
723         unsigned long flags;
724         unsigned int got;
725         int delta_f;
726         int ret;
727
728         delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
729
730         /* if we're post-change and the input clock has slowed down
731          * or at pre-change and the clock is about to speed up, then
732          * adjust our clock rate. <0 is slow, >0 speedup.
733          */
734
735         if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
736             (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
737                 spin_lock_irqsave(&i2c->lock, flags);
738                 ret = s3c24xx_i2c_clockrate(i2c, &got);
739                 spin_unlock_irqrestore(&i2c->lock, flags);
740
741                 if (ret < 0)
742                         dev_err(i2c->dev, "cannot find frequency\n");
743                 else
744                         dev_info(i2c->dev, "setting freq %d\n", got);
745         }
746
747         return 0;
748 }
749
750 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
751 {
752         i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
753
754         return cpufreq_register_notifier(&i2c->freq_transition,
755                                          CPUFREQ_TRANSITION_NOTIFIER);
756 }
757
758 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
759 {
760         cpufreq_unregister_notifier(&i2c->freq_transition,
761                                     CPUFREQ_TRANSITION_NOTIFIER);
762 }
763
764 #else
765 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
766 {
767         return 0;
768 }
769
770 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
771 {
772 }
773 #endif
774
775 /* s3c24xx_i2c_init
776  *
777  * initialise the controller, set the IO lines and frequency 
778 */
779
780 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
781 {
782         unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN;
783         struct s3c2410_platform_i2c *pdata;
784         unsigned int freq;
785
786         /* get the plafrom data */
787
788         pdata = s3c24xx_i2c_get_platformdata(i2c->adap.dev.parent);
789
790         /* inititalise the gpio */
791
792         s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA);
793         s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL);
794
795         /* write slave address */
796         
797         writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
798
799         dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
800
801         writel(iicon, i2c->regs + S3C2410_IICCON);
802
803         /* we need to work out the divisors for the clock... */
804
805         if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
806                 writel(0, i2c->regs + S3C2410_IICCON);
807                 dev_err(i2c->dev, "cannot meet bus frequency required\n");
808                 return -EINVAL;
809         }
810
811         /* todo - check that the i2c lines aren't being dragged anywhere */
812
813         dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
814         dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon);
815
816         /* check for s3c2440 i2c controller  */
817
818         if (s3c24xx_i2c_is2440(i2c)) {
819                 dev_dbg(i2c->dev, "S3C2440_IICLC=%08x\n", pdata->sda_delay);
820
821                 writel(pdata->sda_delay, i2c->regs + S3C2440_IICLC);
822         }
823
824         return 0;
825 }
826
827 /* s3c24xx_i2c_probe
828  *
829  * called by the bus driver when a suitable device is found
830 */
831
832 static int s3c24xx_i2c_probe(struct platform_device *pdev)
833 {
834         struct s3c24xx_i2c *i2c = &s3c24xx_i2c;
835         struct s3c2410_platform_i2c *pdata;
836         struct resource *res;
837         int ret;
838
839         pdata = s3c24xx_i2c_get_platformdata(&pdev->dev);
840
841         /* find the clock and enable it */
842
843         i2c->dev = &pdev->dev;
844         i2c->clk = clk_get(&pdev->dev, "i2c");
845         if (IS_ERR(i2c->clk)) {
846                 dev_err(&pdev->dev, "cannot get clock\n");
847                 ret = -ENOENT;
848                 goto err_noclk;
849         }
850
851         dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
852
853         clk_enable(i2c->clk);
854
855         /* map the registers */
856
857         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
858         if (res == NULL) {
859                 dev_err(&pdev->dev, "cannot find IO resource\n");
860                 ret = -ENOENT;
861                 goto err_clk;
862         }
863
864         i2c->ioarea = request_mem_region(res->start, (res->end-res->start)+1,
865                                          pdev->name);
866
867         if (i2c->ioarea == NULL) {
868                 dev_err(&pdev->dev, "cannot request IO\n");
869                 ret = -ENXIO;
870                 goto err_clk;
871         }
872
873         i2c->regs = ioremap(res->start, (res->end-res->start)+1);
874
875         if (i2c->regs == NULL) {
876                 dev_err(&pdev->dev, "cannot map IO\n");
877                 ret = -ENXIO;
878                 goto err_ioarea;
879         }
880
881         dev_dbg(&pdev->dev, "registers %p (%p, %p)\n", i2c->regs, i2c->ioarea, res);
882
883         /* setup info block for the i2c core */
884
885         i2c->adap.algo_data = i2c;
886         i2c->adap.dev.parent = &pdev->dev;
887
888         /* initialise the i2c controller */
889
890         ret = s3c24xx_i2c_init(i2c);
891         if (ret != 0)
892                 goto err_iomap;
893
894         /* find the IRQ for this unit (note, this relies on the init call to
895          * ensure no current IRQs pending 
896          */
897
898         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
899         if (res == NULL) {
900                 dev_err(&pdev->dev, "cannot find IRQ\n");
901                 ret = -ENOENT;
902                 goto err_iomap;
903         }
904
905         ret = request_irq(res->start, s3c24xx_i2c_irq, IRQF_DISABLED,
906                           pdev->name, i2c);
907
908         if (ret != 0) {
909                 dev_err(&pdev->dev, "cannot claim IRQ\n");
910                 goto err_iomap;
911         }
912
913         i2c->irq = res;
914                 
915         dev_dbg(&pdev->dev, "irq resource %p (%lu)\n", res,
916                 (unsigned long)res->start);
917
918         ret = s3c24xx_i2c_register_cpufreq(i2c);
919         if (ret < 0) {
920                 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
921                 goto err_irq;
922         }
923
924         /* Note, previous versions of the driver used i2c_add_adapter()
925          * to add the bus at any number. We now pass the bus number via
926          * the platform data, so if unset it will now default to always
927          * being bus 0.
928          */
929
930         i2c->adap.nr = pdata->bus_num;
931
932         ret = i2c_add_numbered_adapter(&i2c->adap);
933         if (ret < 0) {
934                 dev_err(&pdev->dev, "failed to add bus to i2c core\n");
935                 goto err_cpufreq;
936         }
937
938         platform_set_drvdata(pdev, i2c);
939
940         dev_info(&pdev->dev, "%s: S3C I2C adapter\n", i2c->adap.dev.bus_id);
941         return 0;
942
943  err_cpufreq:
944         s3c24xx_i2c_deregister_cpufreq(i2c);
945
946  err_irq:
947         free_irq(i2c->irq->start, i2c);
948
949  err_iomap:
950         iounmap(i2c->regs);
951
952  err_ioarea:
953         release_resource(i2c->ioarea);
954         kfree(i2c->ioarea);
955
956  err_clk:
957         clk_disable(i2c->clk);
958         clk_put(i2c->clk);
959
960  err_noclk:
961         return ret;
962 }
963
964 /* s3c24xx_i2c_remove
965  *
966  * called when device is removed from the bus
967 */
968
969 static int s3c24xx_i2c_remove(struct platform_device *pdev)
970 {
971         struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
972
973         s3c24xx_i2c_deregister_cpufreq(i2c);
974
975         i2c_del_adapter(&i2c->adap);
976         free_irq(i2c->irq->start, i2c);
977
978         clk_disable(i2c->clk);
979         clk_put(i2c->clk);
980
981         iounmap(i2c->regs);
982
983         release_resource(i2c->ioarea);
984         kfree(i2c->ioarea);
985
986         return 0;
987 }
988
989 #ifdef CONFIG_PM
990 static int s3c24xx_i2c_suspend_late(struct platform_device *dev,
991                                     pm_message_t msg)
992 {
993         struct s3c24xx_i2c *i2c = platform_get_drvdata(dev);
994         i2c->suspended = 1;
995         return 0;
996 }
997
998 static int s3c24xx_i2c_resume(struct platform_device *dev)
999 {
1000         struct s3c24xx_i2c *i2c = platform_get_drvdata(dev);
1001
1002         i2c->suspended = 0;
1003         s3c24xx_i2c_init(i2c);
1004
1005         return 0;
1006 }
1007
1008 #else
1009 #define s3c24xx_i2c_suspend_late NULL
1010 #define s3c24xx_i2c_resume NULL
1011 #endif
1012
1013 /* device driver for platform bus bits */
1014
1015 static struct platform_driver s3c2410_i2c_driver = {
1016         .probe          = s3c24xx_i2c_probe,
1017         .remove         = s3c24xx_i2c_remove,
1018         .suspend_late   = s3c24xx_i2c_suspend_late,
1019         .resume         = s3c24xx_i2c_resume,
1020         .driver         = {
1021                 .owner  = THIS_MODULE,
1022                 .name   = "s3c2410-i2c",
1023         },
1024 };
1025
1026 static struct platform_driver s3c2440_i2c_driver = {
1027         .probe          = s3c24xx_i2c_probe,
1028         .remove         = s3c24xx_i2c_remove,
1029         .suspend_late   = s3c24xx_i2c_suspend_late,
1030         .resume         = s3c24xx_i2c_resume,
1031         .driver         = {
1032                 .owner  = THIS_MODULE,
1033                 .name   = "s3c2440-i2c",
1034         },
1035 };
1036
1037 static int __init i2c_adap_s3c_init(void)
1038 {
1039         int ret;
1040
1041         ret = platform_driver_register(&s3c2410_i2c_driver);
1042         if (ret == 0) {
1043                 ret = platform_driver_register(&s3c2440_i2c_driver);
1044                 if (ret)
1045                         platform_driver_unregister(&s3c2410_i2c_driver);
1046         }
1047
1048         return ret;
1049 }
1050
1051 static void __exit i2c_adap_s3c_exit(void)
1052 {
1053         platform_driver_unregister(&s3c2410_i2c_driver);
1054         platform_driver_unregister(&s3c2440_i2c_driver);
1055 }
1056
1057 module_init(i2c_adap_s3c_init);
1058 module_exit(i2c_adap_s3c_exit);
1059
1060 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1061 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
1062 MODULE_LICENSE("GPL");
1063 MODULE_ALIAS("platform:s3c2410-i2c");
1064 MODULE_ALIAS("platform:s3c2440-i2c");