drivers/i2c/busses/i2c-omap.c

   1 /*
   2  * TI OMAP I2C master mode driver
   3  *
   4  * Copyright (C) 2003 MontaVista Software, Inc.
   5  * Copyright (C) 2005 Nokia Corporation
   6  * Copyright (C) 2004 - 2007 Texas Instruments.
   7  *
   8  * Originally written by MontaVista Software, Inc.
   9  * Additional contributions by:
  10  *      Tony Lindgren <tony@atomide.com>
  11  *      Imre Deak <imre.deak@nokia.com>
  12  *      Juha Yrjölä <juha.yrjola@solidboot.com>
  13  *      Syed Khasim <x0khasim@ti.com>
  14  *      Nishant Menon <nm@ti.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License as published by
  18  * the Free Software Foundation; either version 2 of the License, or
  19  * (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  29  */
  30
  31 #include <linux/module.h>
  32 #include <linux/delay.h>
  33 #include <linux/i2c.h>
  34 #include <linux/err.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/completion.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/clk.h>
  39 #include <linux/io.h>
  40 #include <linux/slab.h>
  41 #include <linux/i2c-omap.h>
  42 #include <linux/pm_runtime.h>
  43
  44 /* I2C controller revisions */
  45 #define OMAP_I2C_OMAP1_REV_2            0x20
  46
  47 /* I2C controller revisions present on specific hardware */
  48 #define OMAP_I2C_REV_ON_2430            0x36
  49 #define OMAP_I2C_REV_ON_3430            0x3C
  50 #define OMAP_I2C_REV_ON_3530_4430       0x40
  51
  52 /* timeout waiting for the controller to respond */
  53 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
  54
  55 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
  56 enum {
  57         OMAP_I2C_REV_REG = 0,
  58         OMAP_I2C_IE_REG,
  59         OMAP_I2C_STAT_REG,
  60         OMAP_I2C_IV_REG,
  61         OMAP_I2C_WE_REG,
  62         OMAP_I2C_SYSS_REG,
  63         OMAP_I2C_BUF_REG,
  64         OMAP_I2C_CNT_REG,
  65         OMAP_I2C_DATA_REG,
  66         OMAP_I2C_SYSC_REG,
  67         OMAP_I2C_CON_REG,
  68         OMAP_I2C_OA_REG,
  69         OMAP_I2C_SA_REG,
  70         OMAP_I2C_PSC_REG,
  71         OMAP_I2C_SCLL_REG,
  72         OMAP_I2C_SCLH_REG,
  73         OMAP_I2C_SYSTEST_REG,
  74         OMAP_I2C_BUFSTAT_REG,
  75         /* only on OMAP4430 */
  76         OMAP_I2C_IP_V2_REVNB_LO,
  77         OMAP_I2C_IP_V2_REVNB_HI,
  78         OMAP_I2C_IP_V2_IRQSTATUS_RAW,
  79         OMAP_I2C_IP_V2_IRQENABLE_SET,
  80         OMAP_I2C_IP_V2_IRQENABLE_CLR,
  81 };
  82
  83 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
  84 #define OMAP_I2C_IE_XDR         (1 << 14)       /* TX Buffer drain int enable */
  85 #define OMAP_I2C_IE_RDR         (1 << 13)       /* RX Buffer drain int enable */
  86 #define OMAP_I2C_IE_XRDY        (1 << 4)        /* TX data ready int enable */
  87 #define OMAP_I2C_IE_RRDY        (1 << 3)        /* RX data ready int enable */
  88 #define OMAP_I2C_IE_ARDY        (1 << 2)        /* Access ready int enable */
  89 #define OMAP_I2C_IE_NACK        (1 << 1)        /* No ack interrupt enable */
  90 #define OMAP_I2C_IE_AL          (1 << 0)        /* Arbitration lost int ena */
  91
  92 /* I2C Status Register (OMAP_I2C_STAT): */
  93 #define OMAP_I2C_STAT_XDR       (1 << 14)       /* TX Buffer draining */
  94 #define OMAP_I2C_STAT_RDR       (1 << 13)       /* RX Buffer draining */
  95 #define OMAP_I2C_STAT_BB        (1 << 12)       /* Bus busy */
  96 #define OMAP_I2C_STAT_ROVR      (1 << 11)       /* Receive overrun */
  97 #define OMAP_I2C_STAT_XUDF      (1 << 10)       /* Transmit underflow */
  98 #define OMAP_I2C_STAT_AAS       (1 << 9)        /* Address as slave */
  99 #define OMAP_I2C_STAT_AD0       (1 << 8)        /* Address zero */
 100 #define OMAP_I2C_STAT_XRDY      (1 << 4)        /* Transmit data ready */
 101 #define OMAP_I2C_STAT_RRDY      (1 << 3)        /* Receive data ready */
 102 #define OMAP_I2C_STAT_ARDY      (1 << 2)        /* Register access ready */
 103 #define OMAP_I2C_STAT_NACK      (1 << 1)        /* No ack interrupt enable */
 104 #define OMAP_I2C_STAT_AL        (1 << 0)        /* Arbitration lost int ena */
 105
 106 /* I2C WE wakeup enable register */
 107 #define OMAP_I2C_WE_XDR_WE      (1 << 14)       /* TX drain wakup */
 108 #define OMAP_I2C_WE_RDR_WE      (1 << 13)       /* RX drain wakeup */
 109 #define OMAP_I2C_WE_AAS_WE      (1 << 9)        /* Address as slave wakeup*/
 110 #define OMAP_I2C_WE_BF_WE       (1 << 8)        /* Bus free wakeup */
 111 #define OMAP_I2C_WE_STC_WE      (1 << 6)        /* Start condition wakeup */
 112 #define OMAP_I2C_WE_GC_WE       (1 << 5)        /* General call wakeup */
 113 #define OMAP_I2C_WE_DRDY_WE     (1 << 3)        /* TX/RX data ready wakeup */
 114 #define OMAP_I2C_WE_ARDY_WE     (1 << 2)        /* Reg access ready wakeup */
 115 #define OMAP_I2C_WE_NACK_WE     (1 << 1)        /* No acknowledgment wakeup */
 116 #define OMAP_I2C_WE_AL_WE       (1 << 0)        /* Arbitration lost wakeup */
 117
 118 #define OMAP_I2C_WE_ALL         (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
 119                                 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
 120                                 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
 121                                 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
 122                                 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
 123
 124 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
 125 #define OMAP_I2C_BUF_RDMA_EN    (1 << 15)       /* RX DMA channel enable */
 126 #define OMAP_I2C_BUF_RXFIF_CLR  (1 << 14)       /* RX FIFO Clear */
 127 #define OMAP_I2C_BUF_XDMA_EN    (1 << 7)        /* TX DMA channel enable */
 128 #define OMAP_I2C_BUF_TXFIF_CLR  (1 << 6)        /* TX FIFO Clear */
 129
 130 /* I2C Configuration Register (OMAP_I2C_CON): */
 131 #define OMAP_I2C_CON_EN         (1 << 15)       /* I2C module enable */
 132 #define OMAP_I2C_CON_BE         (1 << 14)       /* Big endian mode */
 133 #define OMAP_I2C_CON_OPMODE_HS  (1 << 12)       /* High Speed support */
 134 #define OMAP_I2C_CON_STB        (1 << 11)       /* Start byte mode (master) */
 135 #define OMAP_I2C_CON_MST        (1 << 10)       /* Master/slave mode */
 136 #define OMAP_I2C_CON_TRX        (1 << 9)        /* TX/RX mode (master only) */
 137 #define OMAP_I2C_CON_XA         (1 << 8)        /* Expand address */
 138 #define OMAP_I2C_CON_RM         (1 << 2)        /* Repeat mode (master only) */
 139 #define OMAP_I2C_CON_STP        (1 << 1)        /* Stop cond (master only) */
 140 #define OMAP_I2C_CON_STT        (1 << 0)        /* Start condition (master) */
 141
 142 /* I2C SCL time value when Master */
 143 #define OMAP_I2C_SCLL_HSSCLL    8
 144 #define OMAP_I2C_SCLH_HSSCLH    8
 145
 146 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
 147 #ifdef DEBUG
 148 #define OMAP_I2C_SYSTEST_ST_EN          (1 << 15)       /* System test enable */
 149 #define OMAP_I2C_SYSTEST_FREE           (1 << 14)       /* Free running mode */
 150 #define OMAP_I2C_SYSTEST_TMODE_MASK     (3 << 12)       /* Test mode select */
 151 #define OMAP_I2C_SYSTEST_TMODE_SHIFT    (12)            /* Test mode select */
 152 #define OMAP_I2C_SYSTEST_SCL_I          (1 << 3)        /* SCL line sense in */
 153 #define OMAP_I2C_SYSTEST_SCL_O          (1 << 2)        /* SCL line drive out */
 154 #define OMAP_I2C_SYSTEST_SDA_I          (1 << 1)        /* SDA line sense in */
 155 #define OMAP_I2C_SYSTEST_SDA_O          (1 << 0)        /* SDA line drive out */
 156 #endif
 157
 158 /* OCP_SYSSTATUS bit definitions */
 159 #define SYSS_RESETDONE_MASK             (1 << 0)
 160
 161 /* OCP_SYSCONFIG bit definitions */
 162 #define SYSC_CLOCKACTIVITY_MASK         (0x3 << 8)
 163 #define SYSC_SIDLEMODE_MASK             (0x3 << 3)
 164 #define SYSC_ENAWAKEUP_MASK             (1 << 2)
 165 #define SYSC_SOFTRESET_MASK             (1 << 1)
 166 #define SYSC_AUTOIDLE_MASK              (1 << 0)
 167
 168 #define SYSC_IDLEMODE_SMART             0x2
 169 #define SYSC_CLOCKACTIVITY_FCLK         0x2
 170
 171 /* Errata definitions */
 172 #define I2C_OMAP_ERRATA_I207            (1 << 0)
 173 #define I2C_OMAP3_1P153                 (1 << 1)
 174
 175 struct omap_i2c_dev {
 176         struct device           *dev;
 177         void __iomem            *base;          /* virtual */
 178         int                     irq;
 179         int                     reg_shift;      /* bit shift for I2C register addresses */
 180         struct completion       cmd_complete;
 181         struct resource         *ioarea;
 182         u32                     latency;        /* maximum mpu wkup latency */
 183         void                    (*set_mpu_wkup_lat)(struct device *dev,
 184                                                     long latency);
 185         u32                     speed;          /* Speed of bus in Khz */
 186         u16                     cmd_err;
 187         u8                      *buf;
 188         u8                      *regs;
 189         size_t                  buf_len;
 190         struct i2c_adapter      adapter;
 191         u8                      fifo_size;      /* use as flag and value
 192                                                  * fifo_size==0 implies no fifo
 193                                                  * if set, should be trsh+1
 194                                                  */
 195         u8                      rev;
 196         unsigned                b_hw:1;         /* bad h/w fixes */
 197         u16                     iestate;        /* Saved interrupt register */
 198         u16                     pscstate;
 199         u16                     scllstate;
 200         u16                     sclhstate;
 201         u16                     bufstate;
 202         u16                     syscstate;
 203         u16                     westate;
 204         u16                     errata;
 205 };
 206
 207 static const u8 reg_map_ip_v1[] = {
 208         [OMAP_I2C_REV_REG] = 0x00,
 209         [OMAP_I2C_IE_REG] = 0x01,
 210         [OMAP_I2C_STAT_REG] = 0x02,
 211         [OMAP_I2C_IV_REG] = 0x03,
 212         [OMAP_I2C_WE_REG] = 0x03,
 213         [OMAP_I2C_SYSS_REG] = 0x04,
 214         [OMAP_I2C_BUF_REG] = 0x05,
 215         [OMAP_I2C_CNT_REG] = 0x06,
 216         [OMAP_I2C_DATA_REG] = 0x07,
 217         [OMAP_I2C_SYSC_REG] = 0x08,
 218         [OMAP_I2C_CON_REG] = 0x09,
 219         [OMAP_I2C_OA_REG] = 0x0a,
 220         [OMAP_I2C_SA_REG] = 0x0b,
 221         [OMAP_I2C_PSC_REG] = 0x0c,
 222         [OMAP_I2C_SCLL_REG] = 0x0d,
 223         [OMAP_I2C_SCLH_REG] = 0x0e,
 224         [OMAP_I2C_SYSTEST_REG] = 0x0f,
 225         [OMAP_I2C_BUFSTAT_REG] = 0x10,
 226 };
 227
 228 static const u8 reg_map_ip_v2[] = {
 229         [OMAP_I2C_REV_REG] = 0x04,
 230         [OMAP_I2C_IE_REG] = 0x2c,
 231         [OMAP_I2C_STAT_REG] = 0x28,
 232         [OMAP_I2C_IV_REG] = 0x34,
 233         [OMAP_I2C_WE_REG] = 0x34,
 234         [OMAP_I2C_SYSS_REG] = 0x90,
 235         [OMAP_I2C_BUF_REG] = 0x94,
 236         [OMAP_I2C_CNT_REG] = 0x98,
 237         [OMAP_I2C_DATA_REG] = 0x9c,
 238         [OMAP_I2C_SYSC_REG] = 0x20,
 239         [OMAP_I2C_CON_REG] = 0xa4,
 240         [OMAP_I2C_OA_REG] = 0xa8,
 241         [OMAP_I2C_SA_REG] = 0xac,
 242         [OMAP_I2C_PSC_REG] = 0xb0,
 243         [OMAP_I2C_SCLL_REG] = 0xb4,
 244         [OMAP_I2C_SCLH_REG] = 0xb8,
 245         [OMAP_I2C_SYSTEST_REG] = 0xbC,
 246         [OMAP_I2C_BUFSTAT_REG] = 0xc0,
 247         [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
 248         [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
 249         [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
 250         [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
 251         [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
 252 };
 253
 254 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
 255                                       int reg, u16 val)
 256 {
 257         __raw_writew(val, i2c_dev->base +
 258                         (i2c_dev->regs[reg] << i2c_dev->reg_shift));
 259 }
 260
 261 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
 262 {
 263         return __raw_readw(i2c_dev->base +
 264                                 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
 265 }
 266
 267 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
 268 {
 269         struct omap_i2c_bus_platform_data *pdata;
 270
 271         pdata = dev->dev->platform_data;
 272
 273         if (pdata->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
 274                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 275                 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
 276                 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
 277                 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
 278                 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, dev->bufstate);
 279                 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, dev->syscstate);
 280                 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
 281                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 282         }
 283
 284         /*
 285          * Don't write to this register if the IE state is 0 as it can
 286          * cause deadlock.
 287          */
 288         if (dev->iestate)
 289                 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
 290 }
 291
 292 static void omap_i2c_idle(struct omap_i2c_dev *dev)
 293 {
 294         struct omap_i2c_bus_platform_data *pdata;
 295         u16 iv;
 296
 297         pdata = dev->dev->platform_data;
 298
 299         dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 300         if (pdata->rev == OMAP_I2C_IP_VERSION_2)
 301                 omap_i2c_write_reg(dev, OMAP_I2C_IP_V2_IRQENABLE_CLR, 1);
 302         else
 303                 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
 304
 305         if (dev->rev < OMAP_I2C_OMAP1_REV_2) {
 306                 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
 307         } else {
 308                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
 309
 310                 /* Flush posted write */
 311                 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 312         }
 313 }
 314
 315 static int omap_i2c_init(struct omap_i2c_dev *dev)
 316 {
 317         u16 psc = 0, scll = 0, sclh = 0, buf = 0;
 318         u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
 319         unsigned long fclk_rate = 12000000;
 320         unsigned long timeout;
 321         unsigned long internal_clk = 0;
 322         struct clk *fclk;
 323         struct omap_i2c_bus_platform_data *pdata;
 324
 325         pdata = dev->dev->platform_data;
 326
 327         if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
 328                 /* Disable I2C controller before soft reset */
 329                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
 330                         omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
 331                                 ~(OMAP_I2C_CON_EN));
 332
 333                 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
 334                 /* For some reason we need to set the EN bit before the
 335                  * reset done bit gets set. */
 336                 timeout = jiffies + OMAP_I2C_TIMEOUT;
 337                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 338                 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
 339                          SYSS_RESETDONE_MASK)) {
 340                         if (time_after(jiffies, timeout)) {
 341                                 dev_warn(dev->dev, "timeout waiting "
 342                                                 "for controller reset\n");
 343                                 return -ETIMEDOUT;
 344                         }
 345                         msleep(1);
 346                 }
 347
 348                 /* SYSC register is cleared by the reset; rewrite it */
 349                 if (dev->rev == OMAP_I2C_REV_ON_2430) {
 350
 351                         omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
 352                                            SYSC_AUTOIDLE_MASK);
 353
 354                 } else if (dev->rev >= OMAP_I2C_REV_ON_3430) {
 355                         dev->syscstate = SYSC_AUTOIDLE_MASK;
 356                         dev->syscstate |= SYSC_ENAWAKEUP_MASK;
 357                         dev->syscstate |= (SYSC_IDLEMODE_SMART <<
 358                               __ffs(SYSC_SIDLEMODE_MASK));
 359                         dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK <<
 360                               __ffs(SYSC_CLOCKACTIVITY_MASK));
 361
 362                         omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
 363                                                         dev->syscstate);
 364                         /*
 365                          * Enabling all wakup sources to stop I2C freezing on
 366                          * WFI instruction.
 367                          * REVISIT: Some wkup sources might not be needed.
 368                          */
 369                         dev->westate = OMAP_I2C_WE_ALL;
 370                         omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
 371                                                         dev->westate);
 372                 }
 373         }
 374         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 375
 376         if (pdata->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
 377                 /*
 378                  * The I2C functional clock is the armxor_ck, so there's
 379                  * no need to get "armxor_ck" separately.  Now, if OMAP2420
 380                  * always returns 12MHz for the functional clock, we can
 381                  * do this bit unconditionally.
 382                  */
 383                 fclk = clk_get(dev->dev, "fck");
 384                 fclk_rate = clk_get_rate(fclk);
 385                 clk_put(fclk);
 386
 387                 /* TRM for 5912 says the I2C clock must be prescaled to be
 388                  * between 7 - 12 MHz. The XOR input clock is typically
 389                  * 12, 13 or 19.2 MHz. So we should have code that produces:
 390                  *
 391                  * XOR MHz      Divider         Prescaler
 392                  * 12           1               0
 393                  * 13           2               1
 394                  * 19.2         2               1
 395                  */
 396                 if (fclk_rate > 12000000)
 397                         psc = fclk_rate / 12000000;
 398         }
 399
 400         if (!(pdata->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
 401
 402                 /*
 403                  * HSI2C controller internal clk rate should be 19.2 Mhz for
 404                  * HS and for all modes on 2430. On 34xx we can use lower rate
 405                  * to get longer filter period for better noise suppression.
 406                  * The filter is iclk (fclk for HS) period.
 407                  */
 408                 if (dev->speed > 400 ||
 409                                pdata->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
 410                         internal_clk = 19200;
 411                 else if (dev->speed > 100)
 412                         internal_clk = 9600;
 413                 else
 414                         internal_clk = 4000;
 415                 fclk = clk_get(dev->dev, "fck");
 416                 fclk_rate = clk_get_rate(fclk) / 1000;
 417                 clk_put(fclk);
 418
 419                 /* Compute prescaler divisor */
 420                 psc = fclk_rate / internal_clk;
 421                 psc = psc - 1;
 422
 423                 /* If configured for High Speed */
 424                 if (dev->speed > 400) {
 425                         unsigned long scl;
 426
 427                         /* For first phase of HS mode */
 428                         scl = internal_clk / 400;
 429                         fsscll = scl - (scl / 3) - 7;
 430                         fssclh = (scl / 3) - 5;
 431
 432                         /* For second phase of HS mode */
 433                         scl = fclk_rate / dev->speed;
 434                         hsscll = scl - (scl / 3) - 7;
 435                         hssclh = (scl / 3) - 5;
 436                 } else if (dev->speed > 100) {
 437                         unsigned long scl;
 438
 439                         /* Fast mode */
 440                         scl = internal_clk / dev->speed;
 441                         fsscll = scl - (scl / 3) - 7;
 442                         fssclh = (scl / 3) - 5;
 443                 } else {
 444                         /* Standard mode */
 445                         fsscll = internal_clk / (dev->speed * 2) - 7;
 446                         fssclh = internal_clk / (dev->speed * 2) - 5;
 447                 }
 448                 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
 449                 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
 450         } else {
 451                 /* Program desired operating rate */
 452                 fclk_rate /= (psc + 1) * 1000;
 453                 if (psc > 2)
 454                         psc = 2;
 455                 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
 456                 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
 457         }
 458
 459         /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
 460         omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
 461
 462         /* SCL low and high time values */
 463         omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
 464         omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
 465
 466         if (dev->fifo_size) {
 467                 /* Note: setup required fifo size - 1. RTRSH and XTRSH */
 468                 buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR |
 469                         (dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR;
 470                 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
 471         }
 472
 473         /* Take the I2C module out of reset: */
 474         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 475
 476         dev->errata = 0;
 477
 478         if (pdata->flags & OMAP_I2C_FLAG_APPLY_ERRATA_I207)
 479                 dev->errata |= I2C_OMAP_ERRATA_I207;
 480
 481         /* Enable interrupts */
 482         dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
 483                         OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
 484                         OMAP_I2C_IE_AL)  | ((dev->fifo_size) ?
 485                                 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
 486         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
 487         if (pdata->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
 488                 dev->pscstate = psc;
 489                 dev->scllstate = scll;
 490                 dev->sclhstate = sclh;
 491                 dev->bufstate = buf;
 492         }
 493         return 0;
 494 }
 495
 496 /*
 497  * Waiting on Bus Busy
 498  */
 499 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
 500 {
 501         unsigned long timeout;
 502
 503         timeout = jiffies + OMAP_I2C_TIMEOUT;
 504         while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
 505                 if (time_after(jiffies, timeout)) {
 506                         dev_warn(dev->dev, "timeout waiting for bus ready\n");
 507                         return -ETIMEDOUT;
 508                 }
 509                 msleep(1);
 510         }
 511
 512         return 0;
 513 }
 514
 515 /*
 516  * Low level master read/write transaction.
 517  */
 518 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 519                              struct i2c_msg *msg, int stop)
 520 {
 521         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 522         int r;
 523         u16 w;
 524
 525         dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
 526                 msg->addr, msg->len, msg->flags, stop);
 527
 528         if (msg->len == 0)
 529                 return -EINVAL;
 530
 531         omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
 532
 533         /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
 534         dev->buf = msg->buf;
 535         dev->buf_len = msg->len;
 536
 537         omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
 538
 539         /* Clear the FIFO Buffers */
 540         w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
 541         w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
 542         omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
 543
 544         init_completion(&dev->cmd_complete);
 545         dev->cmd_err = 0;
 546
 547         w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
 548
 549         /* High speed configuration */
 550         if (dev->speed > 400)
 551                 w |= OMAP_I2C_CON_OPMODE_HS;
 552
 553         if (msg->flags & I2C_M_TEN)
 554                 w |= OMAP_I2C_CON_XA;
 555         if (!(msg->flags & I2C_M_RD))
 556                 w |= OMAP_I2C_CON_TRX;
 557
 558         if (!dev->b_hw && stop)
 559                 w |= OMAP_I2C_CON_STP;
 560
 561         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 562
 563         /*
 564          * Don't write stt and stp together on some hardware.
 565          */
 566         if (dev->b_hw && stop) {
 567                 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
 568                 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 569                 while (con & OMAP_I2C_CON_STT) {
 570                         con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 571
 572                         /* Let the user know if i2c is in a bad state */
 573                         if (time_after(jiffies, delay)) {
 574                                 dev_err(dev->dev, "controller timed out "
 575                                 "waiting for start condition to finish\n");
 576                                 return -ETIMEDOUT;
 577                         }
 578                         cpu_relax();
 579                 }
 580
 581                 w |= OMAP_I2C_CON_STP;
 582                 w &= ~OMAP_I2C_CON_STT;
 583                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 584         }
 585
 586         /*
 587          * REVISIT: We should abort the transfer on signals, but the bus goes
 588          * into arbitration and we're currently unable to recover from it.
 589          */
 590         r = wait_for_completion_timeout(&dev->cmd_complete,
 591                                         OMAP_I2C_TIMEOUT);
 592         dev->buf_len = 0;
 593         if (r < 0)
 594                 return r;
 595         if (r == 0) {
 596                 dev_err(dev->dev, "controller timed out\n");
 597                 omap_i2c_init(dev);
 598                 return -ETIMEDOUT;
 599         }
 600
 601         if (likely(!dev->cmd_err))
 602                 return 0;
 603
 604         /* We have an error */
 605         if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
 606                             OMAP_I2C_STAT_XUDF)) {
 607                 omap_i2c_init(dev);
 608                 return -EIO;
 609         }
 610
 611         if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
 612                 if (msg->flags & I2C_M_IGNORE_NAK)
 613                         return 0;
 614                 if (stop) {
 615                         w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 616                         w |= OMAP_I2C_CON_STP;
 617                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 618                 }
 619                 return -EREMOTEIO;
 620         }
 621         return -EIO;
 622 }
 623
 624
 625 /*
 626  * Prepare controller for a transaction and call omap_i2c_xfer_msg
 627  * to do the work during IRQ processing.
 628  */
 629 static int
 630 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 631 {
 632         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 633         int i;
 634         int r;
 635
 636         pm_runtime_get_sync(dev->dev);
 637
 638         r = omap_i2c_wait_for_bb(dev);
 639         if (r < 0)
 640                 goto out;
 641
 642         if (dev->set_mpu_wkup_lat != NULL)
 643                 dev->set_mpu_wkup_lat(dev->dev, dev->latency);
 644
 645         for (i = 0; i < num; i++) {
 646                 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 647                 if (r != 0)
 648                         break;
 649         }
 650
 651         if (dev->set_mpu_wkup_lat != NULL)
 652                 dev->set_mpu_wkup_lat(dev->dev, -1);
 653
 654         if (r == 0)
 655                 r = num;
 656
 657         omap_i2c_wait_for_bb(dev);
 658 out:
 659         pm_runtime_put(dev->dev);
 660         return r;
 661 }
 662
 663 static u32
 664 omap_i2c_func(struct i2c_adapter *adap)
 665 {
 666         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 667 }
 668
 669 static inline void
 670 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
 671 {
 672         dev->cmd_err |= err;
 673         complete(&dev->cmd_complete);
 674 }
 675
 676 static inline void
 677 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
 678 {
 679         omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 680 }
 681
 682 static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
 683 {
 684         /*
 685          * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
 686          * Not applicable for OMAP4.
 687          * Under certain rare conditions, RDR could be set again
 688          * when the bus is busy, then ignore the interrupt and
 689          * clear the interrupt.
 690          */
 691         if (stat & OMAP_I2C_STAT_RDR) {
 692                 /* Step 1: If RDR is set, clear it */
 693                 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
 694
 695                 /* Step 2: */
 696                 if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
 697                                                 & OMAP_I2C_STAT_BB)) {
 698
 699                         /* Step 3: */
 700                         if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
 701                                                 & OMAP_I2C_STAT_RDR) {
 702                                 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
 703                                 dev_dbg(dev->dev, "RDR when bus is busy.\n");
 704                         }
 705
 706                 }
 707         }
 708 }
 709
 710 /* rev1 devices are apparently only on some 15xx */
 711 #ifdef CONFIG_ARCH_OMAP15XX
 712
 713 static irqreturn_t
 714 omap_i2c_omap1_isr(int this_irq, void *dev_id)
 715 {
 716         struct omap_i2c_dev *dev = dev_id;
 717         u16 iv, w;
 718
 719         if (pm_runtime_suspended(dev->dev))
 720                 return IRQ_NONE;
 721
 722         iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
 723         switch (iv) {
 724         case 0x00:      /* None */
 725                 break;
 726         case 0x01:      /* Arbitration lost */
 727                 dev_err(dev->dev, "Arbitration lost\n");
 728                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
 729                 break;
 730         case 0x02:      /* No acknowledgement */
 731                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
 732                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
 733                 break;
 734         case 0x03:      /* Register access ready */
 735                 omap_i2c_complete_cmd(dev, 0);
 736                 break;
 737         case 0x04:      /* Receive data ready */
 738                 if (dev->buf_len) {
 739                         w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 740                         *dev->buf++ = w;
 741                         dev->buf_len--;
 742                         if (dev->buf_len) {
 743                                 *dev->buf++ = w >> 8;
 744                                 dev->buf_len--;
 745                         }
 746                 } else
 747                         dev_err(dev->dev, "RRDY IRQ while no data requested\n");
 748                 break;
 749         case 0x05:      /* Transmit data ready */
 750                 if (dev->buf_len) {
 751                         w = *dev->buf++;
 752                         dev->buf_len--;
 753                         if (dev->buf_len) {
 754                                 w |= *dev->buf++ << 8;
 755                                 dev->buf_len--;
 756                         }
 757                         omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 758                 } else
 759                         dev_err(dev->dev, "XRDY IRQ while no data to send\n");
 760                 break;
 761         default:
 762                 return IRQ_NONE;
 763         }
 764
 765         return IRQ_HANDLED;
 766 }
 767 #else
 768 #define omap_i2c_omap1_isr              NULL
 769 #endif
 770
 771 /*
 772  * OMAP3430 Errata 1.153: When an XRDY/XDR is hit, wait for XUDF before writing
 773  * data to DATA_REG. Otherwise some data bytes can be lost while transferring
 774  * them from the memory to the I2C interface.
 775  */
 776 static int errata_omap3_1p153(struct omap_i2c_dev *dev, u16 *stat, int *err)
 777 {
 778         unsigned long timeout = 10000;
 779
 780         while (--timeout && !(*stat & OMAP_I2C_STAT_XUDF)) {
 781                 if (*stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
 782                         omap_i2c_ack_stat(dev, *stat & (OMAP_I2C_STAT_XRDY |
 783                                                         OMAP_I2C_STAT_XDR));
 784                         *err |= OMAP_I2C_STAT_XUDF;
 785                         return -ETIMEDOUT;
 786                 }
 787
 788                 cpu_relax();
 789                 *stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 790         }
 791
 792         if (!timeout) {
 793                 dev_err(dev->dev, "timeout waiting on XUDF bit\n");
 794                 return 0;
 795         }
 796
 797         return 0;
 798 }
 799
 800 static irqreturn_t
 801 omap_i2c_isr(int this_irq, void *dev_id)
 802 {
 803         struct omap_i2c_dev *dev = dev_id;
 804         u16 bits;
 805         u16 stat, w;
 806         int err, count = 0;
 807         struct omap_i2c_bus_platform_data *pdata;
 808
 809         pdata = dev->dev->platform_data;
 810
 811         if (pm_runtime_suspended(dev->dev))
 812                 return IRQ_NONE;
 813
 814         bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 815         while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
 816                 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
 817                 if (count++ == 100) {
 818                         dev_warn(dev->dev, "Too much work in one IRQ\n");
 819                         break;
 820                 }
 821
 822                 err = 0;
 823 complete:
 824                 /*
 825                  * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be
 826                  * acked after the data operation is complete.
 827                  * Ref: TRM SWPU114Q Figure 18-31
 828                  */
 829                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat &
 830                                 ~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
 831                                 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
 832
 833                 if (stat & OMAP_I2C_STAT_NACK) {
 834                         err |= OMAP_I2C_STAT_NACK;
 835                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
 836                                            OMAP_I2C_CON_STP);
 837                 }
 838                 if (stat & OMAP_I2C_STAT_AL) {
 839                         dev_err(dev->dev, "Arbitration lost\n");
 840                         err |= OMAP_I2C_STAT_AL;
 841                 }
 842                 /*
 843                  * ProDB0017052: Clear ARDY bit twice
 844                  */
 845                 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
 846                                         OMAP_I2C_STAT_AL)) {
 847                         omap_i2c_ack_stat(dev, stat &
 848                                 (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
 849                                 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR |
 850                                 OMAP_I2C_STAT_ARDY));
 851                         omap_i2c_complete_cmd(dev, err);
 852                         return IRQ_HANDLED;
 853                 }
 854                 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
 855                         u8 num_bytes = 1;
 856
 857                         if (dev->errata & I2C_OMAP_ERRATA_I207)
 858                                 i2c_omap_errata_i207(dev, stat);
 859
 860                         if (dev->fifo_size) {
 861                                 if (stat & OMAP_I2C_STAT_RRDY)
 862                                         num_bytes = dev->fifo_size;
 863                                 else    /* read RXSTAT on RDR interrupt */
 864                                         num_bytes = (omap_i2c_read_reg(dev,
 865                                                         OMAP_I2C_BUFSTAT_REG)
 866                                                         >> 8) & 0x3F;
 867                         }
 868                         while (num_bytes) {
 869                                 num_bytes--;
 870                                 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 871                                 if (dev->buf_len) {
 872                                         *dev->buf++ = w;
 873                                         dev->buf_len--;
 874                                         /*
 875                                          * Data reg in 2430, omap3 and
 876                                          * omap4 is 8 bit wide
 877                                          */
 878                                         if (pdata->flags &
 879                                                  OMAP_I2C_FLAG_16BIT_DATA_REG) {
 880                                                 if (dev->buf_len) {
 881                                                         *dev->buf++ = w >> 8;
 882                                                         dev->buf_len--;
 883                                                 }
 884                                         }
 885                                 } else {
 886                                         if (stat & OMAP_I2C_STAT_RRDY)
 887                                                 dev_err(dev->dev,
 888                                                         "RRDY IRQ while no data"
 889                                                                 " requested\n");
 890                                         if (stat & OMAP_I2C_STAT_RDR)
 891                                                 dev_err(dev->dev,
 892                                                         "RDR IRQ while no data"
 893                                                                 " requested\n");
 894                                         break;
 895                                 }
 896                         }
 897                         omap_i2c_ack_stat(dev,
 898                                 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
 899                         continue;
 900                 }
 901                 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
 902                         u8 num_bytes = 1;
 903                         if (dev->fifo_size) {
 904                                 if (stat & OMAP_I2C_STAT_XRDY)
 905                                         num_bytes = dev->fifo_size;
 906                                 else    /* read TXSTAT on XDR interrupt */
 907                                         num_bytes = omap_i2c_read_reg(dev,
 908                                                         OMAP_I2C_BUFSTAT_REG)
 909                                                         & 0x3F;
 910                         }
 911                         while (num_bytes) {
 912                                 num_bytes--;
 913                                 w = 0;
 914                                 if (dev->buf_len) {
 915                                         w = *dev->buf++;
 916                                         dev->buf_len--;
 917                                         /*
 918                                          * Data reg in 2430, omap3 and
 919                                          * omap4 is 8 bit wide
 920                                          */
 921                                         if (pdata->flags &
 922                                                  OMAP_I2C_FLAG_16BIT_DATA_REG) {
 923                                                 if (dev->buf_len) {
 924                                                         w |= *dev->buf++ << 8;
 925                                                         dev->buf_len--;
 926                                                 }
 927                                         }
 928                                 } else {
 929                                         if (stat & OMAP_I2C_STAT_XRDY)
 930                                                 dev_err(dev->dev,
 931                                                         "XRDY IRQ while no "
 932                                                         "data to send\n");
 933                                         if (stat & OMAP_I2C_STAT_XDR)
 934                                                 dev_err(dev->dev,
 935                                                         "XDR IRQ while no "
 936                                                         "data to send\n");
 937                                         break;
 938                                 }
 939
 940                                 if ((dev->errata & I2C_OMAP3_1P153) &&
 941                                     errata_omap3_1p153(dev, &stat, &err))
 942                                         goto complete;
 943
 944                                 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 945                         }
 946                         omap_i2c_ack_stat(dev,
 947                                 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
 948                         continue;
 949                 }
 950                 if (stat & OMAP_I2C_STAT_ROVR) {
 951                         dev_err(dev->dev, "Receive overrun\n");
 952                         dev->cmd_err |= OMAP_I2C_STAT_ROVR;
 953                 }
 954                 if (stat & OMAP_I2C_STAT_XUDF) {
 955                         dev_err(dev->dev, "Transmit underflow\n");
 956                         dev->cmd_err |= OMAP_I2C_STAT_XUDF;
 957                 }
 958         }
 959
 960         return count ? IRQ_HANDLED : IRQ_NONE;
 961 }
 962
 963 static const struct i2c_algorithm omap_i2c_algo = {
 964         .master_xfer    = omap_i2c_xfer,
 965         .functionality  = omap_i2c_func,
 966 };
 967
 968 static int __devinit
 969 omap_i2c_probe(struct platform_device *pdev)
 970 {
 971         struct omap_i2c_dev     *dev;
 972         struct i2c_adapter      *adap;
 973         struct resource         *mem, *irq, *ioarea;
 974         struct omap_i2c_bus_platform_data *pdata = pdev->dev.platform_data;
 975         irq_handler_t isr;
 976         int r;
 977         u32 speed = 0;
 978
 979         /* NOTE: driver uses the static register mapping */
 980         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 981         if (!mem) {
 982                 dev_err(&pdev->dev, "no mem resource?\n");
 983                 return -ENODEV;
 984         }
 985         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 986         if (!irq) {
 987                 dev_err(&pdev->dev, "no irq resource?\n");
 988                 return -ENODEV;
 989         }
 990
 991         ioarea = request_mem_region(mem->start, resource_size(mem),
 992                         pdev->name);
 993         if (!ioarea) {
 994                 dev_err(&pdev->dev, "I2C region already claimed\n");
 995                 return -EBUSY;
 996         }
 997
 998         dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
 999         if (!dev) {
1000                 r = -ENOMEM;
1001                 goto err_release_region;
1002         }
1003
1004         if (pdata != NULL) {
1005                 speed = pdata->clkrate;
1006                 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
1007         } else {
1008                 speed = 100;    /* Default speed */
1009                 dev->set_mpu_wkup_lat = NULL;
1010         }
1011
1012         dev->speed = speed;
1013         dev->dev = &pdev->dev;
1014         dev->irq = irq->start;
1015         dev->base = ioremap(mem->start, resource_size(mem));
1016         if (!dev->base) {
1017                 r = -ENOMEM;
1018                 goto err_free_mem;
1019         }
1020
1021         platform_set_drvdata(pdev, dev);
1022
1023         dev->reg_shift = (pdata->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
1024
1025         if (pdata->rev == OMAP_I2C_IP_VERSION_2)
1026                 dev->regs = (u8 *)reg_map_ip_v2;
1027         else
1028                 dev->regs = (u8 *)reg_map_ip_v1;
1029
1030         pm_runtime_enable(dev->dev);
1031         pm_runtime_get_sync(dev->dev);
1032
1033         dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
1034
1035         if (dev->rev <= OMAP_I2C_REV_ON_3430)
1036                 dev->errata |= I2C_OMAP3_1P153;
1037
1038         if (!(pdata->flags & OMAP_I2C_FLAG_NO_FIFO)) {
1039                 u16 s;
1040
1041                 /* Set up the fifo size - Get total size */
1042                 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1043                 dev->fifo_size = 0x8 << s;
1044
1045                 /*
1046                  * Set up notification threshold as half the total available
1047                  * size. This is to ensure that we can handle the status on int
1048                  * call back latencies.
1049                  */
1050
1051                 dev->fifo_size = (dev->fifo_size / 2);
1052
1053                 if (dev->rev >= OMAP_I2C_REV_ON_3530_4430)
1054                         dev->b_hw = 0; /* Disable hardware fixes */
1055                 else
1056                         dev->b_hw = 1; /* Enable hardware fixes */
1057
1058                 /* calculate wakeup latency constraint for MPU */
1059                 if (dev->set_mpu_wkup_lat != NULL)
1060                         dev->latency = (1000000 * dev->fifo_size) /
1061                                        (1000 * speed / 8);
1062         }
1063
1064         /* reset ASAP, clearing any IRQs */
1065         omap_i2c_init(dev);
1066
1067         isr = (dev->rev < OMAP_I2C_OMAP1_REV_2) ? omap_i2c_omap1_isr :
1068                                                                    omap_i2c_isr;
1069         r = request_irq(dev->irq, isr, 0, pdev->name, dev);
1070
1071         if (r) {
1072                 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
1073                 goto err_unuse_clocks;
1074         }
1075
1076         dev_info(dev->dev, "bus %d rev%d.%d.%d at %d kHz\n", pdev->id,
1077                  pdata->rev, dev->rev >> 4, dev->rev & 0xf, dev->speed);
1078
1079         pm_runtime_put(dev->dev);
1080
1081         adap = &dev->adapter;
1082         i2c_set_adapdata(adap, dev);
1083         adap->owner = THIS_MODULE;
1084         adap->class = I2C_CLASS_HWMON;
1085         strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
1086         adap->algo = &omap_i2c_algo;
1087         adap->dev.parent = &pdev->dev;
1088
1089         /* i2c device drivers may be active on return from add_adapter() */
1090         adap->nr = pdev->id;
1091         r = i2c_add_numbered_adapter(adap);
1092         if (r) {
1093                 dev_err(dev->dev, "failure adding adapter\n");
1094                 goto err_free_irq;
1095         }
1096
1097         return 0;
1098
1099 err_free_irq:
1100         free_irq(dev->irq, dev);
1101 err_unuse_clocks:
1102         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1103         pm_runtime_put(dev->dev);
1104         iounmap(dev->base);
1105 err_free_mem:
1106         platform_set_drvdata(pdev, NULL);
1107         kfree(dev);
1108 err_release_region:
1109         release_mem_region(mem->start, resource_size(mem));
1110
1111         return r;
1112 }
1113
1114 static int
1115 omap_i2c_remove(struct platform_device *pdev)
1116 {
1117         struct omap_i2c_dev     *dev = platform_get_drvdata(pdev);
1118         struct resource         *mem;
1119
1120         platform_set_drvdata(pdev, NULL);
1121
1122         free_irq(dev->irq, dev);
1123         i2c_del_adapter(&dev->adapter);
1124         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1125         iounmap(dev->base);
1126         kfree(dev);
1127         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1128         release_mem_region(mem->start, resource_size(mem));
1129         return 0;
1130 }
1131
1132 #ifdef CONFIG_PM_RUNTIME
1133 static int omap_i2c_runtime_suspend(struct device *dev)
1134 {
1135         struct platform_device *pdev = to_platform_device(dev);
1136         struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
1137
1138         omap_i2c_idle(_dev);
1139
1140         return 0;
1141 }
1142
1143 static int omap_i2c_runtime_resume(struct device *dev)
1144 {
1145         struct platform_device *pdev = to_platform_device(dev);
1146         struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
1147
1148         omap_i2c_unidle(_dev);
1149
1150         return 0;
1151 }
1152
1153 static struct dev_pm_ops omap_i2c_pm_ops = {
1154         .runtime_suspend = omap_i2c_runtime_suspend,
1155         .runtime_resume = omap_i2c_runtime_resume,
1156 };
1157 #define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops)
1158 #else
1159 #define OMAP_I2C_PM_OPS NULL
1160 #endif
1161
1162 static struct platform_driver omap_i2c_driver = {
1163         .probe          = omap_i2c_probe,
1164         .remove         = omap_i2c_remove,
1165         .driver         = {
1166                 .name   = "omap_i2c",
1167                 .owner  = THIS_MODULE,
1168                 .pm     = OMAP_I2C_PM_OPS,
1169         },
1170 };
1171
1172 /* I2C may be needed to bring up other drivers */
1173 static int __init
1174 omap_i2c_init_driver(void)
1175 {
1176         return platform_driver_register(&omap_i2c_driver);
1177 }
1178 subsys_initcall(omap_i2c_init_driver);
1179
1180 static void __exit omap_i2c_exit_driver(void)
1181 {
1182         platform_driver_unregister(&omap_i2c_driver);
1183 }
1184 module_exit(omap_i2c_exit_driver);
1185
1186 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1187 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1188 MODULE_LICENSE("GPL");
1189 MODULE_ALIAS("platform:omap_i2c");