drm/radeon/dce6: add missing display reg for tiling setup
[linux-2.6.git] / drivers / gpu / drm / radeon / sid.h
1 /*
2  * Copyright 2011 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Alex Deucher
23  */
24 #ifndef SI_H
25 #define SI_H
26
27 #define CG_MULT_THERMAL_STATUS                                  0x714
28 #define         ASIC_MAX_TEMP(x)                                ((x) << 0)
29 #define         ASIC_MAX_TEMP_MASK                              0x000001ff
30 #define         ASIC_MAX_TEMP_SHIFT                             0
31 #define         CTF_TEMP(x)                                     ((x) << 9)
32 #define         CTF_TEMP_MASK                                   0x0003fe00
33 #define         CTF_TEMP_SHIFT                                  9
34
35 #define SI_MAX_SH_GPRS           256
36 #define SI_MAX_TEMP_GPRS         16
37 #define SI_MAX_SH_THREADS        256
38 #define SI_MAX_SH_STACK_ENTRIES  4096
39 #define SI_MAX_FRC_EOV_CNT       16384
40 #define SI_MAX_BACKENDS          8
41 #define SI_MAX_BACKENDS_MASK     0xFF
42 #define SI_MAX_BACKENDS_PER_SE_MASK     0x0F
43 #define SI_MAX_SIMDS             12
44 #define SI_MAX_SIMDS_MASK        0x0FFF
45 #define SI_MAX_SIMDS_PER_SE_MASK        0x00FF
46 #define SI_MAX_PIPES             8
47 #define SI_MAX_PIPES_MASK        0xFF
48 #define SI_MAX_PIPES_PER_SIMD_MASK      0x3F
49 #define SI_MAX_LDS_NUM           0xFFFF
50 #define SI_MAX_TCC               16
51 #define SI_MAX_TCC_MASK          0xFFFF
52
53 #define VGA_HDP_CONTROL                                 0x328
54 #define         VGA_MEMORY_DISABLE                              (1 << 4)
55
56 #define DMIF_ADDR_CONFIG                                0xBD4
57
58 #define DMIF_ADDR_CALC                                  0xC00
59
60 #define SRBM_STATUS                                     0xE50
61
62 #define CC_SYS_RB_BACKEND_DISABLE                       0xe80
63 #define GC_USER_SYS_RB_BACKEND_DISABLE                  0xe84
64
65 #define VM_L2_CNTL                                      0x1400
66 #define         ENABLE_L2_CACHE                                 (1 << 0)
67 #define         ENABLE_L2_FRAGMENT_PROCESSING                   (1 << 1)
68 #define         L2_CACHE_PTE_ENDIAN_SWAP_MODE(x)                ((x) << 2)
69 #define         L2_CACHE_PDE_ENDIAN_SWAP_MODE(x)                ((x) << 4)
70 #define         ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE         (1 << 9)
71 #define         ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE        (1 << 10)
72 #define         EFFECTIVE_L2_QUEUE_SIZE(x)                      (((x) & 7) << 15)
73 #define         CONTEXT1_IDENTITY_ACCESS_MODE(x)                (((x) & 3) << 19)
74 #define VM_L2_CNTL2                                     0x1404
75 #define         INVALIDATE_ALL_L1_TLBS                          (1 << 0)
76 #define         INVALIDATE_L2_CACHE                             (1 << 1)
77 #define         INVALIDATE_CACHE_MODE(x)                        ((x) << 26)
78 #define                 INVALIDATE_PTE_AND_PDE_CACHES           0
79 #define                 INVALIDATE_ONLY_PTE_CACHES              1
80 #define                 INVALIDATE_ONLY_PDE_CACHES              2
81 #define VM_L2_CNTL3                                     0x1408
82 #define         BANK_SELECT(x)                                  ((x) << 0)
83 #define         L2_CACHE_UPDATE_MODE(x)                         ((x) << 6)
84 #define         L2_CACHE_BIGK_FRAGMENT_SIZE(x)                  ((x) << 15)
85 #define         L2_CACHE_BIGK_ASSOCIATIVITY                     (1 << 20)
86 #define VM_L2_STATUS                                    0x140C
87 #define         L2_BUSY                                         (1 << 0)
88 #define VM_CONTEXT0_CNTL                                0x1410
89 #define         ENABLE_CONTEXT                                  (1 << 0)
90 #define         PAGE_TABLE_DEPTH(x)                             (((x) & 3) << 1)
91 #define         RANGE_PROTECTION_FAULT_ENABLE_DEFAULT           (1 << 4)
92 #define VM_CONTEXT1_CNTL                                0x1414
93 #define VM_CONTEXT0_CNTL2                               0x1430
94 #define VM_CONTEXT1_CNTL2                               0x1434
95 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR                0x1438
96 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR                0x143c
97 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR               0x1440
98 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR               0x1444
99 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR               0x1448
100 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR               0x144c
101 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR               0x1450
102 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR               0x1454
103
104 #define VM_INVALIDATE_REQUEST                           0x1478
105 #define VM_INVALIDATE_RESPONSE                          0x147c
106
107 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR       0x1518
108 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR       0x151c
109
110 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR                0x153c
111 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR                0x1540
112 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR                0x1544
113 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR                0x1548
114 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR                0x154c
115 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR                0x1550
116 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR                0x1554
117 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR                0x1558
118 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR               0x155c
119 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR               0x1560
120
121 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR                 0x157C
122 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR                 0x1580
123
124 #define MC_SHARED_CHMAP                                         0x2004
125 #define         NOOFCHAN_SHIFT                                  12
126 #define         NOOFCHAN_MASK                                   0x0000f000
127 #define MC_SHARED_CHREMAP                                       0x2008
128
129 #define MC_VM_FB_LOCATION                               0x2024
130 #define MC_VM_AGP_TOP                                   0x2028
131 #define MC_VM_AGP_BOT                                   0x202C
132 #define MC_VM_AGP_BASE                                  0x2030
133 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR                  0x2034
134 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR                 0x2038
135 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR              0x203C
136
137 #define MC_VM_MX_L1_TLB_CNTL                            0x2064
138 #define         ENABLE_L1_TLB                                   (1 << 0)
139 #define         ENABLE_L1_FRAGMENT_PROCESSING                   (1 << 1)
140 #define         SYSTEM_ACCESS_MODE_PA_ONLY                      (0 << 3)
141 #define         SYSTEM_ACCESS_MODE_USE_SYS_MAP                  (1 << 3)
142 #define         SYSTEM_ACCESS_MODE_IN_SYS                       (2 << 3)
143 #define         SYSTEM_ACCESS_MODE_NOT_IN_SYS                   (3 << 3)
144 #define         SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU       (0 << 5)
145 #define         ENABLE_ADVANCED_DRIVER_MODEL                    (1 << 6)
146
147 #define MC_SHARED_BLACKOUT_CNTL                         0x20ac
148
149 #define MC_ARB_RAMCFG                                   0x2760
150 #define         NOOFBANK_SHIFT                                  0
151 #define         NOOFBANK_MASK                                   0x00000003
152 #define         NOOFRANK_SHIFT                                  2
153 #define         NOOFRANK_MASK                                   0x00000004
154 #define         NOOFROWS_SHIFT                                  3
155 #define         NOOFROWS_MASK                                   0x00000038
156 #define         NOOFCOLS_SHIFT                                  6
157 #define         NOOFCOLS_MASK                                   0x000000C0
158 #define         CHANSIZE_SHIFT                                  8
159 #define         CHANSIZE_MASK                                   0x00000100
160 #define         CHANSIZE_OVERRIDE                               (1 << 11)
161 #define         NOOFGROUPS_SHIFT                                12
162 #define         NOOFGROUPS_MASK                                 0x00001000
163
164 #define MC_SEQ_TRAIN_WAKEUP_CNTL                        0x2808
165 #define         TRAIN_DONE_D0                           (1 << 30)
166 #define         TRAIN_DONE_D1                           (1 << 31)
167
168 #define MC_SEQ_SUP_CNTL                                 0x28c8
169 #define         RUN_MASK                                (1 << 0)
170 #define MC_SEQ_SUP_PGM                                  0x28cc
171
172 #define MC_IO_PAD_CNTL_D0                               0x29d0
173 #define         MEM_FALL_OUT_CMD                        (1 << 8)
174
175 #define MC_SEQ_IO_DEBUG_INDEX                           0x2a44
176 #define MC_SEQ_IO_DEBUG_DATA                            0x2a48
177
178 #define HDP_HOST_PATH_CNTL                              0x2C00
179 #define HDP_NONSURFACE_BASE                             0x2C04
180 #define HDP_NONSURFACE_INFO                             0x2C08
181 #define HDP_NONSURFACE_SIZE                             0x2C0C
182
183 #define HDP_ADDR_CONFIG                                 0x2F48
184 #define HDP_MISC_CNTL                                   0x2F4C
185 #define         HDP_FLUSH_INVALIDATE_CACHE                      (1 << 0)
186
187 #define IH_RB_CNTL                                        0x3e00
188 #       define IH_RB_ENABLE                               (1 << 0)
189 #       define IH_IB_SIZE(x)                              ((x) << 1) /* log2 */
190 #       define IH_RB_FULL_DRAIN_ENABLE                    (1 << 6)
191 #       define IH_WPTR_WRITEBACK_ENABLE                   (1 << 8)
192 #       define IH_WPTR_WRITEBACK_TIMER(x)                 ((x) << 9) /* log2 */
193 #       define IH_WPTR_OVERFLOW_ENABLE                    (1 << 16)
194 #       define IH_WPTR_OVERFLOW_CLEAR                     (1 << 31)
195 #define IH_RB_BASE                                        0x3e04
196 #define IH_RB_RPTR                                        0x3e08
197 #define IH_RB_WPTR                                        0x3e0c
198 #       define RB_OVERFLOW                                (1 << 0)
199 #       define WPTR_OFFSET_MASK                           0x3fffc
200 #define IH_RB_WPTR_ADDR_HI                                0x3e10
201 #define IH_RB_WPTR_ADDR_LO                                0x3e14
202 #define IH_CNTL                                           0x3e18
203 #       define ENABLE_INTR                                (1 << 0)
204 #       define IH_MC_SWAP(x)                              ((x) << 1)
205 #       define IH_MC_SWAP_NONE                            0
206 #       define IH_MC_SWAP_16BIT                           1
207 #       define IH_MC_SWAP_32BIT                           2
208 #       define IH_MC_SWAP_64BIT                           3
209 #       define RPTR_REARM                                 (1 << 4)
210 #       define MC_WRREQ_CREDIT(x)                         ((x) << 15)
211 #       define MC_WR_CLEAN_CNT(x)                         ((x) << 20)
212 #       define MC_VMID(x)                                 ((x) << 25)
213
214 #define CONFIG_MEMSIZE                                  0x5428
215
216 #define INTERRUPT_CNTL                                    0x5468
217 #       define IH_DUMMY_RD_OVERRIDE                       (1 << 0)
218 #       define IH_DUMMY_RD_EN                             (1 << 1)
219 #       define IH_REQ_NONSNOOP_EN                         (1 << 3)
220 #       define GEN_IH_INT_EN                              (1 << 8)
221 #define INTERRUPT_CNTL2                                   0x546c
222
223 #define HDP_MEM_COHERENCY_FLUSH_CNTL                    0x5480
224
225 #define BIF_FB_EN                                               0x5490
226 #define         FB_READ_EN                                      (1 << 0)
227 #define         FB_WRITE_EN                                     (1 << 1)
228
229 #define HDP_REG_COHERENCY_FLUSH_CNTL                    0x54A0
230
231 #define DC_LB_MEMORY_SPLIT                                      0x6b0c
232 #define         DC_LB_MEMORY_CONFIG(x)                          ((x) << 20)
233
234 #define PRIORITY_A_CNT                                          0x6b18
235 #define         PRIORITY_MARK_MASK                              0x7fff
236 #define         PRIORITY_OFF                                    (1 << 16)
237 #define         PRIORITY_ALWAYS_ON                              (1 << 20)
238 #define PRIORITY_B_CNT                                          0x6b1c
239
240 #define DPG_PIPE_ARBITRATION_CONTROL3                           0x6cc8
241 #       define LATENCY_WATERMARK_MASK(x)                        ((x) << 16)
242 #define DPG_PIPE_LATENCY_CONTROL                                0x6ccc
243 #       define LATENCY_LOW_WATERMARK(x)                         ((x) << 0)
244 #       define LATENCY_HIGH_WATERMARK(x)                        ((x) << 16)
245
246 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
247 #define VLINE_STATUS                                    0x6bb8
248 #       define VLINE_OCCURRED                           (1 << 0)
249 #       define VLINE_ACK                                (1 << 4)
250 #       define VLINE_STAT                               (1 << 12)
251 #       define VLINE_INTERRUPT                          (1 << 16)
252 #       define VLINE_INTERRUPT_TYPE                     (1 << 17)
253 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
254 #define VBLANK_STATUS                                   0x6bbc
255 #       define VBLANK_OCCURRED                          (1 << 0)
256 #       define VBLANK_ACK                               (1 << 4)
257 #       define VBLANK_STAT                              (1 << 12)
258 #       define VBLANK_INTERRUPT                         (1 << 16)
259 #       define VBLANK_INTERRUPT_TYPE                    (1 << 17)
260
261 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
262 #define INT_MASK                                        0x6b40
263 #       define VBLANK_INT_MASK                          (1 << 0)
264 #       define VLINE_INT_MASK                           (1 << 4)
265
266 #define DISP_INTERRUPT_STATUS                           0x60f4
267 #       define LB_D1_VLINE_INTERRUPT                    (1 << 2)
268 #       define LB_D1_VBLANK_INTERRUPT                   (1 << 3)
269 #       define DC_HPD1_INTERRUPT                        (1 << 17)
270 #       define DC_HPD1_RX_INTERRUPT                     (1 << 18)
271 #       define DACA_AUTODETECT_INTERRUPT                (1 << 22)
272 #       define DACB_AUTODETECT_INTERRUPT                (1 << 23)
273 #       define DC_I2C_SW_DONE_INTERRUPT                 (1 << 24)
274 #       define DC_I2C_HW_DONE_INTERRUPT                 (1 << 25)
275 #define DISP_INTERRUPT_STATUS_CONTINUE                  0x60f8
276 #       define LB_D2_VLINE_INTERRUPT                    (1 << 2)
277 #       define LB_D2_VBLANK_INTERRUPT                   (1 << 3)
278 #       define DC_HPD2_INTERRUPT                        (1 << 17)
279 #       define DC_HPD2_RX_INTERRUPT                     (1 << 18)
280 #       define DISP_TIMER_INTERRUPT                     (1 << 24)
281 #define DISP_INTERRUPT_STATUS_CONTINUE2                 0x60fc
282 #       define LB_D3_VLINE_INTERRUPT                    (1 << 2)
283 #       define LB_D3_VBLANK_INTERRUPT                   (1 << 3)
284 #       define DC_HPD3_INTERRUPT                        (1 << 17)
285 #       define DC_HPD3_RX_INTERRUPT                     (1 << 18)
286 #define DISP_INTERRUPT_STATUS_CONTINUE3                 0x6100
287 #       define LB_D4_VLINE_INTERRUPT                    (1 << 2)
288 #       define LB_D4_VBLANK_INTERRUPT                   (1 << 3)
289 #       define DC_HPD4_INTERRUPT                        (1 << 17)
290 #       define DC_HPD4_RX_INTERRUPT                     (1 << 18)
291 #define DISP_INTERRUPT_STATUS_CONTINUE4                 0x614c
292 #       define LB_D5_VLINE_INTERRUPT                    (1 << 2)
293 #       define LB_D5_VBLANK_INTERRUPT                   (1 << 3)
294 #       define DC_HPD5_INTERRUPT                        (1 << 17)
295 #       define DC_HPD5_RX_INTERRUPT                     (1 << 18)
296 #define DISP_INTERRUPT_STATUS_CONTINUE5                 0x6150
297 #       define LB_D6_VLINE_INTERRUPT                    (1 << 2)
298 #       define LB_D6_VBLANK_INTERRUPT                   (1 << 3)
299 #       define DC_HPD6_INTERRUPT                        (1 << 17)
300 #       define DC_HPD6_RX_INTERRUPT                     (1 << 18)
301
302 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
303 #define GRPH_INT_STATUS                                 0x6858
304 #       define GRPH_PFLIP_INT_OCCURRED                  (1 << 0)
305 #       define GRPH_PFLIP_INT_CLEAR                     (1 << 8)
306 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
307 #define GRPH_INT_CONTROL                                0x685c
308 #       define GRPH_PFLIP_INT_MASK                      (1 << 0)
309 #       define GRPH_PFLIP_INT_TYPE                      (1 << 8)
310
311 #define DACA_AUTODETECT_INT_CONTROL                     0x66c8
312
313 #define DC_HPD1_INT_STATUS                              0x601c
314 #define DC_HPD2_INT_STATUS                              0x6028
315 #define DC_HPD3_INT_STATUS                              0x6034
316 #define DC_HPD4_INT_STATUS                              0x6040
317 #define DC_HPD5_INT_STATUS                              0x604c
318 #define DC_HPD6_INT_STATUS                              0x6058
319 #       define DC_HPDx_INT_STATUS                       (1 << 0)
320 #       define DC_HPDx_SENSE                            (1 << 1)
321 #       define DC_HPDx_RX_INT_STATUS                    (1 << 8)
322
323 #define DC_HPD1_INT_CONTROL                             0x6020
324 #define DC_HPD2_INT_CONTROL                             0x602c
325 #define DC_HPD3_INT_CONTROL                             0x6038
326 #define DC_HPD4_INT_CONTROL                             0x6044
327 #define DC_HPD5_INT_CONTROL                             0x6050
328 #define DC_HPD6_INT_CONTROL                             0x605c
329 #       define DC_HPDx_INT_ACK                          (1 << 0)
330 #       define DC_HPDx_INT_POLARITY                     (1 << 8)
331 #       define DC_HPDx_INT_EN                           (1 << 16)
332 #       define DC_HPDx_RX_INT_ACK                       (1 << 20)
333 #       define DC_HPDx_RX_INT_EN                        (1 << 24)
334
335 #define DC_HPD1_CONTROL                                   0x6024
336 #define DC_HPD2_CONTROL                                   0x6030
337 #define DC_HPD3_CONTROL                                   0x603c
338 #define DC_HPD4_CONTROL                                   0x6048
339 #define DC_HPD5_CONTROL                                   0x6054
340 #define DC_HPD6_CONTROL                                   0x6060
341 #       define DC_HPDx_CONNECTION_TIMER(x)                ((x) << 0)
342 #       define DC_HPDx_RX_INT_TIMER(x)                    ((x) << 16)
343 #       define DC_HPDx_EN                                 (1 << 28)
344
345 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
346 #define CRTC_STATUS_FRAME_COUNT                         0x6e98
347
348 #define GRBM_CNTL                                       0x8000
349 #define         GRBM_READ_TIMEOUT(x)                            ((x) << 0)
350
351 #define GRBM_STATUS2                                    0x8008
352 #define         RLC_RQ_PENDING                                  (1 << 0)
353 #define         RLC_BUSY                                        (1 << 8)
354 #define         TC_BUSY                                         (1 << 9)
355
356 #define GRBM_STATUS                                     0x8010
357 #define         CMDFIFO_AVAIL_MASK                              0x0000000F
358 #define         RING2_RQ_PENDING                                (1 << 4)
359 #define         SRBM_RQ_PENDING                                 (1 << 5)
360 #define         RING1_RQ_PENDING                                (1 << 6)
361 #define         CF_RQ_PENDING                                   (1 << 7)
362 #define         PF_RQ_PENDING                                   (1 << 8)
363 #define         GDS_DMA_RQ_PENDING                              (1 << 9)
364 #define         GRBM_EE_BUSY                                    (1 << 10)
365 #define         DB_CLEAN                                        (1 << 12)
366 #define         CB_CLEAN                                        (1 << 13)
367 #define         TA_BUSY                                         (1 << 14)
368 #define         GDS_BUSY                                        (1 << 15)
369 #define         VGT_BUSY                                        (1 << 17)
370 #define         IA_BUSY_NO_DMA                                  (1 << 18)
371 #define         IA_BUSY                                         (1 << 19)
372 #define         SX_BUSY                                         (1 << 20)
373 #define         SPI_BUSY                                        (1 << 22)
374 #define         BCI_BUSY                                        (1 << 23)
375 #define         SC_BUSY                                         (1 << 24)
376 #define         PA_BUSY                                         (1 << 25)
377 #define         DB_BUSY                                         (1 << 26)
378 #define         CP_COHERENCY_BUSY                               (1 << 28)
379 #define         CP_BUSY                                         (1 << 29)
380 #define         CB_BUSY                                         (1 << 30)
381 #define         GUI_ACTIVE                                      (1 << 31)
382 #define GRBM_STATUS_SE0                                 0x8014
383 #define GRBM_STATUS_SE1                                 0x8018
384 #define         SE_DB_CLEAN                                     (1 << 1)
385 #define         SE_CB_CLEAN                                     (1 << 2)
386 #define         SE_BCI_BUSY                                     (1 << 22)
387 #define         SE_VGT_BUSY                                     (1 << 23)
388 #define         SE_PA_BUSY                                      (1 << 24)
389 #define         SE_TA_BUSY                                      (1 << 25)
390 #define         SE_SX_BUSY                                      (1 << 26)
391 #define         SE_SPI_BUSY                                     (1 << 27)
392 #define         SE_SC_BUSY                                      (1 << 29)
393 #define         SE_DB_BUSY                                      (1 << 30)
394 #define         SE_CB_BUSY                                      (1 << 31)
395
396 #define GRBM_SOFT_RESET                                 0x8020
397 #define         SOFT_RESET_CP                                   (1 << 0)
398 #define         SOFT_RESET_CB                                   (1 << 1)
399 #define         SOFT_RESET_RLC                                  (1 << 2)
400 #define         SOFT_RESET_DB                                   (1 << 3)
401 #define         SOFT_RESET_GDS                                  (1 << 4)
402 #define         SOFT_RESET_PA                                   (1 << 5)
403 #define         SOFT_RESET_SC                                   (1 << 6)
404 #define         SOFT_RESET_BCI                                  (1 << 7)
405 #define         SOFT_RESET_SPI                                  (1 << 8)
406 #define         SOFT_RESET_SX                                   (1 << 10)
407 #define         SOFT_RESET_TC                                   (1 << 11)
408 #define         SOFT_RESET_TA                                   (1 << 12)
409 #define         SOFT_RESET_VGT                                  (1 << 14)
410 #define         SOFT_RESET_IA                                   (1 << 15)
411
412 #define GRBM_GFX_INDEX                                  0x802C
413
414 #define GRBM_INT_CNTL                                   0x8060
415 #       define RDERR_INT_ENABLE                         (1 << 0)
416 #       define GUI_IDLE_INT_ENABLE                      (1 << 19)
417
418 #define CP_STRMOUT_CNTL                                 0x84FC
419 #define SCRATCH_REG0                                    0x8500
420 #define SCRATCH_REG1                                    0x8504
421 #define SCRATCH_REG2                                    0x8508
422 #define SCRATCH_REG3                                    0x850C
423 #define SCRATCH_REG4                                    0x8510
424 #define SCRATCH_REG5                                    0x8514
425 #define SCRATCH_REG6                                    0x8518
426 #define SCRATCH_REG7                                    0x851C
427
428 #define SCRATCH_UMSK                                    0x8540
429 #define SCRATCH_ADDR                                    0x8544
430
431 #define CP_SEM_WAIT_TIMER                               0x85BC
432
433 #define CP_SEM_INCOMPLETE_TIMER_CNTL                    0x85C8
434
435 #define CP_ME_CNTL                                      0x86D8
436 #define         CP_CE_HALT                                      (1 << 24)
437 #define         CP_PFP_HALT                                     (1 << 26)
438 #define         CP_ME_HALT                                      (1 << 28)
439
440 #define CP_COHER_CNTL2                                  0x85E8
441
442 #define CP_RB2_RPTR                                     0x86f8
443 #define CP_RB1_RPTR                                     0x86fc
444 #define CP_RB0_RPTR                                     0x8700
445 #define CP_RB_WPTR_DELAY                                0x8704
446
447 #define CP_QUEUE_THRESHOLDS                             0x8760
448 #define         ROQ_IB1_START(x)                                ((x) << 0)
449 #define         ROQ_IB2_START(x)                                ((x) << 8)
450 #define CP_MEQ_THRESHOLDS                               0x8764
451 #define         MEQ1_START(x)                           ((x) << 0)
452 #define         MEQ2_START(x)                           ((x) << 8)
453
454 #define CP_PERFMON_CNTL                                 0x87FC
455
456 #define VGT_VTX_VECT_EJECT_REG                          0x88B0
457
458 #define VGT_CACHE_INVALIDATION                          0x88C4
459 #define         CACHE_INVALIDATION(x)                           ((x) << 0)
460 #define                 VC_ONLY                                         0
461 #define                 TC_ONLY                                         1
462 #define                 VC_AND_TC                                       2
463 #define         AUTO_INVLD_EN(x)                                ((x) << 6)
464 #define                 NO_AUTO                                         0
465 #define                 ES_AUTO                                         1
466 #define                 GS_AUTO                                         2
467 #define                 ES_AND_GS_AUTO                                  3
468 #define VGT_ESGS_RING_SIZE                              0x88C8
469 #define VGT_GSVS_RING_SIZE                              0x88CC
470
471 #define VGT_GS_VERTEX_REUSE                             0x88D4
472
473 #define VGT_PRIMITIVE_TYPE                              0x8958
474 #define VGT_INDEX_TYPE                                  0x895C
475
476 #define VGT_NUM_INDICES                                 0x8970
477 #define VGT_NUM_INSTANCES                               0x8974
478
479 #define VGT_TF_RING_SIZE                                0x8988
480
481 #define VGT_HS_OFFCHIP_PARAM                            0x89B0
482
483 #define VGT_TF_MEMORY_BASE                              0x89B8
484
485 #define CC_GC_SHADER_ARRAY_CONFIG                       0x89bc
486 #define GC_USER_SHADER_ARRAY_CONFIG                     0x89c0
487
488 #define PA_CL_ENHANCE                                   0x8A14
489 #define         CLIP_VTX_REORDER_ENA                            (1 << 0)
490 #define         NUM_CLIP_SEQ(x)                                 ((x) << 1)
491
492 #define PA_SU_LINE_STIPPLE_VALUE                        0x8A60
493
494 #define PA_SC_LINE_STIPPLE_STATE                        0x8B10
495
496 #define PA_SC_FORCE_EOV_MAX_CNTS                        0x8B24
497 #define         FORCE_EOV_MAX_CLK_CNT(x)                        ((x) << 0)
498 #define         FORCE_EOV_MAX_REZ_CNT(x)                        ((x) << 16)
499
500 #define PA_SC_FIFO_SIZE                                 0x8BCC
501 #define         SC_FRONTEND_PRIM_FIFO_SIZE(x)                   ((x) << 0)
502 #define         SC_BACKEND_PRIM_FIFO_SIZE(x)                    ((x) << 6)
503 #define         SC_HIZ_TILE_FIFO_SIZE(x)                        ((x) << 15)
504 #define         SC_EARLYZ_TILE_FIFO_SIZE(x)                     ((x) << 23)
505
506 #define PA_SC_ENHANCE                                   0x8BF0
507
508 #define SQ_CONFIG                                       0x8C00
509
510 #define SQC_CACHES                                      0x8C08
511
512 #define SX_DEBUG_1                                      0x9060
513
514 #define SPI_STATIC_THREAD_MGMT_1                        0x90E0
515 #define SPI_STATIC_THREAD_MGMT_2                        0x90E4
516 #define SPI_STATIC_THREAD_MGMT_3                        0x90E8
517 #define SPI_PS_MAX_WAVE_ID                              0x90EC
518
519 #define SPI_CONFIG_CNTL                                 0x9100
520
521 #define SPI_CONFIG_CNTL_1                               0x913C
522 #define         VTX_DONE_DELAY(x)                               ((x) << 0)
523 #define         INTERP_ONE_PRIM_PER_ROW                         (1 << 4)
524
525 #define CGTS_TCC_DISABLE                                0x9148
526 #define CGTS_USER_TCC_DISABLE                           0x914C
527 #define         TCC_DISABLE_MASK                                0xFFFF0000
528 #define         TCC_DISABLE_SHIFT                               16
529
530 #define TA_CNTL_AUX                                     0x9508
531
532 #define CC_RB_BACKEND_DISABLE                           0x98F4
533 #define         BACKEND_DISABLE(x)                      ((x) << 16)
534 #define GB_ADDR_CONFIG                                  0x98F8
535 #define         NUM_PIPES(x)                            ((x) << 0)
536 #define         NUM_PIPES_MASK                          0x00000007
537 #define         NUM_PIPES_SHIFT                         0
538 #define         PIPE_INTERLEAVE_SIZE(x)                 ((x) << 4)
539 #define         PIPE_INTERLEAVE_SIZE_MASK               0x00000070
540 #define         PIPE_INTERLEAVE_SIZE_SHIFT              4
541 #define         NUM_SHADER_ENGINES(x)                   ((x) << 12)
542 #define         NUM_SHADER_ENGINES_MASK                 0x00003000
543 #define         NUM_SHADER_ENGINES_SHIFT                12
544 #define         SHADER_ENGINE_TILE_SIZE(x)              ((x) << 16)
545 #define         SHADER_ENGINE_TILE_SIZE_MASK            0x00070000
546 #define         SHADER_ENGINE_TILE_SIZE_SHIFT           16
547 #define         NUM_GPUS(x)                             ((x) << 20)
548 #define         NUM_GPUS_MASK                           0x00700000
549 #define         NUM_GPUS_SHIFT                          20
550 #define         MULTI_GPU_TILE_SIZE(x)                  ((x) << 24)
551 #define         MULTI_GPU_TILE_SIZE_MASK                0x03000000
552 #define         MULTI_GPU_TILE_SIZE_SHIFT               24
553 #define         ROW_SIZE(x)                             ((x) << 28)
554 #define         ROW_SIZE_MASK                           0x30000000
555 #define         ROW_SIZE_SHIFT                          28
556
557 #define GB_TILE_MODE0                                   0x9910
558 #       define MICRO_TILE_MODE(x)                               ((x) << 0)
559 #              define   ADDR_SURF_DISPLAY_MICRO_TILING          0
560 #              define   ADDR_SURF_THIN_MICRO_TILING             1
561 #              define   ADDR_SURF_DEPTH_MICRO_TILING            2
562 #       define ARRAY_MODE(x)                                    ((x) << 2)
563 #              define   ARRAY_LINEAR_GENERAL                    0
564 #              define   ARRAY_LINEAR_ALIGNED                    1
565 #              define   ARRAY_1D_TILED_THIN1                    2
566 #              define   ARRAY_2D_TILED_THIN1                    4
567 #       define PIPE_CONFIG(x)                                   ((x) << 6)
568 #              define   ADDR_SURF_P2                            0
569 #              define   ADDR_SURF_P4_8x16                       4
570 #              define   ADDR_SURF_P4_16x16                      5
571 #              define   ADDR_SURF_P4_16x32                      6
572 #              define   ADDR_SURF_P4_32x32                      7
573 #              define   ADDR_SURF_P8_16x16_8x16                 8
574 #              define   ADDR_SURF_P8_16x32_8x16                 9
575 #              define   ADDR_SURF_P8_32x32_8x16                 10
576 #              define   ADDR_SURF_P8_16x32_16x16                11
577 #              define   ADDR_SURF_P8_32x32_16x16                12
578 #              define   ADDR_SURF_P8_32x32_16x32                13
579 #              define   ADDR_SURF_P8_32x64_32x32                14
580 #       define TILE_SPLIT(x)                                    ((x) << 11)
581 #              define   ADDR_SURF_TILE_SPLIT_64B                0
582 #              define   ADDR_SURF_TILE_SPLIT_128B               1
583 #              define   ADDR_SURF_TILE_SPLIT_256B               2
584 #              define   ADDR_SURF_TILE_SPLIT_512B               3
585 #              define   ADDR_SURF_TILE_SPLIT_1KB                4
586 #              define   ADDR_SURF_TILE_SPLIT_2KB                5
587 #              define   ADDR_SURF_TILE_SPLIT_4KB                6
588 #       define BANK_WIDTH(x)                                    ((x) << 14)
589 #              define   ADDR_SURF_BANK_WIDTH_1                  0
590 #              define   ADDR_SURF_BANK_WIDTH_2                  1
591 #              define   ADDR_SURF_BANK_WIDTH_4                  2
592 #              define   ADDR_SURF_BANK_WIDTH_8                  3
593 #       define BANK_HEIGHT(x)                                   ((x) << 16)
594 #              define   ADDR_SURF_BANK_HEIGHT_1                 0
595 #              define   ADDR_SURF_BANK_HEIGHT_2                 1
596 #              define   ADDR_SURF_BANK_HEIGHT_4                 2
597 #              define   ADDR_SURF_BANK_HEIGHT_8                 3
598 #       define MACRO_TILE_ASPECT(x)                             ((x) << 18)
599 #              define   ADDR_SURF_MACRO_ASPECT_1                0
600 #              define   ADDR_SURF_MACRO_ASPECT_2                1
601 #              define   ADDR_SURF_MACRO_ASPECT_4                2
602 #              define   ADDR_SURF_MACRO_ASPECT_8                3
603 #       define NUM_BANKS(x)                                     ((x) << 20)
604 #              define   ADDR_SURF_2_BANK                        0
605 #              define   ADDR_SURF_4_BANK                        1
606 #              define   ADDR_SURF_8_BANK                        2
607 #              define   ADDR_SURF_16_BANK                       3
608
609 #define CB_PERFCOUNTER0_SELECT0                         0x9a20
610 #define CB_PERFCOUNTER0_SELECT1                         0x9a24
611 #define CB_PERFCOUNTER1_SELECT0                         0x9a28
612 #define CB_PERFCOUNTER1_SELECT1                         0x9a2c
613 #define CB_PERFCOUNTER2_SELECT0                         0x9a30
614 #define CB_PERFCOUNTER2_SELECT1                         0x9a34
615 #define CB_PERFCOUNTER3_SELECT0                         0x9a38
616 #define CB_PERFCOUNTER3_SELECT1                         0x9a3c
617
618 #define GC_USER_RB_BACKEND_DISABLE                      0x9B7C
619 #define         BACKEND_DISABLE_MASK                    0x00FF0000
620 #define         BACKEND_DISABLE_SHIFT                   16
621
622 #define TCP_CHAN_STEER_LO                               0xac0c
623 #define TCP_CHAN_STEER_HI                               0xac10
624
625 #define CP_RB0_BASE                                     0xC100
626 #define CP_RB0_CNTL                                     0xC104
627 #define         RB_BUFSZ(x)                                     ((x) << 0)
628 #define         RB_BLKSZ(x)                                     ((x) << 8)
629 #define         BUF_SWAP_32BIT                                  (2 << 16)
630 #define         RB_NO_UPDATE                                    (1 << 27)
631 #define         RB_RPTR_WR_ENA                                  (1 << 31)
632
633 #define CP_RB0_RPTR_ADDR                                0xC10C
634 #define CP_RB0_RPTR_ADDR_HI                             0xC110
635 #define CP_RB0_WPTR                                     0xC114
636
637 #define CP_PFP_UCODE_ADDR                               0xC150
638 #define CP_PFP_UCODE_DATA                               0xC154
639 #define CP_ME_RAM_RADDR                                 0xC158
640 #define CP_ME_RAM_WADDR                                 0xC15C
641 #define CP_ME_RAM_DATA                                  0xC160
642
643 #define CP_CE_UCODE_ADDR                                0xC168
644 #define CP_CE_UCODE_DATA                                0xC16C
645
646 #define CP_RB1_BASE                                     0xC180
647 #define CP_RB1_CNTL                                     0xC184
648 #define CP_RB1_RPTR_ADDR                                0xC188
649 #define CP_RB1_RPTR_ADDR_HI                             0xC18C
650 #define CP_RB1_WPTR                                     0xC190
651 #define CP_RB2_BASE                                     0xC194
652 #define CP_RB2_CNTL                                     0xC198
653 #define CP_RB2_RPTR_ADDR                                0xC19C
654 #define CP_RB2_RPTR_ADDR_HI                             0xC1A0
655 #define CP_RB2_WPTR                                     0xC1A4
656 #define CP_INT_CNTL_RING0                               0xC1A8
657 #define CP_INT_CNTL_RING1                               0xC1AC
658 #define CP_INT_CNTL_RING2                               0xC1B0
659 #       define CNTX_BUSY_INT_ENABLE                     (1 << 19)
660 #       define CNTX_EMPTY_INT_ENABLE                    (1 << 20)
661 #       define WAIT_MEM_SEM_INT_ENABLE                  (1 << 21)
662 #       define TIME_STAMP_INT_ENABLE                    (1 << 26)
663 #       define CP_RINGID2_INT_ENABLE                    (1 << 29)
664 #       define CP_RINGID1_INT_ENABLE                    (1 << 30)
665 #       define CP_RINGID0_INT_ENABLE                    (1 << 31)
666 #define CP_INT_STATUS_RING0                             0xC1B4
667 #define CP_INT_STATUS_RING1                             0xC1B8
668 #define CP_INT_STATUS_RING2                             0xC1BC
669 #       define WAIT_MEM_SEM_INT_STAT                    (1 << 21)
670 #       define TIME_STAMP_INT_STAT                      (1 << 26)
671 #       define CP_RINGID2_INT_STAT                      (1 << 29)
672 #       define CP_RINGID1_INT_STAT                      (1 << 30)
673 #       define CP_RINGID0_INT_STAT                      (1 << 31)
674
675 #define CP_DEBUG                                        0xC1FC
676
677 #define RLC_CNTL                                          0xC300
678 #       define RLC_ENABLE                                 (1 << 0)
679 #define RLC_RL_BASE                                       0xC304
680 #define RLC_RL_SIZE                                       0xC308
681 #define RLC_LB_CNTL                                       0xC30C
682 #define RLC_SAVE_AND_RESTORE_BASE                         0xC310
683 #define RLC_LB_CNTR_MAX                                   0xC314
684 #define RLC_LB_CNTR_INIT                                  0xC318
685
686 #define RLC_CLEAR_STATE_RESTORE_BASE                      0xC320
687
688 #define RLC_UCODE_ADDR                                    0xC32C
689 #define RLC_UCODE_DATA                                    0xC330
690
691 #define RLC_MC_CNTL                                       0xC344
692 #define RLC_UCODE_CNTL                                    0xC348
693
694 #define VGT_EVENT_INITIATOR                             0x28a90
695 #       define SAMPLE_STREAMOUTSTATS1                   (1 << 0)
696 #       define SAMPLE_STREAMOUTSTATS2                   (2 << 0)
697 #       define SAMPLE_STREAMOUTSTATS3                   (3 << 0)
698 #       define CACHE_FLUSH_TS                           (4 << 0)
699 #       define CACHE_FLUSH                              (6 << 0)
700 #       define CS_PARTIAL_FLUSH                         (7 << 0)
701 #       define VGT_STREAMOUT_RESET                      (10 << 0)
702 #       define END_OF_PIPE_INCR_DE                      (11 << 0)
703 #       define END_OF_PIPE_IB_END                       (12 << 0)
704 #       define RST_PIX_CNT                              (13 << 0)
705 #       define VS_PARTIAL_FLUSH                         (15 << 0)
706 #       define PS_PARTIAL_FLUSH                         (16 << 0)
707 #       define CACHE_FLUSH_AND_INV_TS_EVENT             (20 << 0)
708 #       define ZPASS_DONE                               (21 << 0)
709 #       define CACHE_FLUSH_AND_INV_EVENT                (22 << 0)
710 #       define PERFCOUNTER_START                        (23 << 0)
711 #       define PERFCOUNTER_STOP                         (24 << 0)
712 #       define PIPELINESTAT_START                       (25 << 0)
713 #       define PIPELINESTAT_STOP                        (26 << 0)
714 #       define PERFCOUNTER_SAMPLE                       (27 << 0)
715 #       define SAMPLE_PIPELINESTAT                      (30 << 0)
716 #       define SAMPLE_STREAMOUTSTATS                    (32 << 0)
717 #       define RESET_VTX_CNT                            (33 << 0)
718 #       define VGT_FLUSH                                (36 << 0)
719 #       define BOTTOM_OF_PIPE_TS                        (40 << 0)
720 #       define DB_CACHE_FLUSH_AND_INV                   (42 << 0)
721 #       define FLUSH_AND_INV_DB_DATA_TS                 (43 << 0)
722 #       define FLUSH_AND_INV_DB_META                    (44 << 0)
723 #       define FLUSH_AND_INV_CB_DATA_TS                 (45 << 0)
724 #       define FLUSH_AND_INV_CB_META                    (46 << 0)
725 #       define CS_DONE                                  (47 << 0)
726 #       define PS_DONE                                  (48 << 0)
727 #       define FLUSH_AND_INV_CB_PIXEL_DATA              (49 << 0)
728 #       define THREAD_TRACE_START                       (51 << 0)
729 #       define THREAD_TRACE_STOP                        (52 << 0)
730 #       define THREAD_TRACE_FLUSH                       (54 << 0)
731 #       define THREAD_TRACE_FINISH                      (55 << 0)
732
733 /*
734  * PM4
735  */
736 #define PACKET_TYPE0    0
737 #define PACKET_TYPE1    1
738 #define PACKET_TYPE2    2
739 #define PACKET_TYPE3    3
740
741 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
742 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
743 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
744 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
745 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) |                         \
746                          (((reg) >> 2) & 0xFFFF) |                      \
747                          ((n) & 0x3FFF) << 16)
748 #define CP_PACKET2                      0x80000000
749 #define         PACKET2_PAD_SHIFT               0
750 #define         PACKET2_PAD_MASK                (0x3fffffff << 0)
751
752 #define PACKET2(v)      (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
753
754 #define PACKET3(op, n)  ((PACKET_TYPE3 << 30) |                         \
755                          (((op) & 0xFF) << 8) |                         \
756                          ((n) & 0x3FFF) << 16)
757
758 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
759
760 /* Packet 3 types */
761 #define PACKET3_NOP                                     0x10
762 #define PACKET3_SET_BASE                                0x11
763 #define         PACKET3_BASE_INDEX(x)                  ((x) << 0)
764 #define                 GDS_PARTITION_BASE              2
765 #define                 CE_PARTITION_BASE               3
766 #define PACKET3_CLEAR_STATE                             0x12
767 #define PACKET3_INDEX_BUFFER_SIZE                       0x13
768 #define PACKET3_DISPATCH_DIRECT                         0x15
769 #define PACKET3_DISPATCH_INDIRECT                       0x16
770 #define PACKET3_ALLOC_GDS                               0x1B
771 #define PACKET3_WRITE_GDS_RAM                           0x1C
772 #define PACKET3_ATOMIC_GDS                              0x1D
773 #define PACKET3_ATOMIC                                  0x1E
774 #define PACKET3_OCCLUSION_QUERY                         0x1F
775 #define PACKET3_SET_PREDICATION                         0x20
776 #define PACKET3_REG_RMW                                 0x21
777 #define PACKET3_COND_EXEC                               0x22
778 #define PACKET3_PRED_EXEC                               0x23
779 #define PACKET3_DRAW_INDIRECT                           0x24
780 #define PACKET3_DRAW_INDEX_INDIRECT                     0x25
781 #define PACKET3_INDEX_BASE                              0x26
782 #define PACKET3_DRAW_INDEX_2                            0x27
783 #define PACKET3_CONTEXT_CONTROL                         0x28
784 #define PACKET3_INDEX_TYPE                              0x2A
785 #define PACKET3_DRAW_INDIRECT_MULTI                     0x2C
786 #define PACKET3_DRAW_INDEX_AUTO                         0x2D
787 #define PACKET3_DRAW_INDEX_IMMD                         0x2E
788 #define PACKET3_NUM_INSTANCES                           0x2F
789 #define PACKET3_DRAW_INDEX_MULTI_AUTO                   0x30
790 #define PACKET3_INDIRECT_BUFFER_CONST                   0x31
791 #define PACKET3_INDIRECT_BUFFER                         0x32
792 #define PACKET3_STRMOUT_BUFFER_UPDATE                   0x34
793 #define PACKET3_DRAW_INDEX_OFFSET_2                     0x35
794 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT                0x36
795 #define PACKET3_WRITE_DATA                              0x37
796 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI               0x38
797 #define PACKET3_MEM_SEMAPHORE                           0x39
798 #define PACKET3_MPEG_INDEX                              0x3A
799 #define PACKET3_COPY_DW                                 0x3B
800 #define PACKET3_WAIT_REG_MEM                            0x3C
801 #define PACKET3_MEM_WRITE                               0x3D
802 #define PACKET3_COPY_DATA                               0x40
803 #define PACKET3_PFP_SYNC_ME                             0x42
804 #define PACKET3_SURFACE_SYNC                            0x43
805 #              define PACKET3_DEST_BASE_0_ENA      (1 << 0)
806 #              define PACKET3_DEST_BASE_1_ENA      (1 << 1)
807 #              define PACKET3_CB0_DEST_BASE_ENA    (1 << 6)
808 #              define PACKET3_CB1_DEST_BASE_ENA    (1 << 7)
809 #              define PACKET3_CB2_DEST_BASE_ENA    (1 << 8)
810 #              define PACKET3_CB3_DEST_BASE_ENA    (1 << 9)
811 #              define PACKET3_CB4_DEST_BASE_ENA    (1 << 10)
812 #              define PACKET3_CB5_DEST_BASE_ENA    (1 << 11)
813 #              define PACKET3_CB6_DEST_BASE_ENA    (1 << 12)
814 #              define PACKET3_CB7_DEST_BASE_ENA    (1 << 13)
815 #              define PACKET3_DB_DEST_BASE_ENA     (1 << 14)
816 #              define PACKET3_DEST_BASE_2_ENA      (1 << 19)
817 #              define PACKET3_DEST_BASE_3_ENA      (1 << 21)
818 #              define PACKET3_TCL1_ACTION_ENA      (1 << 22)
819 #              define PACKET3_TC_ACTION_ENA        (1 << 23)
820 #              define PACKET3_CB_ACTION_ENA        (1 << 25)
821 #              define PACKET3_DB_ACTION_ENA        (1 << 26)
822 #              define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
823 #              define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
824 #define PACKET3_ME_INITIALIZE                           0x44
825 #define         PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
826 #define PACKET3_COND_WRITE                              0x45
827 #define PACKET3_EVENT_WRITE                             0x46
828 #define         EVENT_TYPE(x)                           ((x) << 0)
829 #define         EVENT_INDEX(x)                          ((x) << 8)
830                 /* 0 - any non-TS event
831                  * 1 - ZPASS_DONE
832                  * 2 - SAMPLE_PIPELINESTAT
833                  * 3 - SAMPLE_STREAMOUTSTAT*
834                  * 4 - *S_PARTIAL_FLUSH
835                  * 5 - EOP events
836                  * 6 - EOS events
837                  * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT
838                  */
839 #define         INV_L2                                  (1 << 20)
840                 /* INV TC L2 cache when EVENT_INDEX = 7 */
841 #define PACKET3_EVENT_WRITE_EOP                         0x47
842 #define         DATA_SEL(x)                             ((x) << 29)
843                 /* 0 - discard
844                  * 1 - send low 32bit data
845                  * 2 - send 64bit data
846                  * 3 - send 64bit counter value
847                  */
848 #define         INT_SEL(x)                              ((x) << 24)
849                 /* 0 - none
850                  * 1 - interrupt only (DATA_SEL = 0)
851                  * 2 - interrupt when data write is confirmed
852                  */
853 #define PACKET3_EVENT_WRITE_EOS                         0x48
854 #define PACKET3_PREAMBLE_CNTL                           0x4A
855 #              define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE     (2 << 28)
856 #              define PACKET3_PREAMBLE_END_CLEAR_STATE       (3 << 28)
857 #define PACKET3_ONE_REG_WRITE                           0x57
858 #define PACKET3_LOAD_CONFIG_REG                         0x5F
859 #define PACKET3_LOAD_CONTEXT_REG                        0x60
860 #define PACKET3_LOAD_SH_REG                             0x61
861 #define PACKET3_SET_CONFIG_REG                          0x68
862 #define         PACKET3_SET_CONFIG_REG_START                    0x00008000
863 #define         PACKET3_SET_CONFIG_REG_END                      0x0000b000
864 #define PACKET3_SET_CONTEXT_REG                         0x69
865 #define         PACKET3_SET_CONTEXT_REG_START                   0x00028000
866 #define         PACKET3_SET_CONTEXT_REG_END                     0x00029000
867 #define PACKET3_SET_CONTEXT_REG_INDIRECT                0x73
868 #define PACKET3_SET_RESOURCE_INDIRECT                   0x74
869 #define PACKET3_SET_SH_REG                              0x76
870 #define         PACKET3_SET_SH_REG_START                        0x0000b000
871 #define         PACKET3_SET_SH_REG_END                          0x0000c000
872 #define PACKET3_SET_SH_REG_OFFSET                       0x77
873 #define PACKET3_ME_WRITE                                0x7A
874 #define PACKET3_SCRATCH_RAM_WRITE                       0x7D
875 #define PACKET3_SCRATCH_RAM_READ                        0x7E
876 #define PACKET3_CE_WRITE                                0x7F
877 #define PACKET3_LOAD_CONST_RAM                          0x80
878 #define PACKET3_WRITE_CONST_RAM                         0x81
879 #define PACKET3_WRITE_CONST_RAM_OFFSET                  0x82
880 #define PACKET3_DUMP_CONST_RAM                          0x83
881 #define PACKET3_INCREMENT_CE_COUNTER                    0x84
882 #define PACKET3_INCREMENT_DE_COUNTER                    0x85
883 #define PACKET3_WAIT_ON_CE_COUNTER                      0x86
884 #define PACKET3_WAIT_ON_DE_COUNTER                      0x87
885 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF                 0x88
886 #define PACKET3_SET_CE_DE_COUNTERS                      0x89
887 #define PACKET3_WAIT_ON_AVAIL_BUFFER                    0x8A
888
889 #endif