drm/radeon/kms: add debugfs for power management for AtomBIOS devices
[linux-2.6.git] / drivers / gpu / drm / radeon / rv770.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/firmware.h>
29 #include <linux/platform_device.h>
30 #include "drmP.h"
31 #include "radeon.h"
32 #include "radeon_drm.h"
33 #include "rv770d.h"
34 #include "atom.h"
35 #include "avivod.h"
36
37 #define R700_PFP_UCODE_SIZE 848
38 #define R700_PM4_UCODE_SIZE 1360
39
40 static void rv770_gpu_init(struct radeon_device *rdev);
41 void rv770_fini(struct radeon_device *rdev);
42
43
44 /*
45  * GART
46  */
47 int rv770_pcie_gart_enable(struct radeon_device *rdev)
48 {
49         u32 tmp;
50         int r, i;
51
52         if (rdev->gart.table.vram.robj == NULL) {
53                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
54                 return -EINVAL;
55         }
56         r = radeon_gart_table_vram_pin(rdev);
57         if (r)
58                 return r;
59         /* Setup L2 cache */
60         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
61                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
62                                 EFFECTIVE_L2_QUEUE_SIZE(7));
63         WREG32(VM_L2_CNTL2, 0);
64         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
65         /* Setup TLB control */
66         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
67                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
68                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
69                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
70         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
71         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
72         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
73         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
74         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
75         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
76         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
77         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
78         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
79         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
80         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
81                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
82         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
83                         (u32)(rdev->dummy_page.addr >> 12));
84         for (i = 1; i < 7; i++)
85                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
86
87         r600_pcie_gart_tlb_flush(rdev);
88         rdev->gart.ready = true;
89         return 0;
90 }
91
92 void rv770_pcie_gart_disable(struct radeon_device *rdev)
93 {
94         u32 tmp;
95         int i;
96
97         /* Disable all tables */
98         for (i = 0; i < 7; i++)
99                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
100
101         /* Setup L2 cache */
102         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
103                                 EFFECTIVE_L2_QUEUE_SIZE(7));
104         WREG32(VM_L2_CNTL2, 0);
105         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
106         /* Setup TLB control */
107         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
108         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
109         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
110         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
111         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
112         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
113         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
114         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
115         if (rdev->gart.table.vram.robj) {
116                 radeon_object_kunmap(rdev->gart.table.vram.robj);
117                 radeon_object_unpin(rdev->gart.table.vram.robj);
118         }
119 }
120
121 void rv770_pcie_gart_fini(struct radeon_device *rdev)
122 {
123         rv770_pcie_gart_disable(rdev);
124         radeon_gart_table_vram_free(rdev);
125         radeon_gart_fini(rdev);
126 }
127
128
129 void rv770_agp_enable(struct radeon_device *rdev)
130 {
131         u32 tmp;
132         int i;
133
134         /* Setup L2 cache */
135         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
136                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
137                                 EFFECTIVE_L2_QUEUE_SIZE(7));
138         WREG32(VM_L2_CNTL2, 0);
139         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
140         /* Setup TLB control */
141         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
142                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
143                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
144                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
145         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
146         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
147         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
148         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
149         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
150         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
151         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
152         for (i = 0; i < 7; i++)
153                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
154 }
155
156 static void rv770_mc_program(struct radeon_device *rdev)
157 {
158         struct rv515_mc_save save;
159         u32 tmp;
160         int i, j;
161
162         /* Initialize HDP */
163         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
164                 WREG32((0x2c14 + j), 0x00000000);
165                 WREG32((0x2c18 + j), 0x00000000);
166                 WREG32((0x2c1c + j), 0x00000000);
167                 WREG32((0x2c20 + j), 0x00000000);
168                 WREG32((0x2c24 + j), 0x00000000);
169         }
170         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
171
172         rv515_mc_stop(rdev, &save);
173         if (r600_mc_wait_for_idle(rdev)) {
174                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
175         }
176         /* Lockout access through VGA aperture*/
177         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
178         /* Update configuration */
179         if (rdev->flags & RADEON_IS_AGP) {
180                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
181                         /* VRAM before AGP */
182                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
183                                 rdev->mc.vram_start >> 12);
184                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
185                                 rdev->mc.gtt_end >> 12);
186                 } else {
187                         /* VRAM after AGP */
188                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
189                                 rdev->mc.gtt_start >> 12);
190                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
191                                 rdev->mc.vram_end >> 12);
192                 }
193         } else {
194                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
195                         rdev->mc.vram_start >> 12);
196                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
197                         rdev->mc.vram_end >> 12);
198         }
199         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
200         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
201         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
202         WREG32(MC_VM_FB_LOCATION, tmp);
203         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
204         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
205         WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
206         if (rdev->flags & RADEON_IS_AGP) {
207                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
208                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
209                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
210         } else {
211                 WREG32(MC_VM_AGP_BASE, 0);
212                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
213                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
214         }
215         if (r600_mc_wait_for_idle(rdev)) {
216                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
217         }
218         rv515_mc_resume(rdev, &save);
219         /* we need to own VRAM, so turn off the VGA renderer here
220          * to stop it overwriting our objects */
221         rv515_vga_render_disable(rdev);
222 }
223
224
225 /*
226  * CP.
227  */
228 void r700_cp_stop(struct radeon_device *rdev)
229 {
230         WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
231 }
232
233
234 static int rv770_cp_load_microcode(struct radeon_device *rdev)
235 {
236         const __be32 *fw_data;
237         int i;
238
239         if (!rdev->me_fw || !rdev->pfp_fw)
240                 return -EINVAL;
241
242         r700_cp_stop(rdev);
243         WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
244
245         /* Reset cp */
246         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
247         RREG32(GRBM_SOFT_RESET);
248         mdelay(15);
249         WREG32(GRBM_SOFT_RESET, 0);
250
251         fw_data = (const __be32 *)rdev->pfp_fw->data;
252         WREG32(CP_PFP_UCODE_ADDR, 0);
253         for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
254                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
255         WREG32(CP_PFP_UCODE_ADDR, 0);
256
257         fw_data = (const __be32 *)rdev->me_fw->data;
258         WREG32(CP_ME_RAM_WADDR, 0);
259         for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
260                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
261
262         WREG32(CP_PFP_UCODE_ADDR, 0);
263         WREG32(CP_ME_RAM_WADDR, 0);
264         WREG32(CP_ME_RAM_RADDR, 0);
265         return 0;
266 }
267
268
269 /*
270  * Core functions
271  */
272 static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
273                                                 u32 num_backends,
274                                                 u32 backend_disable_mask)
275 {
276         u32 backend_map = 0;
277         u32 enabled_backends_mask;
278         u32 enabled_backends_count;
279         u32 cur_pipe;
280         u32 swizzle_pipe[R7XX_MAX_PIPES];
281         u32 cur_backend;
282         u32 i;
283
284         if (num_tile_pipes > R7XX_MAX_PIPES)
285                 num_tile_pipes = R7XX_MAX_PIPES;
286         if (num_tile_pipes < 1)
287                 num_tile_pipes = 1;
288         if (num_backends > R7XX_MAX_BACKENDS)
289                 num_backends = R7XX_MAX_BACKENDS;
290         if (num_backends < 1)
291                 num_backends = 1;
292
293         enabled_backends_mask = 0;
294         enabled_backends_count = 0;
295         for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
296                 if (((backend_disable_mask >> i) & 1) == 0) {
297                         enabled_backends_mask |= (1 << i);
298                         ++enabled_backends_count;
299                 }
300                 if (enabled_backends_count == num_backends)
301                         break;
302         }
303
304         if (enabled_backends_count == 0) {
305                 enabled_backends_mask = 1;
306                 enabled_backends_count = 1;
307         }
308
309         if (enabled_backends_count != num_backends)
310                 num_backends = enabled_backends_count;
311
312         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
313         switch (num_tile_pipes) {
314         case 1:
315                 swizzle_pipe[0] = 0;
316                 break;
317         case 2:
318                 swizzle_pipe[0] = 0;
319                 swizzle_pipe[1] = 1;
320                 break;
321         case 3:
322                 swizzle_pipe[0] = 0;
323                 swizzle_pipe[1] = 2;
324                 swizzle_pipe[2] = 1;
325                 break;
326         case 4:
327                 swizzle_pipe[0] = 0;
328                 swizzle_pipe[1] = 2;
329                 swizzle_pipe[2] = 3;
330                 swizzle_pipe[3] = 1;
331                 break;
332         case 5:
333                 swizzle_pipe[0] = 0;
334                 swizzle_pipe[1] = 2;
335                 swizzle_pipe[2] = 4;
336                 swizzle_pipe[3] = 1;
337                 swizzle_pipe[4] = 3;
338                 break;
339         case 6:
340                 swizzle_pipe[0] = 0;
341                 swizzle_pipe[1] = 2;
342                 swizzle_pipe[2] = 4;
343                 swizzle_pipe[3] = 5;
344                 swizzle_pipe[4] = 3;
345                 swizzle_pipe[5] = 1;
346                 break;
347         case 7:
348                 swizzle_pipe[0] = 0;
349                 swizzle_pipe[1] = 2;
350                 swizzle_pipe[2] = 4;
351                 swizzle_pipe[3] = 6;
352                 swizzle_pipe[4] = 3;
353                 swizzle_pipe[5] = 1;
354                 swizzle_pipe[6] = 5;
355                 break;
356         case 8:
357                 swizzle_pipe[0] = 0;
358                 swizzle_pipe[1] = 2;
359                 swizzle_pipe[2] = 4;
360                 swizzle_pipe[3] = 6;
361                 swizzle_pipe[4] = 3;
362                 swizzle_pipe[5] = 1;
363                 swizzle_pipe[6] = 7;
364                 swizzle_pipe[7] = 5;
365                 break;
366         }
367
368         cur_backend = 0;
369         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
370                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
371                         cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
372
373                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
374
375                 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
376         }
377
378         return backend_map;
379 }
380
381 static void rv770_gpu_init(struct radeon_device *rdev)
382 {
383         int i, j, num_qd_pipes;
384         u32 sx_debug_1;
385         u32 smx_dc_ctl0;
386         u32 num_gs_verts_per_thread;
387         u32 vgt_gs_per_es;
388         u32 gs_prim_buffer_depth = 0;
389         u32 sq_ms_fifo_sizes;
390         u32 sq_config;
391         u32 sq_thread_resource_mgmt;
392         u32 hdp_host_path_cntl;
393         u32 sq_dyn_gpr_size_simd_ab_0;
394         u32 backend_map;
395         u32 gb_tiling_config = 0;
396         u32 cc_rb_backend_disable = 0;
397         u32 cc_gc_shader_pipe_config = 0;
398         u32 mc_arb_ramcfg;
399         u32 db_debug4;
400
401         /* setup chip specs */
402         switch (rdev->family) {
403         case CHIP_RV770:
404                 rdev->config.rv770.max_pipes = 4;
405                 rdev->config.rv770.max_tile_pipes = 8;
406                 rdev->config.rv770.max_simds = 10;
407                 rdev->config.rv770.max_backends = 4;
408                 rdev->config.rv770.max_gprs = 256;
409                 rdev->config.rv770.max_threads = 248;
410                 rdev->config.rv770.max_stack_entries = 512;
411                 rdev->config.rv770.max_hw_contexts = 8;
412                 rdev->config.rv770.max_gs_threads = 16 * 2;
413                 rdev->config.rv770.sx_max_export_size = 128;
414                 rdev->config.rv770.sx_max_export_pos_size = 16;
415                 rdev->config.rv770.sx_max_export_smx_size = 112;
416                 rdev->config.rv770.sq_num_cf_insts = 2;
417
418                 rdev->config.rv770.sx_num_of_sets = 7;
419                 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
420                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
421                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
422                 break;
423         case CHIP_RV730:
424                 rdev->config.rv770.max_pipes = 2;
425                 rdev->config.rv770.max_tile_pipes = 4;
426                 rdev->config.rv770.max_simds = 8;
427                 rdev->config.rv770.max_backends = 2;
428                 rdev->config.rv770.max_gprs = 128;
429                 rdev->config.rv770.max_threads = 248;
430                 rdev->config.rv770.max_stack_entries = 256;
431                 rdev->config.rv770.max_hw_contexts = 8;
432                 rdev->config.rv770.max_gs_threads = 16 * 2;
433                 rdev->config.rv770.sx_max_export_size = 256;
434                 rdev->config.rv770.sx_max_export_pos_size = 32;
435                 rdev->config.rv770.sx_max_export_smx_size = 224;
436                 rdev->config.rv770.sq_num_cf_insts = 2;
437
438                 rdev->config.rv770.sx_num_of_sets = 7;
439                 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
440                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
441                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
442                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
443                         rdev->config.rv770.sx_max_export_pos_size -= 16;
444                         rdev->config.rv770.sx_max_export_smx_size += 16;
445                 }
446                 break;
447         case CHIP_RV710:
448                 rdev->config.rv770.max_pipes = 2;
449                 rdev->config.rv770.max_tile_pipes = 2;
450                 rdev->config.rv770.max_simds = 2;
451                 rdev->config.rv770.max_backends = 1;
452                 rdev->config.rv770.max_gprs = 256;
453                 rdev->config.rv770.max_threads = 192;
454                 rdev->config.rv770.max_stack_entries = 256;
455                 rdev->config.rv770.max_hw_contexts = 4;
456                 rdev->config.rv770.max_gs_threads = 8 * 2;
457                 rdev->config.rv770.sx_max_export_size = 128;
458                 rdev->config.rv770.sx_max_export_pos_size = 16;
459                 rdev->config.rv770.sx_max_export_smx_size = 112;
460                 rdev->config.rv770.sq_num_cf_insts = 1;
461
462                 rdev->config.rv770.sx_num_of_sets = 7;
463                 rdev->config.rv770.sc_prim_fifo_size = 0x40;
464                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
465                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
466                 break;
467         case CHIP_RV740:
468                 rdev->config.rv770.max_pipes = 4;
469                 rdev->config.rv770.max_tile_pipes = 4;
470                 rdev->config.rv770.max_simds = 8;
471                 rdev->config.rv770.max_backends = 4;
472                 rdev->config.rv770.max_gprs = 256;
473                 rdev->config.rv770.max_threads = 248;
474                 rdev->config.rv770.max_stack_entries = 512;
475                 rdev->config.rv770.max_hw_contexts = 8;
476                 rdev->config.rv770.max_gs_threads = 16 * 2;
477                 rdev->config.rv770.sx_max_export_size = 256;
478                 rdev->config.rv770.sx_max_export_pos_size = 32;
479                 rdev->config.rv770.sx_max_export_smx_size = 224;
480                 rdev->config.rv770.sq_num_cf_insts = 2;
481
482                 rdev->config.rv770.sx_num_of_sets = 7;
483                 rdev->config.rv770.sc_prim_fifo_size = 0x100;
484                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
485                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
486
487                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
488                         rdev->config.rv770.sx_max_export_pos_size -= 16;
489                         rdev->config.rv770.sx_max_export_smx_size += 16;
490                 }
491                 break;
492         default:
493                 break;
494         }
495
496         /* Initialize HDP */
497         j = 0;
498         for (i = 0; i < 32; i++) {
499                 WREG32((0x2c14 + j), 0x00000000);
500                 WREG32((0x2c18 + j), 0x00000000);
501                 WREG32((0x2c1c + j), 0x00000000);
502                 WREG32((0x2c20 + j), 0x00000000);
503                 WREG32((0x2c24 + j), 0x00000000);
504                 j += 0x18;
505         }
506
507         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
508
509         /* setup tiling, simd, pipe config */
510         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
511
512         switch (rdev->config.rv770.max_tile_pipes) {
513         case 1:
514                 gb_tiling_config |= PIPE_TILING(0);
515                 break;
516         case 2:
517                 gb_tiling_config |= PIPE_TILING(1);
518                 break;
519         case 4:
520                 gb_tiling_config |= PIPE_TILING(2);
521                 break;
522         case 8:
523                 gb_tiling_config |= PIPE_TILING(3);
524                 break;
525         default:
526                 break;
527         }
528
529         if (rdev->family == CHIP_RV770)
530                 gb_tiling_config |= BANK_TILING(1);
531         else
532                 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
533
534         gb_tiling_config |= GROUP_SIZE(0);
535
536         if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
537                 gb_tiling_config |= ROW_TILING(3);
538                 gb_tiling_config |= SAMPLE_SPLIT(3);
539         } else {
540                 gb_tiling_config |=
541                         ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
542                 gb_tiling_config |=
543                         SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
544         }
545
546         gb_tiling_config |= BANK_SWAPS(1);
547
548         backend_map = r700_get_tile_pipe_to_backend_map(rdev->config.rv770.max_tile_pipes,
549                                                         rdev->config.rv770.max_backends,
550                                                         (0xff << rdev->config.rv770.max_backends) & 0xff);
551         gb_tiling_config |= BACKEND_MAP(backend_map);
552
553         cc_gc_shader_pipe_config =
554                 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
555         cc_gc_shader_pipe_config |=
556                 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
557
558         cc_rb_backend_disable =
559                 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
560
561         WREG32(GB_TILING_CONFIG, gb_tiling_config);
562         WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
563         WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
564
565         WREG32(CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
566         WREG32(CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
567         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
568
569         WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
570         WREG32(CGTS_SYS_TCC_DISABLE, 0);
571         WREG32(CGTS_TCC_DISABLE, 0);
572         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
573         WREG32(CGTS_USER_TCC_DISABLE, 0);
574
575         num_qd_pipes =
576                 R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK);
577         WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
578         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
579
580         /* set HW defaults for 3D engine */
581         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
582                                      ROQ_IB2_START(0x2b)));
583
584         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
585
586         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
587                              SYNC_GRADIENT |
588                              SYNC_WALKER |
589                              SYNC_ALIGNER));
590
591         sx_debug_1 = RREG32(SX_DEBUG_1);
592         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
593         WREG32(SX_DEBUG_1, sx_debug_1);
594
595         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
596         smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
597         smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
598         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
599
600         WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
601                                GS_FLUSH_CTL(4) |
602                                ACK_FLUSH_CTL(3) |
603                                SYNC_FLUSH_CTL));
604
605         if (rdev->family == CHIP_RV770)
606                 WREG32(DB_DEBUG3, DB_CLK_OFF_DELAY(0x1f));
607         else {
608                 db_debug4 = RREG32(DB_DEBUG4);
609                 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
610                 WREG32(DB_DEBUG4, db_debug4);
611         }
612
613         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
614                                         POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
615                                         SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
616
617         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
618                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
619                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
620
621         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
622
623         WREG32(VGT_NUM_INSTANCES, 1);
624
625         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
626
627         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
628
629         WREG32(CP_PERFMON_CNTL, 0);
630
631         sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
632                             DONE_FIFO_HIWATER(0xe0) |
633                             ALU_UPDATE_FIFO_HIWATER(0x8));
634         switch (rdev->family) {
635         case CHIP_RV770:
636                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
637                 break;
638         case CHIP_RV730:
639         case CHIP_RV710:
640         case CHIP_RV740:
641         default:
642                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
643                 break;
644         }
645         WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
646
647         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
648          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
649          */
650         sq_config = RREG32(SQ_CONFIG);
651         sq_config &= ~(PS_PRIO(3) |
652                        VS_PRIO(3) |
653                        GS_PRIO(3) |
654                        ES_PRIO(3));
655         sq_config |= (DX9_CONSTS |
656                       VC_ENABLE |
657                       EXPORT_SRC_C |
658                       PS_PRIO(0) |
659                       VS_PRIO(1) |
660                       GS_PRIO(2) |
661                       ES_PRIO(3));
662         if (rdev->family == CHIP_RV710)
663                 /* no vertex cache */
664                 sq_config &= ~VC_ENABLE;
665
666         WREG32(SQ_CONFIG, sq_config);
667
668         WREG32(SQ_GPR_RESOURCE_MGMT_1,  (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
669                                          NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
670                                          NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
671
672         WREG32(SQ_GPR_RESOURCE_MGMT_2,  (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
673                                          NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
674
675         sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
676                                    NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
677                                    NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
678         if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
679                 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
680         else
681                 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
682         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
683
684         WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
685                                                      NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
686
687         WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
688                                                      NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
689
690         sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
691                                      SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
692                                      SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
693                                      SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
694
695         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
696         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
697         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
698         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
699         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
700         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
701         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
702         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
703
704         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
705                                           FORCE_EOV_MAX_REZ_CNT(255)));
706
707         if (rdev->family == CHIP_RV710)
708                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
709                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
710         else
711                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
712                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
713
714         switch (rdev->family) {
715         case CHIP_RV770:
716         case CHIP_RV730:
717         case CHIP_RV740:
718                 gs_prim_buffer_depth = 384;
719                 break;
720         case CHIP_RV710:
721                 gs_prim_buffer_depth = 128;
722                 break;
723         default:
724                 break;
725         }
726
727         num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
728         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
729         /* Max value for this is 256 */
730         if (vgt_gs_per_es > 256)
731                 vgt_gs_per_es = 256;
732
733         WREG32(VGT_ES_PER_GS, 128);
734         WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
735         WREG32(VGT_GS_PER_VS, 2);
736
737         /* more default values. 2D/3D driver should adjust as needed */
738         WREG32(VGT_GS_VERTEX_REUSE, 16);
739         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
740         WREG32(VGT_STRMOUT_EN, 0);
741         WREG32(SX_MISC, 0);
742         WREG32(PA_SC_MODE_CNTL, 0);
743         WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
744         WREG32(PA_SC_AA_CONFIG, 0);
745         WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
746         WREG32(PA_SC_LINE_STIPPLE, 0);
747         WREG32(SPI_INPUT_Z, 0);
748         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
749         WREG32(CB_COLOR7_FRAG, 0);
750
751         /* clear render buffer base addresses */
752         WREG32(CB_COLOR0_BASE, 0);
753         WREG32(CB_COLOR1_BASE, 0);
754         WREG32(CB_COLOR2_BASE, 0);
755         WREG32(CB_COLOR3_BASE, 0);
756         WREG32(CB_COLOR4_BASE, 0);
757         WREG32(CB_COLOR5_BASE, 0);
758         WREG32(CB_COLOR6_BASE, 0);
759         WREG32(CB_COLOR7_BASE, 0);
760
761         WREG32(TCP_CNTL, 0);
762
763         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
764         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
765
766         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
767
768         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
769                                           NUM_CLIP_SEQ(3)));
770
771 }
772
773 int rv770_mc_init(struct radeon_device *rdev)
774 {
775         fixed20_12 a;
776         u32 tmp;
777         int chansize, numchan;
778         int r;
779
780         /* Get VRAM informations */
781         rdev->mc.vram_is_ddr = true;
782         tmp = RREG32(MC_ARB_RAMCFG);
783         if (tmp & CHANSIZE_OVERRIDE) {
784                 chansize = 16;
785         } else if (tmp & CHANSIZE_MASK) {
786                 chansize = 64;
787         } else {
788                 chansize = 32;
789         }
790         tmp = RREG32(MC_SHARED_CHMAP);
791         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
792         case 0:
793         default:
794                 numchan = 1;
795                 break;
796         case 1:
797                 numchan = 2;
798                 break;
799         case 2:
800                 numchan = 4;
801                 break;
802         case 3:
803                 numchan = 8;
804                 break;
805         }
806         rdev->mc.vram_width = numchan * chansize;
807         /* Could aper size report 0 ? */
808         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
809         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
810         /* Setup GPU memory space */
811         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
812         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
813
814         if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
815                 rdev->mc.mc_vram_size = rdev->mc.aper_size;
816
817         if (rdev->mc.real_vram_size > rdev->mc.aper_size)
818                 rdev->mc.real_vram_size = rdev->mc.aper_size;
819
820         if (rdev->flags & RADEON_IS_AGP) {
821                 r = radeon_agp_init(rdev);
822                 if (r)
823                         return r;
824                 /* gtt_size is setup by radeon_agp_init */
825                 rdev->mc.gtt_location = rdev->mc.agp_base;
826                 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
827                 /* Try to put vram before or after AGP because we
828                  * we want SYSTEM_APERTURE to cover both VRAM and
829                  * AGP so that GPU can catch out of VRAM/AGP access
830                  */
831                 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
832                         /* Enought place before */
833                         rdev->mc.vram_location = rdev->mc.gtt_location -
834                                                         rdev->mc.mc_vram_size;
835                 } else if (tmp > rdev->mc.mc_vram_size) {
836                         /* Enought place after */
837                         rdev->mc.vram_location = rdev->mc.gtt_location +
838                                                         rdev->mc.gtt_size;
839                 } else {
840                         /* Try to setup VRAM then AGP might not
841                          * not work on some card
842                          */
843                         rdev->mc.vram_location = 0x00000000UL;
844                         rdev->mc.gtt_location = rdev->mc.mc_vram_size;
845                 }
846         } else {
847                 rdev->mc.vram_location = 0x00000000UL;
848                 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
849                 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
850         }
851         rdev->mc.vram_start = rdev->mc.vram_location;
852         rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
853         rdev->mc.gtt_start = rdev->mc.gtt_location;
854         rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
855         /* FIXME: we should enforce default clock in case GPU is not in
856          * default setup
857          */
858         a.full = rfixed_const(100);
859         rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
860         rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
861         return 0;
862 }
863 int rv770_gpu_reset(struct radeon_device *rdev)
864 {
865         /* FIXME: implement any rv770 specific bits */
866         return r600_gpu_reset(rdev);
867 }
868
869 static int rv770_startup(struct radeon_device *rdev)
870 {
871         int r;
872
873         rv770_mc_program(rdev);
874         if (rdev->flags & RADEON_IS_AGP) {
875                 rv770_agp_enable(rdev);
876         } else {
877                 r = rv770_pcie_gart_enable(rdev);
878                 if (r)
879                         return r;
880         }
881         rv770_gpu_init(rdev);
882
883         r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
884                               &rdev->r600_blit.shader_gpu_addr);
885         if (r) {
886                 DRM_ERROR("failed to pin blit object %d\n", r);
887                 return r;
888         }
889
890         r = radeon_ring_init(rdev, rdev->cp.ring_size);
891         if (r)
892                 return r;
893         r = rv770_cp_load_microcode(rdev);
894         if (r)
895                 return r;
896         r = r600_cp_resume(rdev);
897         if (r)
898                 return r;
899         /* write back buffer are not vital so don't worry about failure */
900         r600_wb_enable(rdev);
901         return 0;
902 }
903
904 int rv770_resume(struct radeon_device *rdev)
905 {
906         int r;
907
908         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
909          * posting will perform necessary task to bring back GPU into good
910          * shape.
911          */
912         /* post card */
913         atom_asic_init(rdev->mode_info.atom_context);
914         /* Initialize clocks */
915         r = radeon_clocks_init(rdev);
916         if (r) {
917                 return r;
918         }
919
920         r = rv770_startup(rdev);
921         if (r) {
922                 DRM_ERROR("r600 startup failed on resume\n");
923                 return r;
924         }
925
926         r = r600_ib_test(rdev);
927         if (r) {
928                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
929                 return r;
930         }
931         return r;
932
933 }
934
935 int rv770_suspend(struct radeon_device *rdev)
936 {
937         /* FIXME: we should wait for ring to be empty */
938         r700_cp_stop(rdev);
939         rdev->cp.ready = false;
940         r600_wb_disable(rdev);
941         rv770_pcie_gart_disable(rdev);
942         /* unpin shaders bo */
943         radeon_object_unpin(rdev->r600_blit.shader_obj);
944         return 0;
945 }
946
947 /* Plan is to move initialization in that function and use
948  * helper function so that radeon_device_init pretty much
949  * do nothing more than calling asic specific function. This
950  * should also allow to remove a bunch of callback function
951  * like vram_info.
952  */
953 int rv770_init(struct radeon_device *rdev)
954 {
955         int r;
956
957         r = radeon_dummy_page_init(rdev);
958         if (r)
959                 return r;
960         /* This don't do much */
961         r = radeon_gem_init(rdev);
962         if (r)
963                 return r;
964         /* Read BIOS */
965         if (!radeon_get_bios(rdev)) {
966                 if (ASIC_IS_AVIVO(rdev))
967                         return -EINVAL;
968         }
969         /* Must be an ATOMBIOS */
970         if (!rdev->is_atom_bios) {
971                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
972                 return -EINVAL;
973         }
974         r = radeon_atombios_init(rdev);
975         if (r)
976                 return r;
977         /* Post card if necessary */
978         if (!r600_card_posted(rdev) && rdev->bios) {
979                 DRM_INFO("GPU not posted. posting now...\n");
980                 atom_asic_init(rdev->mode_info.atom_context);
981         }
982         /* Initialize scratch registers */
983         r600_scratch_init(rdev);
984         /* Initialize surface registers */
985         radeon_surface_init(rdev);
986         /* Initialize clocks */
987         radeon_get_clock_info(rdev->ddev);
988         r = radeon_clocks_init(rdev);
989         if (r)
990                 return r;
991         /* Initialize power management */
992         radeon_pm_init(rdev);
993         /* Fence driver */
994         r = radeon_fence_driver_init(rdev);
995         if (r)
996                 return r;
997         r = rv770_mc_init(rdev);
998         if (r)
999                 return r;
1000         /* Memory manager */
1001         r = radeon_object_init(rdev);
1002         if (r)
1003                 return r;
1004         rdev->cp.ring_obj = NULL;
1005         r600_ring_init(rdev, 1024 * 1024);
1006
1007         if (!rdev->me_fw || !rdev->pfp_fw) {
1008                 r = r600_cp_init_microcode(rdev);
1009                 if (r) {
1010                         DRM_ERROR("Failed to load firmware!\n");
1011                         return r;
1012                 }
1013         }
1014
1015         r = r600_pcie_gart_init(rdev);
1016         if (r)
1017                 return r;
1018
1019         rdev->accel_working = true;
1020         r = r600_blit_init(rdev);
1021         if (r) {
1022                 DRM_ERROR("radeon: failled blitter (%d).\n", r);
1023                 rdev->accel_working = false;
1024         }
1025
1026         r = rv770_startup(rdev);
1027         if (r) {
1028                 rv770_suspend(rdev);
1029                 r600_wb_fini(rdev);
1030                 radeon_ring_fini(rdev);
1031                 rv770_pcie_gart_fini(rdev);
1032                 rdev->accel_working = false;
1033         }
1034         if (rdev->accel_working) {
1035                 r = radeon_ib_pool_init(rdev);
1036                 if (r) {
1037                         DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
1038                         rdev->accel_working = false;
1039                 }
1040                 r = r600_ib_test(rdev);
1041                 if (r) {
1042                         DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1043                         rdev->accel_working = false;
1044                 }
1045         }
1046         return 0;
1047 }
1048
1049 void rv770_fini(struct radeon_device *rdev)
1050 {
1051         rv770_suspend(rdev);
1052
1053         r600_blit_fini(rdev);
1054         radeon_ring_fini(rdev);
1055         r600_wb_fini(rdev);
1056         rv770_pcie_gart_fini(rdev);
1057         radeon_gem_fini(rdev);
1058         radeon_fence_driver_fini(rdev);
1059         radeon_clocks_fini(rdev);
1060         if (rdev->flags & RADEON_IS_AGP)
1061                 radeon_agp_fini(rdev);
1062         radeon_object_fini(rdev);
1063         radeon_atombios_fini(rdev);
1064         kfree(rdev->bios);
1065         rdev->bios = NULL;
1066         radeon_dummy_page_fini(rdev);
1067 }