drm/radeon/kms/pm: enable SetVoltage on r7xx/evergreen
[linux-2.6.git] / drivers / gpu / drm / radeon / rv770.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/firmware.h>
29 #include <linux/platform_device.h>
30 #include <linux/slab.h>
31 #include "drmP.h"
32 #include "radeon.h"
33 #include "radeon_asic.h"
34 #include "radeon_drm.h"
35 #include "rv770d.h"
36 #include "atom.h"
37 #include "avivod.h"
38
39 #define R700_PFP_UCODE_SIZE 848
40 #define R700_PM4_UCODE_SIZE 1360
41
42 static void rv770_gpu_init(struct radeon_device *rdev);
43 void rv770_fini(struct radeon_device *rdev);
44
45 void rv770_pm_misc(struct radeon_device *rdev)
46 {
47         int requested_index = rdev->pm.requested_power_state_index;
48         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
49         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
50
51         if ((voltage->type == VOLTAGE_SW) && voltage->voltage)
52                 radeon_atom_set_voltage(rdev, voltage->voltage);
53 }
54
55 /*
56  * GART
57  */
58 int rv770_pcie_gart_enable(struct radeon_device *rdev)
59 {
60         u32 tmp;
61         int r, i;
62
63         if (rdev->gart.table.vram.robj == NULL) {
64                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
65                 return -EINVAL;
66         }
67         r = radeon_gart_table_vram_pin(rdev);
68         if (r)
69                 return r;
70         radeon_gart_restore(rdev);
71         /* Setup L2 cache */
72         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
73                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
74                                 EFFECTIVE_L2_QUEUE_SIZE(7));
75         WREG32(VM_L2_CNTL2, 0);
76         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
77         /* Setup TLB control */
78         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
79                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
80                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
81                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
82         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
83         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
84         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
85         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
86         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
87         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
88         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
89         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
90         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
91         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
92         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
93                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
94         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
95                         (u32)(rdev->dummy_page.addr >> 12));
96         for (i = 1; i < 7; i++)
97                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
98
99         r600_pcie_gart_tlb_flush(rdev);
100         rdev->gart.ready = true;
101         return 0;
102 }
103
104 void rv770_pcie_gart_disable(struct radeon_device *rdev)
105 {
106         u32 tmp;
107         int i, r;
108
109         /* Disable all tables */
110         for (i = 0; i < 7; i++)
111                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
112
113         /* Setup L2 cache */
114         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
115                                 EFFECTIVE_L2_QUEUE_SIZE(7));
116         WREG32(VM_L2_CNTL2, 0);
117         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
118         /* Setup TLB control */
119         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
120         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
121         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
122         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
123         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
124         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
125         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
126         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
127         if (rdev->gart.table.vram.robj) {
128                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
129                 if (likely(r == 0)) {
130                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
131                         radeon_bo_unpin(rdev->gart.table.vram.robj);
132                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
133                 }
134         }
135 }
136
137 void rv770_pcie_gart_fini(struct radeon_device *rdev)
138 {
139         radeon_gart_fini(rdev);
140         rv770_pcie_gart_disable(rdev);
141         radeon_gart_table_vram_free(rdev);
142 }
143
144
145 void rv770_agp_enable(struct radeon_device *rdev)
146 {
147         u32 tmp;
148         int i;
149
150         /* Setup L2 cache */
151         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
152                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
153                                 EFFECTIVE_L2_QUEUE_SIZE(7));
154         WREG32(VM_L2_CNTL2, 0);
155         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
156         /* Setup TLB control */
157         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
158                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
159                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
160                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
161         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
162         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
163         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
164         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
165         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
166         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
167         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
168         for (i = 0; i < 7; i++)
169                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
170 }
171
172 static void rv770_mc_program(struct radeon_device *rdev)
173 {
174         struct rv515_mc_save save;
175         u32 tmp;
176         int i, j;
177
178         /* Initialize HDP */
179         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
180                 WREG32((0x2c14 + j), 0x00000000);
181                 WREG32((0x2c18 + j), 0x00000000);
182                 WREG32((0x2c1c + j), 0x00000000);
183                 WREG32((0x2c20 + j), 0x00000000);
184                 WREG32((0x2c24 + j), 0x00000000);
185         }
186         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
187
188         rv515_mc_stop(rdev, &save);
189         if (r600_mc_wait_for_idle(rdev)) {
190                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
191         }
192         /* Lockout access through VGA aperture*/
193         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
194         /* Update configuration */
195         if (rdev->flags & RADEON_IS_AGP) {
196                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
197                         /* VRAM before AGP */
198                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
199                                 rdev->mc.vram_start >> 12);
200                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
201                                 rdev->mc.gtt_end >> 12);
202                 } else {
203                         /* VRAM after AGP */
204                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
205                                 rdev->mc.gtt_start >> 12);
206                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
207                                 rdev->mc.vram_end >> 12);
208                 }
209         } else {
210                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
211                         rdev->mc.vram_start >> 12);
212                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
213                         rdev->mc.vram_end >> 12);
214         }
215         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
216         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
217         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
218         WREG32(MC_VM_FB_LOCATION, tmp);
219         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
220         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
221         WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
222         if (rdev->flags & RADEON_IS_AGP) {
223                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
224                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
225                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
226         } else {
227                 WREG32(MC_VM_AGP_BASE, 0);
228                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
229                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
230         }
231         if (r600_mc_wait_for_idle(rdev)) {
232                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
233         }
234         rv515_mc_resume(rdev, &save);
235         /* we need to own VRAM, so turn off the VGA renderer here
236          * to stop it overwriting our objects */
237         rv515_vga_render_disable(rdev);
238 }
239
240
241 /*
242  * CP.
243  */
244 void r700_cp_stop(struct radeon_device *rdev)
245 {
246         WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
247 }
248
249 static int rv770_cp_load_microcode(struct radeon_device *rdev)
250 {
251         const __be32 *fw_data;
252         int i;
253
254         if (!rdev->me_fw || !rdev->pfp_fw)
255                 return -EINVAL;
256
257         r700_cp_stop(rdev);
258         WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
259
260         /* Reset cp */
261         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
262         RREG32(GRBM_SOFT_RESET);
263         mdelay(15);
264         WREG32(GRBM_SOFT_RESET, 0);
265
266         fw_data = (const __be32 *)rdev->pfp_fw->data;
267         WREG32(CP_PFP_UCODE_ADDR, 0);
268         for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
269                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
270         WREG32(CP_PFP_UCODE_ADDR, 0);
271
272         fw_data = (const __be32 *)rdev->me_fw->data;
273         WREG32(CP_ME_RAM_WADDR, 0);
274         for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
275                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
276
277         WREG32(CP_PFP_UCODE_ADDR, 0);
278         WREG32(CP_ME_RAM_WADDR, 0);
279         WREG32(CP_ME_RAM_RADDR, 0);
280         return 0;
281 }
282
283 void r700_cp_fini(struct radeon_device *rdev)
284 {
285         r700_cp_stop(rdev);
286         radeon_ring_fini(rdev);
287 }
288
289 /*
290  * Core functions
291  */
292 static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
293                                              u32 num_tile_pipes,
294                                              u32 num_backends,
295                                              u32 backend_disable_mask)
296 {
297         u32 backend_map = 0;
298         u32 enabled_backends_mask;
299         u32 enabled_backends_count;
300         u32 cur_pipe;
301         u32 swizzle_pipe[R7XX_MAX_PIPES];
302         u32 cur_backend;
303         u32 i;
304         bool force_no_swizzle;
305
306         if (num_tile_pipes > R7XX_MAX_PIPES)
307                 num_tile_pipes = R7XX_MAX_PIPES;
308         if (num_tile_pipes < 1)
309                 num_tile_pipes = 1;
310         if (num_backends > R7XX_MAX_BACKENDS)
311                 num_backends = R7XX_MAX_BACKENDS;
312         if (num_backends < 1)
313                 num_backends = 1;
314
315         enabled_backends_mask = 0;
316         enabled_backends_count = 0;
317         for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
318                 if (((backend_disable_mask >> i) & 1) == 0) {
319                         enabled_backends_mask |= (1 << i);
320                         ++enabled_backends_count;
321                 }
322                 if (enabled_backends_count == num_backends)
323                         break;
324         }
325
326         if (enabled_backends_count == 0) {
327                 enabled_backends_mask = 1;
328                 enabled_backends_count = 1;
329         }
330
331         if (enabled_backends_count != num_backends)
332                 num_backends = enabled_backends_count;
333
334         switch (rdev->family) {
335         case CHIP_RV770:
336         case CHIP_RV730:
337                 force_no_swizzle = false;
338                 break;
339         case CHIP_RV710:
340         case CHIP_RV740:
341         default:
342                 force_no_swizzle = true;
343                 break;
344         }
345
346         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
347         switch (num_tile_pipes) {
348         case 1:
349                 swizzle_pipe[0] = 0;
350                 break;
351         case 2:
352                 swizzle_pipe[0] = 0;
353                 swizzle_pipe[1] = 1;
354                 break;
355         case 3:
356                 if (force_no_swizzle) {
357                         swizzle_pipe[0] = 0;
358                         swizzle_pipe[1] = 1;
359                         swizzle_pipe[2] = 2;
360                 } else {
361                         swizzle_pipe[0] = 0;
362                         swizzle_pipe[1] = 2;
363                         swizzle_pipe[2] = 1;
364                 }
365                 break;
366         case 4:
367                 if (force_no_swizzle) {
368                         swizzle_pipe[0] = 0;
369                         swizzle_pipe[1] = 1;
370                         swizzle_pipe[2] = 2;
371                         swizzle_pipe[3] = 3;
372                 } else {
373                         swizzle_pipe[0] = 0;
374                         swizzle_pipe[1] = 2;
375                         swizzle_pipe[2] = 3;
376                         swizzle_pipe[3] = 1;
377                 }
378                 break;
379         case 5:
380                 if (force_no_swizzle) {
381                         swizzle_pipe[0] = 0;
382                         swizzle_pipe[1] = 1;
383                         swizzle_pipe[2] = 2;
384                         swizzle_pipe[3] = 3;
385                         swizzle_pipe[4] = 4;
386                 } else {
387                         swizzle_pipe[0] = 0;
388                         swizzle_pipe[1] = 2;
389                         swizzle_pipe[2] = 4;
390                         swizzle_pipe[3] = 1;
391                         swizzle_pipe[4] = 3;
392                 }
393                 break;
394         case 6:
395                 if (force_no_swizzle) {
396                         swizzle_pipe[0] = 0;
397                         swizzle_pipe[1] = 1;
398                         swizzle_pipe[2] = 2;
399                         swizzle_pipe[3] = 3;
400                         swizzle_pipe[4] = 4;
401                         swizzle_pipe[5] = 5;
402                 } else {
403                         swizzle_pipe[0] = 0;
404                         swizzle_pipe[1] = 2;
405                         swizzle_pipe[2] = 4;
406                         swizzle_pipe[3] = 5;
407                         swizzle_pipe[4] = 3;
408                         swizzle_pipe[5] = 1;
409                 }
410                 break;
411         case 7:
412                 if (force_no_swizzle) {
413                         swizzle_pipe[0] = 0;
414                         swizzle_pipe[1] = 1;
415                         swizzle_pipe[2] = 2;
416                         swizzle_pipe[3] = 3;
417                         swizzle_pipe[4] = 4;
418                         swizzle_pipe[5] = 5;
419                         swizzle_pipe[6] = 6;
420                 } else {
421                         swizzle_pipe[0] = 0;
422                         swizzle_pipe[1] = 2;
423                         swizzle_pipe[2] = 4;
424                         swizzle_pipe[3] = 6;
425                         swizzle_pipe[4] = 3;
426                         swizzle_pipe[5] = 1;
427                         swizzle_pipe[6] = 5;
428                 }
429                 break;
430         case 8:
431                 if (force_no_swizzle) {
432                         swizzle_pipe[0] = 0;
433                         swizzle_pipe[1] = 1;
434                         swizzle_pipe[2] = 2;
435                         swizzle_pipe[3] = 3;
436                         swizzle_pipe[4] = 4;
437                         swizzle_pipe[5] = 5;
438                         swizzle_pipe[6] = 6;
439                         swizzle_pipe[7] = 7;
440                 } else {
441                         swizzle_pipe[0] = 0;
442                         swizzle_pipe[1] = 2;
443                         swizzle_pipe[2] = 4;
444                         swizzle_pipe[3] = 6;
445                         swizzle_pipe[4] = 3;
446                         swizzle_pipe[5] = 1;
447                         swizzle_pipe[6] = 7;
448                         swizzle_pipe[7] = 5;
449                 }
450                 break;
451         }
452
453         cur_backend = 0;
454         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
455                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
456                         cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
457
458                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
459
460                 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
461         }
462
463         return backend_map;
464 }
465
466 static void rv770_gpu_init(struct radeon_device *rdev)
467 {
468         int i, j, num_qd_pipes;
469         u32 ta_aux_cntl;
470         u32 sx_debug_1;
471         u32 smx_dc_ctl0;
472         u32 db_debug3;
473         u32 num_gs_verts_per_thread;
474         u32 vgt_gs_per_es;
475         u32 gs_prim_buffer_depth = 0;
476         u32 sq_ms_fifo_sizes;
477         u32 sq_config;
478         u32 sq_thread_resource_mgmt;
479         u32 hdp_host_path_cntl;
480         u32 sq_dyn_gpr_size_simd_ab_0;
481         u32 backend_map;
482         u32 gb_tiling_config = 0;
483         u32 cc_rb_backend_disable = 0;
484         u32 cc_gc_shader_pipe_config = 0;
485         u32 mc_arb_ramcfg;
486         u32 db_debug4;
487
488         /* setup chip specs */
489         switch (rdev->family) {
490         case CHIP_RV770:
491                 rdev->config.rv770.max_pipes = 4;
492                 rdev->config.rv770.max_tile_pipes = 8;
493                 rdev->config.rv770.max_simds = 10;
494                 rdev->config.rv770.max_backends = 4;
495                 rdev->config.rv770.max_gprs = 256;
496                 rdev->config.rv770.max_threads = 248;
497                 rdev->config.rv770.max_stack_entries = 512;
498                 rdev->config.rv770.max_hw_contexts = 8;
499                 rdev->config.rv770.max_gs_threads = 16 * 2;
500                 rdev->config.rv770.sx_max_export_size = 128;
501                 rdev->config.rv770.sx_max_export_pos_size = 16;
502                 rdev->config.rv770.sx_max_export_smx_size = 112;
503                 rdev->config.rv770.sq_num_cf_insts = 2;
504
505                 rdev->config.rv770.sx_num_of_sets = 7;
506                 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
507                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
508                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
509                 break;
510         case CHIP_RV730:
511                 rdev->config.rv770.max_pipes = 2;
512                 rdev->config.rv770.max_tile_pipes = 4;
513                 rdev->config.rv770.max_simds = 8;
514                 rdev->config.rv770.max_backends = 2;
515                 rdev->config.rv770.max_gprs = 128;
516                 rdev->config.rv770.max_threads = 248;
517                 rdev->config.rv770.max_stack_entries = 256;
518                 rdev->config.rv770.max_hw_contexts = 8;
519                 rdev->config.rv770.max_gs_threads = 16 * 2;
520                 rdev->config.rv770.sx_max_export_size = 256;
521                 rdev->config.rv770.sx_max_export_pos_size = 32;
522                 rdev->config.rv770.sx_max_export_smx_size = 224;
523                 rdev->config.rv770.sq_num_cf_insts = 2;
524
525                 rdev->config.rv770.sx_num_of_sets = 7;
526                 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
527                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
528                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
529                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
530                         rdev->config.rv770.sx_max_export_pos_size -= 16;
531                         rdev->config.rv770.sx_max_export_smx_size += 16;
532                 }
533                 break;
534         case CHIP_RV710:
535                 rdev->config.rv770.max_pipes = 2;
536                 rdev->config.rv770.max_tile_pipes = 2;
537                 rdev->config.rv770.max_simds = 2;
538                 rdev->config.rv770.max_backends = 1;
539                 rdev->config.rv770.max_gprs = 256;
540                 rdev->config.rv770.max_threads = 192;
541                 rdev->config.rv770.max_stack_entries = 256;
542                 rdev->config.rv770.max_hw_contexts = 4;
543                 rdev->config.rv770.max_gs_threads = 8 * 2;
544                 rdev->config.rv770.sx_max_export_size = 128;
545                 rdev->config.rv770.sx_max_export_pos_size = 16;
546                 rdev->config.rv770.sx_max_export_smx_size = 112;
547                 rdev->config.rv770.sq_num_cf_insts = 1;
548
549                 rdev->config.rv770.sx_num_of_sets = 7;
550                 rdev->config.rv770.sc_prim_fifo_size = 0x40;
551                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
552                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
553                 break;
554         case CHIP_RV740:
555                 rdev->config.rv770.max_pipes = 4;
556                 rdev->config.rv770.max_tile_pipes = 4;
557                 rdev->config.rv770.max_simds = 8;
558                 rdev->config.rv770.max_backends = 4;
559                 rdev->config.rv770.max_gprs = 256;
560                 rdev->config.rv770.max_threads = 248;
561                 rdev->config.rv770.max_stack_entries = 512;
562                 rdev->config.rv770.max_hw_contexts = 8;
563                 rdev->config.rv770.max_gs_threads = 16 * 2;
564                 rdev->config.rv770.sx_max_export_size = 256;
565                 rdev->config.rv770.sx_max_export_pos_size = 32;
566                 rdev->config.rv770.sx_max_export_smx_size = 224;
567                 rdev->config.rv770.sq_num_cf_insts = 2;
568
569                 rdev->config.rv770.sx_num_of_sets = 7;
570                 rdev->config.rv770.sc_prim_fifo_size = 0x100;
571                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
572                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
573
574                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
575                         rdev->config.rv770.sx_max_export_pos_size -= 16;
576                         rdev->config.rv770.sx_max_export_smx_size += 16;
577                 }
578                 break;
579         default:
580                 break;
581         }
582
583         /* Initialize HDP */
584         j = 0;
585         for (i = 0; i < 32; i++) {
586                 WREG32((0x2c14 + j), 0x00000000);
587                 WREG32((0x2c18 + j), 0x00000000);
588                 WREG32((0x2c1c + j), 0x00000000);
589                 WREG32((0x2c20 + j), 0x00000000);
590                 WREG32((0x2c24 + j), 0x00000000);
591                 j += 0x18;
592         }
593
594         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
595
596         /* setup tiling, simd, pipe config */
597         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
598
599         switch (rdev->config.rv770.max_tile_pipes) {
600         case 1:
601         default:
602                 gb_tiling_config |= PIPE_TILING(0);
603                 break;
604         case 2:
605                 gb_tiling_config |= PIPE_TILING(1);
606                 break;
607         case 4:
608                 gb_tiling_config |= PIPE_TILING(2);
609                 break;
610         case 8:
611                 gb_tiling_config |= PIPE_TILING(3);
612                 break;
613         }
614         rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
615
616         if (rdev->family == CHIP_RV770)
617                 gb_tiling_config |= BANK_TILING(1);
618         else
619                 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
620         rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
621
622         gb_tiling_config |= GROUP_SIZE(0);
623         rdev->config.rv770.tiling_group_size = 256;
624
625         if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
626                 gb_tiling_config |= ROW_TILING(3);
627                 gb_tiling_config |= SAMPLE_SPLIT(3);
628         } else {
629                 gb_tiling_config |=
630                         ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
631                 gb_tiling_config |=
632                         SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
633         }
634
635         gb_tiling_config |= BANK_SWAPS(1);
636
637         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
638         cc_rb_backend_disable |=
639                 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
640
641         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
642         cc_gc_shader_pipe_config |=
643                 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
644         cc_gc_shader_pipe_config |=
645                 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
646
647         if (rdev->family == CHIP_RV740)
648                 backend_map = 0x28;
649         else
650                 backend_map = r700_get_tile_pipe_to_backend_map(rdev,
651                                                                 rdev->config.rv770.max_tile_pipes,
652                                                                 (R7XX_MAX_BACKENDS -
653                                                                  r600_count_pipe_bits((cc_rb_backend_disable &
654                                                                                        R7XX_MAX_BACKENDS_MASK) >> 16)),
655                                                                 (cc_rb_backend_disable >> 16));
656         gb_tiling_config |= BACKEND_MAP(backend_map);
657
658
659         WREG32(GB_TILING_CONFIG, gb_tiling_config);
660         WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
661         WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
662
663         WREG32(CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
664         WREG32(CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
665         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
666         WREG32(CC_SYS_RB_BACKEND_DISABLE,  cc_rb_backend_disable);
667
668         WREG32(CGTS_SYS_TCC_DISABLE, 0);
669         WREG32(CGTS_TCC_DISABLE, 0);
670         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
671         WREG32(CGTS_USER_TCC_DISABLE, 0);
672
673         num_qd_pipes =
674                 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
675         WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
676         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
677
678         /* set HW defaults for 3D engine */
679         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
680                                      ROQ_IB2_START(0x2b)));
681
682         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
683
684         ta_aux_cntl = RREG32(TA_CNTL_AUX);
685         WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
686
687         sx_debug_1 = RREG32(SX_DEBUG_1);
688         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
689         WREG32(SX_DEBUG_1, sx_debug_1);
690
691         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
692         smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
693         smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
694         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
695
696         if (rdev->family != CHIP_RV740)
697                 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
698                                        GS_FLUSH_CTL(4) |
699                                        ACK_FLUSH_CTL(3) |
700                                        SYNC_FLUSH_CTL));
701
702         db_debug3 = RREG32(DB_DEBUG3);
703         db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
704         switch (rdev->family) {
705         case CHIP_RV770:
706         case CHIP_RV740:
707                 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
708                 break;
709         case CHIP_RV710:
710         case CHIP_RV730:
711         default:
712                 db_debug3 |= DB_CLK_OFF_DELAY(2);
713                 break;
714         }
715         WREG32(DB_DEBUG3, db_debug3);
716
717         if (rdev->family != CHIP_RV770) {
718                 db_debug4 = RREG32(DB_DEBUG4);
719                 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
720                 WREG32(DB_DEBUG4, db_debug4);
721         }
722
723         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
724                                         POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
725                                         SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
726
727         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
728                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
729                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
730
731         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
732
733         WREG32(VGT_NUM_INSTANCES, 1);
734
735         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
736
737         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
738
739         WREG32(CP_PERFMON_CNTL, 0);
740
741         sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
742                             DONE_FIFO_HIWATER(0xe0) |
743                             ALU_UPDATE_FIFO_HIWATER(0x8));
744         switch (rdev->family) {
745         case CHIP_RV770:
746         case CHIP_RV730:
747         case CHIP_RV710:
748                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
749                 break;
750         case CHIP_RV740:
751         default:
752                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
753                 break;
754         }
755         WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
756
757         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
758          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
759          */
760         sq_config = RREG32(SQ_CONFIG);
761         sq_config &= ~(PS_PRIO(3) |
762                        VS_PRIO(3) |
763                        GS_PRIO(3) |
764                        ES_PRIO(3));
765         sq_config |= (DX9_CONSTS |
766                       VC_ENABLE |
767                       EXPORT_SRC_C |
768                       PS_PRIO(0) |
769                       VS_PRIO(1) |
770                       GS_PRIO(2) |
771                       ES_PRIO(3));
772         if (rdev->family == CHIP_RV710)
773                 /* no vertex cache */
774                 sq_config &= ~VC_ENABLE;
775
776         WREG32(SQ_CONFIG, sq_config);
777
778         WREG32(SQ_GPR_RESOURCE_MGMT_1,  (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
779                                          NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
780                                          NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
781
782         WREG32(SQ_GPR_RESOURCE_MGMT_2,  (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
783                                          NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
784
785         sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
786                                    NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
787                                    NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
788         if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
789                 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
790         else
791                 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
792         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
793
794         WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
795                                                      NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
796
797         WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
798                                                      NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
799
800         sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
801                                      SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
802                                      SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
803                                      SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
804
805         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
806         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
807         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
808         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
809         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
810         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
811         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
812         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
813
814         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
815                                           FORCE_EOV_MAX_REZ_CNT(255)));
816
817         if (rdev->family == CHIP_RV710)
818                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
819                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
820         else
821                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
822                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
823
824         switch (rdev->family) {
825         case CHIP_RV770:
826         case CHIP_RV730:
827         case CHIP_RV740:
828                 gs_prim_buffer_depth = 384;
829                 break;
830         case CHIP_RV710:
831                 gs_prim_buffer_depth = 128;
832                 break;
833         default:
834                 break;
835         }
836
837         num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
838         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
839         /* Max value for this is 256 */
840         if (vgt_gs_per_es > 256)
841                 vgt_gs_per_es = 256;
842
843         WREG32(VGT_ES_PER_GS, 128);
844         WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
845         WREG32(VGT_GS_PER_VS, 2);
846
847         /* more default values. 2D/3D driver should adjust as needed */
848         WREG32(VGT_GS_VERTEX_REUSE, 16);
849         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
850         WREG32(VGT_STRMOUT_EN, 0);
851         WREG32(SX_MISC, 0);
852         WREG32(PA_SC_MODE_CNTL, 0);
853         WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
854         WREG32(PA_SC_AA_CONFIG, 0);
855         WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
856         WREG32(PA_SC_LINE_STIPPLE, 0);
857         WREG32(SPI_INPUT_Z, 0);
858         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
859         WREG32(CB_COLOR7_FRAG, 0);
860
861         /* clear render buffer base addresses */
862         WREG32(CB_COLOR0_BASE, 0);
863         WREG32(CB_COLOR1_BASE, 0);
864         WREG32(CB_COLOR2_BASE, 0);
865         WREG32(CB_COLOR3_BASE, 0);
866         WREG32(CB_COLOR4_BASE, 0);
867         WREG32(CB_COLOR5_BASE, 0);
868         WREG32(CB_COLOR6_BASE, 0);
869         WREG32(CB_COLOR7_BASE, 0);
870
871         WREG32(TCP_CNTL, 0);
872
873         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
874         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
875
876         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
877
878         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
879                                           NUM_CLIP_SEQ(3)));
880
881 }
882
883 int rv770_mc_init(struct radeon_device *rdev)
884 {
885         u32 tmp;
886         int chansize, numchan;
887
888         /* Get VRAM informations */
889         rdev->mc.vram_is_ddr = true;
890         tmp = RREG32(MC_ARB_RAMCFG);
891         if (tmp & CHANSIZE_OVERRIDE) {
892                 chansize = 16;
893         } else if (tmp & CHANSIZE_MASK) {
894                 chansize = 64;
895         } else {
896                 chansize = 32;
897         }
898         tmp = RREG32(MC_SHARED_CHMAP);
899         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
900         case 0:
901         default:
902                 numchan = 1;
903                 break;
904         case 1:
905                 numchan = 2;
906                 break;
907         case 2:
908                 numchan = 4;
909                 break;
910         case 3:
911                 numchan = 8;
912                 break;
913         }
914         rdev->mc.vram_width = numchan * chansize;
915         /* Could aper size report 0 ? */
916         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
917         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
918         /* Setup GPU memory space */
919         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
920         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
921         rdev->mc.visible_vram_size = rdev->mc.aper_size;
922         r600_vram_gtt_location(rdev, &rdev->mc);
923         radeon_update_bandwidth_info(rdev);
924
925         return 0;
926 }
927
928 static int rv770_startup(struct radeon_device *rdev)
929 {
930         int r;
931
932         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
933                 r = r600_init_microcode(rdev);
934                 if (r) {
935                         DRM_ERROR("Failed to load firmware!\n");
936                         return r;
937                 }
938         }
939
940         rv770_mc_program(rdev);
941         if (rdev->flags & RADEON_IS_AGP) {
942                 rv770_agp_enable(rdev);
943         } else {
944                 r = rv770_pcie_gart_enable(rdev);
945                 if (r)
946                         return r;
947         }
948         rv770_gpu_init(rdev);
949         r = r600_blit_init(rdev);
950         if (r) {
951                 r600_blit_fini(rdev);
952                 rdev->asic->copy = NULL;
953                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
954         }
955         /* pin copy shader into vram */
956         if (rdev->r600_blit.shader_obj) {
957                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
958                 if (unlikely(r != 0))
959                         return r;
960                 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
961                                 &rdev->r600_blit.shader_gpu_addr);
962                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
963                 if (r) {
964                         DRM_ERROR("failed to pin blit object %d\n", r);
965                         return r;
966                 }
967         }
968         /* Enable IRQ */
969         r = r600_irq_init(rdev);
970         if (r) {
971                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
972                 radeon_irq_kms_fini(rdev);
973                 return r;
974         }
975         r600_irq_set(rdev);
976
977         r = radeon_ring_init(rdev, rdev->cp.ring_size);
978         if (r)
979                 return r;
980         r = rv770_cp_load_microcode(rdev);
981         if (r)
982                 return r;
983         r = r600_cp_resume(rdev);
984         if (r)
985                 return r;
986         /* write back buffer are not vital so don't worry about failure */
987         r600_wb_enable(rdev);
988         return 0;
989 }
990
991 int rv770_resume(struct radeon_device *rdev)
992 {
993         int r;
994
995         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
996          * posting will perform necessary task to bring back GPU into good
997          * shape.
998          */
999         /* post card */
1000         atom_asic_init(rdev->mode_info.atom_context);
1001         /* Initialize clocks */
1002         r = radeon_clocks_init(rdev);
1003         if (r) {
1004                 return r;
1005         }
1006
1007         r = rv770_startup(rdev);
1008         if (r) {
1009                 DRM_ERROR("r600 startup failed on resume\n");
1010                 return r;
1011         }
1012
1013         r = r600_ib_test(rdev);
1014         if (r) {
1015                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1016                 return r;
1017         }
1018
1019         r = r600_audio_init(rdev);
1020         if (r) {
1021                 dev_err(rdev->dev, "radeon: audio init failed\n");
1022                 return r;
1023         }
1024
1025         return r;
1026
1027 }
1028
1029 int rv770_suspend(struct radeon_device *rdev)
1030 {
1031         int r;
1032
1033         r600_audio_fini(rdev);
1034         /* FIXME: we should wait for ring to be empty */
1035         r700_cp_stop(rdev);
1036         rdev->cp.ready = false;
1037         r600_irq_suspend(rdev);
1038         r600_wb_disable(rdev);
1039         rv770_pcie_gart_disable(rdev);
1040         /* unpin shaders bo */
1041         if (rdev->r600_blit.shader_obj) {
1042                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1043                 if (likely(r == 0)) {
1044                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
1045                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1046                 }
1047         }
1048         return 0;
1049 }
1050
1051 /* Plan is to move initialization in that function and use
1052  * helper function so that radeon_device_init pretty much
1053  * do nothing more than calling asic specific function. This
1054  * should also allow to remove a bunch of callback function
1055  * like vram_info.
1056  */
1057 int rv770_init(struct radeon_device *rdev)
1058 {
1059         int r;
1060
1061         r = radeon_dummy_page_init(rdev);
1062         if (r)
1063                 return r;
1064         /* This don't do much */
1065         r = radeon_gem_init(rdev);
1066         if (r)
1067                 return r;
1068         /* Read BIOS */
1069         if (!radeon_get_bios(rdev)) {
1070                 if (ASIC_IS_AVIVO(rdev))
1071                         return -EINVAL;
1072         }
1073         /* Must be an ATOMBIOS */
1074         if (!rdev->is_atom_bios) {
1075                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
1076                 return -EINVAL;
1077         }
1078         r = radeon_atombios_init(rdev);
1079         if (r)
1080                 return r;
1081         /* Post card if necessary */
1082         if (!r600_card_posted(rdev)) {
1083                 if (!rdev->bios) {
1084                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1085                         return -EINVAL;
1086                 }
1087                 DRM_INFO("GPU not posted. posting now...\n");
1088                 atom_asic_init(rdev->mode_info.atom_context);
1089         }
1090         /* Initialize scratch registers */
1091         r600_scratch_init(rdev);
1092         /* Initialize surface registers */
1093         radeon_surface_init(rdev);
1094         /* Initialize clocks */
1095         radeon_get_clock_info(rdev->ddev);
1096         r = radeon_clocks_init(rdev);
1097         if (r)
1098                 return r;
1099         /* Fence driver */
1100         r = radeon_fence_driver_init(rdev);
1101         if (r)
1102                 return r;
1103         /* initialize AGP */
1104         if (rdev->flags & RADEON_IS_AGP) {
1105                 r = radeon_agp_init(rdev);
1106                 if (r)
1107                         radeon_agp_disable(rdev);
1108         }
1109         r = rv770_mc_init(rdev);
1110         if (r)
1111                 return r;
1112         /* Memory manager */
1113         r = radeon_bo_init(rdev);
1114         if (r)
1115                 return r;
1116
1117         r = radeon_irq_kms_init(rdev);
1118         if (r)
1119                 return r;
1120
1121         rdev->cp.ring_obj = NULL;
1122         r600_ring_init(rdev, 1024 * 1024);
1123
1124         rdev->ih.ring_obj = NULL;
1125         r600_ih_ring_init(rdev, 64 * 1024);
1126
1127         r = r600_pcie_gart_init(rdev);
1128         if (r)
1129                 return r;
1130
1131         rdev->accel_working = true;
1132         r = rv770_startup(rdev);
1133         if (r) {
1134                 dev_err(rdev->dev, "disabling GPU acceleration\n");
1135                 r700_cp_fini(rdev);
1136                 r600_wb_fini(rdev);
1137                 r600_irq_fini(rdev);
1138                 radeon_irq_kms_fini(rdev);
1139                 rv770_pcie_gart_fini(rdev);
1140                 rdev->accel_working = false;
1141         }
1142         if (rdev->accel_working) {
1143                 r = radeon_ib_pool_init(rdev);
1144                 if (r) {
1145                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1146                         rdev->accel_working = false;
1147                 } else {
1148                         r = r600_ib_test(rdev);
1149                         if (r) {
1150                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1151                                 rdev->accel_working = false;
1152                         }
1153                 }
1154         }
1155
1156         r = r600_audio_init(rdev);
1157         if (r) {
1158                 dev_err(rdev->dev, "radeon: audio init failed\n");
1159                 return r;
1160         }
1161
1162         return 0;
1163 }
1164
1165 void rv770_fini(struct radeon_device *rdev)
1166 {
1167         r600_blit_fini(rdev);
1168         r700_cp_fini(rdev);
1169         r600_wb_fini(rdev);
1170         r600_irq_fini(rdev);
1171         radeon_irq_kms_fini(rdev);
1172         rv770_pcie_gart_fini(rdev);
1173         radeon_gem_fini(rdev);
1174         radeon_fence_driver_fini(rdev);
1175         radeon_clocks_fini(rdev);
1176         radeon_agp_fini(rdev);
1177         radeon_bo_fini(rdev);
1178         radeon_atombios_fini(rdev);
1179         kfree(rdev->bios);
1180         rdev->bios = NULL;
1181         radeon_dummy_page_fini(rdev);
1182 }