a65e17ec1c08cd7dd75b512b4e076db9c10b3bcc
[linux-2.6.git] / drivers / gpu / drm / radeon / rv515d.h
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #ifndef __RV515D_H__
29 #define __RV515D_H__
30
31 /*
32  * RV515 registers
33  */
34 #define PCIE_INDEX                      0x0030
35 #define PCIE_DATA                       0x0034
36 #define MC_IND_INDEX                    0x0070
37 #define         MC_IND_WR_EN                            (1 << 24)
38 #define MC_IND_DATA                     0x0074
39 #define RBBM_SOFT_RESET                 0x00F0
40 #define CONFIG_MEMSIZE                  0x00F8
41 #define HDP_FB_LOCATION                 0x0134
42 #define CP_CSQ_CNTL                     0x0740
43 #define CP_CSQ_MODE                     0x0744
44 #define CP_CSQ_ADDR                     0x07F0
45 #define CP_CSQ_DATA                     0x07F4
46 #define CP_CSQ_STAT                     0x07F8
47 #define CP_CSQ2_STAT                    0x07FC
48 #define RBBM_STATUS                     0x0E40
49 #define DST_PIPE_CONFIG                 0x170C
50 #define WAIT_UNTIL                      0x1720
51 #define         WAIT_2D_IDLE                            (1 << 14)
52 #define         WAIT_3D_IDLE                            (1 << 15)
53 #define         WAIT_2D_IDLECLEAN                       (1 << 16)
54 #define         WAIT_3D_IDLECLEAN                       (1 << 17)
55 #define ISYNC_CNTL                      0x1724
56 #define         ISYNC_ANY2D_IDLE3D                      (1 << 0)
57 #define         ISYNC_ANY3D_IDLE2D                      (1 << 1)
58 #define         ISYNC_TRIG2D_IDLE3D                     (1 << 2)
59 #define         ISYNC_TRIG3D_IDLE2D                     (1 << 3)
60 #define         ISYNC_WAIT_IDLEGUI                      (1 << 4)
61 #define         ISYNC_CPSCRATCH_IDLEGUI                 (1 << 5)
62 #define VAP_INDEX_OFFSET                0x208C
63 #define VAP_PVS_STATE_FLUSH_REG         0x2284
64 #define GB_ENABLE                       0x4008
65 #define GB_MSPOS0                       0x4010
66 #define         MS_X0_SHIFT                             0
67 #define         MS_Y0_SHIFT                             4
68 #define         MS_X1_SHIFT                             8
69 #define         MS_Y1_SHIFT                             12
70 #define         MS_X2_SHIFT                             16
71 #define         MS_Y2_SHIFT                             20
72 #define         MSBD0_Y_SHIFT                           24
73 #define         MSBD0_X_SHIFT                           28
74 #define GB_MSPOS1                       0x4014
75 #define         MS_X3_SHIFT                             0
76 #define         MS_Y3_SHIFT                             4
77 #define         MS_X4_SHIFT                             8
78 #define         MS_Y4_SHIFT                             12
79 #define         MS_X5_SHIFT                             16
80 #define         MS_Y5_SHIFT                             20
81 #define         MSBD1_SHIFT                             24
82 #define GB_TILE_CONFIG                  0x4018
83 #define         ENABLE_TILING                           (1 << 0)
84 #define         PIPE_COUNT_MASK                         0x0000000E
85 #define         PIPE_COUNT_SHIFT                        1
86 #define         TILE_SIZE_8                             (0 << 4)
87 #define         TILE_SIZE_16                            (1 << 4)
88 #define         TILE_SIZE_32                            (2 << 4)
89 #define         SUBPIXEL_1_12                           (0 << 16)
90 #define         SUBPIXEL_1_16                           (1 << 16)
91 #define GB_SELECT                       0x401C
92 #define GB_AA_CONFIG                    0x4020
93 #define GB_PIPE_SELECT                  0x402C
94 #define GA_ENHANCE                      0x4274
95 #define         GA_DEADLOCK_CNTL                        (1 << 0)
96 #define         GA_FASTSYNC_CNTL                        (1 << 1)
97 #define GA_POLY_MODE                    0x4288
98 #define         FRONT_PTYPE_POINT                       (0 << 4)
99 #define         FRONT_PTYPE_LINE                        (1 << 4)
100 #define         FRONT_PTYPE_TRIANGE                     (2 << 4)
101 #define         BACK_PTYPE_POINT                        (0 << 7)
102 #define         BACK_PTYPE_LINE                         (1 << 7)
103 #define         BACK_PTYPE_TRIANGE                      (2 << 7)
104 #define GA_ROUND_MODE                   0x428C
105 #define         GEOMETRY_ROUND_TRUNC                    (0 << 0)
106 #define         GEOMETRY_ROUND_NEAREST                  (1 << 0)
107 #define         COLOR_ROUND_TRUNC                       (0 << 2)
108 #define         COLOR_ROUND_NEAREST                     (1 << 2)
109 #define SU_REG_DEST                     0x42C8
110 #define RB3D_DSTCACHE_CTLSTAT           0x4E4C
111 #define         RB3D_DC_FLUSH                           (2 << 0)
112 #define         RB3D_DC_FREE                            (2 << 2)
113 #define         RB3D_DC_FINISH                          (1 << 4)
114 #define ZB_ZCACHE_CTLSTAT               0x4F18
115 #define         ZC_FLUSH                                (1 << 0)
116 #define         ZC_FREE                                 (1 << 1)
117 #define DC_LB_MEMORY_SPLIT              0x6520
118 #define         DC_LB_MEMORY_SPLIT_MASK                 0x00000003
119 #define         DC_LB_MEMORY_SPLIT_SHIFT                0
120 #define         DC_LB_MEMORY_SPLIT_D1HALF_D2HALF        0
121 #define         DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q          1
122 #define         DC_LB_MEMORY_SPLIT_D1_ONLY              2
123 #define         DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q          3
124 #define         DC_LB_MEMORY_SPLIT_SHIFT_MODE           (1 << 2)
125 #define         DC_LB_DISP1_END_ADR_SHIFT               4
126 #define         DC_LB_DISP1_END_ADR_MASK                0x00007FF0
127 #define D1MODE_PRIORITY_A_CNT           0x6548
128 #define         MODE_PRIORITY_MARK_MASK                 0x00007FFF
129 #define         MODE_PRIORITY_OFF                       (1 << 16)
130 #define         MODE_PRIORITY_ALWAYS_ON                 (1 << 20)
131 #define         MODE_PRIORITY_FORCE_MASK                (1 << 24)
132 #define D1MODE_PRIORITY_B_CNT           0x654C
133 #define LB_MAX_REQ_OUTSTANDING          0x6D58
134 #define         LB_D1_MAX_REQ_OUTSTANDING_MASK          0x0000000F
135 #define         LB_D1_MAX_REQ_OUTSTANDING_SHIFT         0
136 #define         LB_D2_MAX_REQ_OUTSTANDING_MASK          0x000F0000
137 #define         LB_D2_MAX_REQ_OUTSTANDING_SHIFT         16
138 #define D2MODE_PRIORITY_A_CNT           0x6D48
139 #define D2MODE_PRIORITY_B_CNT           0x6D4C
140
141 /* ix[MC] registers */
142 #define MC_FB_LOCATION                  0x01
143 #define         MC_FB_START_MASK                        0x0000FFFF
144 #define         MC_FB_START_SHIFT                       0
145 #define         MC_FB_TOP_MASK                          0xFFFF0000
146 #define         MC_FB_TOP_SHIFT                         16
147 #define MC_AGP_LOCATION                 0x02
148 #define         MC_AGP_START_MASK                       0x0000FFFF
149 #define         MC_AGP_START_SHIFT                      0
150 #define         MC_AGP_TOP_MASK                         0xFFFF0000
151 #define         MC_AGP_TOP_SHIFT                        16
152 #define MC_AGP_BASE                     0x03
153 #define MC_AGP_BASE_2                   0x04
154 #define MC_CNTL                         0x5
155 #define         MEM_NUM_CHANNELS_MASK                   0x00000003
156 #define MC_STATUS                       0x08
157 #define         MC_STATUS_IDLE                          (1 << 4)
158 #define MC_MISC_LAT_TIMER               0x09
159 #define         MC_CPR_INIT_LAT_MASK                    0x0000000F
160 #define         MC_VF_INIT_LAT_MASK                     0x000000F0
161 #define         MC_DISP0R_INIT_LAT_MASK                 0x00000F00
162 #define         MC_DISP0R_INIT_LAT_SHIFT                8
163 #define         MC_DISP1R_INIT_LAT_MASK                 0x0000F000
164 #define         MC_DISP1R_INIT_LAT_SHIFT                12
165 #define         MC_FIXED_INIT_LAT_MASK                  0x000F0000
166 #define         MC_E2R_INIT_LAT_MASK                    0x00F00000
167 #define         SAME_PAGE_PRIO_MASK                     0x0F000000
168 #define         MC_GLOBW_INIT_LAT_MASK                  0xF0000000
169
170
171 /*
172  * PM4 packet
173  */
174 #define CP_PACKET0                      0x00000000
175 #define         PACKET0_BASE_INDEX_SHIFT        0
176 #define         PACKET0_BASE_INDEX_MASK         (0x1ffff << 0)
177 #define         PACKET0_COUNT_SHIFT             16
178 #define         PACKET0_COUNT_MASK              (0x3fff << 16)
179 #define CP_PACKET1                      0x40000000
180 #define CP_PACKET2                      0x80000000
181 #define         PACKET2_PAD_SHIFT               0
182 #define         PACKET2_PAD_MASK                (0x3fffffff << 0)
183 #define CP_PACKET3                      0xC0000000
184 #define         PACKET3_IT_OPCODE_SHIFT         8
185 #define         PACKET3_IT_OPCODE_MASK          (0xff << 8)
186 #define         PACKET3_COUNT_SHIFT             16
187 #define         PACKET3_COUNT_MASK              (0x3fff << 16)
188 /* PACKET3 op code */
189 #define         PACKET3_NOP                     0x10
190 #define         PACKET3_3D_DRAW_VBUF            0x28
191 #define         PACKET3_3D_DRAW_IMMD            0x29
192 #define         PACKET3_3D_DRAW_INDX            0x2A
193 #define         PACKET3_3D_LOAD_VBPNTR          0x2F
194 #define         PACKET3_INDX_BUFFER             0x33
195 #define         PACKET3_3D_DRAW_VBUF_2          0x34
196 #define         PACKET3_3D_DRAW_IMMD_2          0x35
197 #define         PACKET3_3D_DRAW_INDX_2          0x36
198 #define         PACKET3_BITBLT_MULTI            0x9B
199
200 #define PACKET0(reg, n) (CP_PACKET0 |                                   \
201                          REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) |      \
202                          REG_SET(PACKET0_COUNT, (n)))
203 #define PACKET2(v)      (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
204 #define PACKET3(op, n)  (CP_PACKET3 |                                   \
205                          REG_SET(PACKET3_IT_OPCODE, (op)) |             \
206                          REG_SET(PACKET3_COUNT, (n)))
207
208 #define PACKET_TYPE0    0
209 #define PACKET_TYPE1    1
210 #define PACKET_TYPE2    2
211 #define PACKET_TYPE3    3
212
213 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
214 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
215 #define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
216 #define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
217 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
218
219 #endif
220