d94291add6db83ed20b7525a4d3fe2ef1b599669
[linux-2.6.git] / drivers / gpu / drm / radeon / rv515.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/seq_file.h>
29 #include "drmP.h"
30 #include "rv515d.h"
31 #include "radeon.h"
32 #include "radeon_asic.h"
33 #include "atom.h"
34 #include "rv515_reg_safe.h"
35
36 /* This files gather functions specifics to: rv515 */
37 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
38 int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
39 void rv515_gpu_init(struct radeon_device *rdev);
40 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
41
42 void rv515_debugfs(struct radeon_device *rdev)
43 {
44         if (r100_debugfs_rbbm_init(rdev)) {
45                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
46         }
47         if (rv515_debugfs_pipes_info_init(rdev)) {
48                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
49         }
50         if (rv515_debugfs_ga_info_init(rdev)) {
51                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
52         }
53 }
54
55 void rv515_ring_start(struct radeon_device *rdev)
56 {
57         int r;
58
59         r = radeon_ring_lock(rdev, 64);
60         if (r) {
61                 return;
62         }
63         radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0));
64         radeon_ring_write(rdev,
65                           ISYNC_ANY2D_IDLE3D |
66                           ISYNC_ANY3D_IDLE2D |
67                           ISYNC_WAIT_IDLEGUI |
68                           ISYNC_CPSCRATCH_IDLEGUI);
69         radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
70         radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
71         radeon_ring_write(rdev, PACKET0(0x170C, 0));
72         radeon_ring_write(rdev, 1 << 31);
73         radeon_ring_write(rdev, PACKET0(GB_SELECT, 0));
74         radeon_ring_write(rdev, 0);
75         radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0));
76         radeon_ring_write(rdev, 0);
77         radeon_ring_write(rdev, PACKET0(0x42C8, 0));
78         radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
79         radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0));
80         radeon_ring_write(rdev, 0);
81         radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
82         radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
83         radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
84         radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
85         radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
86         radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
87         radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0));
88         radeon_ring_write(rdev, 0);
89         radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
90         radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
91         radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
92         radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
93         radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0));
94         radeon_ring_write(rdev,
95                           ((6 << MS_X0_SHIFT) |
96                            (6 << MS_Y0_SHIFT) |
97                            (6 << MS_X1_SHIFT) |
98                            (6 << MS_Y1_SHIFT) |
99                            (6 << MS_X2_SHIFT) |
100                            (6 << MS_Y2_SHIFT) |
101                            (6 << MSBD0_Y_SHIFT) |
102                            (6 << MSBD0_X_SHIFT)));
103         radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0));
104         radeon_ring_write(rdev,
105                           ((6 << MS_X3_SHIFT) |
106                            (6 << MS_Y3_SHIFT) |
107                            (6 << MS_X4_SHIFT) |
108                            (6 << MS_Y4_SHIFT) |
109                            (6 << MS_X5_SHIFT) |
110                            (6 << MS_Y5_SHIFT) |
111                            (6 << MSBD1_SHIFT)));
112         radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0));
113         radeon_ring_write(rdev, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
114         radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0));
115         radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
116         radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0));
117         radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
118         radeon_ring_write(rdev, PACKET0(0x20C8, 0));
119         radeon_ring_write(rdev, 0);
120         radeon_ring_unlock_commit(rdev);
121 }
122
123 int rv515_mc_wait_for_idle(struct radeon_device *rdev)
124 {
125         unsigned i;
126         uint32_t tmp;
127
128         for (i = 0; i < rdev->usec_timeout; i++) {
129                 /* read MC_STATUS */
130                 tmp = RREG32_MC(MC_STATUS);
131                 if (tmp & MC_STATUS_IDLE) {
132                         return 0;
133                 }
134                 DRM_UDELAY(1);
135         }
136         return -1;
137 }
138
139 void rv515_vga_render_disable(struct radeon_device *rdev)
140 {
141         WREG32(R_000300_VGA_RENDER_CONTROL,
142                 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
143 }
144
145 void rv515_gpu_init(struct radeon_device *rdev)
146 {
147         unsigned pipe_select_current, gb_pipe_select, tmp;
148
149         r100_hdp_reset(rdev);
150         r100_rb2d_reset(rdev);
151
152         if (r100_gui_wait_for_idle(rdev)) {
153                 printk(KERN_WARNING "Failed to wait GUI idle while "
154                        "reseting GPU. Bad things might happen.\n");
155         }
156
157         rv515_vga_render_disable(rdev);
158
159         r420_pipes_init(rdev);
160         gb_pipe_select = RREG32(0x402C);
161         tmp = RREG32(0x170C);
162         pipe_select_current = (tmp >> 2) & 3;
163         tmp = (1 << pipe_select_current) |
164               (((gb_pipe_select >> 8) & 0xF) << 4);
165         WREG32_PLL(0x000D, tmp);
166         if (r100_gui_wait_for_idle(rdev)) {
167                 printk(KERN_WARNING "Failed to wait GUI idle while "
168                        "reseting GPU. Bad things might happen.\n");
169         }
170         if (rv515_mc_wait_for_idle(rdev)) {
171                 printk(KERN_WARNING "Failed to wait MC idle while "
172                        "programming pipes. Bad things might happen.\n");
173         }
174 }
175
176 int rv515_ga_reset(struct radeon_device *rdev)
177 {
178         uint32_t tmp;
179         bool reinit_cp;
180         int i;
181
182         reinit_cp = rdev->cp.ready;
183         rdev->cp.ready = false;
184         for (i = 0; i < rdev->usec_timeout; i++) {
185                 WREG32(CP_CSQ_MODE, 0);
186                 WREG32(CP_CSQ_CNTL, 0);
187                 WREG32(RBBM_SOFT_RESET, 0x32005);
188                 (void)RREG32(RBBM_SOFT_RESET);
189                 udelay(200);
190                 WREG32(RBBM_SOFT_RESET, 0);
191                 /* Wait to prevent race in RBBM_STATUS */
192                 mdelay(1);
193                 tmp = RREG32(RBBM_STATUS);
194                 if (tmp & ((1 << 20) | (1 << 26))) {
195                         DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp);
196                         /* GA still busy soft reset it */
197                         WREG32(0x429C, 0x200);
198                         WREG32(VAP_PVS_STATE_FLUSH_REG, 0);
199                         WREG32(0x43E0, 0);
200                         WREG32(0x43E4, 0);
201                         WREG32(0x24AC, 0);
202                 }
203                 /* Wait to prevent race in RBBM_STATUS */
204                 mdelay(1);
205                 tmp = RREG32(RBBM_STATUS);
206                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
207                         break;
208                 }
209         }
210         for (i = 0; i < rdev->usec_timeout; i++) {
211                 tmp = RREG32(RBBM_STATUS);
212                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
213                         DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
214                                  tmp);
215                         DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C));
216                         DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0));
217                         DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724));
218                         if (reinit_cp) {
219                                 return r100_cp_init(rdev, rdev->cp.ring_size);
220                         }
221                         return 0;
222                 }
223                 DRM_UDELAY(1);
224         }
225         tmp = RREG32(RBBM_STATUS);
226         DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
227         return -1;
228 }
229
230 int rv515_gpu_reset(struct radeon_device *rdev)
231 {
232         uint32_t status;
233
234         /* reset order likely matter */
235         status = RREG32(RBBM_STATUS);
236         /* reset HDP */
237         r100_hdp_reset(rdev);
238         /* reset rb2d */
239         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
240                 r100_rb2d_reset(rdev);
241         }
242         /* reset GA */
243         if (status & ((1 << 20) | (1 << 26))) {
244                 rv515_ga_reset(rdev);
245         }
246         /* reset CP */
247         status = RREG32(RBBM_STATUS);
248         if (status & (1 << 16)) {
249                 r100_cp_reset(rdev);
250         }
251         /* Check if GPU is idle */
252         status = RREG32(RBBM_STATUS);
253         if (status & (1 << 31)) {
254                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
255                 return -1;
256         }
257         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
258         return 0;
259 }
260
261 static void rv515_vram_get_type(struct radeon_device *rdev)
262 {
263         uint32_t tmp;
264
265         rdev->mc.vram_width = 128;
266         rdev->mc.vram_is_ddr = true;
267         tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
268         switch (tmp) {
269         case 0:
270                 rdev->mc.vram_width = 64;
271                 break;
272         case 1:
273                 rdev->mc.vram_width = 128;
274                 break;
275         default:
276                 rdev->mc.vram_width = 128;
277                 break;
278         }
279 }
280
281 void rv515_mc_init(struct radeon_device *rdev)
282 {
283
284         rv515_vram_get_type(rdev);
285         r100_vram_init_sizes(rdev);
286         radeon_vram_location(rdev, &rdev->mc, 0);
287         if (!(rdev->flags & RADEON_IS_AGP))
288                 radeon_gtt_location(rdev, &rdev->mc);
289         radeon_update_bandwidth_info(rdev);
290 }
291
292 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
293 {
294         uint32_t r;
295
296         WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
297         r = RREG32(MC_IND_DATA);
298         WREG32(MC_IND_INDEX, 0);
299         return r;
300 }
301
302 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
303 {
304         WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
305         WREG32(MC_IND_DATA, (v));
306         WREG32(MC_IND_INDEX, 0);
307 }
308
309 #if defined(CONFIG_DEBUG_FS)
310 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
311 {
312         struct drm_info_node *node = (struct drm_info_node *) m->private;
313         struct drm_device *dev = node->minor->dev;
314         struct radeon_device *rdev = dev->dev_private;
315         uint32_t tmp;
316
317         tmp = RREG32(GB_PIPE_SELECT);
318         seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
319         tmp = RREG32(SU_REG_DEST);
320         seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
321         tmp = RREG32(GB_TILE_CONFIG);
322         seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
323         tmp = RREG32(DST_PIPE_CONFIG);
324         seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
325         return 0;
326 }
327
328 static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
329 {
330         struct drm_info_node *node = (struct drm_info_node *) m->private;
331         struct drm_device *dev = node->minor->dev;
332         struct radeon_device *rdev = dev->dev_private;
333         uint32_t tmp;
334
335         tmp = RREG32(0x2140);
336         seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
337         radeon_gpu_reset(rdev);
338         tmp = RREG32(0x425C);
339         seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
340         return 0;
341 }
342
343 static struct drm_info_list rv515_pipes_info_list[] = {
344         {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
345 };
346
347 static struct drm_info_list rv515_ga_info_list[] = {
348         {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
349 };
350 #endif
351
352 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
353 {
354 #if defined(CONFIG_DEBUG_FS)
355         return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
356 #else
357         return 0;
358 #endif
359 }
360
361 int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
362 {
363 #if defined(CONFIG_DEBUG_FS)
364         return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
365 #else
366         return 0;
367 #endif
368 }
369
370 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
371 {
372         save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL);
373         save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL);
374         save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
375         save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
376         save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL);
377         save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL);
378
379         /* Stop all video */
380         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
381         WREG32(R_000300_VGA_RENDER_CONTROL, 0);
382         WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
383         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
384         WREG32(R_006080_D1CRTC_CONTROL, 0);
385         WREG32(R_006880_D2CRTC_CONTROL, 0);
386         WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
387         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
388         WREG32(R_000330_D1VGA_CONTROL, 0);
389         WREG32(R_000338_D2VGA_CONTROL, 0);
390 }
391
392 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
393 {
394         WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
395         WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
396         WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
397         WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
398         WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
399         /* Unlock host access */
400         WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
401         mdelay(1);
402         /* Restore video state */
403         WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
404         WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
405         WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
406         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
407         WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control);
408         WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control);
409         WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
410         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
411         WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
412 }
413
414 void rv515_mc_program(struct radeon_device *rdev)
415 {
416         struct rv515_mc_save save;
417
418         /* Stops all mc clients */
419         rv515_mc_stop(rdev, &save);
420
421         /* Wait for mc idle */
422         if (rv515_mc_wait_for_idle(rdev))
423                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
424         /* Write VRAM size in case we are limiting it */
425         WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
426         /* Program MC, should be a 32bits limited address space */
427         WREG32_MC(R_000001_MC_FB_LOCATION,
428                         S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
429                         S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
430         WREG32(R_000134_HDP_FB_LOCATION,
431                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
432         if (rdev->flags & RADEON_IS_AGP) {
433                 WREG32_MC(R_000002_MC_AGP_LOCATION,
434                         S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
435                         S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
436                 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
437                 WREG32_MC(R_000004_MC_AGP_BASE_2,
438                         S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
439         } else {
440                 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
441                 WREG32_MC(R_000003_MC_AGP_BASE, 0);
442                 WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
443         }
444
445         rv515_mc_resume(rdev, &save);
446 }
447
448 void rv515_clock_startup(struct radeon_device *rdev)
449 {
450         if (radeon_dynclks != -1 && radeon_dynclks)
451                 radeon_atom_set_clock_gating(rdev, 1);
452         /* We need to force on some of the block */
453         WREG32_PLL(R_00000F_CP_DYN_CNTL,
454                 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
455         WREG32_PLL(R_000011_E2_DYN_CNTL,
456                 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
457         WREG32_PLL(R_000013_IDCT_DYN_CNTL,
458                 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
459 }
460
461 static int rv515_startup(struct radeon_device *rdev)
462 {
463         int r;
464
465         rv515_mc_program(rdev);
466         /* Resume clock */
467         rv515_clock_startup(rdev);
468         /* Initialize GPU configuration (# pipes, ...) */
469         rv515_gpu_init(rdev);
470         /* Initialize GART (initialize after TTM so we can allocate
471          * memory through TTM but finalize after TTM) */
472         if (rdev->flags & RADEON_IS_PCIE) {
473                 r = rv370_pcie_gart_enable(rdev);
474                 if (r)
475                         return r;
476         }
477         /* Enable IRQ */
478         rs600_irq_set(rdev);
479         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
480         /* 1M ring buffer */
481         r = r100_cp_init(rdev, 1024 * 1024);
482         if (r) {
483                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
484                 return r;
485         }
486         r = r100_wb_init(rdev);
487         if (r)
488                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
489         r = r100_ib_init(rdev);
490         if (r) {
491                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
492                 return r;
493         }
494         return 0;
495 }
496
497 int rv515_resume(struct radeon_device *rdev)
498 {
499         /* Make sur GART are not working */
500         if (rdev->flags & RADEON_IS_PCIE)
501                 rv370_pcie_gart_disable(rdev);
502         /* Resume clock before doing reset */
503         rv515_clock_startup(rdev);
504         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
505         if (radeon_gpu_reset(rdev)) {
506                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
507                         RREG32(R_000E40_RBBM_STATUS),
508                         RREG32(R_0007C0_CP_STAT));
509         }
510         /* post */
511         atom_asic_init(rdev->mode_info.atom_context);
512         /* Resume clock after posting */
513         rv515_clock_startup(rdev);
514         /* Initialize surface registers */
515         radeon_surface_init(rdev);
516         return rv515_startup(rdev);
517 }
518
519 int rv515_suspend(struct radeon_device *rdev)
520 {
521         r100_cp_disable(rdev);
522         r100_wb_disable(rdev);
523         rs600_irq_disable(rdev);
524         if (rdev->flags & RADEON_IS_PCIE)
525                 rv370_pcie_gart_disable(rdev);
526         return 0;
527 }
528
529 void rv515_set_safe_registers(struct radeon_device *rdev)
530 {
531         rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
532         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
533 }
534
535 void rv515_fini(struct radeon_device *rdev)
536 {
537         radeon_pm_fini(rdev);
538         r100_cp_fini(rdev);
539         r100_wb_fini(rdev);
540         r100_ib_fini(rdev);
541         radeon_gem_fini(rdev);
542         rv370_pcie_gart_fini(rdev);
543         radeon_agp_fini(rdev);
544         radeon_irq_kms_fini(rdev);
545         radeon_fence_driver_fini(rdev);
546         radeon_bo_fini(rdev);
547         radeon_atombios_fini(rdev);
548         kfree(rdev->bios);
549         rdev->bios = NULL;
550 }
551
552 int rv515_init(struct radeon_device *rdev)
553 {
554         int r;
555
556         /* Initialize scratch registers */
557         radeon_scratch_init(rdev);
558         /* Initialize surface registers */
559         radeon_surface_init(rdev);
560         /* TODO: disable VGA need to use VGA request */
561         /* BIOS*/
562         if (!radeon_get_bios(rdev)) {
563                 if (ASIC_IS_AVIVO(rdev))
564                         return -EINVAL;
565         }
566         if (rdev->is_atom_bios) {
567                 r = radeon_atombios_init(rdev);
568                 if (r)
569                         return r;
570         } else {
571                 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
572                 return -EINVAL;
573         }
574         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
575         if (radeon_gpu_reset(rdev)) {
576                 dev_warn(rdev->dev,
577                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
578                         RREG32(R_000E40_RBBM_STATUS),
579                         RREG32(R_0007C0_CP_STAT));
580         }
581         /* check if cards are posted or not */
582         if (radeon_boot_test_post_card(rdev) == false)
583                 return -EINVAL;
584         /* Initialize clocks */
585         radeon_get_clock_info(rdev->ddev);
586         /* Initialize power management */
587         radeon_pm_init(rdev);
588         /* initialize AGP */
589         if (rdev->flags & RADEON_IS_AGP) {
590                 r = radeon_agp_init(rdev);
591                 if (r) {
592                         radeon_agp_disable(rdev);
593                 }
594         }
595         /* initialize memory controller */
596         rv515_mc_init(rdev);
597         rv515_debugfs(rdev);
598         /* Fence driver */
599         r = radeon_fence_driver_init(rdev);
600         if (r)
601                 return r;
602         r = radeon_irq_kms_init(rdev);
603         if (r)
604                 return r;
605         /* Memory manager */
606         r = radeon_bo_init(rdev);
607         if (r)
608                 return r;
609         r = rv370_pcie_gart_init(rdev);
610         if (r)
611                 return r;
612         rv515_set_safe_registers(rdev);
613         rdev->accel_working = true;
614         r = rv515_startup(rdev);
615         if (r) {
616                 /* Somethings want wront with the accel init stop accel */
617                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
618                 r100_cp_fini(rdev);
619                 r100_wb_fini(rdev);
620                 r100_ib_fini(rdev);
621                 radeon_irq_kms_fini(rdev);
622                 rv370_pcie_gart_fini(rdev);
623                 radeon_agp_fini(rdev);
624                 rdev->accel_working = false;
625         }
626         return 0;
627 }
628
629 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
630 {
631         int index_reg = 0x6578 + crtc->crtc_offset;
632         int data_reg = 0x657c + crtc->crtc_offset;
633
634         WREG32(0x659C + crtc->crtc_offset, 0x0);
635         WREG32(0x6594 + crtc->crtc_offset, 0x705);
636         WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
637         WREG32(0x65D8 + crtc->crtc_offset, 0x0);
638         WREG32(0x65B0 + crtc->crtc_offset, 0x0);
639         WREG32(0x65C0 + crtc->crtc_offset, 0x0);
640         WREG32(0x65D4 + crtc->crtc_offset, 0x0);
641         WREG32(index_reg, 0x0);
642         WREG32(data_reg, 0x841880A8);
643         WREG32(index_reg, 0x1);
644         WREG32(data_reg, 0x84208680);
645         WREG32(index_reg, 0x2);
646         WREG32(data_reg, 0xBFF880B0);
647         WREG32(index_reg, 0x100);
648         WREG32(data_reg, 0x83D88088);
649         WREG32(index_reg, 0x101);
650         WREG32(data_reg, 0x84608680);
651         WREG32(index_reg, 0x102);
652         WREG32(data_reg, 0xBFF080D0);
653         WREG32(index_reg, 0x200);
654         WREG32(data_reg, 0x83988068);
655         WREG32(index_reg, 0x201);
656         WREG32(data_reg, 0x84A08680);
657         WREG32(index_reg, 0x202);
658         WREG32(data_reg, 0xBFF080F8);
659         WREG32(index_reg, 0x300);
660         WREG32(data_reg, 0x83588058);
661         WREG32(index_reg, 0x301);
662         WREG32(data_reg, 0x84E08660);
663         WREG32(index_reg, 0x302);
664         WREG32(data_reg, 0xBFF88120);
665         WREG32(index_reg, 0x400);
666         WREG32(data_reg, 0x83188040);
667         WREG32(index_reg, 0x401);
668         WREG32(data_reg, 0x85008660);
669         WREG32(index_reg, 0x402);
670         WREG32(data_reg, 0xBFF88150);
671         WREG32(index_reg, 0x500);
672         WREG32(data_reg, 0x82D88030);
673         WREG32(index_reg, 0x501);
674         WREG32(data_reg, 0x85408640);
675         WREG32(index_reg, 0x502);
676         WREG32(data_reg, 0xBFF88180);
677         WREG32(index_reg, 0x600);
678         WREG32(data_reg, 0x82A08018);
679         WREG32(index_reg, 0x601);
680         WREG32(data_reg, 0x85808620);
681         WREG32(index_reg, 0x602);
682         WREG32(data_reg, 0xBFF081B8);
683         WREG32(index_reg, 0x700);
684         WREG32(data_reg, 0x82608010);
685         WREG32(index_reg, 0x701);
686         WREG32(data_reg, 0x85A08600);
687         WREG32(index_reg, 0x702);
688         WREG32(data_reg, 0x800081F0);
689         WREG32(index_reg, 0x800);
690         WREG32(data_reg, 0x8228BFF8);
691         WREG32(index_reg, 0x801);
692         WREG32(data_reg, 0x85E085E0);
693         WREG32(index_reg, 0x802);
694         WREG32(data_reg, 0xBFF88228);
695         WREG32(index_reg, 0x10000);
696         WREG32(data_reg, 0x82A8BF00);
697         WREG32(index_reg, 0x10001);
698         WREG32(data_reg, 0x82A08CC0);
699         WREG32(index_reg, 0x10002);
700         WREG32(data_reg, 0x8008BEF8);
701         WREG32(index_reg, 0x10100);
702         WREG32(data_reg, 0x81F0BF28);
703         WREG32(index_reg, 0x10101);
704         WREG32(data_reg, 0x83608CA0);
705         WREG32(index_reg, 0x10102);
706         WREG32(data_reg, 0x8018BED0);
707         WREG32(index_reg, 0x10200);
708         WREG32(data_reg, 0x8148BF38);
709         WREG32(index_reg, 0x10201);
710         WREG32(data_reg, 0x84408C80);
711         WREG32(index_reg, 0x10202);
712         WREG32(data_reg, 0x8008BEB8);
713         WREG32(index_reg, 0x10300);
714         WREG32(data_reg, 0x80B0BF78);
715         WREG32(index_reg, 0x10301);
716         WREG32(data_reg, 0x85008C20);
717         WREG32(index_reg, 0x10302);
718         WREG32(data_reg, 0x8020BEA0);
719         WREG32(index_reg, 0x10400);
720         WREG32(data_reg, 0x8028BF90);
721         WREG32(index_reg, 0x10401);
722         WREG32(data_reg, 0x85E08BC0);
723         WREG32(index_reg, 0x10402);
724         WREG32(data_reg, 0x8018BE90);
725         WREG32(index_reg, 0x10500);
726         WREG32(data_reg, 0xBFB8BFB0);
727         WREG32(index_reg, 0x10501);
728         WREG32(data_reg, 0x86C08B40);
729         WREG32(index_reg, 0x10502);
730         WREG32(data_reg, 0x8010BE90);
731         WREG32(index_reg, 0x10600);
732         WREG32(data_reg, 0xBF58BFC8);
733         WREG32(index_reg, 0x10601);
734         WREG32(data_reg, 0x87A08AA0);
735         WREG32(index_reg, 0x10602);
736         WREG32(data_reg, 0x8010BE98);
737         WREG32(index_reg, 0x10700);
738         WREG32(data_reg, 0xBF10BFF0);
739         WREG32(index_reg, 0x10701);
740         WREG32(data_reg, 0x886089E0);
741         WREG32(index_reg, 0x10702);
742         WREG32(data_reg, 0x8018BEB0);
743         WREG32(index_reg, 0x10800);
744         WREG32(data_reg, 0xBED8BFE8);
745         WREG32(index_reg, 0x10801);
746         WREG32(data_reg, 0x89408940);
747         WREG32(index_reg, 0x10802);
748         WREG32(data_reg, 0xBFE8BED8);
749         WREG32(index_reg, 0x20000);
750         WREG32(data_reg, 0x80008000);
751         WREG32(index_reg, 0x20001);
752         WREG32(data_reg, 0x90008000);
753         WREG32(index_reg, 0x20002);
754         WREG32(data_reg, 0x80008000);
755         WREG32(index_reg, 0x20003);
756         WREG32(data_reg, 0x80008000);
757         WREG32(index_reg, 0x20100);
758         WREG32(data_reg, 0x80108000);
759         WREG32(index_reg, 0x20101);
760         WREG32(data_reg, 0x8FE0BF70);
761         WREG32(index_reg, 0x20102);
762         WREG32(data_reg, 0xBFE880C0);
763         WREG32(index_reg, 0x20103);
764         WREG32(data_reg, 0x80008000);
765         WREG32(index_reg, 0x20200);
766         WREG32(data_reg, 0x8018BFF8);
767         WREG32(index_reg, 0x20201);
768         WREG32(data_reg, 0x8F80BF08);
769         WREG32(index_reg, 0x20202);
770         WREG32(data_reg, 0xBFD081A0);
771         WREG32(index_reg, 0x20203);
772         WREG32(data_reg, 0xBFF88000);
773         WREG32(index_reg, 0x20300);
774         WREG32(data_reg, 0x80188000);
775         WREG32(index_reg, 0x20301);
776         WREG32(data_reg, 0x8EE0BEC0);
777         WREG32(index_reg, 0x20302);
778         WREG32(data_reg, 0xBFB082A0);
779         WREG32(index_reg, 0x20303);
780         WREG32(data_reg, 0x80008000);
781         WREG32(index_reg, 0x20400);
782         WREG32(data_reg, 0x80188000);
783         WREG32(index_reg, 0x20401);
784         WREG32(data_reg, 0x8E00BEA0);
785         WREG32(index_reg, 0x20402);
786         WREG32(data_reg, 0xBF8883C0);
787         WREG32(index_reg, 0x20403);
788         WREG32(data_reg, 0x80008000);
789         WREG32(index_reg, 0x20500);
790         WREG32(data_reg, 0x80188000);
791         WREG32(index_reg, 0x20501);
792         WREG32(data_reg, 0x8D00BE90);
793         WREG32(index_reg, 0x20502);
794         WREG32(data_reg, 0xBF588500);
795         WREG32(index_reg, 0x20503);
796         WREG32(data_reg, 0x80008008);
797         WREG32(index_reg, 0x20600);
798         WREG32(data_reg, 0x80188000);
799         WREG32(index_reg, 0x20601);
800         WREG32(data_reg, 0x8BC0BE98);
801         WREG32(index_reg, 0x20602);
802         WREG32(data_reg, 0xBF308660);
803         WREG32(index_reg, 0x20603);
804         WREG32(data_reg, 0x80008008);
805         WREG32(index_reg, 0x20700);
806         WREG32(data_reg, 0x80108000);
807         WREG32(index_reg, 0x20701);
808         WREG32(data_reg, 0x8A80BEB0);
809         WREG32(index_reg, 0x20702);
810         WREG32(data_reg, 0xBF0087C0);
811         WREG32(index_reg, 0x20703);
812         WREG32(data_reg, 0x80008008);
813         WREG32(index_reg, 0x20800);
814         WREG32(data_reg, 0x80108000);
815         WREG32(index_reg, 0x20801);
816         WREG32(data_reg, 0x8920BED0);
817         WREG32(index_reg, 0x20802);
818         WREG32(data_reg, 0xBED08920);
819         WREG32(index_reg, 0x20803);
820         WREG32(data_reg, 0x80008010);
821         WREG32(index_reg, 0x30000);
822         WREG32(data_reg, 0x90008000);
823         WREG32(index_reg, 0x30001);
824         WREG32(data_reg, 0x80008000);
825         WREG32(index_reg, 0x30100);
826         WREG32(data_reg, 0x8FE0BF90);
827         WREG32(index_reg, 0x30101);
828         WREG32(data_reg, 0xBFF880A0);
829         WREG32(index_reg, 0x30200);
830         WREG32(data_reg, 0x8F60BF40);
831         WREG32(index_reg, 0x30201);
832         WREG32(data_reg, 0xBFE88180);
833         WREG32(index_reg, 0x30300);
834         WREG32(data_reg, 0x8EC0BF00);
835         WREG32(index_reg, 0x30301);
836         WREG32(data_reg, 0xBFC88280);
837         WREG32(index_reg, 0x30400);
838         WREG32(data_reg, 0x8DE0BEE0);
839         WREG32(index_reg, 0x30401);
840         WREG32(data_reg, 0xBFA083A0);
841         WREG32(index_reg, 0x30500);
842         WREG32(data_reg, 0x8CE0BED0);
843         WREG32(index_reg, 0x30501);
844         WREG32(data_reg, 0xBF7884E0);
845         WREG32(index_reg, 0x30600);
846         WREG32(data_reg, 0x8BA0BED8);
847         WREG32(index_reg, 0x30601);
848         WREG32(data_reg, 0xBF508640);
849         WREG32(index_reg, 0x30700);
850         WREG32(data_reg, 0x8A60BEE8);
851         WREG32(index_reg, 0x30701);
852         WREG32(data_reg, 0xBF2087A0);
853         WREG32(index_reg, 0x30800);
854         WREG32(data_reg, 0x8900BF00);
855         WREG32(index_reg, 0x30801);
856         WREG32(data_reg, 0xBF008900);
857 }
858
859 struct rv515_watermark {
860         u32        lb_request_fifo_depth;
861         fixed20_12 num_line_pair;
862         fixed20_12 estimated_width;
863         fixed20_12 worst_case_latency;
864         fixed20_12 consumption_rate;
865         fixed20_12 active_time;
866         fixed20_12 dbpp;
867         fixed20_12 priority_mark_max;
868         fixed20_12 priority_mark;
869         fixed20_12 sclk;
870 };
871
872 void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
873                                   struct radeon_crtc *crtc,
874                                   struct rv515_watermark *wm)
875 {
876         struct drm_display_mode *mode = &crtc->base.mode;
877         fixed20_12 a, b, c;
878         fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
879         fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
880
881         if (!crtc->base.enabled) {
882                 /* FIXME: wouldn't it better to set priority mark to maximum */
883                 wm->lb_request_fifo_depth = 4;
884                 return;
885         }
886
887         if (crtc->vsc.full > rfixed_const(2))
888                 wm->num_line_pair.full = rfixed_const(2);
889         else
890                 wm->num_line_pair.full = rfixed_const(1);
891
892         b.full = rfixed_const(mode->crtc_hdisplay);
893         c.full = rfixed_const(256);
894         a.full = rfixed_div(b, c);
895         request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair);
896         request_fifo_depth.full = rfixed_ceil(request_fifo_depth);
897         if (a.full < rfixed_const(4)) {
898                 wm->lb_request_fifo_depth = 4;
899         } else {
900                 wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth);
901         }
902
903         /* Determine consumption rate
904          *  pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
905          *  vtaps = number of vertical taps,
906          *  vsc = vertical scaling ratio, defined as source/destination
907          *  hsc = horizontal scaling ration, defined as source/destination
908          */
909         a.full = rfixed_const(mode->clock);
910         b.full = rfixed_const(1000);
911         a.full = rfixed_div(a, b);
912         pclk.full = rfixed_div(b, a);
913         if (crtc->rmx_type != RMX_OFF) {
914                 b.full = rfixed_const(2);
915                 if (crtc->vsc.full > b.full)
916                         b.full = crtc->vsc.full;
917                 b.full = rfixed_mul(b, crtc->hsc);
918                 c.full = rfixed_const(2);
919                 b.full = rfixed_div(b, c);
920                 consumption_time.full = rfixed_div(pclk, b);
921         } else {
922                 consumption_time.full = pclk.full;
923         }
924         a.full = rfixed_const(1);
925         wm->consumption_rate.full = rfixed_div(a, consumption_time);
926
927
928         /* Determine line time
929          *  LineTime = total time for one line of displayhtotal
930          *  LineTime = total number of horizontal pixels
931          *  pclk = pixel clock period(ns)
932          */
933         a.full = rfixed_const(crtc->base.mode.crtc_htotal);
934         line_time.full = rfixed_mul(a, pclk);
935
936         /* Determine active time
937          *  ActiveTime = time of active region of display within one line,
938          *  hactive = total number of horizontal active pixels
939          *  htotal = total number of horizontal pixels
940          */
941         a.full = rfixed_const(crtc->base.mode.crtc_htotal);
942         b.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
943         wm->active_time.full = rfixed_mul(line_time, b);
944         wm->active_time.full = rfixed_div(wm->active_time, a);
945
946         /* Determine chunk time
947          * ChunkTime = the time it takes the DCP to send one chunk of data
948          * to the LB which consists of pipeline delay and inter chunk gap
949          * sclk = system clock(Mhz)
950          */
951         a.full = rfixed_const(600 * 1000);
952         chunk_time.full = rfixed_div(a, rdev->pm.sclk);
953         read_delay_latency.full = rfixed_const(1000);
954
955         /* Determine the worst case latency
956          * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
957          * WorstCaseLatency = worst case time from urgent to when the MC starts
958          *                    to return data
959          * READ_DELAY_IDLE_MAX = constant of 1us
960          * ChunkTime = time it takes the DCP to send one chunk of data to the LB
961          *             which consists of pipeline delay and inter chunk gap
962          */
963         if (rfixed_trunc(wm->num_line_pair) > 1) {
964                 a.full = rfixed_const(3);
965                 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
966                 wm->worst_case_latency.full += read_delay_latency.full;
967         } else {
968                 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
969         }
970
971         /* Determine the tolerable latency
972          * TolerableLatency = Any given request has only 1 line time
973          *                    for the data to be returned
974          * LBRequestFifoDepth = Number of chunk requests the LB can
975          *                      put into the request FIFO for a display
976          *  LineTime = total time for one line of display
977          *  ChunkTime = the time it takes the DCP to send one chunk
978          *              of data to the LB which consists of
979          *  pipeline delay and inter chunk gap
980          */
981         if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) {
982                 tolerable_latency.full = line_time.full;
983         } else {
984                 tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2);
985                 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
986                 tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time);
987                 tolerable_latency.full = line_time.full - tolerable_latency.full;
988         }
989         /* We assume worst case 32bits (4 bytes) */
990         wm->dbpp.full = rfixed_const(2 * 16);
991
992         /* Determine the maximum priority mark
993          *  width = viewport width in pixels
994          */
995         a.full = rfixed_const(16);
996         wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
997         wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
998         wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max);
999
1000         /* Determine estimated width */
1001         estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
1002         estimated_width.full = rfixed_div(estimated_width, consumption_time);
1003         if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
1004                 wm->priority_mark.full = wm->priority_mark_max.full;
1005         } else {
1006                 a.full = rfixed_const(16);
1007                 wm->priority_mark.full = rfixed_div(estimated_width, a);
1008                 wm->priority_mark.full = rfixed_ceil(wm->priority_mark);
1009                 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
1010         }
1011 }
1012
1013 void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
1014 {
1015         struct drm_display_mode *mode0 = NULL;
1016         struct drm_display_mode *mode1 = NULL;
1017         struct rv515_watermark wm0;
1018         struct rv515_watermark wm1;
1019         u32 tmp;
1020         fixed20_12 priority_mark02, priority_mark12, fill_rate;
1021         fixed20_12 a, b;
1022
1023         if (rdev->mode_info.crtcs[0]->base.enabled)
1024                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1025         if (rdev->mode_info.crtcs[1]->base.enabled)
1026                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1027         rs690_line_buffer_adjust(rdev, mode0, mode1);
1028
1029         rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
1030         rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
1031
1032         tmp = wm0.lb_request_fifo_depth;
1033         tmp |= wm1.lb_request_fifo_depth << 16;
1034         WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
1035
1036         if (mode0 && mode1) {
1037                 if (rfixed_trunc(wm0.dbpp) > 64)
1038                         a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
1039                 else
1040                         a.full = wm0.num_line_pair.full;
1041                 if (rfixed_trunc(wm1.dbpp) > 64)
1042                         b.full = rfixed_div(wm1.dbpp, wm1.num_line_pair);
1043                 else
1044                         b.full = wm1.num_line_pair.full;
1045                 a.full += b.full;
1046                 fill_rate.full = rfixed_div(wm0.sclk, a);
1047                 if (wm0.consumption_rate.full > fill_rate.full) {
1048                         b.full = wm0.consumption_rate.full - fill_rate.full;
1049                         b.full = rfixed_mul(b, wm0.active_time);
1050                         a.full = rfixed_const(16);
1051                         b.full = rfixed_div(b, a);
1052                         a.full = rfixed_mul(wm0.worst_case_latency,
1053                                                 wm0.consumption_rate);
1054                         priority_mark02.full = a.full + b.full;
1055                 } else {
1056                         a.full = rfixed_mul(wm0.worst_case_latency,
1057                                                 wm0.consumption_rate);
1058                         b.full = rfixed_const(16 * 1000);
1059                         priority_mark02.full = rfixed_div(a, b);
1060                 }
1061                 if (wm1.consumption_rate.full > fill_rate.full) {
1062                         b.full = wm1.consumption_rate.full - fill_rate.full;
1063                         b.full = rfixed_mul(b, wm1.active_time);
1064                         a.full = rfixed_const(16);
1065                         b.full = rfixed_div(b, a);
1066                         a.full = rfixed_mul(wm1.worst_case_latency,
1067                                                 wm1.consumption_rate);
1068                         priority_mark12.full = a.full + b.full;
1069                 } else {
1070                         a.full = rfixed_mul(wm1.worst_case_latency,
1071                                                 wm1.consumption_rate);
1072                         b.full = rfixed_const(16 * 1000);
1073                         priority_mark12.full = rfixed_div(a, b);
1074                 }
1075                 if (wm0.priority_mark.full > priority_mark02.full)
1076                         priority_mark02.full = wm0.priority_mark.full;
1077                 if (rfixed_trunc(priority_mark02) < 0)
1078                         priority_mark02.full = 0;
1079                 if (wm0.priority_mark_max.full > priority_mark02.full)
1080                         priority_mark02.full = wm0.priority_mark_max.full;
1081                 if (wm1.priority_mark.full > priority_mark12.full)
1082                         priority_mark12.full = wm1.priority_mark.full;
1083                 if (rfixed_trunc(priority_mark12) < 0)
1084                         priority_mark12.full = 0;
1085                 if (wm1.priority_mark_max.full > priority_mark12.full)
1086                         priority_mark12.full = wm1.priority_mark_max.full;
1087                 WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
1088                 WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
1089                 WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
1090                 WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
1091         } else if (mode0) {
1092                 if (rfixed_trunc(wm0.dbpp) > 64)
1093                         a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
1094                 else
1095                         a.full = wm0.num_line_pair.full;
1096                 fill_rate.full = rfixed_div(wm0.sclk, a);
1097                 if (wm0.consumption_rate.full > fill_rate.full) {
1098                         b.full = wm0.consumption_rate.full - fill_rate.full;
1099                         b.full = rfixed_mul(b, wm0.active_time);
1100                         a.full = rfixed_const(16);
1101                         b.full = rfixed_div(b, a);
1102                         a.full = rfixed_mul(wm0.worst_case_latency,
1103                                                 wm0.consumption_rate);
1104                         priority_mark02.full = a.full + b.full;
1105                 } else {
1106                         a.full = rfixed_mul(wm0.worst_case_latency,
1107                                                 wm0.consumption_rate);
1108                         b.full = rfixed_const(16);
1109                         priority_mark02.full = rfixed_div(a, b);
1110                 }
1111                 if (wm0.priority_mark.full > priority_mark02.full)
1112                         priority_mark02.full = wm0.priority_mark.full;
1113                 if (rfixed_trunc(priority_mark02) < 0)
1114                         priority_mark02.full = 0;
1115                 if (wm0.priority_mark_max.full > priority_mark02.full)
1116                         priority_mark02.full = wm0.priority_mark_max.full;
1117                 WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
1118                 WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
1119                 WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
1120                 WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
1121         } else {
1122                 if (rfixed_trunc(wm1.dbpp) > 64)
1123                         a.full = rfixed_div(wm1.dbpp, wm1.num_line_pair);
1124                 else
1125                         a.full = wm1.num_line_pair.full;
1126                 fill_rate.full = rfixed_div(wm1.sclk, a);
1127                 if (wm1.consumption_rate.full > fill_rate.full) {
1128                         b.full = wm1.consumption_rate.full - fill_rate.full;
1129                         b.full = rfixed_mul(b, wm1.active_time);
1130                         a.full = rfixed_const(16);
1131                         b.full = rfixed_div(b, a);
1132                         a.full = rfixed_mul(wm1.worst_case_latency,
1133                                                 wm1.consumption_rate);
1134                         priority_mark12.full = a.full + b.full;
1135                 } else {
1136                         a.full = rfixed_mul(wm1.worst_case_latency,
1137                                                 wm1.consumption_rate);
1138                         b.full = rfixed_const(16 * 1000);
1139                         priority_mark12.full = rfixed_div(a, b);
1140                 }
1141                 if (wm1.priority_mark.full > priority_mark12.full)
1142                         priority_mark12.full = wm1.priority_mark.full;
1143                 if (rfixed_trunc(priority_mark12) < 0)
1144                         priority_mark12.full = 0;
1145                 if (wm1.priority_mark_max.full > priority_mark12.full)
1146                         priority_mark12.full = wm1.priority_mark_max.full;
1147                 WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
1148                 WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
1149                 WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
1150                 WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
1151         }
1152 }
1153
1154 void rv515_bandwidth_update(struct radeon_device *rdev)
1155 {
1156         uint32_t tmp;
1157         struct drm_display_mode *mode0 = NULL;
1158         struct drm_display_mode *mode1 = NULL;
1159
1160         if (rdev->mode_info.crtcs[0]->base.enabled)
1161                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1162         if (rdev->mode_info.crtcs[1]->base.enabled)
1163                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1164         /*
1165          * Set display0/1 priority up in the memory controller for
1166          * modes if the user specifies HIGH for displaypriority
1167          * option.
1168          */
1169         if (rdev->disp_priority == 2) {
1170                 tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1171                 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1172                 tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1173                 if (mode1)
1174                         tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1175                 if (mode0)
1176                         tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1177                 WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1178         }
1179         rv515_bandwidth_avivo_update(rdev);
1180 }